TAS5015PFBG4

 SLES017 − SEPTEMBER 2001
 
     
 
      FEATURES D TAS5015 Plus Discrete Back-End TDAA D D D D D D D D D D DESCRIPTION System — High-Quality Digital Audio Amplification 112-dB Dynamic Range (TAS5015 Device) THD+N < 0.01% Power Efficiency Is 90% into 8-Ω Load 16-, 20-, or 24-Bit Input Data 44.1-kHz, 48-kHz, 88.2-kHz, 96-kHz, 176.4-kHz, 192-kHz Sampling Rates Economical 48-Pin TQFP Package External PLL 3.3-V Power Supply Mute Clicks and Pops Reduction (Patent Pending) APPLICATIONS D High-Performance Digital Amplification For: − Integrated Amplifiers − AV Receiver − Car Audio Digital Audio • Digital Audio Processor Left Discrete Back-End L-C Filter Right Discrete Back-End L-C Filter TAS5015 • DSP • S/PDIF • 1394 • Volume • EQ • DRC • Bass • Treble The true digital audio amplifier (TDAA) is a new paradigm in digital audio. One TDAA system consists of the TAS5015 PCM-PWM modulator device plus a discrete back-end TDAA power output. This system accepts a serial PCM digital audio stream and converts it to a 3.3-V PWM audio stream (TAS5015). The discrete back-end TDAA then provides a large-signal PWM output. This digital PWM signal is then demodulated, providing power output for driving loudspeakers. This patented technology provides low-cost, high-quality, high-efficiency digital audio applicable to many audio systems developed for the digital age. The TAS5015 is an innovative, cost-effective, high-performance 24-bit stereo PCM-PWM modulator based on Equibit technology. The TAS5015 has a wide variety of serial input options including right-justified (16, 20, or 24 bits), IIS (16, 20, or 24 bits), left-justified (16 bits), or DSP (16 bits) data formats. It is fully compatible with AES standard sampling rates (Fs) of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. The TAS5015 also provides a de-emphasis function for 44.1-kHz and 48-kHz sampling rates. • Serial Audio Input Port • External PLL • Equibit Modulator • Up to 192-kHz Sampling • H-Bridges Power Devices • Improved Performance From TAS5100 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Equibit is a trademark of Toccata Technology ApS, Denmark.  
 
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 SLES017 − SEPTEMBER 2001 terminal assignments AVDD1 AVSS1 NC NC AVSS1 DEM_EN DEM_SEL FTEST STEST DBSPD MUTE DVSS3_L 48-Pin TQFP PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 MCLK_IN AVDD2 NC NC AVSS2 HFCLK RESET PDN VALID_R M_S NC DVDD1 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 DVDD3_L PWM_AP_L PWM_AM_L PWM_BM_L PWM_BP_L DVDD2 DVSS2 PWM_AP_R PWM_AM_R PWM_BM_R PWM_BP_R DVDD3_R DVSS1 DVDD1 DVSS1 MCLK_OUT SCLK LRCLK SDIN MOD2 MOD1 MOD0 VALID_L DVSS3_R 13 14 15 16 17 18 19 20 21 22 23 24 NC − No internal connection references D True Digital Audio Amplifier TAS5100 PWM Power Output Stage − Texas Instruments publication SLLS419 D Design Considerations for TAS5000/TAS5110 True Digital Audio Power Amplifiers − Texas Instruments publication SLAA117 D Digital Audio Measurements − Texas Instruments publication SLAA114 D PowerPAD Thermally Enhanced Package − Texas Instruments publication SLMA002 PowerPAD is a trademark of Texas Instruments. 2 www.ti.com 
 SLES017 − SEPTEMBER 2001 MCLK_OUT VALID_R VALID_L HFCLK MCLK_IN functional block diagram Clock Generator LRCLK Serial Audio Port SCLK Digital Interpolation Filter Equibit Modulator PWM_AP_L PWM_AM_L PWM_BP_L PWM_BM_L Buffer PWM_AP_R PWM_AM_R PWM_BP_R PWM_BM_R SDIN Control Section DVDD1 DVSS1 DVDD2 DVSS2 DVDD3_L DVSS3_L DVDD3_R DVSS3_R AVDD1 AVSS1 AVDD2 AVSS2 STEST DBSPD M_S FTEST PDN MUTE RESET DEM_EN DEM_SEL MOD2 MOD1 MOD0 Audio Port Configuration AVAILABLE OPTIONS PACKAGE TA 0°C to 70°C TAS5015PFB −40°C to 85°C TAS5015IPFB NOTE: These packages are available taped and reeled. Add R suffix to ordering number (e.g., TAS5015PFBR). www.ti.com 3 
 SLES017 − SEPTEMBER 2001 Terminal Functions TERMINAL NAME I/O DESCRIPTION AVDD1 48 I Analog supply AVDD2 2 I Analog supply AVSS1 44, 47 I Analog ground AVSS2 5 I Analog ground DBSPD 39 I Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high DEM_EN 43 I De-emphasis enable, active high DEM_SEL 42 I De-emphasis select (0 = 44.1 kHz, 1 = 48 kHz) DVDD1 12, 14 I Digital voltage supply for logic DVDD2 31 I Digital voltage supply for PWM reclocking DVDD3_L 36 I Digital voltage supply for PWM output (left) DVDD3_R 25 I Digital voltage supply for PWM output (right) DVSS1 13, 15 I Digital ground for logic DVSS2 30 I Digital ground for PWM reclocking DVSS3_L 37 I Digital ground for PWM output (left) DVSS3_R 24 I Digital ground for PWM output (right) FTEST 41 I Tied to DVSS1 for normal operation HFCLK 6 I External PLL clock input LRCLK 18 I/O MCLK_IN 1 I MCLK input MCLK_OUT 16 O Buffered system clock output if M_S = 1; otherwise set to 0 MOD0 22 I Serial interface selection pin, bit 0 MOD1 21 I Serial interface selection pin, bit 1 MOD2 20 I Serial interface selection pin, bit 2 (MSB) M_S 10 I Master/slave, master=1, slave=0 38 I Muted signal = 0, normal mode = 1 MUTE NC 4 NO. 3, 4, 11, 45, 46 Left/right clock (input when M_S = 0; output when M_S = 1) No connection PDN 8 I Power down, active low PWM_AM_L 34 O PWM left output A (differential −) PWM_AM_R 28 O PWM right output A (differential −) PWM_AP_L 35 O PWM left output A (differential +) PWM_AP_R 29 O PWM right output A (differential +) PWM_BM_L 33 O PWM left output B (differential −) PWM_BM_R 27 O PWM right output B (differential −) PWM_BP_L 32 O PWM left output B (differential +) PWM_BP_R 26 O PWM right output B (differential +) RESET 7 I Reset (active low) SCLK 17 I/O SDIN 19 I Stereo serial audio data input STEST 40 I Tied to DVSS1 for normal operation VALID_L 23 O PWM left outputs valid (active high) VALID_R 9 O PWM right outputs valid (active high) Shift clock (input when M_S = 0, output when M_S = 1) www.ti.com 
 SLES017 − SEPTEMBER 2001 functional description serial audio port The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin), and a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 44.1-kHz, 48-kHz, 88.2-kHz, 96-kHz, 176.4-kHz, or 192-kHz stereo). See the serial interface formats section. system clocks—master mode and slave mode The TAS5015 allows multiple system clocking schemes. Master mode indicates that the TAS5015 provides system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 128 Fs MCLK_OUT (quad speed), 64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode. Slave mode indicates that a system master other than the TAS5015 provides system clocks (LRCLK, SCLK, and MCLK_IN) to the TAS5015 (M_S = 0). The TAS5015 operates with LRCLK and SCLK synchronized to MCLK. The TAS5015 does not require any specific phase relationship between LRCLK and MCLK, but there must be synchronization. In the slave mode, MCLK_OUT is driven low. Table 1 shows all the possible master and slave modes. sampling frequency The normal sampling frequency is either 11.2896 MHz (Fs = 44.1 kHz) or 12.288 MHz (Fs = 48 kHz). Twice the normal sampling frequency can be selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz or Fs = 96 kHz. In the double-speed slave mode (DBSPD = 1, M_S = 0), the external clock input is either 22.5796 MHz (Fs = 88.2 kHz) or 24.576 MHz (Fs = 96 kHz). Table 1 explains the proper clock selection. Table 1. External Clock and External PLL Functions MCLK_IN (MHz) HFCLK (MHz) SCLK (MHz) LRCLK (KHz) MCLK_OUT (MHz) − 90.3168 2.8224 44.1 11.2896 − 98.304 3.072 48 12.288 0 − 90.3168 5.6448 88.2 22.5792 0 0 − 98.304 6.144 96 24.576 0 0 1 − 90.3168 11.2896 176.4 22.5792 1 0 0 1 − 98.304 12.288 192 24.576 External PLL, slave, normal speed (see Notes 3, 4, and 5) 0 0 0 0 1 0 11.2896 90.3168 2.8224 44.1 11.2896 External PLL, slave, normal speed (see Notes 3, 4, and 5) 1 1 0 0 0 0 12.288 98.304 3.072 48 12.288 DESCRIPTION M_S DBSPD DEM_EN DEM_SEL External PLL, master, normal speed (see Notes 1 and 2) 1 0 0 0 1 0 External PLL, master, normal speed (see Notes 1 and 2) 1 0 1 1 0 0 External PLL, master, double speed (see Notes 1 and 2) 1 1 0 External PLL, master, double speed (see Note 1 and 2) 1 1 External PLL, master, quad speed (see Notes 1 and 2) 1 External PLL, master, quad speed (see Notes 1 and 2) NOTES: 1. 2. 3. 4. 5. SCLK and LRCLK are outputs MCLK_IN tied LOW External MCLK connected to MCLK_IN input SCLK and LRCLK are inputs MCLK_OUT is a buffered version of the external MCLK input www.ti.com 5 
 SLES017 − SEPTEMBER 2001 functional description (continued) Table 1. External Clock and External PLL Functions (Continued) M_S DBSPD DEM_EN DEM_SEL MCLK_IN (MHz) HFCLK (MHz) SCLK (MHz) LRCLK (kHz) MCLK_OUT (MHz) External PLL, slave, double speed (see Notes 3, 4, and 5) 0 1 0 0 22.5792 90.3168 5.6448 88.2 22.5792 External PLL, slave, double speed (see Notes 3, 4, and 5) 0 1 0 0 24.576 98.304 6.144 96 24.576 External PLL, slave, quad speed (see Notes 3, 4, and 5) 0 0 0 0 22.5792 90.3168 11.2896 176.4 22.5792 External PLL, slave, quad speed (see Notes 3, 4, and 5) 0 0 0 0 24.576 98.304 12.288 192 24.576 DESCRIPTION NOTES: 3. External MCLK connected to MCLK_IN input 4. SCLK and LRCLK are inputs 5. MCLK_OUT is a buffered version of the external MCLK input external PLL For the highest system performance, an external PLL must be used with the TAS5015. For normal-speed mode, the external PLL input (HFCLK) must be 2048 Fs, for double-speed mode HFCLK must be 1024 Fs, and for quad-speed mode HFCLK must be 512 Fs. digital interpolation filter The 24-bit high-performance linear phase FIR interpolation filter up-samples the input digital data at a rate of two times (quad-speed mode = 176.4 kHz or 192 kHz), four times (double-speed mode = 88.2 kHz or 96 kHz), or eight times (normal mode = 44.1 kHz or 48 kHz) the incoming sample rate. This filter provides low pass-band ripple and optimized time domain transient response for accurate music reproduction. digital PWM modulator The interpolation filter output is sent to the digital PWM modulator. This modulator consists of a highperformance fourth order digital-noise shaper and a PCM-to-PWM converter. Following the noise shaper, the PCM signal is fed into a low distortion PCM-to-PWM conversion block, buffered, and output from the chip. The modulation scheme is based on a 2-state control of the H-bridge output. control, status, and operational modes The TAS5015 control section consists of several control-input pins. Three serial mode pins (MOD0, MOD1, and MOD2) are provided to select various serial data formats. During normal operating conditions if any of the MOD0, MOD1, or MOD2 pins changes state, a reset sequence is initiated. Also provided are separate power-down (PDN), reset (RESET), and mute (MUTE) pins. power up At power up, the VALID_L and VALID_R pins are asserted low and the PWM outputs go to the hard mute state in which the P outputs are held low and the M outputs are held high. Following initialization, the TAS5015 comes up in the operational state (differential PWM audio). There are two cases of power-up timing. The first case is shown in Figure 1 with RESET preceding PDN. The second case is shown in Figure 2 with PDN preceding RESET. 6 www.ti.com 
 SLES017 − SEPTEMBER 2001 functional description (continued) RESET PDN Initialization Time = 100 ms max VALID_L VALID_R Figure 1. Power-Up Timing (RESET Preceding PDN) Greater Than 16 MCLK Periods RESET PDN Initialization Time = 5 ms max VALID_L VALID_R Figure 2. Power-Up Timing (PDN Preceding RESET) reset The reset signal for the TAS5015 must be applied whenever toggling the M_S, DBSPD signal. This reset is asynchronous. See Figure 3 for reset timing. To initiate the reset sequence the RESET pin is asserted low. As long as the pin is held low the chip is in the reset state. During this reset time, the PWM outputs are hard-muted (P-outputs held low and M-outputs held high) and the PWM outputs valid pins (VALID_L. VALID_R) are held low. Assuming PDN is high, the rising edge of the reset pulse begins chip initialization. After the initialization time, the TAS5015 begins normal operation. RESET 5 ms max VALID_L Initialization Normal Operation VALID_R Normal Operation PDN Figure 3. Reset Timing power down Note that power down is an asynchronous operation. To place the device in total power-down mode, both RESET and PDN must be held low. As long as these pins are held low, the chip is in the power-down state and the PWM outputs are hard muted with the P outputs held low and the M outputs held high. To place the device back into normal mode, see the power up section. NOTE: In order for the dynamic logic to be properly powered down, the clocks should not be stopped before the PDN pin goes low. Otherwise, the device may drain additional supply current. www.ti.com 7 
 SLES017 − SEPTEMBER 2001 functional description (continued) VALID Normal Operation Normal Operation Initialization Chip Power-Down PDN and RESET Figure 4. Power-Down Timing mute The TAS5015 provides a mute function that is used when the MUTE pin is asserted low. See Table 2 for mute description. This mute is a quiet mute; that is, the mute is accomplished by outputting a zero value waveform in which both sides of the differential PWM outputs have a 50% duty cycle (see Figure 5 for mute timing). Table 2. Mute Description MUTE P OUTPUTS M OUTPUTS DESCRIPTION 0 50% duty cycle 50% duty cycle Mute 1 DATA DATA Normal operation 10 µs max MUTE 5 ms max Initialization VALID_L VALID_R PWM Outputs 50−50 Duty Cycle (P, M Complementary) Inactive State Normal State (P, M Complementary) Figure 5. Mute Timing double speed Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz. In order to put the TAS5015 in double-speed mode with the device in normal operating conditions, the RESET pin must be held low while switching the DBSPD pin high. After the RESET pin is brought high again, a reset sequence takes place. If the change is at power up, a power-up sequence is originated. quad speed Quad-speed mode is used to support sampling rates of 176.4 kHz and 192 kHz. In order to put the TAS5015 in quad-speed slave mode, M_S and DBPSB pins are brought low. Quad-speed mode is then automatically detected due to the fact that it is the only mode in which MCLK_IN is 128 Fs. DEM_SEL must be set to low when operating in the quad-speed slave mode. For quad-speed master mode M_S = 1, DBSPD = 0, DEM_SEL = 1, and DEM_EN = 0. 8 www.ti.com 
 SLES017 − SEPTEMBER 2001 functional description (continued) de-emphasis filter Response − dB For audio sources that have been preemphasized, a precision 50 µs/15 µs de-emphasis filter is provided to support the sampling rates of 44.1 kHz and 48 kHz. Pins DEM_SEL and DEM_EN select the de-emphasis functions. See Figure 6 for a graph showing the de-emphasis filtering characteristics. See Table 3 for de-emphasis selection. 0 De-emphasis −10 3.18 (50 µs) 10.6 (15 µs) f − Frequency − kHz Figure 6. De-Emphasis Filter Characteristics de-emphasis selection De-emphasis selection is accomplished by using the DEM_SEL and DEM_EN pins. See Table 3 for de-emphasis selection description. Table 3. De-Emphasis Selection DEM_SEL DEM_EN 0 0 De-emphasis disabled DESCRIPTION 0 1 De-emphasis enabled for Fs = 44.1 kHz 1 1 De-emphasis enabled for Fs = 48 kHz 1 0 Disallowed state. Do not use. error status reporting (VALID_L and VALID_R) The following is a list of the error conditions that will cause the VALID_L and VALID_R pins to be asserted low. − No clocks − Clock phase errors When either of the above conditions is met, the VALID_L and VALID_R goes low and the PWM outputs go to the hard mute state. If the error condition is removed, the TAS5015 is reinitialized and the VALID_L and VALID_R pins are asserted high. serial interface formats The TAS5015 is compatible with eight different serial interfaces. Available interface options are IIS, right justified, left justified, and DSP frame. Table 4 indicates how these options are selected using the MOD0, MOD1, and MOD2 pins. www.ti.com 9 
 SLES017 − SEPTEMBER 2001 functional description (continued) Table 4. Hardware Selection of Serial Audio Modes SERIAL INTERFACE SDIN MODE MOD2 PIN MOD1 PIN MOD0 PIN 0 0 0 0 16-bit, MSB first; right justified 1 0 0 1 20-bit, MSB first; right justified 2 0 1 0 24-bit, MSB first; right justified 3 0 1 1 16-bit IIS 4 1 0 0 20-bit IIS 5 1 0 1 24-bit IIS 6 1 1 0 16-bit MSB first, left justified 7 1 1 1 16-bit DSP frame The following figures illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the different interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded with binary 0s. MSB first, right-justified (for 16, 20, 24 bits) SCLK LRCLK = fs SDIN X MSB LSB Left Channel X MSB Right Channel Figure 7. MSB First Right Justified Note the following characteristics of this protocol. 10 − Left channel is received when LRCLK is high. − Right channel is received when LRCLK is low. − SDIN is sampled at the rising edge of SCLK. www.ti.com LSB 
 SLES017 − SEPTEMBER 2001 functional description (continued) IIS compatible serial format (for 16, 20, 24 bits) SCLK LRCLK = fs SDIN X MSB LSB X Left Channel MSB LSB Right Channel Figure 8. IIS Compatible Serial Format Note the following characteristics of this protocol. − Left channel is received when LRCLK is low. − Right channel is received when LRCLK is high. − SDIN is sampled with the rising edge of the SCLK. MSB left-justified serial interface format (for 16 bits) SCLK LRCLK = fs SDIN MSB LSB MSB Left Channel LSB Right Channel Figure 9. MSB Left-Justified Serial Interface Format Note the following characteristics of this protocol. − Left channel is received when LRCLK is high. − Right channel is received when LRCLK is low. − SDIN is sampled at the rising edge of SCLK. www.ti.com 11 
 SLES017 − SEPTEMBER 2001 functional description (continued) DSP compatible serial interface format (for 16 bits) SCLK LRCLK = fs SDIN 15 14 13 0 15 Left Channel (MSB = 15) 14 13 0 Right Channel (MSB = 15) Figure 10. DSP Compatible Serial Interface Format Note the following characteristic of this protocol. − Serial data is sampled with the falling edge of SCLK. PWM Outputs The TAS5015 is designed to be used with a discrete back-end. The TAS5015 PWM outputs provide differential 3.3-V square-wave signals. During normal operation these outputs represent the input PCM audio in the pulse-width modulation scheme. In the hard-mute state the P outputs (PWM_AP_L, PWM_BP_L, PWM_AP_R, and PWM_BP_R) are held low and the M outputs (PWM_AM_L, PWM_BM_L, PWM_AM_R, and PWM_BM_R) are held high. In the quiet-mute state the differential PWM outputs have a 50% duty cycle. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Analog supply voltage range, AVDD1, AVDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.2 V Digital power supply voltage, DVDD1, DVDD2, DVDD3_L, DVDD3_R . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.2 V Digital input voltage, VI (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDDX + 0.3 V Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 6: DVDD1, DVDD2, DVDD3_L, DVDD3_R. 12 www.ti.com 
 SLES017 − SEPTEMBER 2001 recommended operating conditions, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ±10%, AVDD1 = AVDD2 = 3.3 V ±10%, Fs = 44.1 kHz MIN Supply voltage Digital DVDDX† Analog AVDDX§ Digital Supply current 3 TYP 3.3 Operating 22 Power down‡ 10 Operating Analog Digital Analog UNIT 3.6 V mA µA 20 1 Power down‡ 10 Operating Power dissipation MAX mA Power down‡ 6.6 Operating 3.3 Power down‡ 33 µA 100 59.4 mW µW 72 mW µW 360 † DVDD1, DVDD2, DVDD3_L, DVDD3_R ‡ If the clocks are turned off § AVDD1, AVDD2 electrical characteristics, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ±10%, AVDD1 = AVDD2 = 3.3 V ±10% static digital specifications PARAMETER VIH VIL High-level input voltage VOH VOL High-level output voltage TEST CONDITIONS MIN Low-level input voltage Low-level output voltage IO = −1 mA IO = 4 mA Input leakage current TYP MAX UNIT 2 DVDD1 V 0 0.8 V 2.4 V −10 0.4 V 10 µA digital interpolation filter and PWM modulator, Fs = 44.1 kHz PARAMETER TEST CONDITIONS MIN Pass band Pass-band ripple Stop band Stop-band attenuation TYP 0 24.1 kHz to 152.3 kHz MAX 20 UNIT kHz ±0.012 dB 24.1 kHz 50 dB Group delay 700 µS PWM modulation index (gain) 0.93 dB TAS5015/TAS5110 system performance measured at the speaker terminals See the Design Consideration for TAS5000/TAS5100 True Digital Audio Power Amplifiers application note, Texas Instruments literature number SLAA117 for values. www.ti.com 13 
 SLES017 − SEPTEMBER 2001 switching characteristics, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = AVDD1 = AVDD2 = 3.3 V ±10% serial audio ports slave mode PARAMETER f(SCLK) tsu(SDIN) SCLK frequency th(SDIN) f(LRCLK) SDIN hold time from SCLK rising edge tsu(LRCLK) MIN SDIN setup time before SCLK rising edge TYP MAX UNIT 12.288 MHz 20 ns 10 LRCLK frequency 44.1 ns 48 MCLK duty cycle 50% SCLK duty cycle 50% LRCLK duty cycle 50% LRCLK edge setup before SCLK rising edge 192 20 kHz ns serial audio ports master mode, CL = 50 pF PARAMETER MIN TYP MAX UNIT t(MSD) MCLK to SCLK 0 5 ns t(MLRD) MLCK to LRCLK 0 5 ns DSP serial interface mode PARAMETER f(SCLK) tw(FSHIGH) MIN Pulse duration, sync 1/(64×fs) MAX UNIT 12.288 MHz ns tsu(SDIN), tsu(LRCLK) SDIN and LRCLK setup time before SCLK falling edge 20 ns th(SDIN), th(LRCLK) SDIN and LRCLK hold time from SCLK falling edge 10 ns SCLK duty cycle 14 TYP SCLK frequency 50% www.ti.com 
 SLES017 − SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION SCLK ÎÎÎÎÎÎ ÎÎÎÎÎÎ tsu(SDIN) SDIN th(SDIN) Figure 11. Right-Justified, IIS, Left-Justified Serial Protocol Timing SCLK tsu(LRCLK) LRCLK NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns) Figure 12. Right, Left, and IIS Serial Mode Timing Requirement SCLK LRCLK (Output) t(MSD) t(MLRD) MCLK (Output) Figure 13. Serial Audio Ports Master Mode Timing SCLK th(LRCLK) tsu(LRCLK) LRCLK tw(FSHIGH) tsu(SDIN) SDIN ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ th(SDIN) Figure 14. DSP Serial Port Timing www.ti.com 15 
 SLES017 − SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION SCLK LRCLK tw(FSHIGH) 64 SCLK 16-Bit Left Channel Data SDIN 16-Bit Left Channel Data 32-Bit Ignore 16-Bit Left Channel Data Figure 15. DSP Serial Port Expanded Timing SCLK SDIN th(SDIN) = 10 ns ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ tsu(SDIN) = 20 ns NOTE: Serial data is sampled with the falling edge of SCLK (setup time = 20 ns and hold time = 10 ns) Figure 16. DSP Absolute Timing Requirement 16 www.ti.com 
 SLES017 − SEPTEMBER 2001 APPLICATION INFORMATION TAS5015 PWM_AP_L PWM_AM_L PWM_BP_L PWM_BM_L VALID_L Discrete Back-End RESET DEM_SEL Audio Source Clock Generator 3.3 V DIG DEM_EN DBSPD SDIN LRCLK SCLK MCLK_IN PWM_AP_R PWM_AM_R PWM_BP_R PWM_BM_R VALID_R MOD0 RESET System Controller MOD1 MOD2 External PLL Discrete Back-End RESET M_S MUTE PDN HFCLK FTEST STEST NOTE A: See the Design Consideration for TAS5000/TAS5100 True Digital Audio Power Amplifiers application note, Texas Instruments literature number SLAA117 for values. www.ti.com 17 
 SLES017 − SEPTEMBER 2001 MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°−ā 7° 1,05 0,95 Seating Plane 1,20 MAX 0,75 0,45 0,08 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 18 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TAS5015PFB NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS5015PFBG4 NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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