TM
Data Manual
January 2004
DAV Digital Audio/Speaker
SLES089
Contents
Contents
Section
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Clock and Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1
Normal-Speed, Double-Speed, and Quad-Speed Selection . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2
Clock Master/Slave Mode (M_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3
Clock Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.4
Clock Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.5
PLL External Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.6
DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.7
Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2
Reset, Power Down, and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1
Reset—RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2
Power Down—PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3
General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.4
Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3
Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1
Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.2
Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.3
Automute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.4
Individual Channel Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.5
De-Emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4
Pulse Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.1
Clipping Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.2
Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.3
Individual Channel Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.4
PWM DC-Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.5
Interchannel Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.6
PWM/H-Bridge and Discrete H-Bridge Driver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5
I2C Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5.1
Single-Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5.2
Multiple-Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5.3
Single-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5.4
Multiple-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3
Serial
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Control Interface Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Status Register (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Status Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Register 0 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Register 1 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Recovery Register (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automute Delay Register (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC-Offset Control Registers (0x06−0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1
2
3
4
4
27
27
28
28
29
29
30
30
iii
List of Illustrations
3.8
3.9
4
5
Interchannel Delay Registers (0x0C−0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Individual Channel Mute Register (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
System Procedures for Initialization, Changing Data Rates, and Switching Between Master
and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Data Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Changing Between Master and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
34
37
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Absolute Maximum Ratings Over Operating Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Recommended Operating Conditions (Fs = 48 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1
Static Digital Specifications Over Recommended Operating Conditions . . . . . . . . . . . . . .
5.3.2
Digital Interpolation Filter and PWM Modulator Over Recommended
Operating Conditions (Fs = 48 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3
TAS5066/TAS5110 System Performance Measured at the Speaker
Terminals Over Recommended Operating Conditions (Fs = 48 kHz) . . . . . . . . . . . . . . . . .
5.4
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1
Command Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2
Serial Audio Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.3
Serial Control Port—I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
39
39
39
40
40
40
44
47
6
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Serial Audio Interface Clock Master and Slave Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1
Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2
Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
50
50
50
7
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
39
Appendix A—Volume Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
List of Illustrations
Figure
Title
Page
2−1 Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2−2 PLL External Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2−3 I2S 64-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2−4 I2S 48-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2−5 Left-Justified 64-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2−6 Left-Justified 48-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2−7 Right-Justified 64-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2−8 Right-Justified 48-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2−9 DSP Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2−10 Attenuation Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2−11 De-Emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2−12 PWM Outputs and H-Bridge Driven in BTL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2−13 Typical I2C Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2−14 Single-Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2−15 Multiple-Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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List of Tables
2−16 Single-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−17 Multiple-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 RESET During System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Extending the I2C Write Interval Following Low-to-High Transition of RESET Terminal . . . . . . . . . . . . . . . . .
4−3 Changing the Data Sample Rate Using the DBSPD Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Changing the Data Sample Rate Using the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Changing the Data Sample Rate With an Unstable MCLK_IN Using the DBSPD Terminal . . . . . . . . . . . . . .
4−6 Changing the Data Sample Rate With an Unstable MCLK_IN Using the I2C . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Changing Between Master and Slave Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 Power-Down and Power-Up Timing—RESET Preceding PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−3 Power-Down and Power-Up Timing—RESET Following PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4 Error Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−5 Mute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−6 Right-Justified, I2S, Left-Justified Serial Protocol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−7 Right, Left, and I2S Serial Mode Timing Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8 Serial Audio Ports Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9 DSP Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10 DSP Serial Port Expanded Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 DSP Absolute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 Start and Stop Conditions Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Typical TAS5066 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 TAS5066 Serial Audio Port—Slave Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 TAS5066 Serial Audio Port—Master Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
25
33
34
35
35
36
37
38
40
41
42
43
43
44
45
45
45
46
46
47
47
49
50
50
List of Tables
Table
Title
Page
2−1 Normal-Speed, Double-Speed, and Quad-Speed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2−2 Master and Slave Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2−3 LRCLK and MCLK_IN Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2−4 DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2−5 Supported Word Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2−6 Device Outputs During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2−7 Values Set During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2−8 Device Outputs During Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2−9 Volume Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2−10 De-Emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2−11 Device Outputs During Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3−1 I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3−2 General Status Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3−3 Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3−4 System Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3−5 System Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
January 2004
SLES089
v
List of Tables
3−6 Error Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Automute Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 DC-Offset Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Six Interchannel Delay Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 Individual Channel Mute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
SLES089
29
30
30
30
31
January 2004
Introduction
1
Introduction
The TAS5066 is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse width
modulator (PWM) based on Equibit technology. Combined with a TI PurePath Digital audio amplifier power
stage, these devices use noise-shaping and sophisticated error correction algorithms to achieve high power
efficiency and high-performance digital audio reproduction. The TAS5066 is designed to drive up to six digital
power devices to provide six channels of digital audio amplification. The digital power devices can be six
conventional monolithic power stages (such as TAS5111) or six discrete differential power stages using gate
drivers and MOSFETs.
The TAS5066 has six independent volume controls and mute. The device operates in AD mode. This all-digital
audio system contains only two analog components in the signal chain—an LC low-pass filter at each speaker
terminal and can provide up to 97-dB dynamic range at the speaker terminals. The TAS5066 has a wide variety
of serial input options including right justified (16, 20, or 24 bit), I2S (16, 20, or 24 bit) left justified, or DSP
(16-bit) data formats. The device is fully compatible with AES standard sampling rates of 44.1 kHz, 48 kHz,
88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz including de-emphasis for 44.1-kHz and 48-kHz sample rates. The
TAS5066 was designed for home theater applications such as DVD minicomponent systems, home theater
in a box (HTIB), DVD receiver, A/V receiver, or TV sets.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
TI PurePath Digital Audio Amplifier
High Quality Audio
− 97-dB Dynamic Range
− 5 ms
Volume ramp
up 120 ms
MUTE
Wait a minimum of 100 µs
after the low-to-high
transition of RESET
Set serial interface format, data
rate, volume, ... via I2C
Release ERR_RCVRY and
then MUTE when I2C
registers are programmed
Figure 4−2. Extending the I2C Write Interval Following Low-to-High Transition of RESET Terminal
The operation of the TAS5066 can be tailored as desired to meet specific operating requirements by adjusting
the following:
•
•
•
•
•
•
Volume
Data sample rate
Emphasis/deemphasis settings
Individual channel mute
Automute delay register
DC-offset control registers
If desired, the TAS5066 can be set to perform an unmute sequence following the low-to-high transition of the
ERR_RCVRY terminal or the error recovery I2C command (register X03 bit D2). This capability is set by writing
x7F to the individual error recovery register (x04) and an x84 to x1F (a feature enable register).
4.2
Data Sample Rate
If the master clock is well-behaved during the frequency transition (no MCLK_IN high or low clock periods less
than 20 ns), then a simple speed selection is performed by setting the DBSPD terminal or the serial control
register. If it is known at least 60 ms in advance that the sample rate changes, mute can be used to provide
a completely silent transition. The timing of this control sequence is shown in Figure 4−3 and Figure 4−4.
34
TAS5066
SLES089—January 2004
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Mode
Clock Transition
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
MCLK
> 5 ms
MUTE
Terminal
Volume ramp
down 42 − 65 ms
Volume ramp
up 42 − 65 ms
DBSPD
Terminal
Set within 2 ms
of transition
< 2 ms
< 2 ms
Figure 4−3. Changing the Data Sample Rate Using the DBSPD Terminal
Clock Transition
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
MCLK
> 5 ms
MUTE
Terminal
Volume ramp
down 42 − 65 ms
Volume ramp
up 42 − 65 ms
< 2 ms
< 2 ms
Set data rate via I2C
register 0x02, D7 and D6
ERR_RCVRY
Terminal
Hold ERR_RCVRY low
to give additional timeset registers
Figure 4−4. Changing the Data Sample Rate Using the I2C
However, if the master clock input can encounter a high clock or low clock period of less than 20 ns, then
RESET must be applied during this time. There are two recommended control procedures for this case,
depending upon whether the DBSPD terminal or the serial control interface is used. These control sequences
are shown in Figure 4−5 and Figure 4−6.
Because this sequence employs the RESET terminal, the internal register settings are set to the default
values.
SLES089—January 2004
TAS5066
35
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Mode
Figure 4−5 shows the procedure to change the data rate using the DBSPD terminal and then restore the
register settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization after
RESET is released. This permits the system controller to have as much additional time as necessary to restore
the register settings.
Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system
re-initializes.
Clock unstable during transition.
HIGH and LOW intervals < 20 ns
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
MCLK
> 5 ms
MUTE
Terminal
Volume Ramp
Down 60 ms
Volume Ramp
Up 120 ms
RESET
Terminal
DBSPD
Terminal
Wait a minimum of
100 µs to set DBSPD
< 2 ms
ERR_RCVRY
Terminal
Release ERR_RCVRY and
then MUTE when I2C
registers are programmed
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100 µs after the
LOW to HIGH transition of RESET
Restore register
settings via I2C
Figure 4−5. Changing the Data Sample Rate With an Unstable MCLK_IN Using the DBSPD Terminal
Because this sequence employs the RESET terminal, the internal register settings are set to the default
values.
Figure 4−5 shows the procedure to change the data rate using Register X02 D7 and D6 and then restore the
other register settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization
after RESET is released. This permits the system controller to have as much additional time as necessary to
restore the register settings.
Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system
re-initializes.
36
TAS5066
SLES089—January 2004
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Mode
Clock unstable during transition.
HIGH and LOW intervals < 20 ns
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
MCLK
> 5 ms
MUTE
Terminal
Volume Ramp
Down 60 ms
Volume Ramp
Up 120 ms
RESET
Terminal
< 2 ms
ERR_RCVRY
Terminal
Release ERR_RCVRY and
then MUTE when I2C
registers are programmed
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100 µs after the
LOW to HIGH transition of RESET
Set data rate and
restore other
register settings
via I2C
Figure 4−6. Changing the Data Sample Rate With an Unstable MCLK_IN Using the I2C
4.3
Changing Between Master and Slave Modes
The master and slave mode is set while the RESET terminal is active. Because this sequence employs the
RESET terminal the internal register settings are set to the default values.
Figure 4−7 shows the procedure to switch between master and slave modes and then restore the register
settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization after RESET
is released. This permits the system controller to have as much additional time as necessary to restore the
register settings.
Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system
re-initializes.
SLES089—January 2004
TAS5066
37
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Mode
Clock unstable during transition.
Change from Master Mode
Change to Slave Mode
MCLK
> 5 ms
MUTE
Terminal
Volume Ramp
Down 60 ms
Volume Ramp
Up 120 ms
RESET
Terminal
M_S
Terminal
Wait a minimum of
100 µs to set M_S
< 2 ms
ERR_RCVRY
Terminal
Release ERR_RCVRY and
then MUTE when I2C
registers are programmed
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100 µs after the
LOW to HIGH transition of RESET
Restore register
settings via I2C
Figure 4−7. Changing Between Master and Slave Clock Mode
38
TAS5066
SLES089—January 2004
Specifications
5
Specifications
5.1
Absolute Maximum Ratings Over Operating Temperature Ranges (Unless
Otherwise Noted)†
Digital supply voltage range: DVDD_CORE, DVDD_PWM, DVDD_RCL . . . . . . . . . . . . . . . . . . −0.3 V to 4.2 V
Analog supply voltage range: AVDD_PLL, ADD_OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.2 V
Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDDX + 0.3 V
Operating free-air temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2
Recommended Operating Conditions
Supply voltage
Digital
Supply current
Digital
MIN
TYP
MAX
3
3.3
3.6
DVDDX, See Note 1
Operating
83
Power down, See Note 2
Power dissipation
Digital
Supply voltage
Analog
Supply current
Analog
Power dissipation
Analog
200
Power down
3
3.3
3.6
8
Power down, See Note 2
35
Power down, See Note 2
µW
V
mA
25
Operating
µA
mW
100
AVDDX, See Note 3
Operating
V
mA
25
Operating
UNIT
µA
mW
100
µW
NOTES: 3. DVDD_CORE, DVDD_PWM, DVDD_RCL
4. If the clocks are turned off.
5. AVDD_PLL, AVDD_OSC
5.3
Electrical Characteristics Over Recommended Operating Conditions
5.3.1
Static Digital Specifications Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VIH
VIL
High-level input voltage
2
DVDD1
V
Low-level input voltage
0
0.8
V
VOH
VOL
High-level output voltage
Ilkg
Input leakage current
Low-level output voltage
5.3.2
IO = −1 mA
IO = 4 mA
2.4
−10
V
0.4
V
10
µA
Digital Interpolation Filter and PWM Modulator Over Recommended Operating
Conditions (Unless Otherwise Noted) (Fs = 48 kHz)
PARAMETER
TEST CONDITIONS
Pass band
MIN
Pass band ripple
Stop band
Stop band attenuation
Group delay
PWM modulation index (gain)
SLES089—January 2004
TYP
0
24.1 kHz to 152.3 kHz
MAX
20
UNIT
kHz
±0.012
dB
24.1
kHz
50
dB
µs
700
0.93%
TAS5066
39
Specifications
5.3.3
TAS5066/TAS5110 System Performance Measured at the Speaker Terminals
Over Recommended Operating Conditions (Unless Otherwise Noted)
(Fs = 48 kHz)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SNR (EIAJ)
A-weighted
93
dB
Dynamic range
A-weighted, -60 dB, f = 1 kHz, 20 Hz−20 kHz
97
dB
5.4
Switching Characteristics
5.4.1
Command Sequence Timing
5.4.1.1
Reset Timing—RESET
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER
TEST CONDITIONS
tw(RESET)
Pulses duration, RESET active
tp(VALID_LOW)
tp(VALID_HIGH)
Propagation delay
td(VOLUME)
Delay time
MIN
TYP
MAX
50
Propagation delay
UNIT
ns
1
µs
4
5
ms
42
65
ms
RESET
tw(RESET)
VALID 1−6
VOLUME 1−6
tp(VALID_LOW)
td(VOLUME)
tp(VALID_HIGH)
Figure 5−1. RESET Timing
40
TAS5066
SLES089—January 2004
Specifications
5.4.1.2
Power-Down Timing—PDN
5.4.1.2.1 Long Recovery
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER
tw(PDN)
Pulse duration, PDN active
td(R PDNR)
tp(VALID_LOW)
Reset high to PDN rising edge
TEST CONDITIONS
MIN
TYP
MAX
50
UNIT
ns
16 MCLKS
ns
1
µs
tp(VALID_HIGH)
85
100
ms
td(VOLUME)
42
65
ms
td(R PDNR)
RESET
PDN
tw(PDN)
VALID 1−6
VOLUME 1−6
Normal
Operation
Normal
Operation
tp(VALID_HIGH)
tp(VALID_LOW)
td(VOLUME)
Figure 5−2. Power-Down and Power-Up Timing—RESET Preceding PDN
SLES089—January 2004
TAS5066
41
Specifications
5.4.1.2.2 Short Recovery
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER
tw(PDN)
Pulse duration, PDN active
td(R PDNR)
tp(VALID_LOW)
PDN high to reset rising edge
TEST CONDITIONS
MIN
TYP
MAX
50
ns
16 MCLKs
ns
1
µs
4
5
ms
42
65
ms
tp(VALID_HIGH)
td(VOLUME)
UNIT
td(R PDNR)
RESET
PDN
tw(PDN)
VALID 1−6
VOLUME 1−6
Normal
Operation
Normal
Operation
tp(VALID_HIGH)
tp(VALID_LOW)
td(VOLUME)
Figure 5−3. Power-Down and Power-Up Timing—RESET Following PDN
42
TAS5066
SLES089—January 2004
Specifications
5.4.1.3
Error Recovery Timing—ERR_RCVRY
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(ER)
Pulse duration, ERR_RCVRY active
5 MCLKs
tp(VALID_LOW)
tp(VALID_HIGH)
Selectable for minimum or maximum
6
47
µs
ns
4
5
ms
tw(ER)
ERR_RCVRY
VALID 1−6
Normal
Operation
Normal
Operation
tp(VALID_HIGH)
tp(VALID_LOW)
Figure 5−4. Error Recovery Timing
5.4.1.4
MUTE Timing—MUTE
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER
tw(MUTE)
td(VOL)
TEST CONDITIONS
Pulse duration, PDN active
MIN
TYP
MAX
3 MCLKS
UNIT
ns
42
ms
tw(MUTE)
MUTE
VOLUME
VALID 1−6
Normal
Operation
Normal
Operation
td(VOL)
td(VOL)
Figure 5−5. Mute Timing
SLES089—January 2004
TAS5066
43
Specifications
5.4.2 Serial Audio Port
5.4.2.1
Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
f(SCLK)
tsu(SDIN)
Frequency, SCLK
SDIN setup time before SCLK rising edge
20
th(SDIN)
f(LRCLK)
SDIN hold time before SCLK rising edge
10
LRCLK frequency
32
tsu(LRCLK)
5.4.2.2
TYP
MAX
UNIT
12.288
MHz
ns
ns
48
MCLK_IN duty cycle
50%
SCLK duty cycle
50%
LRCLK duty cycle
50%
192
kHz
LRCLK setup time before SCLK rising edge
20
ns
MCLK high and low time
20
ns
Serial Audio Ports Master Mode, Load Conditions 50 pF Over Recommended
Operating Conditions (Unless Otherwise Noted)
PARAMETER
t(MSD)
t(MLRD)
5.4.2.3
MIN
TYP
MAX
UNIT
MCLK_IN to SCLK
0
5
ns
MCLK_IN to LRCLK
0
5
ns
DSP Serial Interface Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
f(SCLK)
td(FS)
SCLK frequency
tw(FSHIGH)
tsu(SDIN)
Pulse duration, sync
SDIN and LRCLK setup time before SCLK falling edge
20
th(SDIN)
SDIN and LRCLK hold time from SCLK falling edge
10
TYP
Delay time, SCLK rising to Fs
MAX
UNIT
12.288
MHz
ns
1/(64×Fs)
SCLK duty cycle
ns
ns
ns
50%
SCLK
th(SDIN)
tsu(SDIN)
SDIN
Figure 5−6. Right-Justified, I2S, Left-Justified Serial Protocol Timing
44
TAS5066
SLES089—January 2004
Specifications
SCLK
tsu(LRCLK)
LRCLK
NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns).
Figure 5−7. Right, Left, and I2S Serial Mode Timing Requirement
SCLK
LRCLK
t(MRLD)
t(MSD)
MCLK
Figure 5−8. Serial Audio Ports Master Mode Timing
SCLK
tsu(LRCLK)
th(LRCLK)
LRCLK
tw(FSHIGH)
tsu(SDIN)
th(SDIN)
SDIN
Figure 5−9. DSP Serial Port Timing
SLES089—January 2004
TAS5066
45
Specifications
SCLK
64 SCLKS
LRCLK
tw(FSHIGH)
SDIN
16 Bits
Left
Channel
16 Bits
Right
Channel
32 Bits Unused
Figure 5−10. DSP Serial Port Expanded Timing
SCLK
tsu(SDIN) = 20 ns
th(SDIN) = 10 ns
SDIN
Figure 5−11. DSP Absolute Timing
46
TAS5066
SLES089—January 2004
Specifications
5.4.3 Serial Control Port—I 2C Operation
5.4.3.1
Timing Characteristics for I2C Interface Signals Over Recommended Operating
Conditions (Unless Otherwise Noted)
PARAMETER
fSCL
tw(H)
Frequency, SCL
tw(L)
tr
Pulse duration, SCL low
tf
tsu1
Fall time, SCL and SDA
th1
t(buf)
Hold time, SCL to SDA
tsu2
th2
tsu3
CL
STANDARD
MODE
TEST CONDITIONS
FAST MODE
MIN
MAX
MIN
MAX
0
100
0
400
Pulse duration, SCL high
4
0.6
4.7
1.3
Rise time, SCL and SDA
1000
300
Setup time, SDA to SCL
UNIT
kHz
µs
µs
300
ns
300
ns
250
100
ns
0
0
ns
Bus free time between stop and start condition
4.7
1.3
µs
Setup time, SCL to start condition
4.7
0.6
µs
Hold time, start condition to SCL
4
0.6
µs
Setup time, SCL to stop condition
4
0.6
Load capacitance for each bus line
400
tw(H)
tw(L)
tr
µs
400
pF
tf
SCLK
tsu
th1
SDA
Figure 5−12. SCL and SDA Timing
SCLK
th2
t(buf)
tsu2
tsu3
Start Condition
Stop Condition
SDA
Figure 5−13. Start and Stop Conditions Timing
SLES089—January 2004
TAS5066
47
Specifications
48
TAS5066
SLES089—January 2004
SLES089—January 2004
MSP430
P1.3
P2.0
P1.0
P1.1
P1.2
P1.4/SMCLK/TCK
P1.5/IA1/TDI
ALKX1
ALKX2
ALKX0
ACLKX
AFSX
DA610
DSP
CLKOUT
MCLK_IN
MUTE
ERR_RCVRY
CLIP
PDN
RESET
SDA
SCL
CSO
DM_SEL1
DM_SEL2
DBSPD
MCLKOUT
SDIN1
SDIN2
SDIN3
SCLK
LRCLK
PLL_FLT_2
PLL_FLT_1
M_S
XTAL_OUT
XTAL_IN
AVDD_PLL
Reset,
Pwr Dwn
and
Status
Serial
Control
I/F
Clock,
PLL
and
Serial
Data
I/F
DVDD_PWM
DVSS_RCL
VREGC_CAP
DVDD_RCL
Auto Mute
De-Emphasis
Soft Volume
Error Recovery
Soft Mute
Clip Detect
Signal
Processing
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM
Section
TAS5110
PWAP
H-Bridge
PWAM
PWBM
PWBP SHUTDOWN
RESET
PWM_AP_6
PWM_AM_6
VALID_6
VALID_5
TAS5110
PWAP
H-Bridge
PWAM
PWBM
PWBP SHUTDOWN
RESET
TAS5110
PWAP
H-Bridge
PWAM
PWBM
PWBP SHUTDOWN
RESET
TAS5110
PWAP
H-Bridge
PWAM
PWBM
PWBP SHUTDOWN
RESET
TAS5110
PWAP
H-Bridge
PWAM
PWBM
PWBP SHUTDOWN
RESET
TAS5110
PWAP
H-Bridge
PWAM
PWBM
PWBP SHUTDOWN
RESET
PWM_AP_5
PWM_AM_5
PWM_AM_4
VALID_4
PWM_AP_4
VALID_3
PWM AP_3
PWM AM_3
VALID_2
PWM_AM_2
PWM_AP_2
PWM_AM_1
VALID_1
PWM_AP_1
6
VREGB_CAP
VREGA_CAP
Power Supply
Application Information
Application Information
Figure 6−1. Typical TAS5066 Application
TAS5066
49
Output Control
DVSS_PWM
AVSS_PLL
Application Information
6.1
Serial Audio Interface Clock Master and Slave Interface Configuration
6.1.1 Slave Configuration
Other Digital
Audio Sources
DA610 DSP
(Master Mode)
PCM1800
ADC
Left
Analog
OSCI
ALKR0
DOUT
Right
Analog
BCK
SYSCLK
GND
TAS5066
(Slave Mode)
XTALI
OSCO
XTALO
ALKX0
SDIN1
ALKR1
ALKX1
SDIN2
ALKR2
ALKX2
SDIN3
ACLKR
ACLKX
SCLK
AFSX
LRCK
AFSR
LRCK
12.288
MHz XTAL
CLKIN
MCLKO
CLKOUT
MCLKO
NC
Figure 6−2. TAS5066 Serial Audio Port—Slave Mode Connection Diagram
6.1.2 Master Configuration
Other Digital
Audio Sources
TAS5066
(Master Mode)
DA610 DSP
PCM1800
ADC
Left
Analog
12.288
MHz XTAL
DOUT
Right
Analog
BCK
LRCK
SYSCLK
ALKR0
XTALI
XTALO
ALKX0
SDIN1
ALKR1
ALKX1
SDIN2
ALKR2
ALKX2
SDIN3
ACLKR
ACLKX
SCLK
AFSX
LRCK
AFSR
CLKIN
CLKOUT
GND
MCLKO
MCLKO
Figure 6−3. TAS5066 Serial Audio Port—Master Mode Connection Diagram
50
TAS5066
SLES089—January 2004
Mechanical Data
7
Mechanical Data
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
10,20
SQ
9,80
12,20
SQ
11,80
Gage Plane
0,25
0,05 MIN
1,05
0,95
0°−ā 7°
0,75
0,45
Seating Plane
1,20 MAX
0,08
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
SLES089—January 2004
TAS5066
51
Mechanical Data
52
TAS5066
SLES089—January 2004
Appendix A—Volume Table
Appendix A—Volume Table
VOLUME
SETTING
REGISTER VOLUME
(BIN)
GAIN dB
VOLUME
SETTING
REGISTER VOLUME
(BIN)
249
1111 1001
24
205
1100 1101
2
248
1111 1000
23.5
204
1100 1100
1.5
247
1111 0111
23
203
1100 1011
1
246
1111 0110
22.5
202
1100 1010
0.5
245
1111 0101
22
201
1100 1001
0
244
1111 0100
21.5
200
1100 1000
−0.5
D7 − D0
GAIN dB
D7 − D0
243
1111 0011
21
199
1100 0111
−1
242
1111 0010
20.5
198
1100 0110
−1.5
241
1111 0001
20
197
1100 0101
−2
240
1111 0000
19.5
196
1100 0100
−2.5
239
1110 1111
19
195
1100 0011
−3
238
1110 1110
18.5
194
1100 0010
−3.5
237
1110 1101
18
193
1100 0001
−4
236
1110 1100
17.5
192
1100 0000
−4.5
235
1110 1011
170
191
1011 1111
−5
234
1110 1010
16.5
190
1011 1110
−5.5
233
1110 1001
16
189
1011 1101
−6
232
1110 1000
15.5
188
1011 1100
−6.5
231
1110 0111
15
187
1011 1011
−7
230
1110 0110
14.5
186
1011 1010
−7.5
229
1110 0101
14
185
1011 1001
−8
228
1110 0100
13.5
184
1011 1000
−8.5
227
1110 0011
13
183
1011 0111
−9
226
1110 0010
12.5
182
1011 0110
−9.5
225
1110 0001
12
181
1011 0101
−10
224
1110 0000
11.5
180
1011 0100
−10.5
223
1101 1111
11
179
1011 0011
−11
222
1101 1110
10.5
178
1011 0010
−11.5
221
1101 1101
10
177
1011 0001
−12
220
1101 1100
9.5
176
1011 0000
−12.5
219
1101 1011
9
175
1010 1111
−13
218
1101 1010
8.5
174
1010 1110
−13.5
217
1101 1001
8
173
1010 1101
−14
216
1101 1000
7.5
172
1010 1100
−14.5
215
1101 0111
7
171
1010 1011
−15
214
1101 0110
6.5
170
1010 1010
−15.5
213
1101 0101
6
169
1010 1001
−16
212
1101 0100
5.5
168
1010 1000
−16.5
211
1101 0011
5
167
1010 0111
−17
210
1101 0010
4.5
166
1010 0110
−17.5
209
1101 0001
4
165
1010 0101
−18
208
1101 0000
3.5
164
1010 0100
−18.5
207
1100 1111
3
163
1010 0011
−19
206
1100 1110
2.5
162
1010 0010
−19.5
SLES089—January 2004
TAS5066
53
Appendix A—Volume Table
VOLUME
SETTING
REGISTER VOLUME
(BIN)
GAIN dB
VOLUME
SETTING
REGISTER VOLUME
(BIN)
161
1010 0001
−20
116
0111 0100
160
−42.5
1010 0000
−20.5
115
0111 0011
−43
D7 − D0
54
GAIN dB
D7 − D0
159
1001 1111
−21
114
0111 0010
−43.5
158
1001 1110
−21.5
113
0111 0001
−44
157
1001 1101
−22
112
0111 0000
−44.5
156
1001 1100
−22.5
111
0110 1111
−45
−45.5
155
1001 1011
−23
110
0110 1110
154
1001 1010
−23.5
109
0110 1101
−46
153
1001 1001
−24
108
0110 1100
−46.5
152
1001 1000
−24.5
107
0110 1011
−47
151
1001 0111
−25
106
0110 1010
−47.5
150
1001 0110
−25.5
105
0110 1001
−48
149
1001 0101
−26
104
0110 1000
−48.5
148
1001 0100
−26.5
103
0110 0111
−49
147
1001 0011
−27
102
0110 0110
−49.5
146
1001 0010
−27.5
101
0110 0101
−50
145
1001 0001
−28
100
0110 0100
−50.5
144
1001 0000
−28.5
99
0110 0011
−51
143
1000 1111
−29
98
0110 0010
−51.5
142
1000 1110
−29.5
97
0110 0001
−52
141
1000 1101
−30
96
0110 0000
−52.5
140
1000 1100
−30.5
95
0101 1111
−53
139
1000 1011
−31
94
0101 1110
−53.5
138
1000 1010
−31.5
93
0101 1101
−54
137
1000 1001
−32
92
0101 1100
−54.5
136
1000 1000
−32.5
91
0101 1011
−55
135
1000 0111
−33
90
0101 1010
−55.5
134
1000 0110
−33.5
89
0101 1001
−56
133
1000 0101
−34
88
0101 1000
−56.5
132
1000 0100
−34.5
87
0101 0111
−57
131
1000 0011
−35
86
0101 0110
−57.5
130
1000 0010
−35.5
85
0101 0101
−58
129
1000 0001
−36
84
0101 0100
−58.5
128
1000 0000
−36.5
83
0101 0011
−59
−59.5
127
0111 1111
−37
82
0101 0010
126
0111 1110
−37.5
81
0101 0001
−60
125
0111 1101
−38
80
0101 0000
−60.5
124
0111 1100
−38.5
79
0100 1111
−61
123
0111 1011
−39
78
0100 1110
−61.5
122
0111 1010
−39.5
77
0100 1101
−62
121
0111 1001
−40
76
0100 1100
−62.5
120
0111 1000
−40.5
75
0100 1011
−63
119
0111 0111
−41
74
0100 1010
−63.5
118
0111 0110
−41.5
73
0100 1001
−64
117
0111 0101
−42
72
0100 1000
−64.5
TAS5066
SLES089—January 2004
Appendix A—Volume Table
VOLUME
SETTING
REGISTER VOLUME
(BIN)
71
0100 0111
−65
36
0010 0100
70
0100 0110
−65.5
35
0010 0011
−83
69
0100 0101
−66
34
0010 0010
−83.5
68
0100 0100
−66.5
33
0010 0001
−84
0010 0000
−84.6
GAIN dB
VOLUME
SETTING
D7 − D0
REGISTER VOLUME
(BIN)
GAIN dB
D7 − D0
−82.6
67
0100 0011
−67
32
66
0100 0010
−67.5
31
0001 1111
−85.1
−68
30
0001 1110
−85.8
29
0001 1101
−86.1
28
0001 1100
−86.8
27
0001 1011
−87.2
26
0001 1010
−87.5
25
0001 1001
−88.4
24
0001 1000
−88.8
65
0100 0001
64
0100 0000
−68.5
63
0011 1111
−69
62
0011 1110
−69.5
61
0011 1101
−70
60
0011 1100
−70.5
59
0011 1011
−71
23
0001 0111
−89.3
58
0011 1010
−71.5
22
0001 0110
−89.8
57
0011 1001
−72
21
0001 0101
−90.3
56
0011 1000
−72.5
20
0001 0100
−90.9
55
0011 0111
−73
19
0001 0011
−91.5
54
0011 0110
−73.5
18
0001 0010
−92.1
53
0011 0101
−74
17
0001 0001
−92.8
0001 0000
−93.6
52
0011 0100
−74.5
16
51
0011 0011
−75
15
0000 1111
−94.4
0000 1110
−95.3
50
0011 0010
−75.5
14
49
0011 0001
−76
13
0000 1101
−96.3
12
0000 1100
−97.5
11
0000 1011
−98.8
10
0000 1010
−100.4
9
0000 1001
−102.4
8
0000 1000
−104.9
7
0000 0111
−108.4
6
0000 0110
−114.4
48
0011 0000
−76.6
47
0010 1111
−77
46
0010 1110
−77.5
45
0010 1101
−78
44
0010 1100
−78.5
43
0010 1011
−79
42
0010 1010
−79.6
5
0000 0101
MUTE
41
0010 1001
−80.1
4
0000 0100
MUTE
40
0010 1000
−80.6
3
0000 0011
MUTE
39
0010 0111
−81.1
2
0000 0010
MUTE
38
0010 0110
−81.5
1
0000 0001
MUTE
37
0010 0101
−82.1
0
0000 0000
MUTE
SLES089—January 2004
TAS5066
55
Appendix A—Volume Table
56
TAS5066
SLES089—January 2004
PACKAGE OPTION ADDENDUM
www.ti.com
1-Aug-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TAS5066PAG
NRND
TQFP
PAG
64
TBD
Call TI
Call TI
TAS5066PAGG4
NRND
TQFP
PAG
64
TBD
Call TI
Call TI
TAS5066PAGR
NRND
TQFP
PAG
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
TAS5066PAGRG4
NRND
TQFP
PAG
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5066PAGR
Package Package Pins
Type Drawing
TQFP
PAG
64
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
1500
330.0
24.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
13.0
1.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5066PAGR
TQFP
PAG
64
1500
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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