TAS5086
www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
PurePath Digital™ AUDIO SIX-CHANNEL PWM PROCESSOR
FEATURES
1
• Audio Input/Output
– Automatic Master Clock Rate and Data
Sample Rate Detection
– Four Serial Audio Inputs (Eight Channels)
– Support for 32-, 44.1-, 48-, 88.2-, 96-, 176.4-,
and 192-kHz Sampling Rates
– Data Formats: 16-, 20-, or 24-Bit Input Data;
Left-Justified, Right-Justified, and I2S
– 64- or 48-fS Bit-Clock Rate
– 128-, 192-, 256-, 384-, and 512-fS Master
Clock Rates (Up to a Maximum of 50 MHz)
– Six PWM Audio Output Channels
– Any Output Channel Can be Mapped to Any
Output Pin
– Supports Single-Ended and Bridge-Tied
Loads
– I2S Serial Audio Output
• Audio Processing
– Volume Control Range of 48 dB to –100 dB
– Master Volume Control from 24 dB to –100
dB in 0.5-dB Increments
– Six Individual Channel Volume Controls
With 24-dB to –100-dB Attenuation in
0.5-dB Increments
– Serial Output Can Be Produced by
Downmix of 5.1-Channel Input or Fourth
Serial Input
– 5.1-Channel Downmix to 2.1 or 3.1 PWM
Output Speaker System
– Integrated Bass Management
– Two Programmable Biquads in Subwoofer
Channel
23
•
•
– Full Six-Channel Input and Output Mapping
– Selectable DC Blocking Filters
PWM Processing
– 8× Oversampling With Fourth-Order Noise
Shaping at 44.1, 48 kHz; 4× Oversampling
at 88.2, 96 kHz; 2× Oversampling at 176.4,
192 kHz; and 12× Oversampling at 32 kHz
– ≥105-dB Dynamic Range
(TAS5086+TAS5186)
– THD < 0.06% (TAS5086 Only)
– 20-Hz–20-kHz Flat Noise Floor for 44.1-, 48-,
88.2-, 96-, 176.4- and 192-kHz Data Rates
– Digital De-Emphasis for 32-kHz, 44.1-kHz
and 48-kHz Data Rates
– Intelligent AM Interference Avoidance
System Provides Clear AM Reception
– Optimized PWM Sequence for Click- and
Popless Start and Stop
– Optimized PWM Sequence for Charging of
AC-Coupling Capacitors in Single-Ended
Configurations
– Adjustable Modulation Limit From 93.8% to
99.2%
General Features
– Automated Operation With Easy-to-Use
Control Interface
– I2C Serial Control Slave Interface
– Control Interface Operational Without
MCLK
– Single 3.3-V Power Supply
– 38-Pin TSSOP Package
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated
TAS5086
SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The TAS5086 is a six-channel digital pulse-width modulator (PWM) that provides both advanced performance
and a high level of system integration. The TAS5086 is designed to interface seamlessly with most audio digital
signal processors and MPEG decoders, accepting a wide range of input data and clock formats.
The TAS5086 drives six channels of speakers in either single-ended or bridge-tied load configurations that
accept a 1N + 1 interface format. The TAS5086 also supports 2N + 1 power stages with the use of some
external logic (e.g., TAS5112). Stereo line out in I2S format is available with either a pass-through signal (SDIN4)
or an internal downmix.
The TAS5086 uses AD modulation operating at a 384-kHz switching rate for 32-, 44.1-, 48-, 88.2-, 96-, 176.4-,
and 192-kHz data. The 8× oversampling, combined with the 4th-order noise shaper, provides a broad, flat noise
floor and excellent dynamic range from 20 Hz to 20 kHz.
The TAS5086 is only an I2C slave device, which always receives MCLK, SCLK, and LRCLK from other system
components. The TAS5086 accepts clock rates of 128, 192, 256, 384, and 512 fS. The TAS5086 accepts a 64-fS
master clock for 176.4-kHz and 192-kHz data.
The TAS5086 accepts a 64-fS bit clock for all data rates. The TAS5086 also can accept a 48-fS SCLK rate for
MCLK ratios of 192 fS and 384 fS.
The TAS5086 is composed of five functional blocks.
• Power supply
• Clock, PLL, and serial data interface
• Serial control interface
• Device control
• PWM section
For detailed application information, see the Using the PurePath Digital PWM Processor application report
(SLEA046).
Figure 1 shows the functional structure of the TAS5086.
2
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DVDD
DVSS
DVSS_ESD
VR_DIG
VR_ANA
VR_OSC
AVDD
AVSS_PLL
VREG_EN
SDIN1
SDIN2
SDIN3
SDIN4
1 LF
Power
Supply
SCL
MUX
PWM1
MUX
PWM2
MUX
PWM3
MUX
PWM4
MUX
PWM5
MUX
PWM6
6
Serial
Data
Interface
R’
Chan.
1−6
MUX
MUX
6
3 LS
Ch
1−6
1−5
Channel
Selector
Block
1− 5
Clock Rate
/Error
Detection
and PLL
Down−
mix
L’
Vol
4 RS
PWM
6
R’
5C
(L’+R’)/2
1− 6
SDA
6
MUX
2 RF
SDIN4
MCLK
SCLK
LRCLK
PLLFLTP
PLLFLTM
HFCLK
OSCFLT
OSC_RES
L’
(L’+R’) / 2
6
MUX
6
Channel Six Processing
Bass Management
Serial
Control
Interface
PWM
Control
RESET
PDN
MUTE
BKNDERR
VALID1
VALID2
Downmix
System
Control
SDIN4
MUX
I2S Serial
Output
SDOUT
B0080-01
Figure 1. TAS5086 Functional Block Diagram
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TAS5086
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
Input voltage
DVDD and DVD_ESD
–0.3 V to 3.6 V
AVDD
–0.3 V to 3.6 V
3.3-V-digital input
–0.5 V to DVDD + 0.5 V
5-V-tolerant (2) digital input
–0.5 V to 6 V
Input clamp current, IIK (VI < 0 or VI > 1.8 V)
±20 mA
Output clamp current, IOK (VO < 0 or VO > 1.8 V)
±20 mA
Operating free-air temperature
0°C to 70°C
Storage temperature range, Tstg
(1)
(2)
–65°C to 150°C
Stresses beyond those listed under “absolute ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operation conditions”
are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are RESET, PDN, MUTE, SCLK, LRCLK, MCLK, SDA, and SCL.
DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DBT
817.16 mW
10.214 mW/C
357.5 mW
204.29 mW
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Digital supply voltage
DVDD
3
3.3
3.6
V
3.3
3.6
V
Analog supply voltage
AVDD
3
VIH
High-level input voltage
3.3-V TTL, 5-V tolerant
2
VIL
Low-level input voltage
3.3-V TTL, 5-V tolerant
TA
Operating ambient-air temperature range
UNIT
V
0
25
0.8
V
70
°C
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
VOH
High-level output voltage
3.3-V TTL and 5-V
VOL
Low-level output voltage
3.3-V TTL and 5-V (1) tolerant
tolerant
IOZ
High-impedance output current
3.3-V TTL
IIL
Low-level input current
IIH
High-level input current
4
MAX
2.4
0.5
V
20
µA
VI = VIL
1
VI = 0 V, DVDD = 3 V
1
3.3-V TTL
VI = VIH
5-V tolerant (2)
VI = 5.5 V, DVDD = 3 V
Input supply current
1
20
fS = 48 kHz
140
fS = 96 kHz
150
fS = 192 kHz
155
Power down
Normal
Power down
UNIT
V
IOL = 4 mA
5-V tolerant (2)
Analog supply voltage, AVDD
(1)
(2)
TYP
3.3-V TTL
Digital supply voltage, DVDD
IDD
IOH = –4 mA
MIN
µA
µA
mA
8
20
2
mA
5-V-tolerant outputs are SCL and SDA
5-V-tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
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Serial Audio Port
Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER
fSCLKIN SCLK input frequency
TEST CONDITIONS
MIN
CL = 30 pF, SCLK = 64 fS
2.048
TYP
MAX
UNIT
12.288
MHz
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
LRCLK frequency
32
48
192
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
64
64
SCLK
edges
–1/4
1/4
SCLK
period
SCLK rising edges between LRCLK rising edges
LRCLK clock edge with respect to the falling edge of
SCLK
ns
kHz
SCLK
(Input)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN1
SDIN2
SDIN3
T0026-01
Figure 2. Slave Mode Serial Data Interface Timing
TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus
Devices
PARAMETER
TEST CONDITIONS
STANDARD MODE
MIN
MAX
VIL
LOW-level input voltage
–0.5
VIH
HIGH-level input voltage
0.7 VDD
Vhys
Hysteresis of Schmitt-trigger inputs
VOL1
LOW-level output voltage (open drain or
open collector)
3-mA sink current
tof
Output fall time from VIHmin to VILmax
Bus capacitance from 10 pF
to 400 pF
tSP
Pulse duration of spikes suppressed
Ii
Input current, each I/O pin
Ci
Capacitance, each I/O pin
(1)
(2)
(3)
N/A
(2)
0.3 VDD
N/A
250
FAST MODE
MIN
MAX
–0.5
0.3 VDD
UNIT
V
0.7 VDD
V
0.05 VDD
V
0
0.4
V
7 + 0.1 Cb
250
ns
(1)
N/A
N/A
0
30
ns
–30
30
–30 (3)
30 (3)
µA
10
pF
10
2
Cb = capacitance of one bus line in pF. The output fall time is faster than the standard I C specification.
SCL and SDA have a 30-ns glitch filter.
The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if VDD is switched off.
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TAS5086
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TAS5086 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus
Devices
All values are referred to VIHmin and VILmax (see TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for
F/S-Mode I2C-Bus Devices).
A
PARAMETER
TEST CONDITIONS
STANDARD MODE
MIN
FAST MODE
MAX
MIN
MAX
100
0
400
UNIT
fSCL
SCL clock frequency
0
kHz
tHD-STA
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
4
0.6
µs
tLOW
LOW period of the SCL clock
4.7
1.3
µs
tHIGH
HIGH period of the SCL clock
4
0.6
µs
tSU-STA
Setup time for repeated START
4.7
0.6
µs
tSU-DAT
Data setup time
250
100
µs
tHD-DAT
Data hold time
3.45
0
0.9
µs
tr
Rise time of both SDA and SCL
1000
7 + 0.1 Cb (3)
500 (4)
ns
tf
Fall time of both SDA and SCL
300
7 + 0.1 Cb (3)
300
ns
tSU-STO
Setup time for STOP condition
tBUF
Bus free time between a STOP and
START condition
Cb
Capacitive loads for each bus line
VnL
Noise margin at the LOW level for each
connected device (including hysteresis)
0.1 VDD
0.1 VDD
V
VnH
Noise margin at the HIGH level for each
connected device (including hysteresis)
0.2 VDD
0.2 VDD
V
(1)
(2)
(3)
(4)
(1) (2)
0
4
0.6
µs
4.7
1.3
µs
400
400
pF
Note that SDA does not have the standard I2C specification 300-ns hold time and that SDA must be valid by the rising and falling edges
of SCL. TI recommends that a 3.3-kΩ pullup resistor be used to avoid potential timing issues.
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU-DAT ≥ 250 ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tr-max + tSU-DAT = 1000 + 250 = 1250 ns (according to the
standard-mode I2C bus specification) before the SCL line is released.
Cb = total capacitance of one bus line in pF.
Rise time varies with pullup resistor.
SDA
tf
tSU-DAT
tHD-STA
tLOW
tr
tr
tSP
tBUF
tf
SCL
tHD-DAT
tSU-STA
tHD-STA
tSU-STO
tHIGH
S
Sr
P
S
T0114-01
Figure 3. Start and Stop Conditions Timing Waveforms
6
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Recommended I2C Pullup Resistors
It is recommended that the I2C pullup resistors RP be 3.3 kΩ (see Figure 4). If a series resistor is in the circuit
(see Figure 5), then the series resistor RS should be less than or equal to 300 Ω.
5V
TAS5086
External
Microcontroller
IP
RP
SDA
SCL
IP
RP
VI(SDA)
VI(SCL)
B0099-05
2
Figure 4. I C Pullup Circuit (With No Series Resistor)
5V
TAS5086
External
Microcontroller
RP
SDA
or
SCL
VI
RS
IP
(2)
VS
RS
(2)
(1)
B0100-05
(1)
VS = 5 × RS/(RS + RP). When driven low, VS logic 1 input; pulldowns => logic 0 input). Devices that drive
inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 µA while maintaining a logic-1 drive level.
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Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O (1)
5-V
TERMINATION (2)
TOLERANT
Pullup
Power down, active-low. PDN powers down all logic, stops all clocks, and
performs a soft stop whenever a logic low is applied. The internal
parameters are preserved through a power-down cycle, as long as RESET
is not active. The duration for system recovery from power down is 100
ms. When released, PDN powers up all logic, starts all clocks, and
performs a soft start that returns to the previous configuration.
PDN
10
DI
PLL_FLTM
5
AO
PLL negative input
PLL_FLTP
6
AI
PLL positive input
PWM_ 1
38
DO
PWM 1 output
PWM_ 2
37
DO
PWM 2 output
PWM_ 3
36
DO
PWM 3 output
PWM_ 4
35
DO
PWM 4 output
PWM_ 5
34
DO
PWM 5 output
PWM_ 6
33
DO
PWM 6 output
RESERVED
21
–
RESERVED (connect to ground)
A system reset is generated by applying a logic low to this terminal.
RESET is an asynchronous control signal that restores the TAS5086 to its
default conditions, sets the VALID2 output low, and places the PWM in the
hard-mute (M) state. Master volume is immediately set to full attenuation.
On the release of RESET, if PDN is high, the system performs a 4–5-ms
device initialization and sets the volume at mute.
(3)
5-V
DESCRIPTION
RESET
9
DI
5-V
Pullup
SCL
18
DI
5-V
SCLK
20
DI
5-V
SDA
17
DIO
5-V
SDIN1
26
DI
Pulldown
Serial audio data 1 input is one of the serial data input ports. SDIN1
supports four discrete (stereo) data formats.
SDIN2
25
DI
Pulldown
Serial audio data 2 input is one of the serial data input ports. SDIN2
supports four discrete (stereo) data formats.
SDIN3
24
DI
Pulldown
Serial audio data 3 input is one of the serial data input ports. SDIN3
supports four discrete (stereo) data formats.
SDIN4
23
DI
Pulldown
Serial audio data 4 input is one of the serial data input ports. SDIN4
supports four discrete (stereo) data formats.
SDOUT
22
DI
Serial audio data 1 output is the only serial data output port. SDOUT
supports I2S format only.
VALID1
31
DO
Soft start valid. Output indicating validity of soft-start PWM output,
active-high
VALID2
32
DO
Output indicating validity of PWM outputs, active-high.
VR_ANA
1
P
Voltage reference for analog supply, 1.8 V. A pinout of the internally
regulated 1.8-V power. A 0.1-µF, low-ESR capacitor should be connected
between this terminal and AVSS_PLL. This terminal must not be used to
power external devices.
VR_DIG
30
P
Voltage reference for digital PWM core supply, 1.8 V. A pinout of the
internally regulated 1.8-V power used by digital PWM core logic. A 0.1-µF,
low-ESR (3) capacitor should be connected between this terminal and
DVSS_PWM. This terminal must not be used to power external devices.
VR_OSC
15
P
Voltage reference for analog supply, 1.8 V. A pinout of the internally
regulated 1.8-V power. A 0.1-µF, low-ESR (3) capacitor should be
connected between this terminal and AVSS_PLL. This terminal must not
be used to power external devices.
I2C serial control clock input
Pulldown
Serial audio data clock (shift clock). SCLKIN is the serial audio port (SAP)
input data bit clock.
I2C serial control data interface input/output
If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.
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DETAILED DESCRIPTION
POWER SUPPLY
The TAS5086 power-supply section contains regulators that provide analog and digital regulated power for
various sections of the TAS5086. The analog supply supports the analog PLL while digital supplies support the
digital PLL, the digital audio processor, the pulse width modulator, and the output control (reclocker). The
power-supply section is enabled via VREG_EN.
CLOCK, ERROR RATE DETECTION, AND PLL
This module provides the timing and serial data interface for the TAS5086.
The TAS5086 is a clock slave device. It accepts MCLK, SCLK, and LRCLK.
The TAS5086 supports 64-fS MCLK for the 176.4-kHz and 192-kHz data rates.
The TAS5086 accepts a 64-fS SCLK rate for all MCLK ratios and a 48-fS SCLK rate for MCLK ratios of 192 fS
and 384 fS.
TAS5086 checks to verify that SCLK is a specific value of 64 fS or 48 fS.
The TAS5086 supports a 1-fS LRCLK.
The timing relationship of these clocks to SDIN[1:4] and SDOUT is shown in subsequent sections.
The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce a
196-MHz PLL output.
The TAS5086 can auto-detect and set the internal clock control logic to the appropriate settings for the
frequencies of 32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed
(176.4 kHz or 192 kHz). The automatic sample rate detection can be disabled and the values set via I2C.
The TAS5086 also supports an AM interference-avoidance mode during which the clock rate is adjusted, in
concert with the PWM sample rate converter, to produce a PWM output at 7-fS, 8-fS, or 9-fS.
The sample rate must be set manually during AM interference avoidance and when de-emphasis is enabled.
The TAS5086 uses an internal oscillator time base to provide reference timing information for the following
functions:
• MCLK, SCLK, and LRCLK error detection
• I2C communication when power is first applied to the device
• Automatic data-rate detection and setting (32 kHz, normal, double, and quad speed)
• Automatic MCLK rate detection and setting (64, 128, 192, 256, 384, and 512 fS)
OSCILLATOR TRIM
The TAS5086 PWM processor contains an internal oscillator for PLL reference. This reduces system cost
because an external reference is not required. After each power up or reset, a oscillator trim is needed; see the
Oscillator Trim Register (0x1B) section for a detailed procedure.
10
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SERIAL DATA INTERFACE
Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The PWM outputs and downmix are derived from
SDIN1, SDIN2, and SDIN3. SDIN4 is a selectable pass-through signal that is available at SDOUT as an I2S
output. The TAS5086 accepts 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 20-, or 24-bit,
left-justified, right-justified, and I2S serial data formats.
Serial data is output on SDOUT. The SDOUT data format is I2S 24-bit at the same data rate as the input. The
SDOUT output is synchronized to use the SCLK and LRCLK signals. There is a 1- to 2.5-LRCLK frame delay
from the input data to the output data, depending on the input serial data format. The SDOUT output has no
I2C-controllable functions. It is always operational.
The parameters of this clock and serial data interface input format are I2C configurable.
I2C SERIAL CONTROL INTERFACE
The TAS5086 has an I2C serial control slave interface to receive commands from a system controller. The serial
control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait states.
As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multi-byte read and write operations for status registers
and the general control registers associated with the PWM.
The I2C interface supports a special mode that permits I2C write operations to be broken up into multiple-data
write operations that are multiples of 4 data bytes. These are 6-, 10-, 14-, 18-, ... etc., -byte write operations that
are composed of a device address, read/write bit, subaddress, and any multiple of 4 bytes of data. This permits
the system to write large register values incrementally without blocking other I2C transactions.
Figure 6 shows the data flow and control through the TAS5086. The major I2C registers are shown above each
applicable block (e.g., 0x04 is the serial data format control register).
1 LF
L'
0x04
SDIN1
SDIN2
SDIN3
R'
MUX
SDIN4
0x07– 0x0D
MUX
VOL
MUX
VOL
0x25
PWM_1
2 RF
0x20
Channel
1–6
Format
0x21
PWM_2
PWM_3
3 LS
VOL
0x21
SDIN4
Downmix
1–5
L'
PWM_4
4 RS
R'
VOL
PWM
MUX
5C
PWM_5
MUX
VOL
(L'+R')/2
1–5
SEL
PWM_6
Ch-6 Processing
Channel
1–6
0x03
Downmix
SDOUT
2
IS
SDIN4
B0048-01
Figure 6. TAS5086 Data Flow Diagram With I2C Registers
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Channel-6 Processing Section
Channel 6 has processing features that are directly applicable to the subwoofer channel.
Bass Management
0x21
Ch 1–5
Ch 6 Sub
10 dB
S
MUX
0x0D
0x23
GainCompensated
Biquad
0x24
LowPass
Biquad
VOL
BQ1
BQ2
BQ1 (G)
From Downmix (L’+R’)/2
B0050-01
Figure 7. Channel-6 Processing Block Diagram
PWM Section
The TAS5086 has six channels of high-performance digital PWM modulators that are designed to drive switching
output stages (back ends) in both single-ended (SE) and H-bridge (bridge-tied load) configurations. The
TAS5086 device uses noise-shaping and sophisticated error correction algorithms to achieve high power
efficiency and high-performance digital audio reproduction. The TAS5086 uses a fourth-order noise shaper to
provide >105-dB SNR performance from 20 Hz to 20 kHz.
The TAS5086 PWM interface is described by using the following notation:
PN + V
where
P = number of PWM signals per channel
N = number of channels
V = total number of valid signals used to reset the power stage
For example, the TAS5086 initial interface format means that there is 1 PWM signal per channel (N = 6) and 1
valid signal is used to reset the power stages. The shorthand notation to describe this is 1N+1.
The PWM section accepts 24-bit PCM data from the serial data interface and outputs six PWM audio output
channels to drive 1N+1 single-ended and BTL power stages.
The PWM interface supports:
• TAS5186 in BTL or SE mode without any external glue logic, uses 1N+1 signaling.
• TAS5142 in BTL or SE mode without any external glue logic, uses 1N+1 signaling.
• TAS5111 SE without any external glue logic, and with a pulldown on the output, uses 1N+1 signaling.
• TAS5111 BTL or TAS5112 BTL with one inverter per BTL channel of glue logic and a pulldown on the output,
uses 1N+1 signaling from TAS5086, 2N+1 input to TAS5111/12.
• TAS5112 SE (with external glue logic)
See the application schematics for an example of the TAS5086 with the TAS5186 and the TAS5086 with
TAS5112 SE and TAS5111 SE.
The TAS5086 has input multiplexers that allow any of the input channels to be routed to any PWM channel and
output multiplexers to enable any PWM output to be routed to any PWM output pin.
12
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It also has individual channel dc-blocking filters that are enabled by default.
Individual channel de-emphasis filters for 32, 44.1, and 48 kHz are included and can be enabled and disabled.
There is also a two-channel downmix result that can be output on SDOUT (I2S format). This result also can be
sent to the left and right front channels (channels 1 and 2) and/or to the center and subwoofer (channels 5 and 6)
as well.
A mixer on the subwoofer channel supports bass management configuration 1.
PWM output characteristics
• Up to 8× oversampling
• 12× at fS = 32 kHz, 8× at fS = 48 kHz, 4× at fS = 96 kHz, 2× at fS = 192 kHz
• Fourth-order noise shaping
• ≥105-dB dynamic range, 0–20 kHz (TAS5086 + TAS5186 system measured at speaker terminals)
• THD < 0.06% (measured at TAS5086 outputs)
• Adjustable maximum modulation limit of 93.8% to 99.2%
Transitions Between Shutdown and Playing
The TAS5086 outputs are switching all the time with the noise shaper active. Mute is acheived by inputting a
zero into the noise shaper, with the noise shaper running and the output still switching. By using this approach,
the transitions between off and operation is avoided. The only exception is shutdown of surround channels as
described in the Surround Register (0x19) section.
Futhermore, the TAS5086 is designed to drive a load in single-ended and bridge-tied-load configurations. The
principle in the SE and BTL configurations is shown in Figure 8 and Figure 9. In both situations, care must be
taken to ensure correct start-up sequences which charge the bootstrap capacitor and do not produce audible
artifacts; the TAS5086 is designed to do that.
Output Stage
TAS5086
VPP
PWM
IN
OUT
GND
PSU
VPP
IN
OUT
GND
S0269-01
Figure 8. BTL Filter Configuration
The SE configuration presents an additional challenge in order for starting up quietly. The second terminal of the
loudspeaker is connected to a split capacitor between power and ground. The advantage of this circuitly is that it
provides some degree of power-supply ripple rejection. The problem related to the split capacitor is that the
voltage over it must be controlled when the modulator starts (i.e., when the power stage output goes out of high
impedance state) to avoid a click in the speaker.
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Power Stage
TAS5086
VPP
PWM
PSU
IN
OUT
GND
S0270-01
Figure 9. SE Filter Configuration
The TAS5086 supports two mechanisms for controlling the split-capacitor midpoint.
In the extra half-bridge scheme (the TAS5186 power stage is an example of this) an additional half-bridge is
started and brought to a 50-percent duty cycle, i.e., a situation where the average voltage of the half-bridge is
equal to the voltage which must be applied to the split-capacitor midpoint to start up without clicks in the speaker.
A resistor per channel is connected between the extra half-bridge and each midpoint for the split capacitors. The
split capacitors are charged through this resistor. This approach requires an extra VALID pin on the modulator to
control the extra half-bridge, therefore the 1N+2 interface. Figure 10 shows the topology of the extra half-bridge.
In some situations, a channel configured in BTL can be used to charge the split capacitor instead of the extra
half-bridge. This is shown in Figure 11.
The mid-Z scheme charges the split capacitor through the loudspeaker. In order to do this without audible
artifacts the charge current must be limited. This is done by applying a start sequence which charges the output
state between low, high and high-Z. Because the ouput stage is in high-Z in a part of the sequence, the resulting
output impedance can be brought to a level suitable for charging the split capacitors without audible artifacts.
This solution does not require external components, as shown in Figure 9. Not all power stages are compatible
with the mid-Z scheme, double-check the power-stage data sheet for compabitility. The PWM start register
(0x18) programs the TAS5086 for mid-Z or the standard low-Z start sequence.
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Extra Half-Bridge
TAS5086
VPP
PWM
ValidSS
IN
OUT
RES
GND
PSU
Power Stage
VPP
IN
Valid
OUT
RES
GND
S0271-01
Figure 10. Split-Capacitor Charging With Extra Half-Bridge
Power Stage BTL
TAS5086
VPP
PWM
IN OUT+
ValidSS
RES
OUT–
PSU
GND
Power Stage SE
VPP
PWM
IN
Valid
RES
OUT
GND
S0272-01
Figure 11. Split-Capacitor Charging With BTL Subwoofer
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Reset Timing (RESET)
Control-signal parameters over recommended operating conditions (unless otherwise noted)
Earliest time
that M-State
could be exited
RESET
tw(RESET)
M-State
tr(I2C_ready)
tr(run)
tr(DMSTATE) < 200 ns
Determine SCLK rate
and MCLK ratio. Enable via I2C.
Start system
T0029-03
PARAMETER
tr(DMSTATE)
Time to M-STATE low
tw(RESET)
Pulse duration, RESET active
MIN
TYP
400
2
tr(I2C_ready)
Time to enable I C
tr(run)
Device start-up time
MAX
UNIT
370
ns
None
ns
3
ms
10
ms
NOTE: Because a crystal time base is used, the system determines the CLK rates. Once the data rate and master clock ratio
are determined, the system outputs audio if a master volume command is issued.
Figure 12. Reset Timing
Power-Down (PDN) Timing
Control-signal parameters over recommended operating conditions (unless otherwise noted). Note that PDN does not clear
I2C registers.
PDN
M-State
tp(DMSTATE) < 1 ms
tsu
T0030-02
PARAMETER
tp(DMSTATE)
MIN
Time to M-STATE low
Number of MCLKs preceding the release of PDN
tsu
TYP
MAX
UNIT
300
µs
5
Device start-up time
120
ms
Figure 13. Power-Down Timing
Back-End Error (BKND_ERR)
Control-signal parameters over recommended operating conditions (unless otherwise noted)
16
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Control-signal parameters over recommended operating conditions (unless otherwise noted)
tw(ER)
BKND_ERR
M-State
or
Valid2
Normal
Operation
Normal
Operation
tp(valid_high)
tp(valid_low)
tp(valid_high)
tp(valid_low)
tp(valid_low)
T0031-02
PARAMETER
tw(ER)
MIN
Pulse duration, BKND_ERR active
TYP
350
tp(valid_low)
MAX
UNIT
None
ns
µs
