SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
FEATURES
D 50-W RMS Power Into 6 Ω at 10% THD
D 40-W RMS Power Into 6 Ω at 0.1% THD
D THD+N < 0.09% Typical (1-kHz Input Signal)
D 93-dB Dynamic Range (TDAA System)
D Power Efficiency > 90% Into 6-Ω and 8-Ω Load
D Low Profile, SMD 32-Pin PowerPAD Package
D Self-Protecting Design
D 3.3-V Digital Interface
D EMI Compliant When Used With
DESCRIPTION
The TAS5110 is a high-performance true digital audio
amplifier (TDAA) power stage, designed to drive 50 W
per channel. The TAS5110 incorporates TI’s equibitt
technology and is used in conjunction with a digital
audio PWM processor (TAS50xx) to deliver high-power,
true digital audio amplification. The efficiency of this
digital amplifier can be greater than 90%, reducing the
size of both the power supplies and heat sinks needed.
The TAS5110 accepts a mono PWM 3.3-V input and
controls the switching of an internal CMOS H-bridge.
When used with the TAS50xx PWM processor, system
performance of less than 0.09% THD is attainable.
Over-current protection, over-temperature, and
under-voltage protections are built into the TAS5110,
safeguarding the H-bridge and speakers against output
shorts, over-voltage conditions, and other fault
conditions that could damage the system.
Recommended System Design
APPLICATIONS
D DVD Receiver
D Home Theater
D Mini/Micro Component Systems
D Internet Music Appliance
D Car Audio Amplifiers and Head Units
TYPICAL TDAA STEREO AUDIO SYSTEM
Left
Digital Audio
• TAS3001
• DSP
• SPDIF
• 1394
•
•
•
•
•
Volume
EQ
DRC
Bass
Treble
TAS5110
L-C
Filter
TAS5110
L-C
Filter
TAS50xx
Right
• Serial Audio Input Port
• Internal PLL
• PCM−PWM Modulator
• Two H-Bridge Power Devices
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and Equibit are trademarks of Texas Instruments.
! " #$ % !&
% "! "! '! ! !( !
%% ) *& % " ! + %! ! ! $* $ %!
! + $$ "! ! &
Copyright 2002, Texas Instruments Incorporated
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1
SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
terminal assignments
The TAS5110 is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP). The DAP
package has the PowerPAD on the bottom.
DAP PACKAGE
(TOP VIEW)
PWM_AP
PWM_AM
ERR1
ERR0
SHUTDOWN
DVDD
DVSS
DVSS
DVSS
VRFILT
BIAS_A
BIAS_B
PWDN
RESET
PWM_BM
PWM_BP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ordering information
2
TC
0°C to 70°C
PACKAGE
TAPE AND REEL
TAS5110DAP
TAS5110DAPR
−40°C to 85°C
TAS5110IDAP
TAS5110IDAPR
www.ti.com
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVDDA2
LDROUTA
BOOTSTRAPA
PVDDA1
PVDDA1
OUTPUTA
OUTPUTA
PVSS
PVSS
OUTPUTB
OUTPUTB
PVDDB1
PVDDB1
BOOTSTRAPB
LDROUTB
PVDDB2
SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
terminal assignments
In addition to the 32-pin HTSSOP DAP package, the TAS5110 is offered in a thermally enhanced 32-pin TSSOP
surface-mount package (DAD). The DAD package has the PowerPAD on top.
DAD PACKAGE
(TOP VIEW)
PWM_BP
PWM_BM
RESET
PWDN
BIAS_B
BIAS_A
VRFILT
DVSS
DVSS
DVSS
DVDD
SHUTDOWN
ERR0
ERR1
PWM_AM
PWM_AP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVDDB2
LDROUTB
BOOTSTRAPB
PVDDB1
PVDDB1
OUTPUTB
OUTPUTB
PVSS
PVSS
OUTPUTA
OUTPUTA
PVDDA1
PVDDA1
BOOTSTRAPA
LDROUTA
PVDDA2
ordering information
TC
0°C to 70°C
PACKAGE
TAPE AND REEL
TAS5110DAD
TAS5110DADR
−40°C to 85°C
TAS5110IDAD
TAS5110IDADR
references
TAS5000 Digital Audio PWM Processor data manual − TI Literature Number SLAS270
TAS5001 Digital Audio PWM Processor data manual − TI Literature Number SLES009
TAS5010 Digital Audio PWM Processor data manual − TI Literature Number SLAS328
TAS5012 Digital Audio PWM Processor data manual − TI Literature Number SLES006
Digital Audio Measurements − TI literature number SLAA114
PowerPAD Thermally Enhanced Package − TI literature number SLMA002
www.ti.com
3
SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
PVDDA1
PVDDA1
BOOTSTRAPA
PVDDA2
LDROUTA
functional block diagram
1/2 H-Bridge
LDR
OUTPUTA
PWM_AP
PWM_AM
DIFF
RCVR
OUTPUTA
Boot Strap
Gate Drive
PVSS
BIAS_A
PWDN
RESET
SHUTDOWN
ERR1
ERR0
Control/Sense
Circuit
Bandgap
Reference
LDROUTB
PVDDB2
VRFILT
BOOTSTRAPB
PVDDB1
1/2 H-Bridge
BIAS_B
PVDDB1
LDR
DIFF
RCVR
4
OUTPUTB
Boot Strap
Gate Drive
OUTPUTB
PVSS
DVDD
PWM_BP
DVSS
PWM_BM
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SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
suggested system block diagrams
Digital Audio
• USB
• IEEE 1394
• SPDIF
• ADC
• Automotive
MOST
Network
TAS30xx
IIC
Audio
Control
L-C
Filter
TAS5110
Left
TAS50xx
Right
L-C
Filter
TAS5110
• Digital Parametric EQ • Serial Audio Input Port
• Volume
• Internal PLL
• DRC
• Two H-Bridges
• Bass
• Treble
Figure 1. System #1: Stereo Configuration With a TAS3001 Digital Audio Processor
CH1
TAS50xx
Home Theater
DVD 6-Channel
Encoded Digital
Audio Source
6
TI DSP
• Dolby AC-3
• DTS
• Volume
• EQ
• DRC
• Bass
• Treble
TAS5110
L-C
Filter
TAS5110
L-C
Filter
Surround Left
TAS5110
L-C
Filter
Surround Right
TAS5110
L-C
Filter
Center
TAS5110
L-C
Filter
Subwoofer
Left
Right
CH4
CH5
TAS50xx
L-C
Filter
CH2
CH3
TAS50xx
TAS5110
CH6
Figure 2. System #3: 6-Channel Audio Playback
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5
SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
Terminal Functions
TERMINAL
DAP
NO.
DAD
NO.
I/O
BIAS_A
11
6
I
Connect external resistor to DVSS.
BIAS_B
12
5
I
Connect external resistor to DVSS.
BOOTSTRAPA
30
19
O
Bootstrap capacitor pin for H-bridge A
BOOTSTRAPB
19
30
O
Bootstrap capacitor pin for H-bridge B
DVDD
6
11
I
3.3-V digital voltage supply for logic
DVSS
7, 8, 9
8, 9,
10
I
Digital ground for logic is internally connected to PVSS. All three pins must be tied
together but not connected externally to PVSS. See Figure 5.
ERR1
3
14
O
Error/warning report indicator. This output is open drain with internal pullup resistor.
ERR0
4
13
O
Error/warning report indicator. This output is open drain with internal pullup resistor.
LDROUTA
31
18
O
Low voltage drop-out regulator output A (not to be used to supply current to external
circuitry)
LDROUTB
18
31
O
Low voltage drop-out regulator output B (not to be used to supply current to external
circuitry)
OUTPUTA
26, 27
22, 23
O
H-bridge output A
OUTPUTB
22, 23
26, 27
O
H-bridge output B
PVDDA1
28, 29
20, 21
I
High voltage power supply, H-bridge A
PVDDA2
32
17
I
High voltage power supply for low-dropout voltage regulator A-side
PVDDB1
20, 21
28, 29
I
High voltage power supply, H-bridge B
PVDDB2
17
32
I
High voltage power supply for low-dropout voltage regulator B-side
PVSS
24, 25
24, 25
I
High voltage power supply ground
PWDN
13
4
I
Power down = 0, normal mode = 1
PWM_AM
2
15
I
PWM input A(−)
PWM_AP
1
16
I
PWM input A(+)
PWM_BP
16
1
I
PWM input B(+)
PWM_BM
15
2
I
PWM input B(−)
RESET
14
3
I
Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are
in low-low output state. Asserting the RESET signal low causes all fault conditions to be
cleared.
SHUTDOWN
5
12
O
Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when
device is in shutdown mode the H-bridge MOSFETs are in low-low output state. The
latched output can be cleared by asserting the RESET signal. This output is open drain
with internal pullup resistor.
VRFILT
10
7
O
A filter capacitor must be added between VRFILT and DVSS pins.
NAME
DESCRIPTION
NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS50xx output pins, and never
left floating. Floating PWM input pins causes an illegal PWM input state signal to be asserted.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1, and PVDDB1 must have both pins connected externally to the same point on the circuit board,
respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high-current DMOS output
devices. Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires
and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same
node, respectively.
6
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SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
functional description
PWM H-bridge state control
The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals
are a complementary differential signal format for the A-side half-bridge and the B-side half-bridge.
bootstrapped gate drive
The TAS5110 includes two dedicated bootstrapped power supplies. A bootstrap capacitor is connected
between the individual bootstrap pin and the associated output. For example, a capacitor is connected between
the BOOTSTRAPA pin and OUTPUTA pin, and another capacitor is connected between the BOOTSTRAPB
pin and the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply
levels externally supplied to the system while providing a low-noise supply level for driving the high-side
N-channel DMOS transistors.
low-dropout voltage regulator
Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power
supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for
external circuitry. Each LDO is dedicated to a half-bridge and its gate driver. An LDO output capacitor is
connected between the individual LDO output pin and the associated output return. For example, a capacitor
is connected between the LDROUTA pin and PVSS pin, and another capacitor is connected between the
LDROUTB pin and PVSS pin.
high-current H-bridge output stage
The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the
two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output
mapping section below. When the TAS5110 is in the normal mode, as seen in the H-bridge output mapping
tables, the outputs are decoded from the inputs. However, the TAS5110 is immediately shut down if any of the
following error conditions occur: over-current, over-temperature, low regulator output voltage, or an illegal PWM
input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified
in the H-bridge output mapping section, and the SHUTDOWN pin is set low.
H-bridge output mapping
The A-side half-bridge output is designed to the following truth table:
INPUTS
OUTPUTS
DESCRIPTION
RESET
PWDN
PWM_AP
PWM_AM
SHUTDOWN
X
X
X
X
0
OUTPUTA
0 or Hi-Z†
X
0
X
X
1
Hi-Z
0
1
X
X
1
0
Reset
1
1
0
0
0
0
Shutdown
1
1
0
1
1
0
Normal
1
1
1
0
1
1
Normal
1
1
1
1
0
0
† Output is 0 for low voltage, over temperature, and illegal input. Hi-Z is for over current.
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Shutdown
Powerdown
Shutdown
7
SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
H-bridge output mapping (continued)
The B-side half-bridge output is designed to the following truth table:
INPUTS
OUTPUTS
DESCRIPTION
RESET
PWDN
PWM_BP
PWM_BM
SHUTDOWN
X
X
X
X
0
OUTPUTB
0 or Hi-Z†
X
0
X
X
1
Hi-Z
Powerdown
0
1
X
X
1
0
Reset
1
1
0
0
0
0
Shutdown
1
1
0
1
1
0
Normal
1
1
1
0
1
1
Normal
1
1
1
1
0
0
Shutdown
Shutdown
† Output is 0 for low voltage, over temperature, or illegal input. Hi-Z is for over current.
control/sense circuitry
The control/sense circuitry consists of the following 3.3-V logic level pins: PWDN, RESET, ERR0, ERR1, and
SHUTDOWN. The active-low PWDN input pin powers down all internal circuitry and forces the H-bridge outputs
to the Hi-Z state. When the PWDN pin is low, the open drain ERR0, ERR1, and SHUTDOWN pins are also
disabled so that their outputs can be pulled high. The active-low RESET input pin forces the H-bridge outputs
to the low-low state and resets the over-current shutdown latch. The PWDN pin overrides the RESET pin. The
ERR0, ERR1, and SHUTDOWN outputs indicate the following conditions in the TAS5110 as shown in the table
below. These three outputs are open-drain connections with internal pullup resistors so that wire-ORed
connections can be made by the user with other external control devices. The short-circuit protect error
condition latches the TAS5110 in this shutdown state and forces the H-bridge outputs to the Hi-Z state until the
device is reset by means of the RESET pin. The illegal PWM input state, over-temperature, and low regulator
voltage error conditions does not latch the device in the shutdown condition. Instead the H-bridge outputs are
forced to the low-low state and the TAS5110 returns to normal operation as soon as the error condition ends.
Loss of clocking PWM signal is also considered an illegal PWM input state.
8
SHUTDOWN
ERR1
ERR0
OUTPUTA
OUTPUTB
0
0
0
Illegal PWM input state
FUNCTION
Low
Low
0
0
1
Short circuit protect (latch)
Hi-Z
Hi-Z
0
1
0
Over temperature protect
Low
Low
0
1
1
Low regulator voltage protect
Low
Low
1
0
0
Reserved
—
—
1
0
1
Reserved
—
—
1
1
0
High temperature − warning
Normal
Normal
1
1
1
Normal operation
Normal
Normal
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SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
device operation
power sequences
system power-up/power-down sequencing
The recommended power-up/power-down sequence is shown in Figure 3. For proper operation the RESET
signal should be kept low when both DVDD and output power (PVDDA1, PVDDA2, PVDDB1, and PVDDB2)
are being applied. The RESET signal should remain low for at least 1 ms after output power is applied.
DVDD†
PWDN
> 1 ms
PVDDA2
PVDDB2
> 100 µs
PVDDA1
PVDDB1
> 100 µs
RESET
> 1 ms
† For most applications, it is recommended that the PWDN pin be connected directly to the DVDD pin.
Figure 3. Power-Up/Power-Down Sequence
RESET function
The device is put into a reset condition when the (active low) RESET signal is asserted. While in the reset state,
the input H-bridge control signals consisting of PWM_AP, PWM_AM, PWM_BP, and PWM_BM are ignored, and
the H-bridge MOSFETs are placed in a state where OUTPUTA and OUTPUTB are both low. Asserting the
RESET signal low also causes the short circuit protection latch to be reset. The RESET signal is normally
connected to the VALID signal from the TAS50xx.
reinitialization sequence
Proper initial conditions for this device include asserting the RESET signal until the reset operation has
completed (1 ms). Additionally, when using this device with the TAS50xx controller, this function can be
accomplished by asserting the reset pin on the TAS50xx during the reset sequence (see Figure 3).
audio application considerations
optimal power transfer for H-bridge
The TAS5110 is a power H-bridge that is designed to deliver a maximum of 50 W RMS into a 6-Ω load. In order
to achieve 50 W into 6 Ω, the system designer must provide an adequate thermal design. See the Thermal
Methodology for the 32-Pin DAD Package 50 W, 6-Ω Test and the Thermal Methodology for the 32-Pin DAP
Package 50 W, 6-Ω sections for a discussion of possible thermal solutions. Careful attention must be given to
the value of the high-voltage power supply level for a given load resistance. See recommended operating
conditions. See the Maximum Available Power at Common Load Impedances for Both DAP and DAD Packages
section.
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9
SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
audio application considerations (continued)
reconstruction output filter
An output reconstruction filter is required between the H-bridge outputs and the loudspeaker load. This second
order low-pass filter passes the audio information to the loudspeaker, while filtering out the high frequency
out-of-band information contained in the H-bridge output PWM pulses. The values of the L and C components
selected are dependent on the loudspeaker load impedance.
fault indicator usage
The TAS5110 is a self-protecting device that provides device fault reporting, including over-temperature protect,
under-voltage lockout (low-regulator voltage), and short circuit protection. The short circuit protection protects
against short circuits that may occur at the loudspeaker load when configured. The TAS5110 is not
recommended for driving loads less than 6 Ω, since the internal current limit protection might be activated.
An under-voltage lockout signal occurs when an insufficient voltage level is present on the LDROUTA or
LDROUTB pins. During this condition gate drive levels are not sufficient for driving the power MOSFETs. Normal
operation is resumed when the minimum proper LDROUTA or LDROUTB level is obtained and the low regulator
voltage protect signal is de-asserted. See the control/sense circuitry section for error and warning conditions.
A high temperature warning signal is asserted on pin ERR0 when the device temperature exceeds 125°C
typical.
If the internal device temperature exceeds 150°C typical, the over temperature protect signal is asserted and
the TAS5110 is shut down. The device re-enables once the temperature drops to 125°C typical. See the
control/sense circuitry section for error and warning conditions.
Detection of an illegal PWM input state or the loss of a clocking PWM input signal causes an illegal PWM input
state signal to be asserted on the ERR1and ERR0 pins and sets the SHUTDOWN pin to the low state.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
DC supply voltage range: DVDD to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.2 V
PWM_AP, PWM_AM, PWM_BP, PWM_BM . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V
RESET, PWDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V
PVDDA1 to PVSS, PVDDB1 to PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 28 V
PVDDA2 to PVSS, PVDDB2 to PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 27 V
Output DMOS drain-to-source breakdown voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 V
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
10
www.ti.com
SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
recommended operating conditions (maximum output power = 50 W (RMS), TJ = 25°C)
thermal data†
MIN
PARAMETER
NOM
MAX
UNIT
Shutdown junction temperature, TJ(SD)
150
°C
Warning junction temperature, TJ(W)
125
°C
Commercial
Operating temperature, TC
Industrial
0
25
70
°C
−40
25
85
°C
Thermal resistance junction-to-case, θjc}
1.6
°C/W
2 oz. trace and copper pad without solder
}
Thermal resistance junction-to-ambient, θja
44.3
°C/W
† One of the most influential components on the thermal performance of a package is board design. In order to take full advantage of the heat
dissipating abilities of the PowerPAD packages, a board must be used that acts similar to a heat sink and allows for the use of the exposed (and
solderable), deep downset pad. See Appendix A of the PowerPAD Thermally Enhanced Package application note, TI literature number
SLMA002.
‡ For both DAD and DAP packages.
RL = 6 Ω to 8 Ω
Digital
Supply voltage
Regulator
PARAMETER
MIN
NOM
MAX
DVDD to DVSS
3
3.3
3.6
PVDDA2 to PVSS
16.5
22
26.5
PVDDB2 to PVSS
16.5
22
26.5
PVDDA2 to PVSSw
10.5
16.5
PVDDB2 to PVSSw
10.5
16.5
UNIT
V
V
§ Connect LDROUTA to PVDDA2 and connect LDROUTB to PVDDB2. Under this condition, the H-bridge forward on-state resistance is increased.
This increases internal power dissipation. Maximum output power may need to be reduced to meet thermal conditions.
maximum available power at common load impedances for both DAP and DAD packages unclipped (0 dB)
level, test conditions described in the Thermal Methodology for the 32-Pin DAD Package 50 W, 6-Ω Test and
Thermal Methodology for the 32-Pin DAP Package 50 W, 6-Ω Test sections
LOAD IMPEDANCE (Ω)
PVDAA1/PVDDB1 (VDC)
APPROXIMATE MAX OUTPUT POWER (W)
THD+N AT MAX POWER AND 1 kHz
INPUT¶
6
27
50
< 10%
6
27
43
< 0.09%
8
27
34
< 0.09%
¶ Dependent on board design and component selection.
static digital specifications
RESET, PWDN, PWM_AP, PWM_AM, PWM_BP, PWM_BM, TJ = 25°C, DVDD = 3.3 V
PARAMETERS
High-level input voltage, VIH
MIN
MAX
2
Low-level input voltage, VIL
Input leakage current
−10
UNIT
V
0.8
V
10
µA
ERR0, ERR1, SHUTDOWN, (open drain with internal pullup resistor) TJ = 25°C, DVDD = 3.3 V)
PARAMETERS
Internal pullup resistors from SHUTDOWN, ERR0, ERR1 to DVDD
Low-level output voltage (IO = 4 mA), VOL
MIN
MAX
15
kΩ
0.4
www.ti.com
UNIT
V
11
SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
electrical characteristics
supply, TJ = 25°C (Fswitching = 384 kHz, OUTPUTA and OUTPUTB not connected, DVDD = 3.3 V,
PVDDA1 = 25 V, PVDDB1 = 25 V, PVDDA2 = 22 V, PVDDB2 = 22 V, 50% input duty cycle)
PARAMETER
TYP
Operating
DVDD
PVDDA1
PVDDB1
Supply current
PVDDA2
PVDDB2
MAX
2
PWDN = 0
Operating†
mA
500
6.3
PWDN = 0
6.5
PWDN = 0
† 13-kΩ resistor from BIAS_A (pin 11) to DVSS and 13-kΩ resistor from BIAS_B (pin 12) to DVSS.
µA
mA
25
Operating
UNIT
µA
mA
250
µA
H-Bridge transistors, PVDDA2 = PVDDB2 = 22 V, DVDD = 3.3 V, TJ = 25°C (unless otherwise noted)
PARAMETER
Drain-to-source breakdown voltage
TEST CONDITIONS
Forward on-state resistance, low-side drivers
OUTPUTA and OUTPUTB to PVSS
ID = 1 mA,
PWDN = 0,
Hi-Z state
ISINK = 2.5 A,
PWM_AP = PWM_BP = 0,
See Notes 1, 2, and 3, PWM_AM = PWM_BM = 1
Forward on-state resistance, high-side drivers
PVDDA1 to OUTPUTA, PVDDB1 to OUTPUTB
ISOURCE = 2.5 A,
See Notes 1, 2, and 4,
MIN
TYP
MAX
28
PWM_AP = PWM_BP = 1,
PWM_AM = PWM_BM = 0
UNIT
V
0.2
0.24
Ω
0.2
0.24
Ω
On-state resistance matching low-side drivers
98%
On-state resistance matching high-side drivers
98%
NOTES: 1. Test time should be < 1 ms to avoid temperature change.
2. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
3. Connect PVDDA2 and PVDDB2 to a 22-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA, and
BOOTSTRAPB pins open.
4. Connect PVDDA2 to 22-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA, and BOOTSTRAPB
capacitors are connected respectively. Clock PWM inputs to allow bootstrap capacitors to charge. 93−99% modulation must be used
on PWM_AP, PWM_AM, PWM_BP, and PWM_BM inputs to prevent the activity detector from shutting down the device during this
measurement. Note that Fswitching = 384 kHz.
electrical characteristics, voltage regulator, TJ = 25°C (unless otherwise noted)
PARAMETER
Output voltage (LDROUTA, LDROUTB)
TEST CONDITIONS
IO = 5 mA,
See Note 5,
PVDDA2 = PVDDB2 = 18 V to 27 V,
DVDD = 3.3 V
MIN
TYP
MAX
14.5
15.3
16
UNIT
V
NOTE 5: These voltage regulators are for internal gate drive circuits only and are not to be used under any circumstances to supply current to
external circuity.
12
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SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
JUNCTION TEMPERATURE
vs
ON-STATE RESISTANCE
160
TJ − Junction Temperature − °C
140
120
100
80
60
40
20
0
0.15
0.20
0.25
0.30
0.35
0.40
r(on) − On-State Resistance − Ω
Figure 4. Temperature vs On-State Resistance
APPLICATION INFORMATION
TAS5110 (DAP Package)
1
TAS50xx
2
3
Error
Reporting
RESET
PWM_M_L
4
5
3.3 V
6
PWM_P_L
C7
7
8
VALID
9
C2
10
R1
R2
11
12
PWM_AP
PVDDA2
PWM_AM
LDROUTA
ERR1
BOOTSTRAPA
ERR0
PVDDA1
SHUTDOWN
PVDDA1
OUTPUTA
DVDD
DVSS
OUTPUTA
32
22 V
31
30
C3
29
C4
Snubber
Circuit
28
27
L1
26
dc
C1
25
DVSS
PVSS
DVSS
PVSS
VRFILT
OUTPUTB
BIAS_A
OUTPUTB
BIAS_B
PVDDB1
PWDN
PVDDB1
RESET
BOOTSTRAPB
13
14
15
PWM_BM
LDROUTB
PWM_BP
PVDDB2
16
+
_
24
23
22
L2
21
Snubber
Circuit
20
19
C5
C6
18
17
22 V
Figure 5. Typical TAS5110 Application (One Channel Shown)
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13
SLES028A − MAY 2002 − REVISED SEPTEMBER 2002
THERMAL INFORMATION
The thermally enhanced DAP package is based on the 32-pin HTSSOP, but includes a thermal pad (see
Figure 6) to provide an effective thermal contact between the IC and the PCB.
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO-220
type packages have leads formed as gull wings to make them applicable for surface-mount applications. These
packages, however, have two shortcomings: they do not address the low profile requirements (
