TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
TM
DIGITAL AMPLIFIER POWER STAGE
FEATURES
D 50 W per Channel (BTL) Into 6 Ω (Stereo)
D 95-dB Dynamic Range With TAS5026
D Less Than 0.1% THD+N (1 W RMS Into 6 Ω)
D Less Than 0.2% THD+N (50 W RMS into 6 Ω)
D Power Efficiency Typically 90% Into 6-Ω Load
D Self-Protecting Design (Undervoltage,
D
D
Overtemperature and Short Conditions) With
Error Reporting
Internal Gate Drive Supply Voltage Regulator
EMI Compliant When Used With
Recommended System Design
APPLICATIONS
D DVD Receiver
D Home Theatre
D Mini/Micro Component Systems
D Internet Music Appliance
DESCRIPTION
The TAS5112A is a high-performance, integrated stereo
digital amplifier power stage designed to drive 6-Ω
speakers at up to 50 W per channel. The device
incorporates TI’s PurePath Digitalt technology and is
used with a digital audio PWM processor (TAS50XX) and
a simple passive demodulation filter to deliver high-quality,
high-efficiency, true-digital audio amplification.
The efficiency of this digital amplifier is typically 90%,
reducing the size of both the power supplies and heatsinks
needed. Overcurrent protection, overtemperature
protection, and undervoltage protection are built into the
TAS5112A, safeguarding the device and speakers against
fault conditions that could damage the system.
THD + NOISE vs OUTPUT POWER
THD + NOISE vs FREQUENCY
1
RL = 6 Ω
TC = 75°C
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
1
0.1
0.01
100m
1
10
100
PO - Output Power - W
RL = 6 Ω
TC = 75°C
PO = 50 W
0.1
PO = 10 W
PO = 1 W
0.01
0.001
20
100
1k
10k 20k
f - Frequency - Hz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5112A is offered in a thermally enhanced 56-pin
TSSOP DFD (thermal pad is on the top) and DCA (thermal
pad is on the bottom), shown as follows.
DFD PACKAGE
(TOP VIEW)
GND
GND
GREG
OTW
SD_CD
SD_AB
PWM_DP
PWM_DM
RESET_CD
PWM_CM
PWM_CP
DREG_RTN
M3
M2
M1
DREG
PWM_BP
PWM_BM
RESET_AB
PWM_AM
PWM_AP
GND
DGND
GND
DVDD
GREG
GND
GND
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DCA PACKAGE
(TOP VIEW)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
GVDD
BST_D
PVDD_D
PVDD_D
OUT_D
OUT_D
GND
GND
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
GND
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GVDD
GND
GND
GND
GREG
DVDD
GND
DGND
GND
PWM_AP
PWM_AM
RESET_AB
PWM_BM
PWM_BP
DREG
M1
M2
M3
DREG_RTN
PWM_CP
PWM_CM
RESET_CD
PWM_DM
PWM_DP
SD_AB
SD_CD
OTW
GREG
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
GVDD
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND
GND
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND
GND
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD
GND
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
Absolute Maximum Ratings
Package Dissipation Ratings
over operating free-air temperature range unless otherwise noted(1)
PACKAGE
RθJC
(°C/W)
RθJA
(°C/W)
–0.3 V to 4.2 V
56-pin DFD TSSOP
1.14
See Note 4
GVDD TO GND
33.5 V
56-pin DCA TSSOP
1.14
See Note 4
PVDD_X TO GND (dc voltage)
33.5 V
TAS5112A
DVDD TO DGND
PVDD_X TO GND (spike voltage(2))
OUT_X TO GND (dc voltage)
UNITS
48 V
33.5 V
OUT_X TO GND (spike voltage(2))
48 V
BST_X TO GND (dc voltage)
48 V
BST_X TO GND (spike voltage(2))
53 V
GREG TO GND (3)
PWM_XP, RESET, M1, M2, M3, SD,
OTW
14.2 V
–0.3 V to DVDD + 0.3 V
Maximum operating junction
temperature, TJ
–40°C to 150°C
Storage temperature
–40°C to 125°C
(1)
Stresses beyond those listed under “absolute maximum ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device
reliability.
(2) The duration of voltage spike should be less than 100 ns; see
application note SLEA025.
(3) GREG is treated as an input when the GREG pin is overdriven by
GVDD of 12 V.
(4)
The TAS5112A package is thermally enhanced for conductive
cooling using an exposed metal pad area. It is impractical to use the
device with the pad exposed to ambient air as the only heat sinking
of the device.
For this reason, RθJA, a system parameter that characterizes the
thermal treatment, is provided in the Application Information section
of the data sheet. An example and discussion of typical system
RθJA values are provided in the Thermal Information section. This
example provides additional information regarding the power
dissipation ratings. This example should be used as a reference to
calculate the heat dissipation ratings for a specific application. TI
application engineering provides technical support to design
heatsinks if needed.
Ordering Information
TA
PACKAGE
DESCRIPTION
0°C to 70°C
TAS5112ADFD
56-pin small TSSOP
0°C to 70°C
TAS5112ADCA
56-pin small TSSOP
For the most current specification and package
information, refer to our Web site at www.ti.com.
3
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
Terminal Functions
TERMINAL
FUNCTION(1)
DESCRIPTION
54
P
High-side bootstrap supply (BST), external capacitor to OUT_A required
42
43
P
High-side bootstrap supply (BST), external capacitor to OUT_B required
43
42
P
HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D
54
31
P
HS bootstrap supply (BST), external capacitor to OUT_D required
DGND
23
6
P
Digital I/O reference ground
DREG
16
13
P
Digital supply voltage regulator decoupling pin, capacitor connected to
GND
DREG_RTN
12
17
P
Digital supply voltage regulator decoupling return pin
25
4
P
I/O reference supply input (3.3 V)
1, 2, 22, 24,
27, 28, 29, 36,
37, 48, 49, 56
1, 2, 5, 7, 27,
28, 29, 36, 37,
48, 49, 56
P
Power ground
NAME
DFD NO.
DCA NO.
BST_A
31
BST_B
BST_C
DVDD
GND
GREG
3, 26
3, 26
P
Gate drive voltage regulator decoupling pin, capacitor to REG_GND
GVDD
30, 55
30, 55
P
Voltage supply to on-chip gate drive and digital supply voltage regulators
M1 (TST0)
15
14
I
Mode selection pin
M2
14
15
I
Mode selection pin
M3
13
16
I
Mode selection pin
OTW
4
25
O
Overtemperature warning output, open drain with internal pullup resistor
OUT_A
34, 35
50, 51
O
Output, half-bridge A
OUT_B
38, 39
46, 47
O
Output, half-bridge B
OUT_C
46, 47
38, 39
O
Output, half-bridge C
OUT_D
50, 51
34, 35
O
Output, half-bridge D
PVDD_A
32, 33
52, 53
P
Power supply input for half-bridge A
PVDD_B
40, 41
44, 45
P
Power supply input for half-bridge B
PVDD_C
44, 45
40,41
P
Power supply input for half-bridge C
PVDD_D
52, 53
32, 33
P
Power supply input for half-bridge D
PWM_AM
20
9
I
Input signal (negative), half-bridge A
PWM_AP
21
8
I
Input signal (positive), half-bridge A
PWM_BM
18
11
I
Input signal (negative), half-bridge B
PWM_BP
17
12
I
Input signal (positive), half-bridge B
PWM_CM
10
19
I
Input signal (negative), half-bridge C
PWM_CP
11
18
I
Input signal (positive), half-bridge C
PWM_DM
8
21
I
Input signal (negative), half-bridge D
PWM_DP
7
22
I
Input signal (positive), half-bridge D
RESET_AB
19
10
I
Reset signal, active low
RESET_CD
9
20
I
Reset signal, active low
SD_AB
6
23
O
Shutdown signal for half-bridges A and B, active-low
SD_CD
5
24
O
Shutdown signal for half-bridges C and D, active-low
(1)
4
I = input, O = Output, P = Power
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
FUNCTIONAL BLOCK DIAGRAM
BST_A
GREG
PVDD_A
Gate
Drive
PWM_AP
PWM
Receiver
OUT_A
Timing
Control
Gate
Drive
GND
Protection A
BST_B
RESET
GREG
PVDD_B
Protection B
Gate
Drive
PWM_BP
PWM
Receiver
OUT_B
Timing
Control
Gate
Drive
To Protection
Blocks
GND
DREG
DREG
GVDD
OTW
GREG
OT
Protection
SD
GREG
GREG
DREG
GREG
UVP
DREG_RTN
DREG_RTN
This diagram shows one channel.
5
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
RECOMMENDED OPERATING CONDITIONS
(1)
MIN
TYP
MAX
UNIT
DVDD
Digital supply
Relative to DGND
3
3.3
3.6
V
GVDD
Supply for internal gate drive and logic
regulators
Relative to GND
16
29.5
30.5
V
PVDD_x
Half-bridge supply
Relative to GND, RL= 6 Ω to 8 Ω
0
29.5
30.5
V
TJ
Junction temperature
125
_C
(1)
0
It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted
TYPICAL
SYMBOL
PARAMETER
TEST CONDITIONS
TA=25°C
OVER TEMPERATURE
TA=25°C
TCase=
75°C
TA=40°C
TO 85°C
UNITS
MIN/TYP/
MAX
AC PERFORMANCE, BTL Mode, 1 kHz
Po
THD+N
Output power
Total harmonic distortion
+ noise
RL = 8 Ω, THD = 0.2%,
AES17 filter, 1 kHz
40
W
Typ
RL = 8 Ω, THD = 10%, AES17
filter, 1 kHz
50
W
Typ
RL = 6 Ω, THD = 0.2%,
AES17 filter, 1 kHz
50
W
Typ
RL = 6 Ω, THD = 10%, AES17
filter, 1 kHz
62
W
Typ
Po = 1 W/ channel, RL = 6 Ω,
AES17 filter
0.03%
Typ
Po = 10 W/channel, RL = 6 Ω,
AES17 filter
0.04%
Typ
Po = 50 W/channel, RL = 6 Ω,
AES17 filter
0.2%
Typ
Vn
Output integrated voltage
noise
A-weighted, mute, RL = 6 Ω,,
20 Hz to 20 kHz, AES17 filter
260
µV
Max
SNR
Signal-to-noise ratio
A-weighted, AES17 filter
96
dB
Typ
DR
Dynamic range
f = 1 kHz, A-weighted,
AES17 filter
96
dB
Typ
INTERNAL VOLTAGE REGULATOR
DREG
Voltage regulator
Io = 1 mA,
PVDD = 18 V to 30.5 V
3.1
V
Typ
GREG
Voltage regulator
Io = 1.2 mA,
PVDD = 18 V to 30.5 V
13.4
V
Typ
IGVDD
GVDD supply current,
operating
fS = 384 kHz, no load, 50%
duty cycle
24 (1)
mA
Max
IDVDD
DVDD supply current,
operating
fS = 384 kHz, no load
5
mA
Max
1
OUTPUT STAGE MOSFETs
RDSon,LS
Forward on-resistance,
low side
TJ = 25°C
155
mΩ
Typ
RDSon,HS
Forward on-resistance,
high side
TJ = 25°C
155
mΩ
Typ
(1)
6
Measured with TI standard manufacturing hardware configuration
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
ELECTRICAL CHARACTERISTICS
PVDD_x = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted
TYPICAL
SYMBOL
PARAMETER
TEST CONDITIONS
TA=25°C
OVER TEMPERATURE
TCase=
75°C
TA=40°C
TO 85°C
UNITS
MIN/TYP/
MAX
6.9
V
Min
7.9
V
Max
TA=25°C
INPUT/OUTPUT PROTECTION
Vuvp,G
Undervoltage protection
limit, GVDD
Set the DUT in normal
operation mode with all the
protections enabled. Sweep
GVDD up and down.
down Monitor
SD output. Record the
GREG reading when SD is
triggered.
74
7.4
OTW
Overtemperature warning,
junction temperature
125
°C
Typ
OTE
Overtemperature error,
junction temperature
150
°C
Typ
OC
Overcurrent protection
6.7
A
Typ
2
V
Min
DVDD
V
Max
0.8
V
Max
-10
µA
Min
10
µA
Max
22.5
kΩ
Min
0.4
V
Max
See Note 1.
STATIC DIGITAL SPECIFICATION
PWM_AP, PWM_BP, M1,
M2, M3, SD, OTW
VIH
High level input voltage
High-level
VIL
Low-level input voltage
L k
Leakage
I
Input
t leakage
l k
currentt
OTW/SHUTDOWN (SD)
Internally pull up R from
OTW/SD to DVDD
VOL
(1)
Low-level output voltage
30
IO = 4 mA
To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care.
See Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors
for optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5112A. It is recommended
to follow the TAS5112F2EVM (S/N 112) design and layout guidelines for best performance.
7
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
SYSTEM CONFIGURATION USED FOR CHARACTERIZATION
Gate-Drive
Power Supply
External Power Supply
H-Bridge
Power Supply
TAS5112ADFD
1
1 µF
56
GND
GND
2
55
GND
GVDD
3
GREG
4
53
OTW
PVDD_D
SD_CD
PVDD_D
SD_AB
OUT_D
PWM_DP
OUT_D
5
6
ERR_RCVY
49
PWM_DM
11
12
100 nF
PWM PROCESSOR
TAS5026
13
14
PWM_AP_2
PWM_CP
M3
PVDD_C
M2
BST_C
M1
BST_B
PWM_BP
PVDD_B
PWM_BM
OUT_B
RESET_AB
OUT_B
PWM_AM
GND
PWM_AP
GND
8
†
1.5 Ω
35
GND
OUT_A
34
DGND
10 µH
4.7 kΩ
470 nF 100 nF
OUT_A
1.5 Ω
PVDD_A
31
BST_A
27
GND
GVDD
GND
GND
Voltage suppressor diodes: 1SMA33CAT
LPCB : Track in the PCB (1,0 mm wide and 50 mm long)
100 nF 4.7 kΩ
100 nF
PVDD_A
32
GREG
10 µH
†
33
DVDD
‡
37
36
25
†
100 nF
38
24
28
LPCB‡
33 nF
39
GND
1 µF
1000 µF
42 1.5 Ω
40
23
26
LPCB‡
33 nF
43
PVDD_B
21
100 nF
44
41
DREG
100 nF 4.7 kΩ
100 nF
45
PVDD_C
20
22
10 µH
†
OUT_C
DREG_RTN
19
100 Ω
1.5 Ω
46
18
VALID_2
4.7 kΩ
GND
OUT_C
17
PWM_AM_2
10 µH
470 nF 100 nF
47
PWM_CM
15
16
†
1.5 Ω
48
RESET_CD
10
100 nF
GND
9
VALID_1
52
50
8
PWM_AM_1
100 nF
LPCB‡
33 nF
51
7
PWM_AP_1
54 1.5 Ω
BST_D
33 nF
LPCB‡
1000 µF
30 1.5 Ω
29
100 nF
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
TYPICAL CHARACTERISTICS AND SYSTEM PERFORMANCE
OF TAS5112ADFD EVM WITH TAS5026 PWM PROCESSOR
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
NOISE AMPLITUDE
vs
FREQUENCY
0
RL = 6 Ω
TC = 75°C
RL = 6Ω
FFT = -60 dB
TC = 75°C
TAS5026 Front End Device
−20
PO = 50 W
−40
Noise Amplitude - dBr
THD+N - Total Harmonic Distortion + Noise - %
1
0.1
PO = 10 W
PO = 1 W
0.01
−60
−80
−100
−120
−140
0.001
20
−160
100
1k
0
10k 20k
2
4
6
f - Frequency - Hz
Figure 1
10
12
14
16
18
20
22
Figure 2
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
H-BRIDGE VOLTAGE
10
60
RL = 6 Ω
TC = 75°C
TA = 75°C
50
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
8
f - Frequency - kHz
1
0.1
40
RL = 6 Ω
30
RL = 8 Ω
20
10
0.01
0.1
0
1
10
PO - Output Power - W
Figure 3
100
0
4
8
12
16
20
24
28
32
VDD - Supply Voltage - V
Figure 4
9
TAS5112A
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SLES094B - OCTOBER 2003 - REVISED JUNE 2008
POWER LOSS
vs
OUTPUT POWER
100
11
90
10
80
9
f = 1 kHz
RL = 6 Ω
TC = 75°C
8
70
Ptot - Power Loss - W
η - System Output Stage Efficiency - %
SYSTEM OUTPUT STAGE EFFICIENCY
vs
OUTPUT POWER
60
50
40
30
20
6
5
4
3
2
f = 1 kHz
RL = 6 Ω
TC = 75°C
10
7
1
0
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
0
PO - Output Power - W
5
10 15 20 25 30 35 40 45 50 55 60 65
PO - Output Power - W
Figure 5
Figure 6
OUTPUT POWER
vs
CASE TEMPERATURE
AMPLITUDE
vs
FREQUENCY
60
3.0
PVDD = 29.5 V
RL = 6 Ω
58
2.5
2.0
56
Amplitude - dBr
PO - Output Power - W
1.5
54
52
50
Channel 1
48
Channel 2
46
1.0
RL = 8 Ω
0.5
0.0
−0.5
−1.0
RL = 6 Ω
−1.5
44
−2.0
42
−2.5
40
0
20
40
60
80
100
TC - Case Temperature - °C
Figure 7
10
120
140
−3.0
10
100
1k
f - Frequency - Hz
Figure 8
10k
50k
TAS5112A
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SLES094B - OCTOBER 2003 - REVISED JUNE 2008
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
200
ron - On-State Resistance - mΩ
190
180
170
160
150
140
130
120
0
10
20
30
40
50
60
70
80
90 100
TJ - Junction Temperature - °C
Figure 9
11
TAS5112A
www.ti.com
From
PWM
Processor
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
Figure 10. Typical Single-Ended Design With TAS5112A DCA
12
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
THEORY OF OPERATION
POWER SUPPLIES
The power device only requires two supply voltages,
GVDD and PVDD_X.
GVDD is the gate drive supply for the device, regulated
internally down to approximately 12 V, and decoupled with
regards to board GND on the GREG pins through an
external capacitor. GREG powers both the low side and
high side via a bootstrap step-up conversion. The
bootstrap supply is charged after the first low-side turn-on
pulse. Internal digital core voltage DREG is also derived
from GVDD and regulated down by internal circuitry to
3.3 V.
The gate-driver regulator can be bypassed for reducing
idle loss in the device by shorting GREG to GVDD and
directly feeding in 12.0 V. This can be useful in an
application where thermal conduction of heat from the
device is difficult.
PVDD_X is the H-bridge power supply pin. Two power pins
exists for each half-bridge to handle the current density. It
is important that the circuitry recommendations
concerning the PVDD_X pins are followed carefully both
topologyand
layout-wise.
For
topology
recommendations, see the System Configuration Used for
Characterization
section.
Following
these
recommendations is important for parameters like EMI,
reliability, and performance.
POWERING UP
> 1 ms
> 1 ms
RESET
GVDD
4.7-kΩ pulldown resistor on each PWM output node to
ground. This precharges the bootstrap supply capacitors
and discharges the output filter capacitor.
After GVDD has been applied, it takes approximately 800
µs to fully charge the BST capacitor. Within this time,
RESET must be kept low. After approximately 1 ms, the
back-end bootstrap capacitor is charged.
RESET can now be released if the modulator is powered
up and streaming valid PWM signals to the back-end
PWM_xP. Valid means a switching PWM signal which
complies with the frequency and duty cycle ranges stated
in the Recommended Operating Conditions.
A constant HIGH dc level on the PWM_xP is not permitted,
because it would force the high-side MOSFET ON until it
eventually ran out of BST capacitor energy and might
damage the device.
An unknown state of the PWM output signals from the
modulator is illegal and should be avoided, which in
practice means that the PWM processor must be powered
up and initialized before RESET is de-asserted HIGH to
the back end.
POWERING DOWN
For power down of the back end, an opposite approach is
necessary. The RESET must be asserted LOW before the
valid PWM signal is removed.
When PWM processors are used with TI PurePath Digital
amplifiers, the correct timing control of RESET and
PWM_xP is performed by the modulator.
PRECAUTION
The TAS5112A must always start up in the
high-impedance (Hi-Z) state. In this state, the bootstrap
(BST) capacitor is precharged by a resistor on each PWM
output node to ground. See the system configuration. This
ensures that the back end is ready for receiving PWM
pulses, indicating either HIGH- or LOW-side turnon after
RESET is de-asserted to the back end.
With the following pulldown resistor and BST capacitor
size, the charge time is:
PVDD_X
PWM_xP
NOTE:
PVDD should not be powered up before GVDD.
During power up when RESET is asserted LOW, all
MOSFETs are turned off and the two internal half-bridges
are in the high-impedance state (Hi-Z). The bootstrap
capacitors supplying high-side gate drive are not charged
at this point. To comply with the click and pop scheme and
use of non-TI modulators, it is recommended to use a
C = 33 nF, R = 4.7 kΩ
R × C × 5 = 775.5 µs
After GVDD has been applied, it takes approximately 800
µs to fully charge the BST capacitor. During this time,
RESET must be kept low. After approximately 1 ms the
back end BST is charged and ready. RESET can now be
released if the PWM modulator is ready and is streaming
valid PWM signals to the back end. Valid PWM signals are
switching PWM signals with a frequency between
350–400 kHz. A constant HIGH level on the PWM+ would
force the high-side MOSFET ON until it eventually ran out
of BST capacitor energy. Putting the device in this
condition should be avoided.
13
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
In practice this means that the DVDD-to-PWM processor
(front-end) should be stable and initialization should be
completed before RESET is de-asserted to the back end.
The device can be recovered by toggling RESET low and
then high, after all errors are cleared.
Overcurrent (OC) Protection
CONTROL I/O
Shutdown Pin: SD
The SD pin functions as an output pin and is intended for
protection-mode signaling to, for example, a controller or
other front-end device. The pin is open-drain with an
internal pullup resistor to DVDD.
The logic output is, as shown in the following table, a
combination of the device state and RESET input:
Overtemperature (OT) Protection
A dual temperature protection system asserts a warning
signal when the device junction temperature exceeds
125°C. The OT protection circuit is shared by all
half-bridges.
SD
RESET
0
0
Reserved
0
1
Device in protection mode, i.e., UV and/or OC
and/or OT error
Undervoltage (UV) Protection
1(2)
0
Device set high-impedance (Hi-Z), SD forced high
1
1
Normal operation
Undervoltage lockout occurs when GVDD is insufficient
for proper device operation. The UV protection system
protects the device under power-up and power-down
situations. The UV protection circuits are shared by all
half-bridges.
(2)
DESCRIPTION
The device has individual forward current protection on
both high-side and low-side power stage FETs. The OC
protection works only with the demodulation filter present
at the output. See Demodulation Filter Design in the
Application Information section of the data sheet for design
constraints.
SD is pulled high when RESET is asserted low independent
of chip state (i.e., protection mode). This is desirable to
maintain compatibility with some TI PWM front ends.
Temperature Warning Pin: OTW
The OTW pin gives a temperature warning signal when
temperature exceeds the set limit. The pin is of the
open-drain type with an internal pullup resistor to DVDD.
OTW
DESCRIPTION
0
Junction temperature higher than 125°C
1
Junction temperature lower than 125°C
Reset Function
The reset has two functions:
D
Reset is used for re-enabling operation after a
latching error event.
D
Reset is used for disabling output stage
switching (mute function).
Overall Reporting
The SD pin, together with the OTW pin, gives chip state
information as described in Table 1.
The error latch is cleared on the falling edge of reset and
normal operation is resumed when reset goes high.
Table 1. Error Signal Decoding
OTW
SD
DESCRIPTION
0
0
Overtemperature error (OTE)
0
1
Overtemperature warning (OTW)
1
0
Overcurrent (OC) or undervoltage (UV) error
1
1
Normal operation, no errors/warnings
Chip Protection
The TAS5112A protection function is implemented in a
closed loop with, for example, a system controller and TI
PWM processor. The TAS5112A contains three individual
systems protecting the device against error conditions. All
of the error events covered result in the output stage being
set in a high-impedance state (Hi-Z) for maximum
protection of the device and connected equipment.
14
PROTECTION MODE
Autorecovery (AR) After Errors (PMODE0)
In autorecovery mode (PMODE0) the TAS5112A is
self-supported in handling of error situations. All protection
systems are active, setting the output stage in the
high-impedance state to protect the output stage and
connected equipment. However, after a short time period
the device autorecovers, i.e., operation is automatically
resumed provided that the system is fully operational.
The autorecovery timing is set by counting PWM input
cycles, i.e., the timing is relative to the switching frequency.
The AR system is common to both half-bridges.
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
Timing and Function
Table 3. Output Mode Selection
The function of the autorecovery circuit is as follows:
1. An error event occurs and sets the
protection latch (output stage goes Hi-Z).
2. The counter is started.
3. After n/2 cycles, the protection latch is
cleared but the output stage remains Hi-Z
(identical to pulling RESET low).
4. After n cycles, operation is resumed
(identical to pulling RESET high) (n = 512).
Error
Protection
Latch
Shutdown
M3
OUTPUT MODE
0
Bridge-tied load output stage (BTL)
1
Reserved
APPLICATION INFORMATION
DEMODULATION FILTER DESIGN AND
SPIKE CONSIDERATIONS
The output square wave is susceptible to overshoots
(voltage spikes). The spike characteristics depend on
many elements, including silicon design and application
design and layout. The device should be able to handle
narrow spike pulses, less than 65 ns, up to 65 volts peak.
For more detailed information, see TI application report
SLEA025.
The PurePath Digital amplifier outputs are driven by
heavy-duty DMOS transistors in an H-bridge
configuration. These transistors are either off or fully on,
which reduces the DMOS transistor on-state resistance,
RDSon, and the power dissipated in the device, thereby
increasing efficiency.
SD
Autorecovery
PWM
Counter
AR-RESET
Figure 11. Autorecovery Function
Latching Shutdown on All Errors (PMODE1)
In latching shutdown mode, all error situations result in a
power down (output stage Hi-Z). Re-enabling can be done
by toggling the RESET pin.
The result is a square-wave output signal with a duty cycle
that is proportional to the amplitude of the audio signal. It
is recommended that a second-order LC filter be used to
recover the audio signal. For this application, EMI is
considered important; therefore, the selected filter is the
full-output type shown in Figure 12.
TAS51xx
Output A
L
All Protection Systems Disabled (PMODE2)
In PMODE2, all protection systems are disabled. This
mode is purely intended for testing and characterization
purposes and thus not recommended for normal device
operation.
R(Load)
C1A
C2
C1B
Output B
L
MODE Pins Selection
The protection mode is selected by shorting M1/M2 to
DREG or DGND according to Table 2.
Table 2. Protection Mode Selection
M1
M2
0
0
Autorecovery after errors (PMODE 0)
PROTECTION MODE
0
1
Latching shutdown on all errors (PMODE 1)
1
0
All protection systems disabled (PMODE 2)
1
1
Reserved
The output configuration mode is selected by shorting the
M3 pin to DREG or DGND according to Table 3.
Figure 12. Demodulation Filter
The main purpose of the output filter is to attenuate the
high-frequency switching component of the PurePath
Digital amplifier while preserving the signals in the audio
band.
Design of the demodulation filter affects the performance
of the power amplifier significantly. As a result, to ensure
proper operation of the overcurrent (OC) protection circuit
and meet the device THD+N specifications, the selection
of the inductors used in the output filter must be considered
according to the following. The rule is that the inductance
15
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
should remain stable within the range of peak current seen
at maximum output power and deliver at least 5 µH of
inductance at 15 A.
If this rule is observed, the TAS5112A does not have
distortion issues due to the output inductors, and
overcurrent conditions do not occur due to inductor
saturation in the output filter.
Another parameter to be considered is the idle current loss
in the inductor. This can be measured or specified as
inductor dissipation (D). The target specification for
dissipation is less than 0.05.
In general, 10-µH inductors suffice for most applications.
The frequency response of the amplifier is slightly altered
by the change in output load resistance; however, unless
tight control of frequency response is necessary (better
than 0.5 dB), it is not necessary to deviate from 10 µH.
The graph in Figure 13 displays the inductance vs current
characteristics of two inductors that are recommended for
use with the TAS5112A.
INDUCTANCE
vs
CURRENT
11
The thermally augmented package provided with the
TAS5112A is designed to be interfaced directly to
heatsinks using a thermal interface compound (for
example, Wakefield Engineering type 126 thermal
grease.) The heatsink then absorbs heat from the ICs and
couples it to the local air. If the heatsink is carefully
designed, this process can reach equilibrium and heat can
be continually removed from the ICs. Because of the
efficiency of the TAS5112A, heatsinks can be smaller than
those required for linear amplifiers of equivalent
performance.
RθJA is a system thermal resistance from junction to
ambient air. As such, it is a system parameter with roughly
the following components:
D
RθJC (the thermal resistance from junction to
case, or in this case the metal pad)
D
D
Thermal grease thermal resistance
Heatsink thermal resistance
The thermal grease thermal resistance can be calculated
from the exposed pad area and the thermal grease
manufacturer’s area thermal resistance (expressed in
°C-in2/W). The area thermal resistance of the example
thermal grease with a 0.002-inch thick layer is about 0.1
°C-in2/W. The approximate exposed pad area is as
follows:
9
L - Inductance - µH
THERMAL INFORMATION
RθJC has been provided in the General Information
section.
DFB1310A
10
DASL983XX-1023
8
7
6
56-pin HTSSOP
5
0.045 in2
Dividing the example thermal grease area resistance by
the surface area gives the actual resistance through the
thermal grease for both ICs inside the package:
4
0
5
10
15
I - Current - A
Figure 13. Inductance Saturation
The selection of the capacitor that is placed across the
output of each inductor (C2 in Figure 12) is simple. To
complete the output filter, use a 0.47-µF capacitor with a
voltage rating at least twice the voltage applied to the
output stage (PVDD).
This capacitor should be a good quality polyester dielectric
such as a Wima MKS2-047ufd/100/10 or equivalent.
16
In order to minimize the EMI effect of unbalanced ripple
loss in the inductors, 0.1-µF 50-V SMD capacitors (X7R or
better) (C1A and C1B in Figure 12) should be added from
the output of each inductor to ground.
56-pin HTSSOP
2.27 °C/W
The thermal resistance of thermal pads is generally
considerably higher than a thin thermal grease layer.
Thermal tape has an even higher thermal resistance.
Neither pads nor tape should be used with either of these
two packages. A thin layer of thermal grease with careful
clamping of the heatsink is recommended. It may be
difficult to achieve a layer 0.001-inch thick or less, so the
modeling below is done with a 0.002-inch thick layer,
which may be more representative of production thermal
grease thickness.
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
Table 5. Case 2 (2 × 50 W Unclipped Into 6 Ω,
Channels in Separate Packages) (1)
Heatsink thermal resistance is generally predicted by the
heatsink vendor, modeled using a continuous flow
dynamics (CFD) model, or measured.
Thus, for a single monaural IC, the system RθJA = RθJC +
thermal grease resistance + heatsink resistance.
Table 4, Table 5, and Table 6 indicate modeled
parameters for one or two TAS5112A ICs on a single
heatsink. The final junction temperature is set at 110°C in
all cases. It is assumed that the thermal grease is 0.002
inch thick and that it is similar in performance to Wakefield
Type 126 thermal grease. It is important that the thermal
grease layer is ≤0.002 inches thick and that thermal pads
or tape are not used in the pad-to-heatsink interface due
to the high power density that results in these extreme
power cases.
Table 4. Case 1 (2 × 50 W Unclipped Into 6 Ω,
Both Channels in Same IC) (1)
56-Pin HTSSOP
Ambient temperature
25°C
Power to load (per channel)
50 W (unclipped)
Power dissipation
4.5 W
Delta T inside package
5.1°C
Delta T through thermal grease
18.6°C
Required heatsink thermal resistance
6.9°C/W
Junction temperature
110°C
System RθJA
19°C/W
RθJA * power dissipation
85°C
Junction temperature
85°C + 25°C = 110°C
(1)
In this case, the power is separated into two packages. Note that
this allows a considerably smaller heatsink because twice as much
area is available for heat transfer through the thermal grease. For
this reason, separating the stereo channels into two ICs is
recommended in full-power stereo tests made on multichannel
systems.
Table 6. Case 2A (2 × 60 W Into 6 Ω, Channels in
Separate IC Packages) (1)
56-Pin HTSSOP
56-Pin HTSSOP
Ambient temperature
25°C
Ambient temperature
25°C
Power to load (per channel)
60 W (10% THD)
Power to load (per channel)
50 W (unclipped)
Power dissipation per channel
5.4 W
Power dissipation
4.5 W
Delta T inside package
Delta T inside package
10.2°C, note 2 ×
channel dissipation
6.1°C, note 2 ×
channel dissipation
Delta T through thermal grease
Delta T through thermal grease
37.1°C, note 2 ×
channel dissipation
22.3°C, note 2 ×
channel dissipation
Required heatsink thermal resistance
5.3°C/W
Required heatsink thermal resistance
4.2°C/W
Junction temperature
110°C
Junction temperature
110°C
System RθJA
15.9°C/W
System RθJA
19°C/W
RθJA * power dissipation
85°C
RθJA * power dissipation
85°C
Junction temperature
85°C + 25°C = 110°C
Junction temperature
85°C + 25°C = 110°C
(1)
This case represents a stereo system with only one package. See
Case 2 and Case 2A if doing a full-power, 2-channel test in a
multichannel system.
(1)
In this case, the power is also separated into two packages, but
overdriving causes clipping to 10% THD. In this case, the high
power requires extreme care in attachment of the heatsink to
ensure that the thermal grease layer is ≤ 0.002 inches thick. Note
that this power level should not be attempted with both channels in
a single IC because of the high power density through the thermal
grease layer.
17
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
DCA THERMAL INFORMATION
The thermally enhanced DCA package is based on the
56-pin HTSSOP, but includes a thermal pad (see
Figure 14) to provide an effective thermal contact between
the IC and the PCB.
The PowerPAD™ package (thermally enhanced
HTSSOP) combines fine-pitch, surface-mount technology
with thermal performance comparable to much larger
power packages.
Thermal
Pad
8,20 mm
7,20 mm
The PowerPAD package is designed to optimize the heat
transfer to the PWB. Because of the small size and limited
mass of an HTSSOP package, thermal enhancement is
achieved by improving the thermal conduction paths that
remove heat from the component. The thermal pad is
formed using a patented lead-frame design and
manufacturing technique to provide a direct connection to
the heat-generating IC. When this pad is soldered or
otherwise thermally coupled to an external heat dissipater,
high power dissipation in the ultrathin, fine-pitch,
surface-mount package can be reliably achieved.
Thermal Methodology for the DCA 56-Pin,
2y15-W, 8-W Package
3,90 mm
2,98 mm
The thermal design for the DCA part (e.g., thermal pad
soldered to the board) should be similar to the design in the
following figures. The cooling approach is to conduct the
dissipated heat into the via pads on the board, through the
vias in the board, and into a heatsink (aluminum bar) (if
necessary).
Figure 14 shows a recommended land pattern on the
PCB.
18
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
Copper Layer − Component Side
Solder
PowerPAD
TAS5112ACDA
5y11 Vias (f 0.3 mm)
4 mm
8 mm
Figure 14. Recommended Land Pattern
The lower via pad area, slightly larger than the IC pad itself,
is exposed with a window in the solder resist on the bottom
surface of the board. It is not coated with solder during the
board construction to maintain a flat surface. In production,
this can be accomplished with a peelable solder mask.
An aluminum bar is used to keep the through-hole leads
from shorting to the chassis. The thermal compound
shown has a pad-to-aluminum bar thermal resistance of
about 3.2°C/W.
The chassis provides the only heatsink to air and is chosen
as representative of a typical production cooling approach.
19
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
Insulating
Front Panel
Stereo
Amplifier
Board
Insulating
Back Panel
Plastic Top
PCB (3.65C/W)
56-Pin DCA Package
(1.145C/W)
ÔÔÔ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÔÔÔ
Wakefield Type 126
Thermal Compound
Under Via Pads
(3.2°C/W)
1 mm
8-mm y 10-mm y 40-mm
Aluminum Bar
(0.09°C/W)
Wakefield Type 126
Thermal Compound
(0.1°C/W)
Aluminum Chassis 7.2 in. y 1 in. y 0.1 in. Thick
Sides of U-Shaped Chassis Are 1.25 in. High (3.9°C/W)
Figure 15. 56-Pin DCA Package Cross-Sectional View (Side)
Plastic Top
PCB (3.6°C/W)
Stereo
Amplifier
Board
56-Pin DCA Package
(1.14°C/W)
(2 Places)
4-40 Machine Screw
With Star Washer
and Nut
(3 Places)
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÖÖÖ
ÔÔÔ
ÖÖ
ÔÔ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
Wakefield Type 126
Thermal Compound
(0.1°C/W)
Aluminum Chassis 7.2 in. y 1 in. y 0.1 in. Thick
Sides of U-Shaped Chassis Are 1.25 in. High (3.9°C/W)
Wakefield Type 126
Thermal Compound
Under Via Pads
(3.2°C/W)
8-mm y 10-mm y 40-mm
Aluminum Bar
(0.09°C/W)
Figure 16. Spatial Separation With Multiple Packages
The land pattern recommendation shown in Figure 14 is
for optimal performance with aluminum bar thermal
resistance of 0.09°C/W. The following table shows the
20
decrease in thermal resistance through the PCB with a
corresponding increase in the land pattern size. Use the
table for thermal design tradeoffs.
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
LAND PATTERN
PCB THERMAL
RESISTANCE
7 × 13 vias (5 × 10 mm)
2.2°C/W
5 × 11 vias (4 × 8 mm)
3.6°C/W
Thermal
Pad
To make this system work properly, the following design
rules must be followed when using the TAS5112A back
end:
D
The relative timing between the PWM_AP/M_x
signals and their corresponding VALID_x signal
should not be skewed by inserting delays,
because this increases the audible amplitude
level of the click.
D
The output stage must start switching from a
fully discharged output filter capacitor. Because
the output stage prior to operation is in the
high-impedance state, this is done by having a
passive pulldown resistor on each speaker
output to GND (see System Configuration Used
for Characterization).
8,20 mm
7,20 mm
Other things that can affect the audible click level:
3,90 mm
2,98 mm
Figure 17. Thermal Pad Dimensions for DCA
Package
D
The spectrum of the click seems to follow the
speaker impedance vs. frequency curve—the
higher the impedance, the higher the click
energy.
D
Crossover filters used between woofer and
tweeter in a speaker can have high impedance
in the audio band, which should be avoided if
possible.
Another way to look at it is that the speaker impulse
response is a major contributor to how the click energy is
shaped in the audio band and how audible the click will be.
The following mode transitions feature click and pop
reduction.
STATE
CLICK AND POP REDUCTION
TI modulators feature a pop and click reduction system
that controls the timing when switching starts and stops.
Going from nonswitching to switching operation causes a
spectral energy burst to occur within the audio bandwidth,
which is heard in the speaker as an audible click, for
instance, after having asserted RESET LH during a
system start-up.
Normal(1)
→ Mute
CLICK AND
POP REDUCED
Yes
Mute
→
Normal(1)
Yes
Normal(1)
Error recovery
→
(ERRCVY)
Yes
Error recovery
→ Normal(1)
Yes
Normal(1)
→ Hard reset
No
Hard reset
(1)
→
Normal(1)
Yes
Normal = switching
21
TAS5112A
www.ti.com
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
REFERENCES
6.
TAS5036A Six-Channel Digital Audio
Processor data manual—TI (SLES061)
PWM
1.
TAS5000 Digital Audio PWM Processor data
manual—TI (SLAS270)
7.
TAS3103 Digital Audio Processor With 3D Effects
data manual—TI (SLES038)
2.
True Digital Audio Amplifier TAS5001 Digital Audio
PWM Processor data sheet—TI (SLES009)
8.
True Digital Audio Amplifier TAS5010 Digital Audio
PWM Processor data sheet—TI (SLAS328)
Digital Audio Measurements application report—TI
(SLAA114)
9.
PowerPAD™ Thermally Enhanced
technical brief—TI (SLMA002)
3.
4.
True Digital Audio Amplifier TAS5012 Digital Audio
PWM Processor data sheet—TI (SLES006)
5.
TAS5026 Six-Channel Digital Audio
Processor data manual—TI (SLES041)
22
PWM
Package
10. System Design Considerations for True Digital
Audio Power Amplifiers application report—TI
(SLAA117)
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TAS5112ADCA
ACTIVE
HTSSOP
DCA
56
35
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TAS5112A
TAS5112ADFD
ACTIVE
HTSSOP
DFD
56
35
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
5112A
TAS5112ADFDR
ACTIVE
HTSSOP
DFD
56
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
5112A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of