TAS5132DDVG4

TM TAS5132 www.ti.com SLES190 – DECEMBER 2006 STEREO DIGITAL AMPLIFIER POWER STAGE FEATURES • • • • • • • • • • • • • 2×20 W at 10% THD+N Into 8-Ω BTL 2×25 W at 10% THD+N Into 6-Ω BTL >100-dB SNR (A-Weighted) 90%) With 140-mΩ Output MOSFETs Power-On Reset for Protection on Power Up Without Any Power-Supply Sequencing Integrated Self-Protection Circuits Including Undervoltage, Overtemperature, Overload, Short Circuit PWM Activity Detector to detect stopped PWM inputs and protect the system Error Reporting EMI Compliant When Used With Recommended System Design Intelligent Gate Drive Pin Compatible With the TAS5142DDV A low-cost, high-fidelity audio system can be built using a TI chipset, comprising a modulator (e.g., TAS5086) and the TAS5132. This system only requires a simple passive LC demodulation filter to deliver high-quality, high-efficiency audio amplification with proven EMI compliance. This device requires two power supplies, at 12 V for GVDD and VDD, and at 18 V for PVDD. The TAS5132 does not require power-up sequencing due to internal power-on reset. The efficiency of this digital amplifier is greater than 90% into 8 Ω, which enables the use of smaller power supplies and heatsinks. The TAS5132 has an innovative protection system integrated on chip, safeguarding the device against a wide range of fault conditions that could damage the system. These safeguards are short-circuit protection, overcurrent protection, undervoltage protection, and overtemperature protection. The TAS5132 has a new proprietary current-limiting circuit that reduces the possibility of device shutdown during high-level music transients. BTL OUTPUT POWER vs SUPPLY VOLTAGE 30 TC = 75°C THD+N @ 10% 25 • • • • Televisions Mini/Micro Audio Systems DVD Receivers Home Theaters DESCRIPTION The TAS5132 is an integrated stereo digital amplifier power stage with an advanced protection system. The TAS5132 is capable of driving a 6-Ω bridge-tied load (BTL) at up to 25 W per channel with low integrated noise at the output, low THD+N performance, and low idle power dissipation. PO − Output Power − W APPLICATIONS 20 6Ω 15 10 8Ω 5 0 0 5 10 15 20 PVDD − Supply Voltage − V G002 PurePath Digital™ These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Digital, PowerPAD are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TAS5132 www.ti.com SLES190 – DECEMBER 2006 GENERAL INFORMATION Terminal Assignment The TAS5132 is available in a thermally enhanced package: • 44-pin HTSSOP PowerPAD™ package (DDV) This package type contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heatsink. DDV PACKAGE (TOP VIEW) GVDD_B OTW NC NC SD PWM_A RESET_AB PWM_B OC_ADJ GND AGND VREG M3 M2 M1 PWM_C RESET_CD PWM_D NC NC VDD GVDD_C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 GVDD_A BST_A NC PVDD_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D PVDD_D NC BST_D GVDD_D P0016-02 2 Submit Documentation Feedback TAS5132 www.ti.com SLES190 – DECEMBER 2006 GENERAL INFORMATION (continued) MODE Selection Pins MODE PINS PWM INPUT M3 M2 M1 0 0 0 2N 0 0 1 Reserved 0 1 0 1N (1) 0 1 1 1N (1) 1N (1) 1 0 0 1 0 1 2N (1) (2) 1 1 0 1 1 1 (1) (1) OUTPUT CONFIGURATION PROTECTION SCHEME 2 channels BTL output BTL mode (2) AD modulation 2 channels BTL output BTL mode (2) AD modulation 1 channel PBTL output PBTL mode. Only PWM_A input is used. 4 channels SE output Protection works similarly to BTL mode (2). Only difference in SE mode is that OUT_X is Hi-Z instead of a pulldown through internal pulldown resistor. AD/BD modulation AD modulation AD/BD modulation 2 channels BTL output Protection system work similarly to BTL mode (2) (0, 0, 0); however the PWM input protection is disabled. Also, overcurrent detection will be more sensitive and will latch if an error occurs. Reserved The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific mode. An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels. Package Heat Dissipation Ratings (1) (1) (2) PARAMETER TAS5132DDV RθJC (°C/W)—2 BTL or 4 SE channels (8 transistors) 1.4 RθJC (°C/W)—1 BTL or 2 SE channel(s) (4 transistors) 2.6 RθJC (°C/W)—(1 transistor) 8.7 Pad area (2) 15 mm2 JC is junction-to-case, CH is case-to-heatsink. RθCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The RθCH with this condition is 2.5°C/W for the DDV package. Submit Documentation Feedback 3 TAS5132 www.ti.com SLES190 – DECEMBER 2006 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VDD to AGND –0.3 V to 13.2 V GVDD_X to AGND –0.3 V to 13.2 V PVDD_X to GND_X (2) –0.3 V to 30 V OUT_X to GND_X (2) –0.3 V to 30 V BST_X to GND_X (2) –0.3 V to 43.2 V VREG to AGND –0.3 V to 4.2 V GND_X to GND –0.3 V to 0.3 V GND_X to AGND –0.3 V to 0.3 V GND to AGND –0.3 V to 0.3 V PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V RESET_X, SD, OTW to AGND –0.3 V to 7 V Maximum continuous sink current (SD, OTW) 9 mA Maximum operating junction temperature range, TJ 0°C to 150°C Storage temperature range –40°C to 125°C Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 260°C Minimum pulse duration, low 50 ns (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. ORDERING INFORMATION TA PACKAGE DESCRIPTION 0°C to 70°C TAS5132DDV 44-pin HTSSOP For the most current specification and package information, see the TI Web site at www.ti.com. 4 Submit Documentation Feedback TAS5132 www.ti.com SLES190 – DECEMBER 2006 Terminal Functions TERMINAL NAME NO. FUNCTION (1) DESCRIPTION AGND 11 P Analog ground BST_A 43 P HS bootstrap supply (BST). External capacitor to OUT_A required. BST_B 34 P HS bootstrap supply (BST). External capacitor to OUT_B required. BST_C 33 P HS bootstrap supply (BST). External capacitor to OUT_C required. BST_D 24 P HS bootstrap supply (BST). External capacitor to OUT_D required. GND 10 P Ground GND_A 38 P Power ground for half-bridge A GND_B 37 P Power ground for half-bridge B GND_C 30 P Power ground for half-bridge C GND_D 29 P Power ground for half-bridge D GVDD_A 44 P Gate-drive voltage supply. Requires 0.1-µF capacitor to GND. GVDD_B 1 P Gate-drive voltage supply. Requires 0.1-µF capacitor to GND. GVDD_C 22 P Gate-drive voltage supply. Requires 0.1-µF capacitor to GND. GVDD_D 23 P Gate-drive voltage supply. Requires 0.1-µF capacitor to GND. M1 15 I Mode selection 1 M2 14 I Mode selection 2 M3 13 I Mode selection 3 NC 3, 4, 19, 20, 25, 42 – No connect. Pins may be grounded. OC_ADJ 9 O Analog overcurrent programming. Requires resistor to ground. OTW 2 O Overtemperature warning signal, open drain, active low OUT_A 39 O Output, half-bridge A OUT_B 36 O Output, half-bridge B OUT_C 31 O Output, half-bridge C OUT_D 28 O Output, half-bridge D PVDD_A 40, 41 P Power supply input for half-bridge A. Requires close decoupling of 0.1-µF capacitor to GND_A. PVDD_B 35 P Power supply input for half-bridge B. Requires close decoupling of 0.1-µF capacitor to GND_B. PVDD_C 32 P Power supply input for half-bridge C. Requires close decoupling of 0.1-µF capacitor to GND_C. PVDD_D 26, 27 P Power supply input for half-bridge D. Requires close decoupling of 0.1-µF capacitor to GND_D. PWM_A 6 I Input signal for half-bridge A PWM_B 8 I Input signal for half-bridge B PWM_C 16 I Input signal for half-bridge C PWM_D 18 I Input signal for half-bridge D RESET_AB 7 I Reset signal for half-bridge A and half-bridge B, active low RESET_CD 17 I Reset signal for half-bridge C and half-bridge D, active low SD 5 O Shutdown signal, open-drain, active-low VDD 21 P Power supply for digital voltage regulator. Requires 0.1-µF capacitor in parallel with a 10-µF capacitor to GND. VREG 12 P Digital regulator supply filter. Requires 0.1-µF capacitor to AGND. (1) I = input, O = output, P = power Submit Documentation Feedback 5 TAS5132 www.ti.com SLES190 – DECEMBER 2006 SYSTEM BLOCK DIAGRAM OTW System Microcontroller SD TAS5508 OTW SD BST_A BST_B RESET_AB RESET_CD VALID PWM_A LeftChannel Output OUT_A Output H-Bridge 1 Input H-Bridge 1 PWM_B OUT_B Bootstrap Capacitors 2nd-Order L-C Output Filter for Each Half-Bridge 2-Channel H-Bridge BTL Mode OUT_C PWM_C 4 18 V PVDD System Power Supply GND 12 V 4 PVDD Power Supply Decoupling BST_D Bootstrap Capacitors 4 GVDD VDD VREG Power Supply Decoupling Hardwire OC Limit GND GVDD (12 V)/VDD (12 V) VAC 6 OC_ADJ AGND VDD M3 OUT_D 2nd-Order L-C Output Filter for Each Half-Bridge BST_C VREG M2 GND PVDD_A, B, C, D M1 GVDD_A, B, C, D Input H-Bridge 2 PWM_D Hardwire Mode Control Output H-Bridge 2 GND_A, B, C, D RightChannel Output B0047-01 Submit Documentation Feedback TAS5132 www.ti.com SLES190 – DECEMBER 2006 FUNCTIONAL BLOCK DIAGRAM VDD Undervoltage Protection OTW Internal Pullup Resistors to VREG SD M1 Protection and I/O Logic M2 M3 4 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD Isense OC_ADJ GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D BTL/PBTL−Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv . Ctrl. Timing Gate Drive OUT_C BTL/PBTL−Configuration Pulldown Resistor GND_C GVDD_B BST_B PVDD_B PWM_B PWM Rcv . Ctrl. Timing Gate Drive OUT_B BTL/PBTL−Configuration Pulldown Resistor GND_B GVDD_A BST_A PVDD_A PWM_A PWM Rcv . Ctrl. Timing Gate Drive OUT_A BTL/PBTL−Configuration Pulldown Resistor GND_A B0034-02 Submit Documentation Feedback 7 TAS5132 www.ti.com SLES190 – DECEMBER 2006 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT PVDD_X Half-bridge supply DC supply voltage 0 18 19 V GVDD_X Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator input DC supply voltage 10.8 12 13.2 V RL (BTL) RL (SE) Output filter: L = 10 µH, C = 470 nF. Output AD modulation, switching frequency > 350 kHz Load impedance RL (PBTL) LOutput (BTL) LOutput (SE) 6-8 Ω 3-4 3-4 10 Minimum output inductance under short-circuit condition Output-filter inductance µH 10 LOutput (PBTL) 10 FPWM PWM frame rate TJ Junction temperature 192 384 0 432 kHz 125 °C AUDIO SPECIFICATIONS (BTL) PVDD_X = 18 V, GVDD = VDD = 12 V, BTL mode, RL = 8 Ω, ROC = 22 KΩ, CBST = 33-nF, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75°C (unless otherwise noted). Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER PO Power output per channel, DDV package MIN TYP 26 RL = 8 Ω, 10% THD, clipped input signal 20 RL = 6 Ω, 0 dBFS, unclipped input signal 20 RL = 8 Ω, 0 dBFS, unclipped input signal 16 0 dBFS MAX UNIT W