TAS5162DKD

TM TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 2 x 210 Watt STEREO DIGITAL AMPLIFIER POWER STAGE • • • • • • • • • • • • • 2×160 W at 10% THD+N Into 8-Ω BTL 2×210 W at 10% THD+N Into 6-Ω BTL 1×300 W at 10% THD+N Into 4-Ω PBTL (1) >110 dB SNR (A-Weighted, TAS5518 Modulator) 90%) With 80-mΩ Output MOSFETs Power-On Reset for Protection on Power Up Without Any Power-Supply Sequencing Integrated Self-Protection Circuits Including Undervoltage, Overtemperature, Overload, Short Circuit Error Reporting EMI Compliant When Used With Recommended System Design Intelligent Gate Drive Mid-Z Ramp Compatible for reduced "pop noise" This system only requires a simple passive LC demodulation filter to deliver high-quality, high-efficiency audio amplification with proven EMI compliance. This device requires two power supplies, at 12 V for GVDD and VDD, and at 50V for PVDD. The TAS5162 does not require power-up sequencing due to internal power-on reset. The efficiency of this digital amplifier is greater than 90% into 6 Ω, which enables the use of smaller power supplies and heatsinks. The TAS5162 has an innovative protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These safeguards are short-circuit protection, overcurrent protection, undervoltage protection, and overtemperature protection. The TAS5162 has a new proprietary current-limiting circuit that reduces the possibility of device shutdown during high-level music transients. A new programmable overcurrent detector allows the use of lower-cost inductors in the demodulation output filter. BTL OUTPUT POWER vs SUPPLY VOLTAGE 220 6W 180 APPLICATIONS • • • TC = 75°C, Digital Gain = 2.5 dB 200 PO - Output Power - W FEATURES Mini/Micro Audio System DVD Receiver Home Theater 160 140 4W 120 8W 100 80 60 DESCRIPTION 40 The TAS5162 is a high performance, integrated stereo digital amplifier power stage with an improved protection system. The TAS5162 is capable of driving a 6-Ω bridge-tied load (BTL) at up to 210 W per channel at THD = 10%, low integrated noise at the output, low THD+N performance without clipping, and low idle power dissipation. A low-cost, high-fidelity audio system can be built using a TI chipset, comprising a modulator (e.g., TAS5508) and the TAS5162. PurePath Digital™ 20 0 0 (1) 5 10 15 20 25 30 35 40 45 PVDD - Supply Voltage (BTL) - Vrms 50 The DDV package will deliver the stated maximum power levels; however, this is dependant on system configuration. The smaller pad area also makes the thermal interface to the heatsink more important. For multichannel systems that require two channels to be driven at full power with the DDV package option, it is recommended to design the system so that the two channels are in two separate devices. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Digital, PowerPad are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. GENERAL INFORMATION Terminal Assignment The TAS5162 is available in two thermally enhanced packages: • 36-pin PSOP3 package (DKD) • 44-pin HTSSOP PowerPad™ package (DDV) Both package types contain a heat slug that is located on the top side of the device for convenient thermal coupling to the heatsink. DDV PACKAGE (TOP VIEW) DKD PACKAGE (TOP VIEW) GVDD_B OTW SD PWM_A RESET_AB PWM_B OC_ADJ GND AGND VREG M3 M2 M1 PWM_C RESET_CD PWM_D VDD GVDD_C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GVDD_A BST_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D BST_D GVDD_D P0018-01 GVDD_B OTW NC NC SD PWM_A RESET_AB PWM_B OC_ADJ GND AGND VREG M3 M2 M1 PWM_C RESET_CD PWM_D NC NC VDD GVDD_C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 GVDD_A BST_A NC PVDD_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D PVDD_D NC BST_D GVDD_D P0016-02 2 Submit Documentation Feedback TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 GENERAL INFORMATION (continued) MODE Selection Pins for Both Packages MODE PINS M3 M2 M1 0 0 0 0 0 1 PWM INPUT 2N 2N (2) BTL mode, full protection AD/BD modulation 2 channels BTL output BTL mode, latching shutdown 1 0 1N 0 1 1 1N (1) 1N (1) 0 0 1 0 1 1 1 0 1 1 1 (1) (2) 2 channels BTL output 0 1 PROTECTION SCHEME AD/BD modulation (1) 1N (1) (1) (1) OUTPUT CONFIGURATION AD modulation 2 channels BTL output AD modulation 1 channel PBTL output AD modulation AD modulation BTL mode, full protection (2) (2) PBTL mode, full protection. Only PWM_A input is used. 4 channels SE output Protection works similarly to BTL mode (2). Only difference in SE mode is that OUT_X is Hi-Z instead of a pulldown through internal pulldown resistor. 4 channels SE output - No PWM Input protection, latching shutdown Protection works similarly to SE Mode (2) (1,0,0); however, the PWM input protection is disabled. Also, overcurrent detection will latch if an error occurs. Reserved The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific mode. An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels. Package Heat Dissipation Ratings (1) (1) (2) PARAMETER TAS5162DKD TAS5162DDV RθJC (°C/W)—2 BTL or 4 SE channels (8 transistors) 1.0 1.1 RθJC (°C/W)—1 BTL or 2 SE channel(s) (4 transistors) 1.5 2.2 RθJC (°C/W)—(1 transistor) 5.0 7.4 Pad area (2) 80 mm2 34 mm2 JC is junction-to-case, CH is case-to-heatsink. RθCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink and both channels active. The RθCH with this condition is 2.6°C/W for the DKD package and 4.0°C/W for the DDV package. Submit Documentation Feedback 3 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TAS5162 VDD to AGND –0.3 V to 13.2 V GVDD_X to AGND –0.3 V to 13.2 V PVDD_X to GND_X (2) –0.3 V to 71 V OUT_X to GND_X (2) –0.3 V to 71V BST_X to GND_X (2) –0.3 V to 79.7 V VREG to AGND –0.3 V to 4.2 V GND_X to GND –0.3 V to 0.3 V GND_X to AGND –0.3 V to 0.3 V GND to AGND –0.3 V to 0.3 V PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V RESET_X, SD, OTW to AGND –0.3 V to 7 V Maximum continuous sink current (SD, OTW) 9 mA Maximum operating junction temperature range, TJ 0°C to 125°C Storage temperature –40°C to 125°C Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 260°C Minimum pulse duration, low 50 ns (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. ORDERING INFORMATION TA PACKAGE DESCRIPTION 0°C to 70°C TAS5162DKD 36-pin PSOP3 0°C to 70°C TAS5162DDV 44-pin HTSSOP For the most current specification and package information, see the TI Web site at www.ti.com. 4 Submit Documentation Feedback TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 Terminal Functions TERMINAL NAME (1) DKD NO. DDV NO. FUNCTION (1) DESCRIPTION AGND 9 11 P Analog ground BST_A 35 43 P HS bootstrap supply (BST), external .033-μF capacitor to OUT_A required BST_B 28 34 P HS bootstrap supply (BST), external .033-μF capacitor to OUT_B required BST_C 27 33 P HS bootstrap supply (BST), external .033-μF capacitor to OUT_C required BST_D 20 24 P HS bootstrap supply (BST), external .033-μF capacitor to OUT_D required GND 8 10 P Ground GND_A 32 38 P Power ground for half-bridge A GND_B 31 37 P Power ground for half-bridge B GND_C 24 30 P Power ground for half-bridge C GND_D 23 29 P Power ground for half-bridge D GVDD_A 36 44 P Gate-drive voltage supply requires 0.1-μF capacitor to AGND GVDD_B 1 1 P Gate-drive voltage supply requires 0.1-μF capacitor to AGND GVDD_C 18 22 P Gate-drive voltage supply requires 0.1-μF capacitor to AGND GVDD_D 19 23 P Gate-drive voltage supply requires 0.1-μF capacitor to AGND M1 13 15 I Mode selection pin M2 12 14 I Mode selection pin M3 11 13 I Mode selection pin NC – 3, 4, 19, 20, 25, 42 – No connect. Pins may be grounded. OC_ADJ 7 9 O Analog overcurrent programming pin requires resistor to ground OTW 2 2 O Overtemperature warning signal, open-drain, active-low OUT_A 33 39 O Output, half-bridge A OUT_B 30 36 O Output, half-bridge B OUT_C 25 31 O Output, half-bridge C OUT_D 22 28 O Output, half-bridge D PVDD_A 34 40, 41 P Power supply input for half-bridge A requires close decoupling of 0.01-μF capacitor in parallel with a 1.0-μF capacitor to GND_A. PVDD_B 29 35 P Power supply input for half-bridge B requires close decoupling of 0.01-μF capacitor in parallel with a 1.0-μF capacitor to GND_B. PVDD_C 26 32 P Power supply input for half-bridge C requires close decoupling of 0.01-μF capacitor in parallel with a 1.0-μF capacitor to GND_C. PVDD_D 21 26, 27 P Power supply input for half-bridge D requires close decoupling of 0.01-μF capacitor in parallel with a 1.0-μF capacitor to GND_D. PWM_A 4 6 I Input signal for half-bridge A PWM_B 6 8 I Input signal for half-bridge B PWM_C 14 16 I Input signal for half-bridge C PWM_D 16 18 I Input signal for half-bridge D RESET_AB 5 7 I Reset signal for half-bridge A and half-bridge B, active-low RESET_CD 15 17 I Reset signal for half-bridge C and half-bridge D, active-low SD 3 5 O Shutdown signal, open-drain, active-low VDD 17 21 P Power supply for digital voltage regulator requires a 47-μF capacitor in parallel with a 0.1-μF capacitor to GND for decoupling. VREG 10 12 P Digital regulator supply filter pin requires 0.1-μF capacitor to AGND. I = input, O = output, P = power Submit Documentation Feedback 5 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 SYSTEM BLOCK DIAGRAM VDD 4 Undervoltage Protection OTW Internal Pullup Resistors to VREG SD M1 Protection and I/O Logic M2 M3 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD Isense OC_ADJ GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D BTL/PBTL−Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv. Ctrl. Timing Gate Drive OUT_C BTL/PBTL−Configuration Pulldown Resistor GND_C GVDD_B BST_B PVDD_B PWM_B PWM Rcv. Ctrl. Timing Gate Drive OUT_B BTL/PBTL−Configuration Pulldown Resistor GND_B GVDD_A BST_A PVDD_A PWM_A PWM Rcv. Ctrl. Timing Gate Drive OUT_A BTL/PBTL−Configuration Pulldown Resistor GND_A B0034-03 6 Submit Documentation Feedback TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 FUNCTIONAL BLOCK DIAGRAM OTW System Microcontroller SD TAS5508 OTW SD BST_A BST_B RESET_AB RESET_CD VALID PWM_A LeftChannel Output OUT_A Output H-Bridge 1 Input H-Bridge 1 PWM_B OUT_B Bootstrap Capacitors 2nd-Order L-C Output Filter for Each Half-Bridge 2-Channel H-Bridge BTL Mode OUT_C PWM_C 4 50 V PVDD System Power Supply GND 12 V 4 PVDD Power Supply Decoupling OC_ADJ AGND VDD M3 OUT_D 2nd-Order L-C Output Filter for Each Half-Bridge BST_C VREG M2 GND PVDD_A, B, C, D M1 GVDD_A, B, C, D Input H-Bridge 2 PWM_D Hardwire Mode Control Output H-Bridge 2 GND_A, B, C, D RightChannel Output BST_D Bootstrap Capacitors 4 GVDD VDD VREG Power Supply Decoupling Hardwire OC Limit GND GVDD (12 V)/VDD (12 V) VAC B0047-01 Submit Documentation Feedback 7 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT PVDD_X Half-bridge supply DC supply voltage 0 50 52.5 V GVDD_X Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator input DC supply voltage 10.8 12 13.2 V 4.6 6-8 2.5 3-8 RL (BTL) RL (SE) Output filter: L = 10 μH, C = 470 nF. Output AD modulation, switching frequency > 350 kHz Load impedance RL (PBTL) LOutput (BTL) LOutput (SE) Minimum output inductance under short-circuit condition Output-filter inductance LOutput (PBTL) FPWM PWM frame rate TJ Junction temperature Ω 4-8 5 10 5 10 5 10 192 384 0 μH 432 kHz 125 °C AUDIO SPECIFICATIONS (BTL) PVDD_X = 50 V, GVDD = VDD = 12 V, BTL mode, RL = 6 Ω, ROC = 22 KΩ, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified. PARAMETER PO Power output per channel, DKD package THD+N Total harmonic distortion + noise Vn Output integrated noise SNR DNR Pidle (1) (2) TEST CONDITIONS Signal-to-noise ratio Dynamic range (1) TAS5162 MIN TYP RL = 4 Ω, 10% THD, clipped input signal (PVDD = 38.5 Volts) 160 RL = 6 Ω, 10% THD, clipped input signal 210 RL = 8 Ω, 10% THD, clipped input signal 160 RL = 4 Ω, 0 dBFS, unclipped input signal (PVDD = 38.5 Volts) 120 RL = 6 Ω, 0 dBFS, unclipped input signal 165 RL = 8 Ω, 0 dBFS, unclipped input signal 125 0 dBFS 1W UNIT W 0.2% 0.09% A-weighted, TAS5508 Modulator 140 A-Weighted, TAS5518 Modulator 85 A-weighted, TAS5508 Modulator 102 A-weighted, TAS5518 Modulator 112 A-weighted, input level = –60 dBFS using TAS5508 modulator 102 A-weighted, input level = –60 dBFS using TAS5518 modulator 112 Power dissipation due to idle losses (IPVDD_X) PO = 0 W, 4 channels switching (2) MAX μV dB dB 2.5 W SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. AUDIO SPECIFICATIONS (Single-Ended Output) PVDD_X = 50 V, GVDD = VDD = 12 V, SE mode, RL = 3 Ω, ROC = 22 KΩ, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended 8 Submit Documentation Feedback TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 AUDIO SPECIFICATIONS (Single-Ended Output) (continued) PVDD_X = 50 V, GVDD = VDD = 12 V, SE mode, RL = 3 Ω, ROC = 22 KΩ, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified. operating conditions unless otherwise specified. PARAMETER PO TEST CONDITIONS Power output per channel, DKD package TAS5162 MIN TYP RL = 3 Ω, 10% THD, clipped input signal 105 RL = 4 Ω, 10% THD, clipped input signal 80 RL = 3 Ω, 0 dBFS, unclipped input signal 80 RL = 4 Ω, 0 dBFS, unclipped input signal 60 MAX UNIT W 0 dBFS 0.2% THD+N Total harmonic distortion + noise Vn Output integrated noise A-weighted 85 μV SNR Signal-to-noise ratio (1) A-weighted 110 dB DNR Dynamic range A-weighted, input level = –60 dBFS using TAS5086 modulator 110 dB Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0 W, 4 channels switching (2) 2.5 W (1) (2) 1W 0.09% SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. AUDIO SPECIFICATIONS (PBTL) PVDD_X = 50 V, GVDD = VDD = 12 V, PBTL mode, RL = 4Ω, ROC = 22 KΩ, 1/2 of an MBRM5100-13 dual, 5A@100V, Schottky diode connected from each output pin to to ground, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified. PARAMETER PO TEST CONDITIONS Power output per channel, DKD package TAS5162 MIN TYP RL = 4 Ω, 10% THD, clipped input signal 300 RL = 4 Ω, 0 dBFS, unclipped input signal 240 RL = 3 Ω, 10% THD, clipped input signal 400 RL = 3 Ω, 0 dBFS, unclipped input signal 300 0 dBFS MAX UNIT W 0.2% THD+N Total harmonic distortion + noise Vn Output integrated noise A-weighted 140 μV SNR Signal-to-noise ratio (1) A-weighted 102 dB A-weighted, input level = –60 dBFS using TAS5508 modulator 102 A-weighted, input level = –60 dBFS using TAS5518 modulator 110 DNR Pidle (1) (2) Dynamic range 1W Power dissipation due to idle losses (IPVDD_X) PO = 0 W, 1 channel switching (2) 0.09% dB 2.5 W SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback 9 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS RL= 6 Ω, FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS TAS5162 MIN TYP MAX 2.95 3.3 3.65 UNIT Internal Voltage Regulator and Current Consumption VREG Voltage regulator, only used as a reference node IVDD VDD supply current IGVDD_X Gate supply current per half-bridge IPVDD_X Half-bridge idle current VDD = 12 V Operating, 50% duty cycle 10 Idle, reset mode mA 6 50% duty cycle V 8 mA Reset mode 0.3 50% duty cycle, without output filter or load 15 mA 500 μA Reset mode, no switching Output Stage MOSFETs RDSon,LS Drain-to-source resistance, LS TJ = 25°C, includes metallization resistance, GVDD = 12 V 90 mΩ RDSon,HS Drain-to-source resistance, HS TJ = 25°C, includes metallization resistance, GVDD = 12 V 90 mΩ 8.5 V I/O Protection Undervoltage protection limit, GVDD_X Vuvp,G Vuvp,hyst (1) 400 mV °C OTW (1) Overtemperature warning OTWHYST (1) Temperature drop needed below OTW temp. for OTW to be inactive after the OTW event OTE (1) Overtemperature error OTEOTWdifferential (1) OTE-OTW differential 25 °C OTEHYST (1) A reset needs to occur for SD for be released following an OTE event. 25 °C OLPC Overload protection counter FPWM = 384 kHz 1.3 ms IOC Overcurrent limit protection Resistor—programmable, nominal, ROCP = 22 kΩ 12 A IOCT Overcurrent response time Time from application of short condition to Hi-Z of affected 1/2 bridge 250 ns ROCP OC programming resistor range Resistor tolerance = 5% RPD Internal pulldown resistor at the output of each half-bridge Connected when RESET is active to provide bootstrap capacitor charge. Not used in SE mode 115 125 135 °C 25 145 155 22 165 69 1.0 °C kΩ kΩ Static Digital Specifications VIH High-level input voltage VIL Low-level input voltage Leakage Input leakage current PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD 2 V -100 0.8 V 100 μA kΩ OTW/SHUTDOWN (SD) RINT_PU Internal pullup resistance, OTW to VREG, SD to VREG VOH High-level output voltage VOL Low-level output voltage IO = 4 mA 0.2 FANOUT Device fanout OTW, SD No external pullup 30 (1) 10 Internal pullup resistor External pullup of 4.7 kΩ to 5 V Specified by design Submit Documentation Feedback 20 26 35 2.95 3.3 3.65 4.5 5 0.4 V V Devices TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 5 220 PVDD (4 W) = 38.5 V, TC = 75°C, Digital Gain = 2.5 dB 1 0.5 4W 6W 0.1 0.05 160 140 4W 120 8W 100 80 60 8W 0.02 40 20 0.01 0.005 20m 0 100m 200m 1 2 10 20 100 0 300 5 PO - Output Power (BTL) - W 10 15 20 25 30 35 40 45 PVDD - Supply Voltage (BTL) - Vrms Figure 1. Figure 2. UNCLIPPED OUTPUT POWER vs SUPPLY VOLTAGE SYSTEM EFFICIENCY vs OUTPUT POWER 180 170 TC = 75°C 160 6W 150 140 130 120 4W 110 100 90 8W 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 45 50 PVDD - Supply Voltage (BTL) - Vrms Efficiency = % PO - Output Power - W 6W 180 2 0.2 TC = 75°C, Digital Gain = 2.5 dB 200 PO - Output Power - W THD+N - Total Harmonic Distortion + Noise - % 10 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 50 8W 6W 4W PVDD (4 W) = 38.5 V, TC = 75°C, Digital Gain = 2.5 dB 0 40 Figure 3. 80 120 160 200 240 280 320 360 400 440 2 CH Output Power - W Figure 4. Submit Documentation Feedback 11 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) SYSTEM POWER LOSS vs OUTPUT POWER SYSTEM OUTPUT POWER vs CASE TEMPERATURE 52 240 TC = 75°C, Digital Gain = 2.5 dB, PVDD (4 W) = 38.5 V 48 44 4W 200 PO - Output Power - W 40 Power Loss 36 32 28 24 8W 20 4W 180 8W 160 140 120 100 16 80 60 12 PVDD (4 W) = 38.5 V, Digital Gain = 2.5 dB 40 8 20 4 0 6W 220 6W 0 40 0 10 80 120 160 200 240 280 320 360 400 420 PO - Output Power - W 20 30 40 50 60 70 80 90 100 110 120 TC - Case Temperature (BTL) - °C Figure 5. Figure 6. NOISE AMPLITUDE vs FREQUENCY 0 -10 -20 TC = 75°C, Vref = 31.71 V Noise Amplitude - dBr -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k f - Frequency - Hz Figure 7. 12 Submit Documentation Feedback TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 TYPICAL CHARACTERISTICS, SE CONFIGURATION OUTPUT POWER vs SUPPLY VOLTAGE 10 5 110 TC = 75°C, Digital Gain = 2.5 dB 90 1 80 PO - Output Power - W 2 0.5 0.2 TC = 75°C, Digital Gain = 2.5 dB 100 3W 0.1 0.05 4W 3W 70 60 4W 50 40 30 0.02 20 0.01 0.005 20m 10 100m 200m 1 2 10 20 100 0 0 PO - Output Power (SE) - W 5 10 15 20 25 30 35 40 45 PVDD - Supply Voltage (SE) - Vrms Figure 8. 50 Figure 9. OUTPUT POWER vs CASE TEMPERATURE 120 110 3W 100 PO - Output Power - W THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 90 4W 80 70 60 50 40 30 20 Digital Gain = 2.5 dB 10 0 10 20 30 40 50 60 70 80 90 100 110 120 TC - Case Temperature (SE) - °C Figure 10. Submit Documentation Feedback 13 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 5 TC = 75°C, Digital Gain = 2.5 dB 2 PO - Output Power - W THD+N - Total Harmonic Distortion + Noise - % 10 1 0.5 6W 0.2 0.1 0.05 4W 8W 0.02 0.01 0.005 20m 100m 200m 1 2 10 20 100 200 500 PO - Output Power (PBTL) - W 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 TC = 75°C, Digital Gain = 2.5 dB 4W 6W 8W 5 10 15 20 25 30 35 40 45 PVDD - Supply Voltage (PBTL) - Vrms Figure 11. Figure 12. SYSTEM OUTPUT POWER vs CASE TEMPERATURE 400 360 4W PO - Output Power - W 320 280 6W 240 8W 200 160 120 Digital Gain = 2.5 dB 80 40 0 10 20 30 40 50 60 70 80 90 100 110 120 TC - Case Temperature - °C Figure 13. 14 Submit Documentation Feedback 50 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 PVDD 10 Ω GVDD 10 mF 3.3 Ω 100 nF 1000 mF 63 V 10 nF 100 V 10 Ω 10 nF 100 V TAS5162DKD 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown 35 5 VALID OTW PVDD_A 22 kΩ 7 PWM2_P 1Ω OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ 12 13 28 AGND BST_B VREG BST_C 26 M3 PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D 10 Ω 100 nF 33 nF 100 nF 100 V 1.0 mF 100 V 100 nF 100 V 1.0 mF 100 V 10 nF 100 V 100 nF 100 V 470 nF 100 V 10 mH@10 A 22 PWM_D 21 PVDD_D 100 nF 100 V 20 BST_D 19 18 GVDD_C 3.3 Ω 10 mH@10 A 24 23 VDD 47 mF 33 nF 25 17 GVDD 10 nF 100 V 27 15 1Ω 3.3 Ω 29 14 16 100 nF 100 V OUT_B 10 TAS5508 1.0 mF 100 V PVDD_B 9 11 32 30 GND 100 nF 470 nF 100 V 10 mH@10 A 31 8 PWM2_M 100 nF 100 V 33 PWM_A 3.3 Ω 10 mH@10 A 34 SD 6 PWM1_M 33 nF BST_A 4 PWM1_P 100 nF 100 V 36 GVDD_A GVDD_B 1.0 mF 100 V 100 nF 100 V 3.3 Ω 10 nF 100 V 33 nF GVDD_D PVDD 100 nF 100 nF 3.3 Ω 10 Ω 10 nF 100 V 1000 mF 63 V ai_d_btl_les194 Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters (For Reference Only, component values and connection will change.) Submit Documentation Feedback 15 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 PVDD 10 Ω GVDD 10 mF 3.3 Ω 100 nF 1000 mF 63 V 10 nF 100 V 10 Ω 10 nF 100 V TAS5162DKD 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown 35 5 VALID PVDD_A OUT_A RESET_AB GND_A PWM_B GND_B 1Ω 7 OC_ADJ 12 13 28 AGND BST_B VREG BST_C 16 26 M3 PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D 10 Ω 100 nF 100 nF 100 V 1.0 mF 100 V 1.0 mF 100 V 10 nF 100 V 100 nF 100 V 470 nF 100 V 10 mH@10 A 22 PWM_D 21 PVDD_D 100 nF 100 V 20 BST_D 19 18 GVDD_C 3.3 Ω 10 mH@10 A 24 23 VDD 47 mF 33 nF 100 nF 100 V 25 17 GVDD 33 nF 27 15 No connect 10 nF 100 V 29 14 1Ω 3.3 Ω OUT_B 10 11 100 nF 100 V PVDD_B 9 TAS5508 1.0 mF 100 V 30 GND 100 nF 10 mH@10 A 32 31 8 PWM2 470 nF 100 V 100 nF 100 V 33 PWM_A 3.3 Ω 10 mH@10 A 34 SD 6 No connect 22 kΩ 33 nF BST_A OTW 4 PWM1 100 nF 100 V 36 GVDD_A GVDD_B 1.0 mF 100 V 100 nF 100 V 3.3 Ω 10 nF 100 V 33 nF GVDD_D PVDD 100 nF 100 nF 3.3 Ω 10 Ω 10 nF 100 V 1000 mF 63 V ai_se_btl_les194 Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters (For Reference Only, component values and connection will change.) 16 Submit Documentation Feedback TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 10 Ω 100 nF GVDD 10 mF PVDD 1.0 mF 100 V 10 Ω 3.3 Ω TAS5162DKD 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown 36 GVDD_B GVDD_A 35 OTW 5 VALID 33 PWM_A OUT_A RESET_AB GND_A 22 kW PWM3_P 1Ω 7 PWM_B GND_B OC_ADJ OUT_B 29 GND PVDD_B 9 100 nF TAS5508 12 13 BST_B VREG BST_C PVDD_C M2 OUT_C 1.0 mF 100 V 10 nF 100 V 1.0 mF 100 V 25 C 10 mH@10 A 24 M1 GND_C PWM_C GND_D RESET_CD OUT_D 23 10 mH@10 A 22 D 21 16 PWM_D PVDD_D 100 nF 100 V 20 17 VDD 47 mF 33 nF 26 M3 15 100 nF 100 nF 100 V 27 14 GVDD 33 nF 28 AGND 10 11 B 31 30 8 PWM4_P 10 mH@10 A 32 6 PWM2_P A 10 mH@10 A 100 nF 100 V PVDD_A 4 PWM1_P1 33 nF BST_A 34 SD 1000 mF 63 V 10 nF 100 V BST_D 19 18 GVDD_C 1.0 mF 100 V 33 nF GVDD_D PVDD 10 Ω 100 nF 100 nF 3.3 Ω 100 nF 100 V 1000 mF 63 V 10 nF 100 V 10 Ω 10 nF 100 V 100 nF 100 V 3.3 Ω A 10 nF 100 V 3.3 Ω C 2.7 kΩ PVDD 220 mF 50 V 1 mF 50 V 100 nF 100 V 10 nF @ 100 V 2.7 kΩ PVDD 3.3 Ω PVDD/2 220 mF 50 V 1 mF 50 V 100 nF 100 V 10 nF @ 100 V 3.3 Ω PVDD/2 220 mF 50 V 220 mF 50 V 100 nF 100 V 10 nF 100 V 100 nF 100 V 3.3 Ω B 10 nF 100 V 3.3 Ω D 2.7 kΩ PVDD 220 mF 50 V 1 mF 50 V 100 nF 100 V 10 nF @ 100 V 2.7 kΩ PVDD 3.3 Ω 220 mF 50 V 1 mF 50 V 100 nF 100 V 10 nF @ 100 V 3.3 Ω PVDD/2 PVDD/2 220 mF 50 V 220 mF 50 V ai_se_o_les194 Figure 16. Typical SE Application (For Reference Only, component values and connection will change.) Submit Documentation Feedback 17 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 10 Ω GVDD PVDD 100 nF 3.3 Ω 10 mF 10 Ω TAS5162DKD 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown GVDD_A 35 OTW SD 5 VALID 22 kW 1Ω 7 RESET_AB GND_A PWM_B GND_B OC_ADJ 28 BST_C 26 M3 PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D 47 mF 10 Ω 1.0 mF 100 V 1.0 mF 100 V 10 mH@10 A 23 10 mH@10 A 22 PWM_D 21 PVDD_D 100 nF 100 V 20 VDD 100 nF 100 nF 100 V 24 17 GVDD 33 nF 100 nF 100 V 25 15 16 33 nF BST_B 14 1Ω 3.3 Ω 10 nF 100 V PVDD_B 27 VREG 13 100 nF 100 V OUT_B 10 12 10 mH@10 A 32 29 AGND TAS5508 470 nF 63 V 30 9 11 1.0 mF 100 V 31 8 GND 100 nF 100 nF 100 V 33 OUT_A 3.3 Ω 10 mH@10 A 34 PVDD_A 6 PWM1_M 33 nF BST_A PWM_A 10 nF 100 V 100 nF 100 V 36 GVDD_B 4 PWM1_P 1000 mF 63 V 10 nF 100 V BST_D 19 18 GVDD_C 1.0 mF 100 V 33 nF 3.3 Ω GVDD_D 100 nF 100 nF 10 Ω PVDD 10 nF 100 V 1000 mF 63 V ai_d_pbtl_les194 Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters (For Reference Only, component values and connection will change.) 18 Submit Documentation Feedback TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 10 Ω GVDD 10 mF PVDD 100 nF 3.3 Ω 10 Ω 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown 36 GVDD_B GVDD_A 35 OTW SD 5 VALID 1Ω 7 33 PWM_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B 13 28 AGND BST_B VREG BST_C M3 26 No connect 16 M2 OUT_C M1 GND_C PWM_C GND_D 47 mF 10 Ω 100 nF 100 V 470 nF 63 V 1.0 mF 100 V 1.0 mF 100 V 100 nF 100 V 3.3 Ω RESET_CD OUT_D 10 nF 100 V 10 mH@10 A 24 23 10 mH@10 A 22 PWM_D 21 PVDD_D 100 nF 100 V 20 VDD 100 nF 3.3 Ω 25 17 GVDD 33 nF 100 nF 100 V PVDD_C 15 1Ω 33 nF 27 14 No connect 10 nF 100 V 100 nF 100 V PVDD_B 10 12 10 mH@10 A 29 GND TAS5508 32 1.0 mF 100 V 30 9 11 100 nF 100 V 31 8 100 nF 10 mH@10 A 34 PVDD_A 6 No connect 22 kW 33 nF BST_A 4 PWM1 1000 mF 63 V 10 nF 100 V TAS5162DKD BST_D 19 18 GVDD_C 1.0 mF 100 V PVDD 33 nF GVDD_D 100 nF 100 nF 10 Ω 3.3 Ω 10 nF 100 V 1000 mF 63 V se2pbtl_les194 Figure 18. Typical Non-Differential (1N) PBTL Application (For Reference Only, component values and connection will change.) Submit Documentation Feedback 19 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5162 needs only a 12-V supply in addition to the (typical) 50-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. (See reference board documentation for additional information.) For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. In an application running at a reduced switching frequency, generally 192 kHz, the bootstrap capacitor might need to be increased in value. 20 Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TAS5162 reference design. For additional information on recommended power supply and required components, see the application diagrams given previously in this data sheet. The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5162 is fully protected against erroneous power-stage turn-on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions section of this data sheet). SYSTEM POWER-UP/POWER-DOWN SEQUENCE Powering Up The TAS5162 does not require a power-up sequence. The outputs of the H-bridges remain in a highimpedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is recommended to hold RESET_AB and RESET_CD in a low state while powering up the device. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. When the TAS5162 is being used with TI PWM modulators such as the TAS5508, no special attention to the state of RESET_AB and RESET_CD is required, provided that the chipset is configured as recommended. Powering Down The TAS5162 does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Submit Documentation Feedback TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET_AB and RESET_CD low during power down, thus preventing audible artifacts including pops or clicks. When the TAS5162 is being used with TI PWM modulators such as the TAS5508, no special attention to the state of RESET_AB and RESET_CD is required, provided that the chipset is configured as recommended. Mid Z Sequence Compatibility The TAS5162 is compatible with the Mid Z Sequence from the TAS5086 Modulator. The Mid Z Sequence is a series of pulses that is generated by the modulator that causes the power stage to slowly enable its outputs as it begins to switch. By slowly starting the PWM switching, the impulse response created by the onset of switching is reduced. This impulse response is the acoustic artifact that is heard in the output transducers (loudspeakers) and is commonly termed a "click" or "pop". The low acoustic artifact noise of TAS5162 will be further decreased when used in combination with a TAS5086 modulator and the Mid Z sequence is enabled. The Mid Z Sequence is primarily used for the single-ended mode of operation. It facilitates a "softer" PWM output start after the split cap output configuration is charged. ERROR REPORTING The SD and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW goes low when the device junction temperature exceeds 125°C (see the following table). SD OTW DESCRIPTION 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) 0 1 Overload (OLP) or undervoltage (UVP) 1 0 Junction temperature higher than 125°C (overtemperature warning) 1 1 Junction temperature lower than 125°C and no OLP or UVP faults (normal operation) being present. TI recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown (OTE). To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the Electrical Characteristics section of this data sheet for further specifications). DEVICE PROTECTION SYSTEM The TAS5162 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5162 responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than overload or over temperature, the device automatically recovers when the fault condition has been removed or the gate supply voltage has increased. For highest possible reliability, recovering from an overload/over-temperature fault requires external reset of the device (see the Device Reset section of this data sheet) no sooner than 1 second after the shutdown. The TAS5162 contains circuitry associated with its PWM inputs that will detect the condition when a PWM input is continuously high or low. Without this protection circuitry, if a PWM input is not correct, the PVDD power supply could appear on the associated output pin. This condition could damage either the output load (loudspeaker) or the device. If a PWM input remains either high or low over 15μS, the device's outputs will be set into a Hi-Z state. If this error condition occurs, SD will not be asserted low. The above mentioned operation is used for all of the BTL output modes except for Mode 0,0,1 and the Single-ended Mode 1,0,1 those are the Latching Shutdown Modes. In the Latching Shutdown Mode, the over current error recovery circuitry is disabled and an over current condition will cause the device to shutdown immediately. After shutdown, RESET_AB and/or RESET_CD must be asserted to restore normal operation after the over current condition is removed. Note that asserting either RESET_AB or RESET_CD low forces the SD signal high, independent of faults Submit Documentation Feedback 21 TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 Use of TAS5162 Capable Systems in High-Modulation-Index This device requires at least 50 ns of low time on the output per 384-kHz PWM frame rate in order to keep the bootstrap capacitors charged. As an example, if the modulation index is set to 99.2% in the TAS5508, this setting allows PWM pulse durations down to 20 ns. This signal, which does not meet the 50-ns requirement, is sent to the PWM_X pin and this low-state pulse time does not allow the bootstrap capacitor to stay charged. In this situation, the low voltage across the bootstrap capacitor can cause a failure of the high-side MOSFET transistor, especially when driving a low-impedance load. The TAS5162 device requires limiting the TAS5508 modulation index to less than 97.0% to keep the bootstrap capacitor charged under all signals and loads. The device contains bootstrap capacitor under voltage protection circuit (BST_UVP) that monitors the voltage on the bootstrap capacitors. When the voltage on the on the bootstrap capacitors is less than required for safe operation, the TAS5162 will initiate bootstrap capacitor recharge sequences until the bootstrap capacitors are properly charged for safe operation. This function may be activated at a modulation index of greater than 97.0% overload protection are independent for half-bridges A and B and, respectively, C and D. That is, if the bridge-tied load between half-bridges A and B causes an overload fault, only half-bridges A and B are shut down. • For the lowest-cost bill of materials in terms of component selection, the OC threshold measure should be limited, considering the power output requirement and minimum load impedance. Higher-impedance loads require a lower OC threshold. • The demodulation-filter inductor must retain at least 5 μH of inductance at twice the OC threshold setting. Unfortunately, most inductors have decreasing inductance with increasing temperature and increasing current (saturation). To some degree, an increase in temperature naturally occurs when operating at high output currents, due to core losses and the dc resistance of the inductor's copper winding. A thorough analysis of inductor saturation and thermal properties is strongly recommended. Setting the OC threshold too low might cause issues such as lack of enough output power and/or unexpected shutdowns due to too-sensitive overload detection. TI strongly recommends using a TI PWM processor, such as TAS5508 or TAS5086, with the modulation index set at 96.1% to interface with TAS5162. In general, it is recommended to follow closely the external component selection and PCB layout as given in the Application section. The Modulation Index is set by writing 0x04 to the Modulation Index Limit Register (0x16) in the TAS5508B or TAS5518A. In the case of the TAS5086 a 0x04 is written to the Modulation Limit Register (0x10). For added flexibility, the OC threshold is programmable within a limited range using a single external resistor connected between the OC_ADJ pin and AGND. (See the Electrical Characteristics section of this data sheet for information on the correlation between programming-resistor value and the OC threshold.) It should be noted that a properly functioning overcurrent detector assumes the presence of a properly designed demodulation filter at the power-stage output. Short-circuit protection is not provided directly at the output pins of the power stage but only on the speaker terminals (after the demodulation filter). It is required to follow certain guidelines when selecting the OC threshold and an appropriate demodulation inductor: Overcurrent (OC) Protection Limiting and Overload Detection With Current The device has independent, fast-reacting current detectors with programmable trip threshold (OC threshold) on all high-side and low-side power-stage FETs. See the following table for OC-adjust resistor values. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current from further increasing, i.e., it performs a current-limiting function rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. If the high-current situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. Current limiting and OC-Adjust Resistor Values Max. Current Before OC Occurs (kΩ) (A) 22 12.2 27 10.5 47 6.4 68 4.0 100 3.0 Overtemperature Protection The TAS5162 has a two-level temperature-protection 22 Submit Documentation Feedback TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds 155°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case and RESET_AB and RESET_CD must be asserted low. Undervoltage Protection (UVP) and Power-On Reset (POR) The UVP and POR circuits of the TAS5162 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach 9.8 V (typical). Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply voltage on the bootstrap capacitors have increased above the UVP threshold. DEVICE RESET Two reset pins are provided for independent control of half-bridges A/B and C/D. When RESET_AB is asserted low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance (Hi-Z) state. Likewise, asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high-impedance state. Thus, both reset pins are well suited for hard-muting the power stage if needed. In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset inputs low enables weak pulldown of the half-bridge outputs. In the SE mode, the weak pulldowns are not enabled, and it is therefore recommended to ensure bootstrap capacitor charging by providing a low pulse on the PWM inputs when reset is asserted high. Asserting either reset input low removes any fault information to be signaled on the SD output, i.e., SD is forced high. A rising-edge transition on either reset input allows the device to resume operation after an overload fault. Submit Documentation Feedback 23 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TAS5162DDV ACTIVE HTSSOP DDV 44 35 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TAS5162 TAS5162DDVR ACTIVE HTSSOP DDV 44 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TAS5162 TAS5162DKD ACTIVE HSSOP DKD 36 29 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5162 TAS5162DKDR ACTIVE HSSOP DKD 36 500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5162 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TAS5162DDVR HTSSOP DDV 44 2000 330.0 24.4 TAS5162DKDR HSSOP DKD 36 500 330.0 24.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.6 1.8 12.0 24.0 Q1 14.7 16.4 4.0 20.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5162DDVR HTSSOP DDV 44 2000 367.0 367.0 45.0 TAS5162DKDR HSSOP DKD 36 500 367.0 367.0 45.0 Pack Materials-Page 2 PACKAGE OUTLINE DKD0036A PowerPAD TM SSOP - 3.6 mm max height SCALE 1.000 PLASTIC SMALL OUTLINE C SEATING PLANE 14.5 TYP 13.9 A 0.1 C PIN 1 ID AREA 34X 0.65 36 1 EXPOSED THERMAL PAD 12.7 12.6 16.0 15.8 NOTE 3 2X 11.05 18 19 36X 0.38 0.25 0.12 (2.95) C A B 5.9 5.8 B 11.1 10.9 NOTE 4 (0.15) EXPOSED THERMAL PAD 3.6 3.1 (0.28) TYP SEE DETAIL A 0.35 GAGE PLANE 0 -8 0.3 0.1 1.1 0.8 DETAIL A TYPICAL 4222166/A 12/2015 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. The exposed thermal pad is designed to be attached to an external heatsink. www.ti.com EXAMPLE BOARD LAYOUT DKD0036A PowerPAD TM SSOP - 3.6 mm max height PLASTIC SMALL OUTLINE 36X (2) SEE DETAILS SYMM 1 36 36X (0.45) 34X (0.65) SYMM (R0.05) TYP 18 19 (13.2) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.05 MAX AROUND 0.05 MIN AROUND NON SOLDER MASK DEFINED SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4222166/A 12/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DKD0036A PowerPAD TM SSOP - 3.6 mm max height PLASTIC SMALL OUTLINE 36X (2) 1 SYMM 36 36X (0.45) 34X (0.65) SYMM (R0.05) TYP 19 18 (13.2) SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE:6X 4222166/A 12/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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