TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS
Check for Samples: TAS5414A, TAS5424A
FEATURES
Heat Slug Up for the TAS5414A
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TAS5414A – Single-Ended Input
TAS5424A – Differential Input
Four-Channel Digital Power Amplifier
Four Analog Inputs, Four BTL Power Outputs
Typical Output Power per Channel at 10%
THD+N
– 28 W/Ch Into 4 Ω at 14.4 Vdc
– 45 W/Ch Into 2 Ω at 14.4 Vdc
– 58 W/Ch Into 4 Ω at 21 Vdc
– 116 W/Ch Into 2 Ω at 21 Vdc PBTL
Channels Can Be Paralleled (PBTL) for 1-Ω
Applications
THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω
Patented Pop- and Click-Reduction
Technology
– Soft Muting With Gain Ramp Control
– Common-Mode Ramping
Patented AM Interference Avoidance
Patented Cycle-by-Cycle Current Limit
75-dB PSRR
Four-Address I2C Serial Interface for Device
Configuration and Control
Channel Gains: 12-dB, 20-dB, 26-dB, 32-dB
Load Diagnostic Functions:
– Output Open and Shorted Load
– Output-to-Power and -to-Ground Shorts
– Patented Tweeter Detection
Protection and Monitoring Functions:
– Short-Circuit Protection
– Load-Dump Protection to 50 V
– Fortuitous Open Ground and Power
Tolerant
– Patented Output DC Level Detection While
Music Playing
– Overtemperature Protection
– Over- and Undervoltage Conditions
– Clip Detection
36-Pin PSOP3 (DKD) Power SOP Package With
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44-Pin PSOP3 (DKD) Power SOP Package With
Heat Slug Up for the TAS5424A
64-Pin QFP (PHD) Power Package With Heat
Slug Up for TAS5414A
Designed for Automotive EMC Requirements
Qualified According to AEC-Q100
ISO9000:2002 TS16949 Certified
–40°C to 105°C Ambient Temperature Range
APPLICATIONS
•
High-Power OEM/Retail Head Units and
Amplifier Modules Where Feature Densities
and System Configurations Require Reduction
in Heat From the Audio Power Amplifier
DESCRIPTION
The TAS5414A and TAS5424A are four-channel
digital audio amplifiers designed for use in automotive
head units and external amplifier modules. The
TAS5414A and TAS5424A provide four channels at
23 W continuously into 4 Ω at less than 1% THD+N
from a 14.4-V supply. Each channel can also deliver
38 W into 2 Ω at 1% THD+N. The TAS5414A uses
single-ended analog inputs, while the TAS5424A
employs differential inputs for increased immunity to
common-mode system noise. The digital PWM
topology of the TAS5414A and TAS5424A provides
dramatic improvements in efficiency over traditional
linear amplifier solutions. This reduces the power
dissipated by the amplifier by a factor of ten under
typical music playback conditions. The TAS5414A
and TAS5424A incorporate all the functionality
needed to perform in the demanding OEM
applications area. They have built-in load diagnostic
functions for detecting and diagnosing misconnected
outputs to help to reduce test time during the
manufacturing process.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TAS5414A FUNCTIONAL BLOCK DIAGRAM
3.3 V–5 V
TAS5414A, 36 Pins
Pullup Resistors
System
mP
AVDD (6.5 V)
SDA
SCL
STANDBY
Supplies
and
References
D_BYP
A_BYP
DVDD (3.3 V)
2
I C
GND
OverTemp
Warn/SD
FAULT
CLIP_OTW
REXT
VREF and IREF
I2C_ADDR
0–3
Fault
and
Timing
Logic
Channel
Utilities
GND
CP
AVDD
Over/Under
Voltage
CPC_TOP
PVDD
Load Dump
OSC_SYNC
Charge
Pump
Osc
and
Clock
CPC_BOT
CP
Battery
8 VDC–22 VDC
Channel 1 of 4
MUTE
Load Diagnostics and Fault Monitors
Optional
DC Detect
Open/Short Diagnostic
OC Timer
AVSS
Clip Detect
FLV
RLV
FRV
RRV
Radio DSP
Signal Path
PVDD
Current
Limit
IN1_P
IN2_P
IN3_P
IN4_P
IN_M
OUT1_P
PreAmp
Tweeter
Detect
PWM
Gate
Driver
OUT1_M
GND
Feedback
Channels 2, 3, 4: Same as Ch 1
B0198-03
2
Copyright © 2009–2011, Texas Instruments Incorporated
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
TAS5424A FUNCTIONAL BLOCK DIAGRAM
3.3 V–5 V
TAS5424A, 44 Pins
Pullup Resistors
System
mP
AVDD (6.5 V)
SDA
SCL
STANDBY
Supplies
and
References
D_BYP
A_BYP
DVDD (3.3 V)
2
I C
GND
OverTemp
Warn/SD
FAULT
CLIP_OTW
REXT
VREF and IREF
I2C_ADDR
0–3
Fault
and
Timing
Logic
Channel
Utilities
GND
CP
AVDD
Over/Under
Voltage
CPC_TOP
PVDD
Load Dump
OSC_SYNC
Charge
Pump
Osc
and
Clock
CPC_BOT
CP
Battery
8 VDC–22 VDC
Channel 1 of 4
MUTE
Load Diagnostics and Fault Monitors
Optional
DC Detect
Clip Detect
Open/Short Diagnostic
OC Timer
Signal Path
PVDD
Current
Limit
IN1_P
Audio
Input
IN1_M
OUT1_P
PreAmp
Tweeter
Detect
PWM
Gate
Driver
Feedback
OUT1_M
GND
Channels 2, 3, 4: Same as Ch 1
B0198-04
Copyright © 2009–2011, Texas Instruments Incorporated
3
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
PIN ASSIGNMENTS AND FUNCTIONS
The pin assignments for the TAS5414A and TAS5424A are shown as follows.
TAS5414A
DKD Package
(Top View)
OSC_SYNC
I2C_ADDR
SDA
SCL
FAULT
MUTE
STANDBY
D_BYP
CLIP_OTW
GND
GND
REXT
A_BYP
IN1_P
IN2_P
IN_M
IN3_P
IN4_P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TAS5424A
DKD Package
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PVDD
PVDD
OUT1_M
OUT1_P
GND
OUT2_M
OUT2_P
CPC_TOP
CP
CPC_BOT
GND
OUT3_M
OUT3_P
GND
OUT4_M
OUT4_P
PVDD
PVDD
P0018-04
OSC_SYNC
I2C_ADDR
SDA
SCL
FAULT
MUTE
GND
STANDBY
D_BYP
CLIP_OTW
GND
GND
REXT
A_BYP
IN1_P
IN1_M
IN2_P
IN2_M
IN3_P
IN3_M
IN4_P
IN4_M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
PVDD
PVDD
PVDD
OUT1_M
OUT1_P
GND
GND
OUT2_M
OUT2_P
CPC_TOP
CP
CP_BOT
GND
OUT3_M
OUT3_P
GND
GND
OUT4_M
OUT4_P
PVDD
PVDD
PVDD
P0055-02
4
Copyright © 2009–2011, Texas Instruments Incorporated
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
GND
GND
PVDD
GND
PVDD
PVDD
GND
GND
GND
GND
GND
GND
OSC_SYNC
I2C_ADDR
SDA
SCL
TAS5414A
PHD Package
(Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
FAULT
1
48
OUT1_M
MUTE
2
47
OUT1_P
GND
3
46
GND
STANDBY
4
45
OUT2_M
D_BYP
5
44
OUT2_P
CLIP_OTW
6
43
GND
GND
7
42
CPC_TOP
GND
8
41
CP
GND
9
40
CP_BOT
REXT
10
39
GND
A_BYP
11
38
GND
GND
12
37
OUT3_M
IN1_P
13
36
OUT3_P
GND
14
35
GND
IN2_P
15
34
OUT4_M
GND
16
33
OUT4_P
GND
GND
GND
PVDD
PVDD
PVDD
GND
GND
GND
GND
GND
GND
IN4_P
IN3_P
IN_M
GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0070-01
Copyright © 2009–2011, Texas Instruments Incorporated
5
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
Table 1. TERMINAL FUNCTIONS
TERMINAL
DKD Package
NAME
PHD
Package
TYPE (1)
DESCRIPTION
TAS5414A
NO.
TAS5424A
NO.
TAS5414A
NO.
A_BYP
13
14
11
PBY
Bypass pin for the AVDD analog regulator
CLIP_OT
W
9
10
6
DO
Open-drain CLIP, OTW, or logical OR of the CLIP and OTW outputs. It
also reports tweeter detection during tweeter mode.
CP
28
34
41
CP
Top of main storage capacitor for charge pump (bottom goes to PVDD)
CPC_BOT
27
33
40
CP
Bottom of flying capacitor for charge pump
CPC_TOP
29
35
42
CP
Top of flying capacitor for charge pump
D_BYP
8
9
5
PBY
Bypass pin for DVDD regulator output
FAULT
5
5
1
DO
Global fault output (open drain): UV, OV, OTSD, OCSD, DC
10, 11, 23,
26, 32
7, 11, 12,
28, 29, 32,
38, 39
3, 7, 8, 9, 12,
14, 16, 17,
21, 22, 23,
24, 25, 26,
30, 31, 32,
35, 38, 39,
43, 46, 49,
50, 51, 55,
56, 57, 58,
59, 60
AG / DG /
PGND
2
2
62
AI
I2C address bit
IN1_M
N/A
16
N/A
AI
Inverting analog input for channel 1 (TAS5424A only)
IN1_P
14
15
13
AI
Non-inverting analog input for channel 1
IN2_M
N/A
18
N/A
AI
Inverting analog input for channel 2 (TAS5424A only)
IN2_P
15
17
15
AI
Non-inverting analog input for channel 2
IN3_M
N/A
20
N/A
AI
Inverting analog input for channel 3 (TAS5424A only)
IN3_P
17
19
19
AI
Non-inverting analog input for channel 3
IN4_M
N/A
22
N/A
AI
Inverting analog input for channel 4 (TAS5424A only)
Non-inverting analog input for channel 4
GND
I2C_ADDR
Ground
IN4_P
18
21
20
AI
IN_M
16
N/A
18
ARTN
MUTE
6
6
2
AI
OSC_SYN
C
1
1
61
DI/DO
OUT1_M
34
41
48
PO
– polarity output for bridge 1
OUT1_P
33
40
47
PO
+ polarity output for bridge 1
OUT2_M
31
37
45
PO
– polarity output for bridge 2
OUT2_P
30
36
44
PO
+ polarity output for bridge 2
OUT3_M
25
31
37
PO
– polarity output for bridge 3
OUT3_P
24
30
36
PO
+ polarity output for bridge 3
OUT4_M
22
27
34
PO
– polarity output for bridge 4
OUT4_P
21
26
33
PO
+ polarity output for bridge 4
PVDD
19, 20, 35,
36
23, 24, 25,
42, 43, 44
27, 28, 29,
52, 53, 54
PWR
REXT
12
13
10
AI
Precision resistor pin to set analog reference
SCL
4
4
64
DI
I2C clock input from system I2C master
SDA
3
3
63
DI/DO
STANDBY
7
8
4
DI
(1)
6
Signal return for the 4 analog channel inputs (TAS5414A only)
Gain ramp control: mute (low), play (high)
Oscillator sync input from master or output to slave amplifiers (20 MHz
divided by 5, 6, or 7)
PVDD supply
I2C data I/O for communication with system I2C master
Active-low STANDBY pin. Standby (low), power up (high)
DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PGND = power ground,
PBY = power bypass, PO = power output, AG = analog ground, DG = digital ground, CP = charge pump.
Copyright © 2009–2011, Texas Instruments Incorporated
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.3 to 30
V
–1 to 50
V
Supply voltage ramp rate
15
V/ms
Externally imposed dc supply current per PVDD or GND pin
±12
A
PVDD
DC supply voltage range
Relative to GND
PVDDMAX
Pulsed supply voltage range
t ≤ 100 ms exposure
PVDDRAMP
IPVDD
IPVDD_MAX
Pulsed supply current per PVDD pin (one shot)
IO
Maximum allowed dc current per output pin
IO_MAX
(1)
UNIT
t < 100 ms
Pulsed output current per output pin (single pulse)
(2)
t < 100 ms
17
A
±13.5
A
±17
A
DC or pulsed
±1
mA
DC or pulsed
±20
mA
7
mA
Supply voltage range:
6.5 V < PVDD < 24 V
–0.3 to 7
V
Input voltage range for I2C_ADDR pin relative to GND
Supply voltage range:
6.5 V < PVDD < 24 V
–0.3 to 7
V
VSTANDBY
Input voltage range for STANDBY pin
Supply voltage range:
6.5 V < PVDD < 24 V
–0.3 to 5.5
V
VOSC_SYNC
Input voltage range for OSC_SYNC pin relative to GND
Supply voltage range:
6.5 V < PVDD < 24 V
–0.3 to 3.6
V
VAIN_MAX
Maximum instantaneous input voltage (per pin), analog input
pins
Supply voltage range:
6.5 V < PVDD < 24 V
6.5
V
IIN_MAX
Maximum current, all digital and analog input pins
IMUTE_MAX
Maximum current on MUTE pin
IIN_ODMAX
Maximum sinking current for open-drain pins
VLOGIC
Input voltage range for logic pin relative to GND (SCL and
SDA pins)
VI2C_ADDR
(2)
VAIN_AC_MAX_5414
Maximum ac-coupled input voltage for TAS5414A , analog
input pins
Supply voltage range:
6.5 V < PVDD < 24 V
0 to 6.5
V
VAIN_AC_MAX_5424
Maximum ac-coupled differential input voltage for
TAS5424A (2), analog input pins
Supply voltage range:
6.5 V < PVDD < 24 V
0 to 6.5
V
VAIN_DC
Input voltage range for analog pin relative to GND (INx pins)
Supply voltage range:
6.5 V < PVDD < 24 V
–0.3 to 6.5
V
VGND
Maximum voltage between GND pins
TJ
Maximum operating junction temperature range
Tstg
Storage temperature range
Power dissipation
Continuous power dissipation
(1)
(2)
Tcase = 70°C
±0.3
V
–55 to 150
°C
–55 to 150
°C
80
W
Pulsed current ratings are maximum survivable currents externally applied to the TAS5414A and TAS5424A. High currents may be
encountered during reverse battery, fortuitous open ground, and fortuitous open supply fault conditions.
See Application Information section for information on analog input voltage and ac coupling.
THERMAL CHARACTERISTICS
PARAMETER
VALUE (Typical)
UNIT
RθJC
Junction-to-case (heat slug) thermal
resistance, DKD package
1
°C/W
RθJC
Junction-to-case (heat slug) thermal
resistance, PHD package
1.2
°C/W
RθJA
Junction-to-ambient thermal resistance
This device is not intended to be used without a heatsink. Therefore, RθJA
is not specified. See the Thermal Information section.
°C/W
Exposed pad dimensions, DKD package
13.8 × 5.8
mm
Exposed pad dimensions, PHD package
8×8
mm
RECOMMENDED OPERATING CONDITIONS (1)
MIN
TYP
MAX
UNIT
PVDDOP
DC supply voltage range relative to GND
8
14.4
22
V
PVDDI2C
DC supply voltage range for I2C reporting
6
14.4
26.5
V
(1)
The Recommended Operating Conditions table specifies only that the device is functional in the given range. See the Electrical
Characteristics table for specified performance limits.
Copyright © 2009–2011, Texas Instruments Incorporated
7
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS(1) (continued)
MIN
VAIN_5414
(2)
VAIN_5424
(2)
Analog audio input signal level (TAS5414A)
Analog audio input signal level (TAS5424A)
fAUDIO_TW
Audio frequency for tweeter detect
TA
Ambient temperature
AC-coupled input voltage
AC-coupled input voltage
MAX
UNIT
0
0.25–1 (3)
Vrms
0
(3)
Vrms
25
kHz
–40
105
°C
–40
115
°C
10
An adequate heat sink is required
to keep TJ within specified range.
TYP
0.5–2
20
TJ
Junction temperature
RL
Nominal speaker load impedance
2
4
VPU
Pullup voltage supply (for open-drain logic outputs)
3
3.3 or 5
5.5
V
10
47
100
kΩ
1
4.7
10
kΩ
100
kΩ
RPU_EXT
External pullup resistor on open-drain logic outputs
RPU_I2C
I2C pullup resistance on SDA and SCL pins
Resistor connected between
open-drain logic output and VPU
supply
Ω
2
RI2C_ADD
Total resistance of voltage divider for I C address
slave 1 or slave 2, connected between D_BYP and
GND pins
RREXT
External resistance on REXT pin
20.2
kΩ
CD_BYP
External capacitance on D_BYP pin
10
120
nF
CA_BYP
External capacitance on A_BYP pin
10
120
nF
CIN
External capacitance to analog input pin in series
with input signal
10
1% tolerance required
19.8
20
μF
1
CFLY
Flying capacitor on charge pump
0.47
1
1.5
μF
CP
Charge pump capacitor
0.47
1
1.5
μF
CMUTE
Capacitance on MUTE pin
100
330
nF
COSCSYNC_MAX
Allowed loading capacitance on OSC_SYNC pin
5
pF
(2)
(3)
8
Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB
Maximum recommended input voltage is determined by the gain setting.
Copyright © 2009–2011, Texas Instruments Incorporated
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 Filter, master mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
240
300
UNIT
OPERATING CURRENT
IPVDD_IDLE
IPVDD_Hi-Z
IPVDD_STBY
PVDD idle current
PVDD standby current
All four channels running in MUTE mode
All four channels in Hi-Z mode
80
STANDBY mode, TJ ≤ 85°C
2
20
mA
μA
OUTPUT POWER
4 Ω, PVDD = 14.4 V, THD+N ≤ 1%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C
23
25
4 Ω, PVDD = 14.4 V, square wave, 1 kHz, Tc = 75°C
43
4 Ω, PVDD = 21 V, THD+N = 1%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 21 V, THD+N = 10%, 1 kHz, Tc = 75°C
POUT
Output power per channel
47
50
58
40
45
2 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, Tc = 75°C
2 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C
38
2 Ω, PVDD = 14.4 V, square wave 1 kHz, Tc = 75°C
70
PBTL 2-Ω operation, PVDD = 21 V, THD+N = 10%,
1 kHz, Tc = 75°C
116
PBTL 1-Ω operation, PVDD = 14.4 V, THD+N = 10%,
1 kHz, Tc = 75°C
EFFP
Power efficiency
28
W
90
4 channels operating, 23-W output power/ch, L = 10 μH,
TJ ≤ 85°C
90%
AUDIO PERFORMANCE
Noise voltage at output
G = 26 dB, zero input, and A-weighting
Channel crosstalk
1 W, G = 26 dB, 1 kHz
60
75
dB
CMRR5424
Common-mode rejection ratio (TAS5424A)
1 kHz, 1 Vrms referenced to GND, G = 26 dB
60
75
dB
PSRR
Power supply rejection ratio
G = 26 dB, PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
60
75
THD+N
Total harmonic distortion + noise
P = 1 W, G = 26 dB, f = 1 kHz, 0°C ≤ TJ ≤ 75°C
fS
Switching frequency
Switching frequency selectable for AM interference
avoidance
RAIN
Analog input resistance
Internal shunt resistance on each input pin
VCM_INT
Internal common-mode input bias voltage
Internal bias applied to IN_M pin
60
100
μV
VNOISE
Crosstalk
dB
0.02%
0.1%
336
357
378
392
417
442
470
500
530
80
100
60
3.25
kHz
kΩ
V
11
12
13
19
20
21
25
26
27
31
32
33
–1
0
1
G
Voltage gain (VO/VIN)
Source impedance = 0 Ω, gain measurement taken at 1
W of power per channel
GCH
Channel-to-channel variation
Any gain commanded
tCM
Output-voltage common-mode ramping time
External CMUTE = 330 nF
35
ms
tGAIN
Gain ramping time
External CMUTE = 330 nF
30
ms
FET drain-to-source resistance
Not including bond wire resistance, TJ = 25°C
75
95
mΩ
Output offset voltage
Zero input signal, dc offset reduction enabled, and
G = 26 dB
±10
±25
mV
23.7
26.3
V
dB
dB
PWM OUTPUT STAGE
RDS(on)
VO_OFFSET
PVDD OVERVOLTAGE (OV) PROTECTION
VOV
PVDD overvoltage shutdown
22.1
LOAD DUMP (LD) PROTECTION
VLD_SD_SET
Load-dump shutdown voltage
26.6
29
32
V
VLD_SD_CLEAR
Recovery voltage for load-dump shutdown
23.5
26.4
28.4
V
6.5
7
7.5
V
7
7.5
8
V
PVDD UNDERVOLTAGE (UV) PROTECTION
VUV_SET
PVDD undervoltage shutdown
VUV_CLEAR
Recovery voltage for PVDD UV
AVDD
VA_BYP
A_BYP pin voltage
Copyright © 2009–2011, Texas Instruments Incorporated
6.5
V
9
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 Filter, master mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VA_BYP_UV_SET
A_BYP UV voltage
4.8
V
VA_BYP_UV_CLEAR
Recovery voltage A_BYP UV
5.3
V
D_BYP pin voltage
3.3
V
DVDD
VD_BYP
POWER-ON RESET (POR)
VPOR
Maximum PVDD voltage for POR; I2C active
above this voltage
VPOR_HY
PVDD recovery hysteresis voltage for POR
6
V
0.1
V
1.24
V
REXT
VREXT
Rext pin voltage
CHARGE PUMP (CP)
VCPUV_SET
CP undervoltage
4.8
V
VCPUV_CLEAR
Recovery voltage for CP UV
5.2
V
OVERTEMPERATURE (OT) PROTECTION
TOTW1_CLEAR
TOTW1_SET /
TOTW2_CLEAR
TOTW2_SET /
TOTW3_CLEAR
Junction temperature for overtemperature
warning
TOTW3_SET /
TOTSD_CLEAR
TOTSD
Junction temperature for overtemperature
shutdown
102
115
128
112
125
138
122
135
148
132
145
158
142
155
168
°C
CURRENT LIMITING PROTECTION
ILIM1
Current limit 1 (load current)
Load < 4 Ω
5.5
7.3
9
A
ILIM2
Current limit 2 (load current), through I2C
setting
Load < 2 Ω
8.5
11
13.5
A
OVERCURRENT (OC) SHUTDOWN PROTECTION
IMAX1
Maximum current 1 (peak output current)
IMAX2
Maximum current 2 (peak output current)
Any short to supply, ground, or other channels
9.5
11.3
13
A
11.5
14.3
17
A
325
540
750
mA
TWEETER DETECT
ITH_TW
Load current threshold for tweeter detect
ILIM_TW
Load current limit for tweeter detect
2
A
STANDBY MODE
VIH_STBY
STANDBY input voltage for logic-level high
2
5.5
VIL_STBY
STANDBY input voltage for logic-level low
0
0.7
V
ISTBY_PIN
STANDBY pin current
0.2
μA
0.1
V
MUTE MODE
Output attenuation
MUTE pin ≤ 0.9 Vdc, VIN = 1 Vrms on all inputs
VTH_DCD_POS
DC detect positive threshold default value
VTH_DCD_NEG
DC detect negative threshold default value
tDCD
DC detect step response time for four
channels
GMUTE
85
dB
PVDD = 14.4 Vdc, register 0x0E = 8EH
6.5
V
PVDD = 14.4 Vdc, register 0x0F = 3DH
–6.5
V
DC DETECT
4.3
s
CLIP_OTW REPORT
VOH_CLIPOTW
CLIP_OTW pin output voltage for logic level
high (open-drain logic output)
VOL_CLIPOTW
CLIP_OTW pin output voltage for logic level
low (open-drain logic output)
tDELAY_CLIPDET
CLIP_OTW signal delay when output
clipping detected
2.4
V
External 47-kΩ pullup resistor to 3 V–5.5 V
0.5
V
20
μs
FAULT REPORT
10
Copyright © 2009–2011, Texas Instruments Incorporated
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 Filter, master mode operation (see application diagram)
PARAMETER
VOH_FAULT
VOL_FAULT
FAULT pin output voltage for logic-level high
(open-drain logic output)
FAULT pin output voltage for logic-level low
(open-drain logic output)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.4
External 47-kΩ pullup resistor to 3 V–5.5 V
V
0.5
OPEN/SHORT DIAGNOSTICS
RS2P, RS2G
Maximum resistance to detect a short from
OUT pin(s) to PVDD or ground
ROPEN_LOAD
Minimum load resistance to detect open
circuit
Including speaker wires
300
RSHORTED_LOAD
Maximum load resistance to detect short
circuit
Including speaker wires
0.5
200
Ω
800
1300
Ω
1
1.5
Ω
I2C ADDRESS DECODER
tLATCH_I2CADDR
Time delay to latch I2C address after POR
μs
300
Voltage on I2C_ADDR pin for address 0
Connect to GND
0%
0%
15%
Voltage on I2C_ADDR pin for address 1
25%
35%
45%
Voltage on I2C_ADDR pin for address 2
External resistors in series between D_BYP and GND as
a voltage divider
55%
65%
75%
Voltage on I2C_ADDR pin for address 3
Connect to D_BYP
85%
100%
100%
tHOLD_I2C
Power-on hold time before I2C
communication
STANDBY high
fSCL
SCL clock frequency
VI2C_ADDR
VD_BYP
I2C
VIH_SCL
SCL pin input voltage for logic-level high
VIL_SCL
SCL pin input voltage for logic-level low
VOH_SDA
VOL_SDA
SDA pin output voltage for logic-level high
RPU_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V
I2C read, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
2
1
ms
100
kHz
2.1
5.5
V
–0.5
1.1
V
2.4
V
SDA pin output voltage for logic-level low
I C read, 3-mA sink current
0
0.4
V
VIH_SDA
SDA pin input voltage for logic-level high
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
2.1
5.5
V
VIL_SDA
SDA pin input voltage for logic-level low
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
–0.5
1.1
V
CI
Capacitance for SCL and SDA pins
10
pF
3.6
V
0.5
V
3.6
V
0.8
V
OSCILLATOR
VOH_OSCSYNC
OSC_SYNC pin output voltage for
logic-level high
VOL_OSCSYNC
OSC_SYNC pin output voltage for
logic-level low
VIH_OSCSYNC
OSC_SYNC pin input voltage for logic-level
high
VIL_OSCSYNC
OSC_SYNC pin input voltage for logic-level
low
fOSC_SYNC
OSC_SYNC pin clock frequency
Copyright © 2009–2011, Texas Instruments Incorporated
2.4
I2C_ADDR pin set to MASTER mode
2
I2C_ADDR pin set to SLAVE mode
I2C_ADDR pin set to MASTER mode, fS = 500 kHz
3.76
4.0
4.24
I2C_ADDR pin set to MASTER mode, fS = 417 kHz
3.13
3.33
3.63
I2C_ADDR pin set to MASTER mode, fS = 357 kHz
2.68
2.85
3.0
MHz
11
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
TIMING REQUIREMENTS FOR I2C INTERFACE SIGNALS
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
ns
tr
Rise time for both SDA and SCL signals
1000
tf
Fall time for both SDA and SCL signals
300
tw(H)
SCL pulse duration, high
tw(L)
ns
4
μs
SCL pulse duration, low
4.7
μs
tsu2
Setup time for START condition
4.7
μs
th2
START condition hold time after which first clock pulse is generated
4
μs
tsu1
Data setup time
250
ns
th1
Data hold time
tsu3
Setup time for STOP condition
CB
Load capacitance for each bus line
(1)
0
(1)
ns
4
μs
400
pF
A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
tw(H)
tw(L)
tr
tf
SCL
tsu1
th1
SDA
T0027-01
Figure 1. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 2. Timing for Start and Stop Conditions
12
Copyright © 2009–2011, Texas Instruments Incorporated
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
TYPICAL CHARACTERISTICS
THD+N
vs
POWER at 1kHz
THD+N
vs
FREQUENCY at 1 Watt
10
10
21 VDC, 4 Ω
14.4 VDC, 4 Ω
1
0.1
THD+N − Total Harmonic Distrotion + Noise − %
THD+N − Total Harmonic Distrotion + Noise − %
100
14.4 VDC, 2 Ω
21 VDC, 2 Ω, PBTL
0.01
0.1
1
10
14.4 VDC, 4 Ω
0.01
21 VDC, 4 Ω
100
1k
10k 20k
f − Frequency − Hz
G001
G002
Figure 3.
Figure 4.
TAS5424A
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
0
−30
−20
−40
−40
−50
Crosstalk − dBV
CMRR − Common-Mode Rejection Ratio − dBV
14.4 VDC, 2 Ω
0.1
0.001
10
100 200
PO − Output Power − W
1
−60
−70
−60
−80
−100
−80
−90
10
−120
100
1k
10k 20k
−140
10
100
1k
f − Frequency − Hz
G004
G003
Figure 5.
Copyright © 2009–2011, Texas Instruments Incorporated
10k 20k
f − Frequency − Hz
Figure 6.
13
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
IMD SMPTE 19 kHz, 20 kHz 1:1
NOISE FFT
−60
−70
−20
−80
−40
Voltage − dBV
IMD SMPTE 19 kHz, 20 kHz 1:1 − dBV
0
−60
−90
−80
−100
−100
−110
−120
10
100
1k
10k
−120
10
30k
100
f − Frequency − Hz
1k
10k
30k
f − Frequency − Hz
G005
G006
Figure 7.
Figure 8.
EFFICIENCY,
FOUR CHANNELS AT 4 Ω EACH
DEVICE POWER DISSIPATION
FOUR CHANNELS AT 4 Ω EACH
100
12
90
10
80
Power Dissipation − W
Efficiency − %
70
60
50
40
30
20
8
6
4
2
10
0
0
0
4
8
12
16
20
24
28
32
P − Power Per Channel − W
G007
Figure 9.
14
0
5
10
15
20
P − Power Per Channel − W
G008
Figure 10.
Copyright © 2009–2011, Texas Instruments Incorporated
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
DC DETECT VOLTAGE
vs
REGISTER 0E VALUES
20
18
DC Detect Voltage − V
16
14
PVDD = 20 V
PVDD = 14.4 V
12
10
8
PVDD = 8 V
6
4
2
0
65
6a
6f
74 79
7e
83
88 8d 92 97 9c a1
Register 0E − Hex
a6
ab b0 b5
ba
bf
c4
c9
G009
Figure 11.
DC DETECT VOLTAGE
vs
REGISTER 0F VALUES
0
−2
DC Detect Voltage − V
−4
PVDD = 8 V
−6
−8
PVDD = 14.4 V
−10
−12
−14
PVDD = 20 V
−16
−18
−20
00
05 0a
0f
14
19
1e
23 28 2d 32 37 3c
Register 0F − Hex
41
46 4b 50
55
5a
5f
64
G010
Figure 12.
Copyright © 2009–2011, Texas Instruments Incorporated
15
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
DESCRIPTION OF OPERATION
OVERVIEW
The TAS5414A and TAS5424A are single-chip, four-channel, analog-input audio amplifiers for use in the
automotive environment. The design uses an ultra-efficient class-D technology developed by Texas Instruments,
but with changes needed by the automotive industry. This technology allows for reduced power consumption,
reduced heat, and reduced peak currents in the electrical system. The TAS5414A and TAS5424A realize an
audio sound system design with smaller size and lower weight than traditional class-AB solutions.
The TAS5414A and TAS5424A are composed of eight elements:
• Preamplifier
• PWM
• Gate drive
• Power FETs
• Diagnostics
• Protection
• Power supply
• I2C serial communication bus
Preamplifier
The preamplifier of the TAS5414A and TAS5424A is a high-input-impedance, low-noise, low-offset-voltage input
stage with adjustable gain. The high input impedance of the TAS5414A and TAS5424A allows the use of
low-cost 1-μF input capacitors while still achieving extended low-frequency response. The preamplifier is
powered by a dedicated, internally regulated supply, which gives it excellent noise immunity and channel
separation. Also included in the preamp are:
1. Mute Pop-and-Click Control—An audio input signal is reshaped and amplified as a step when a mute is
applied at the crest or trough of the signal. Such a step is perceived as a loud click. This is avoided in the
TAS5414A and TAS5424A by ramping the gain gradually when a mute or play command is received.
Another form of click and pop can be caused by the start or stopping of switching in a class-D amplifier. The
TAS5414A and TAS5424A incorporate a patented method to reduce the pop energy during the switching
startup and shutdown sequence. Fault conditions require rapid protection response by the TAS5414A and
the TAS5424A, which do not have time to ramp the gain down in a pop-free manner. The device transitions
into Hi-Z mode when an OV, UV, OC, OT, or DC fault is encountered. Also, activation of the STANDBY pin
may not be pop-free.
2. Gain Control—The four gain settings are set in the preamplifier via I2C control registers. The gain is set
outside of the global feedback resistors of the TAS5414A and the TAS5424A, thus allowing for stability in the
system all gain settings with properly loaded conditions.
3. DC Offset Reduction Circuitry—Circuitry has been incorporated to reduce the dc offset. DC offset in
high-gain amplifiers can produce audible clicks and pops when the amplifier is started or stopped. The offset
reduction circuitry can be disabled or enabled via I2C.
Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5414A and TAS5424A, the modulator is an
advanced design with high bandwidth, low noise, low distortion, excellent stability, and full 0–100% modulation
capability. The patented PWM uses clipping recovery circuitry to eliminate the deep saturation characteristic of
PWMs when the input signal exceeds the modulator waveform.
Gate Drive
The gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge, power
FET stage. The TAS5414A and TAS5424A use patent-pending techniques to avoid shoot-through and are
optimized for EMI and audio performance.
16
Copyright © 2009–2011, Texas Instruments Incorporated
TAS5414A: Not Recommended For New Designs
TAS5414A, TAS5424A
SLOS535C – MAY 2009 – REVISED APRIL 2011
www.ti.com
Power FETs
The BTL output for each channel comprises four rugged N-channel 30-V FETs, each of which has an RDSon of 75
mΩ for high efficiency and maximum power transfer to the load. These FETs are designed to handle large
voltage transients during load dump.
Load Diagnostics
The TAS5414A and TAS5424A incorporate load diagnostic circuitry designed to help pinpoint the nature of
output misconnections during installation. The TAS5414A and the TAS5424A include functions for detecting and
determining the status of output connections. The following diagnostics are supported:
• Short to GND
• Short to PVDD
• Short across load (R < 1 Ω, typical)
• Open load (R > 800 Ω, typical)
• Tweeter detection
The presence of any of the short or open conditions is reported to the system via I2C register read. The tweeter
detect status can be read from the CLIP_OTW pin when properly configured.
1. Output Short and Open Diagnostics—The TAS5414A and TAS5424A contain circuitry designed to detect
shorts and open conditions on the outputs. The load diagnostic function can only be invoked when the output
is in the Hi-Z mode. There are four phases of test during load diagnostics and two levels of test. In the full
level, all channels must be in the Hi-Z state. All four phases are tested on each channel, all four channels at
the same time. When fewer than four channels are in Hi-Z, the reduced level of test is the only available
option. In the reduced level, only short to PVDD and short to GND can be tested. Load diagnostics can occur
at power up before the amplifier is moved out of Hi-Z mode. If the amplifier is already in play mode, it must
Mute and then Hi-Z before the load diagnostic can be performed. By performing the mute function, the
normal pop- and click-free transitions occur before the diagnostics begin. The diagnostics are performed as
shown in Figure 13. Figure 14 shows the impedance ranges for the open-load and shorted-load diagnostics.
The results of the diagnostic are read from the diagnostic register for each channel via I2C. Note: Do not
send a command via I2C to register 0x0C during the load diagnostic test.
Hi-Z
Channel Synchronization
Playback
/
Mute
OUT1_M
Phase1
Phase2
Phase3
Phase4
S2G
S2P
OL
SL
OUT1_P
VSpeaker
(OUT1_P – OUT1_M)
200 ms
200 ms
~50 ms
~50 ms
~50 ms
~50 ms
150 ms
~50 ms
~50 ms
~50 ms
~50 ms
150 ms
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