TAS5424TDKDRQ1G4

TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS FEATURES • • • • • • • • • • • • • • • • TAS5414 – Single-Ended Input TAS5424 – Differential Input Four-Channel Digital Power Amplifier Four Analog Inputs, Four BTL Power Outputs Typical Output Power per Channel at 10% THD+N – 28 W/Ch Into 4 Ω at 14.4 Vdc – 45 W/Ch Into 2 Ω at 14.4 Vdc – 58 W/Ch Into 4 Ω at 21 Vdc – 116 W/Ch Into 2 Ω at 21 Vdc PBTL Channels Can Be Paralleled (PBTL) for 1-Ω Applications THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω Patented Pop- and Click-Reduction Technology – Soft Muting With Gain Ramp Control – Common-Mode Ramping Patented AM Interference Avoidance Patented Cycle-by-Cycle Current Limit 75-dB PSRR Four-Address I2C Serial Interface for Device Configuration and Control Configurable Channel Gains: 12-dB, 20-dB, 26-dB, 32-dB Load Diagnostic Functions: – Output Open and Shorted Load – Output-to-Power and -to-Ground Shorts – Patented Tweeter Detection Protection and Monitoring Functions: – Short-Circuit Protection – Load-Dump Protection to 50 V – Fortuitous Open Ground and Power Tolerant – Patented Output DC Level Detection While Music Playing – Overtemperature Protection – Over- and Undervoltage Conditions – Clip Detection 36-Pin PSOP3 (DKD) Power SOP Package • • • • • • With Heat Slug Up for the TAS5414 44-Pin PSOP3 (DKD) Power SOP Package With Heat Slug Up for the TAS5424 Designed for Automotive EMC Requirements Pb-Free Soldering Supported AECQ100 Compliant ISO9000:2002 TS16949 Certified –40°C to 105°C Ambient Temperature Range APPLICATIONS • High-power OEM/retail head units and amplifier modules where feature densities and system configurations require reduction in heat from the audio power amplifier DESCRIPTION The TAS5414 and TAS5424 are four-channel digital audio amplifiers designed for use in automotive head units and external amplifier modules. The TAS5414 and TAS5424 provide four channels at 23 W continuously into 4 Ω at less than 1% THD+N from a 14.4-V supply. Each channel can also deliver 38 W into 2 Ω at 1% THD+N. The TAS5414 uses single-ended analog inputs, while the TAS5424 employs differential inputs for increased immunity to common-mode system noise. The digital PWM topology of the TAS5414 and TAS5424 provides dramatic improvements in efficiency over traditional linear amplifier solutions. This reduces the power dissipated by the amplifier by a factor of ten under typical music playback conditions. High efficiency is accomplished without the need for complicated power-supply schemes. Multiple TAS5414s or TAS5424s can be synchronized to meet high-channel-count applications. The TAS5414 and TAS5424 incorporate all the functionality needed to perform in the demanding OEM applications area. They have built-in load diagnostic functions for detecting and diagnosing misconnected outputs to help to reduce test time during the manufacturing process. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 TAS5414 FUNCTIONAL BLOCK DIAGRAM 3.3 V–5 V TAS5414-36 Pins Pull-Up Resistors System mP AVDD (6.5 V) SDA SCL STANDBY Supplies and References D_BYP A_BYP DVDD (3.3 V) 2 I C SGND OverTemp Warn/SD FAULT CLIP_OTW REXT VREF and IREF I2C ADDR “0” – “3” Fault and Timing Logic Channel Utilities GND CP AVDD Over/Under Voltage GND/SGND PGND CPC_TOP PVDD Load Dump OSC_SYNC Charge Pump Osc and Clock CPC_BOT CP Battery 8 VDC–22 VDC Channel 1 of 4 MUTE Load Diagnostics and Fault Monitors Optional DC Detect Open/Short Diagnostic OC Timer AVSS Clip Detect FLV RLV FRV RRV Radio DSP Signal Path PVDD Current Limit IN1_P IN2_P IN3_P IN4_P IN_M OUT1_P PreAmp Tweeter Detect PWM Gate Driver Feedback OUT1_M PGND Channels 2, 3, 4: Same as Ch 1 B0198-01 2 Submit Documentation Feedback TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 TAS5424 FUNCTIONAL BLOCK DIAGRAM 3.3 V–5 V TAS5424-44 Pins Pull-Up Resistors System mP AVDD (6.5 V) SDA SCL STANDBY Supplies and References D_BYP A_BYP DVDD (3.3 V) 2 I C SGND OverTemp Warn/SD FAULT CLIP_OTW REXT VREF and IREF I2C ADDR “0” – “3” Fault and Timing Logic Channel Utilities GND CP AVDD Over/Under Voltage GND/SGND PGND CPC_TOP PVDD Load Dump OSC_SYNC Charge Pump Osc and Clock CPC_BOT CP Battery 8 VDC–22 VDC Channel 1 of 4 MUTE Load Diagnostics and Fault Monitors Optional DC Detect Clip Detect Open/Short Diagnostic OC Timer Signal Path PVDD Current Limit IN1_P Audio Input IN1_M OUT1_P PreAmp Tweeter Detect PWM Gate Driver Feedback OUT1_M PGND Channels 2, 3, 4: Same as Ch 1 B0198-02 Submit Documentation Feedback 3 TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 PIN ASSIGNMENTS AND FUNCTIONS The pin assignments for the TAS5414 and TAS5424 are shown as follows. TAS5414 DKD PACKAGE (TOP VIEW) OSC_SYNC I2C_ADDR SDA SCL FAULT MUTE STANDBY D_BYP CLIP_OTW GND SGND REXT A_BYP IN1_P IN2_P IN_M IN3_P IN4_P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TAS5424 DKD PACKAGE (TOP VIEW) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 PVDD PVDD OUT1_M OUT1_P PGND OUT2_M OUT2_P CPC_TOP CP CPC_BOT PGND OUT3_M OUT3_P PGND OUT4_M OUT4_P PVDD PVDD P0018-03 OSC_SYNC I2C_ADDR SDA SCL FAULT MUTE GND STANDBY D_BYP CLIP_OTW GND SGND REXT A_BYP IN1_P IN1_M IN2_P IN2_M IN3_P IN3_M IN4_P IN4_M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 PVDD PVDD PVDD OUT1_M OUT1_P PGND PGND OUT2_M OUT2_P CPC_TOP CP CP_BOT PGND OUT3_M OUT3_P PGND PGND OUT4_M OUT4_P PVDD PVDD PVDD P0055-01 4 Submit Documentation Feedback TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 Table 1. TERMINAL FUNCTIONS TERMINAL DKD Package NAME TYPE (1) DESCRIPTION TAS5414 TAS5424 NO. NO. A_BYP 13 14 PBY Bypass capacitor for the AVDD analog regulator CLIP_OTW 9 10 DO Open-drain CLIP, OTW, or logical OR of the CLIP and OTW outputs. It also reports tweeter detection during tweeter mode. CP 28 34 CP Top of main storage capacitor for charge pump (bottom goes to PVDD) CPC_BOT 27 33 CP Bottom of flying capacitor for charge pump CPC_TOP 29 35 CP Top of flying capacitor for charge pump D_BYP 8 9 PBY Bypass pin for DVDD regulator output FAULT 5 5 DO Global fault output (open drain): UV, OV, OTSD, OCSD, DC GND 10 7, 11 DG Ground I2C_ADDR 2 2 AI I2C address bit N/A 16 AI Inverting analog input for channel 1 (TAS5424 only) IN1_P 14 15 AI Non-inverting analog input for channel 1 IN2_M N/A 18 AI Inverting analog input for channel 2 (TAS5424 only) IN2_P 15 17 AI Non-inverting analog input for channel 2 IN3_M N/A 20 AI Inverting analog input for channel 3 (TAS5424 only) IN3_P 17 19 AI Non-inverting analog input for channel 3 IN4_M N/A 22 AI Inverting analog input for channel 4 (TAS5424 only) IN4_P 18 21 AI Non-inverting analog input for channel 4 IN_M 16 N/A ARTN MUTE 6 6 AI OSC_SYNC 1 1 DI/DO OUT1_M 34 41 PO – polarity output for bridge 1 OUT1_P 33 40 PO + polarity output for bridge 1 OUT2_M 31 37 PO – polarity output for bridge 2 OUT2_P 30 36 PO + polarity output for bridge 2 OUT3_M 25 31 PO – polarity output for bridge 3 OUT3_P 24 30 PO + polarity output for bridge 3 OUT4_M 22 27 PO – polarity output for bridge 4 OUT4_P 21 26 PO + polarity output for bridge 4 PGND 23, 26, 32 28, 29, 32, 38, 39 PGND Power GND PVDD 19, 20, 35, 36 23, 24, 25, 42, 43, 44 PWR PVDD supply REXT 12 13 AI Precision resistor pin to set clock frequency SCL 4 4 DI I2C clock input from system I2C master SDA 3 3 DI/DO I2C data I/O for communication with system I2C master SGND 11 12 AG/DG Signal ground (analog and digital signal ground) STANDBY 7 8 DI IN1_M (1) Signal return for the 4 analog channel inputs (TAS5414 only) Gain ramp control: mute (low), play (high) Oscillator sync input from master or output to slave amplifiers (20 MHz divided by 5, 6, or 7) Active-low STANDBY pin. Standby (low), power up (high) DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PGND = power ground, PBY = power bypass, PO = power output, AG = analog ground, DG = digital ground, CP = charge pump. Submit Documentation Feedback 5 TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE UNIT –0.3 to 30 V –1 to 50 V PVDD DC supply voltage range Relative to PGND PVDDMAX Pulsed supply voltage range t ≤ 100 ms exposure PVDDRAMP Supply voltage ramp rate Voltage rising up to PVDDMAX IPVDD Externally imposed dc supply current per PVDD or PGND pin IPVDD_MAX Pulsed supply current per PVDD pin (one shot) IO Maximum allowed dc current per output pin IO_MAX (1) Pulsed output current per output pin (single pulse) t < 100 ms ±17 A IIN_MAX Maximum current, all digital and analog input pins (2) DC or pulsed ±1 mA IMUTE_MAX Maximum current on MUTE pin DC or pulsed ±20 mA IIN_ODMAX Maximum sinking current for open-drain pins 7 mA VLOGIC Input voltage range for logic pin relative to SGND (SCL and SDA pins) Supply voltage range: 6.5 V < PVDD < 24 V –0.3 to 7 V VI2C_ADDR Input voltage range for I2C_ADDR pin relative to SGND Supply voltage range: 6.5 V < PVDD < 24 V –0.3 to 7 V VSTANDBY Input voltage range for STANDBY pin Supply voltage range: 6.5 V < PVDD < 24V –0.3 to 5.8 V VOSC_SYNC Input voltage range for OSC_SYNC pin relative to SGND Supply voltage range: 6.5 V < PVDD < 24 V –0.3 to 3.6 V VAIN_MAX Maximum instantaneous input voltage (per pin), analog input pins Supply voltage range: 6.5 V < PVDD < 24 V 6.5 V VAIN_AC_MAX_5414 Maximum ac coupled input voltage for TAS5414 (2), analog input pins Supply voltage range: 6.5 V < PVDD < 24 V 1.9 Vrms VAIN_AC_MAX_5424 Maximum ac coupled differential input voltage for TAS5424 (2), Supply voltage range: analog input pins 6.5 V < PVDD < 24 V 3.8 (1.9 per pin) Vrms VAIN_DC Input voltage range for analog pin relative to AGND (INx pins) –0.3 to 6.5 V TJ Maximum operating junction temperature range –55 to 150 °C Tstg Storage temperature range –55 to 150 °C TSOLDER Lead temperature during soldering 1,6 mm (1/16 inch) from case for 10 seconds 260 °C Power dissipation Continuous power dissipation 80 W (1) (2) t < 100 ms Supply voltage range: 6.5 V < PVDD < 24 V Tcase = 70°C 25 V/ms ±12 A 17 A ±13.5 A Pulsed current ratings are maximum survivable currents externally applied to the TAS5414 and TAS5424. High currents may be encountered during reverse battery, fortuitous open ground, and fortuitous open supply fault conditions. See Application Information section for information on analog input voltage and ac coupling. THERMAL CHARACTERISTICS 6 PARAMETER VALUE UNIT RθJC Junction-to-case (heat slug) thermal resistance 1 °C/W RθJA Junction-to-ambient thermal resistance This device is not intended to be used without a heatsink. Therefore, RθJA is not specified. See the Thermal Information section. °C/W Submit Documentation Feedback TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 RECOMMENDED OPERATING CONDITIONS PVDDOP (1) DC supply voltage range relative to PGND 2 PVDDI2C DC supply voltage range for I C reporting MIN TYP MAX 8 14.4 22 V 6 14.4 26.5 V (2) Analog audio input signal level (TAS5414) AC-coupled input voltage 0 VAIN_5424 (2) Analog audio input signal level (TAS5424) AC-coupled input voltage 0 fAUDIO_TW Audio frequency for tweeter detect TA Ambient temperature VAIN_5414 (3) Vrms 0.5–2(3) Vrms 25 kHz –40 105 °C –40 115 °C 10 An adequate heat sink is required to keep TJ within specified range UNIT 0.25–1 20 TJ Junction temperature RL Nominal speaker load impedance 2 4 VPU Pullup voltage supply (for open-drain logic outputs) 3 3.3 or 5 5.5 V 10 50 100 kΩ 1 5 10 kΩ 100 kΩ RPU_EXT External pullup resistor on open-drain logic outputs RPU_I2C I2C pullup resistance on SDA and SCL pins Resistor connected between open-drain logic output and VPU supply Ω 2 RI2C_ADD Total resistance of voltage divider for I C address slave 1 or slave 2, connected between D_BYP and SGND pins RREXT External resistance on REXT pin 20.2 kΩ CD_BYP External capacitance on D_BYP pin 10 120 nF CA_BYP External capacitance on A_BYP pin 10 120 nF CIN External capacitance to analog input pin in series with input signal CFLY Flying capacitor on charge pump 0.47 1 1.5 μF CP Charge pump capacitor 0.47 1 1.5 μF CMUTE Capacitance on MUTE pin 3.3 330 nF COSCSYNC_MAX Allowed loading capacitance on OSC_SYNC pin 5 pF (1) (2) (3) 10 1% tolerance required 19.8 20 μF 1 The Recommended Operating Conditions table specifies only that the device is functional in the given range. See the Electrical Characteristics table for specified performance limits. Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB Maximum recommended input voltage is determined by the gain setting. Submit Documentation Feedback 7 TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Rext = 20 kΩ, master mode operation (see application diagram) PARAMETER TEST CONDITIONS MIN TYP MAX 240 300 UNIT OPERATING CURRENT IPVDD_IDLE IPVDD_Hi-Z IPVDD_STBY All four channels running in MUTE mode PVDD idle current All four channels in Hi-Z mode 80 STANDBY mode, TJ ≤ 85°C PVDD standby current 2 20 mA μA OUTPUT POWER 4 Ω, PVDD = 14.4V, THD+N ≤ 1%, 1 kHz, Tc = 75°C 4 Ω, PVDD = 14.4V, THD+N = 10%, 1 kHz, Tc = 75°C 23 25 4 Ω, PVDD = 14.4V, square wave, 1 kHz, Tc = 75°C 43 4 Ω, PVDD = 21 V, THD+N = 1%, 1 kHz, Tc = 75°C 4 Ω, PVDD = 21 V, THD+N = 10%, 1 kHz, Tc = 75°C POUT 47 50 2 Ω, PVDD = 14.4V, THD+N = 1%, 1 kHz, Tc = 75°C Output power per channel 2 Ω, PVDD = 14.4V, THD+N = 10%, 1 kHz, Tc = 75°C W 45 2 Ω, PVDD = 14.4 V, square wave 1 kHz, Tc = 75°C 70 PBTL 2-Ω operation, PVDD = 21 V, THD+N = 10%, 1 kHz, Tc = 75°C 116 90 4 channels operating, 23W output power/ch, L = 10 μH, TJ ≤ 85°C Power efficiency 58 38 40 PBTL 1-Ω operation, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C EFFP 28 90% AUDIO PERFORMANCE Noise voltage at output G = 26 dB, zero input, AES17 filter, and A-weighting Crosstalk Channel crosstalk 1W, G = 26 dB, 1 kHz 60 75 dB CMRR5424 Common-mode rejection ratio (TAS5424) 1 kHz, 1 Vrms referenced to SGND, G = 26 dB 60 75 dB PSRR Power supply rejection ratio G = 26 dB, PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz 60 75 THD+N Total harmonic distortion + noise P = 1 W, G = 26 dB, f = 1 kHz, 0°C ≤ TJ ≤ 75°C Switching frequency Switching frequency selectable for AM interference avoidance fS RAIN Analog input resistance Internal shunt resistance on each input pin VIN_CM Common-mode input voltage (non-clipping) AC-coupled common-mode input voltage (zero differential input) VCM_INT Internal common-mode input bias voltage Internal bias applied to IN_M pin G Voltage gain (VO/VIN) Source impedance = 0 Ω GCH Channel-to-channel variation Any gain commanded tCM Output-voltage common-mode ramping time tGAIN Gain ramping time 60 100 μV VNOISE dB 0.02% 0.1% 336 357 378 392 417 442 470 500 530 60 80 100 kΩ 1.3 Vrms 3.25 V 11 12 13 19 20 21 25 26 27 31 32 33 –1 0 1 External CMUTE = 330 nF kHz dB dB 35 ms 30 ms PWM OUTPUT STAGE RDSon FET Drain-to-source resistance Not including bond wire resistance, TJ = 25°C VO_OFFSET Output offset voltage Zero input signal and G = 26 dB 75 95 mΩ ±10 ±25 mV 23.7 26.3 V PVDD OVER VOLTAGE (OV) PROTECTION VOV PVDD over voltage shutdown 22.1 LOAD DUMP (LD) PROTECTION VLD_SD_SET Load-dump shutdown voltage 26.6 29 32 V VLD_SD_CLEAR Recovery voltage for load-dump shutdown 23.5 26.4 28.4 V PVDD UNDER VOLTAGE (UV) PROTECTION 8 VUV_SET PVDD under voltage shutdown 6.5 7 7.5 V VUV_CLEAR Recovery voltage for PVDD UV 7 7.5 8 V Submit Documentation Feedback TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS (continued) Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Rext = 20 kΩ, master mode operation (see application diagram) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVDD VA_BYP A_BYP pin voltage 6.5 V VA_BYP_UV_SET A_BYP UV voltage 4.8 V VA_BYP_UV_CLEAR Recovery voltage A_BYP UV 5.3 V D_BYP pin voltage 3.3 V DVDD VD_BYP POWER-ON RESET (POR) VPOR Maximum PVDD voltage for POR; I2C active above this voltage VPOR_HY PVDD recovery hysteresis voltage for POR 6 V 0.1 V 1.24 V REXT VREXT Rext pin voltage CHARGE PUMP (CP) VCPUV_SET CP undervoltage 4.8 V VCPUV_CLEAR Recovery voltage for CP UV 5.2 V OVERTEMPERATURE (OV) PROTECTION TOTW1_CLEAR TOTW1_SET / TOTW2_CLEAR TOTW2_SET / TOTW3_CLEAR Junction temperature for overtemperature warning TOTW3_SET / TOTWD_CLEAR TOTSD Junction temperature for overtemperature shutdown 102 115 128 112 125 138 122 135 148 132 145 158 142 155 168 °C CURRENT LIMITING PROTECTION ILIM1 Current limit 1 (load current) Load < 4 Ω 5.5 7.3 9 A ILIM2 Current limit 2 (load current), I2C setting current limit level 2 Load < 2 Ω 8.5 11 13.5 A 9.5 11.3 13 A 11.5 14.3 17 A 325 540 750 mA OVERCURRENT (OC) SHUTDOWN PROTECTION IMAX1 Maximum current 1 (peak output current) IMAX2 Maximum current 2 (peak output current) Any short to supply, ground, or other channels TWEETER DETECT ITH_TW Load current threshold for tweeter detect ILIM_TW Load current limit for tweeter detect 2 A STANDBY MODE VIH_STBY STANDBY input voltage for logic-level high 2 5.5 VIL_STBY STANDBY input voltage for logic-level low 0 0.7 V ISTBY_PIN STANDBY pin current 0.2 μA 0.1 V MUTE MODE Output attenuation MUTE pin ≤ 0.9Vdc, VIN = 1 Vrms on all inputs VTH_DCD_POS DC detect positive threshold default value VTH_DCD_NEG DC detect negative threshold default value tDCD DC detect step response time for four channels GMUTE 85 dB PVDD = 14.4 Vdc, register 0x0E = 8EH 6.5 V PVDD = 14.4 Vdc, register 0x0F = 3DH –6.5 V DC DETECT 4.3 s CLIP_OTW REPORT VOH_CLIPOTW VOL_CLIPOTW CLIP_OTW pin output voltage for logic level high (open-drain logic output) CLIP_OTW pin output voltage for logic level low (open-drain logic output) 2.4 V External 47-kΩ pullup resistor to 3 V–5.5 V Submit Documentation Feedback 0.5 V 9 TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS (continued) Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Rext = 20 kΩ, master mode operation (see application diagram) PARAMETER tDELAY_CLIPDET TEST CONDITIONS MIN TYP CLIP_OTW signal delay when output clipping detected MAX 20 UNIT μs FAULT REPORT VOH_FAULT VOL_FAULT FAULT pin output voltage for logic-level high (open-drain logic output) 2.4 FAULT pin output voltage for logic-level low (open-drain logic output) External 47-kΩ pullup resistor to 3 V–5.5 V V 0.5 OPEN/SHORT DIAGNOSTICS RS2P, RS2G Maximum resistance to detect a short from OUT pin(s) to PVDD or ground ROPEN_LOAD Minimum load resistance to detect open circuit Including speaker wires 300 RSHORTED_LOAD Maximum load resistance to detect short circuit Including speaker wires 0.5 Voltage on I2C_ADDR pin for address 0 Connect to SGND 0% 0% 15% Voltage on I2C_ADDR pin for address 1 External resistors in series between D_BYP and SGND as a voltage divider 25% 35% 45% Voltage on I2C_ADDR pin for address 2 55% 65% 75% Voltage on I2C_ADDR pin for address 3 Connect to D_BYP 85% 100% 100% tHOLD_I2C Power-on hold time before I2C communication STANDBY high fSCL SCL clock frequency VIH_SCL SCL pin input voltage for logic-level high VIL_SCL SCL pin input voltage for logic-level low 200 Ω 800 1300 Ω 1 1.5 Ω I2C ADDRESS DECODER tLATCH_I2CADDR VI2C_ADDR Time delay to latch I2C address after POR μs 300 VD_BYP I2C RPU_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V VOH_SDA SDA pin output voltage for logic-level high I2C read, RI2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V VOL_SDA SDA pin output voltage for logic-level low I2C read, 3-mA sink current 1 ms 100 kHz 2.1 5.5 V –0.5 1.1 V 2.4 V 0 0.4 V 2 VIH_SDA SDA pin input voltage for logic-level high I C write, RI2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V 2.1 5.5 V VIL_SDA SDA pin input voltage for logic-level low I2C write, RI2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V –0.5 1.1 V Ci Capacitance for SCL and SDA pins 10 pF 3.6 V 0.5 V 3.6 V 0.8 V OSCILLATOR VOH_OSCSYNC OSC_SYNC pin output voltage for logic-level high 2.4 I2C_ADDR pin set to MASTER mode VOL_OSCSYNC OSC_SYNC pin output voltage for logic-level low VIH_OSCSYNC OSC_SYNC pin input voltage for logic-level high VIL_OSCSYNC fOSC_SYNC 10 OSC_SYNC pin input voltage for logic-level low OSC_SYNC pin clock frequency 2 I2C_ADDR pin set to SLAVE mode I2C_ADDR pin set to MASTER mode, fS = 500 kHz, maximum capacitive loading = 5 pF 3.76 4.0 4.24 I2C_ADDR pin set to MASTER mode, fS = 417 kHz, maximum capacitive loading = 5 pF 3.13 3.33 3.63 I2C_ADDR pin set to MASTER mode, fS = 357 kHz, maximum capacitive loading = 5 pF 2.68 2.85 3.0 Submit Documentation Feedback MHz TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 2 TIMING REQUIREMENTS FOR I C INTERFACE SIGNALS over recommended operating conditions (unless otherwise noted) MAX UNIT tr Rise time for both SDA and SCL signals PARAMETER 1000 ns tf Fall time for both SDA and SCL signals 300 ns tw(H) SCL pulse duration, high 4 μs tw(L) SCL pulse duration, low 4.7 μs tsu2 Setup time for START condition 4.7 μs th2 START condition hold time after which first clock pulse is generated 4 μs tsu1 Data setup time 250 ns th1 Data hold time 0 (1) ns tsu3 Setup time for STOP condition 4 μs t(buf) Time between a STOP and START condition CB Load capacitance for each bus line (1) MIN TYP μs 4.7 400 pF A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. tw(H) tw(L) tf tr SCL tsu1 th1 SDA T0027-01 Figure 1. SCL and SDA Timing SCL t(buf) th2 tsu2 tsu3 SDA Start Condition Stop Condition T0028-01 Figure 2. Timing for Start and Stop Conditions Submit Documentation Feedback 11 TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS THD+N vs POWER at 1kHz THD+N vs FREQUENCY at 1 Watt 10 10 21 VDC, 4 Ω 14.4 VDC, 4 Ω 1 0.1 THD+N − Total Harmonic Distrotion + Noise − % THD+N − Total Harmonic Distrotion + Noise − % 100 14.4 VDC, 2 Ω 21 VDC, 2 Ω, PBTL 0.01 0.1 1 10 14.4 VDC, 4 Ω 0.01 21 VDC, 4 Ω 100 1k G002 G001 Figure 3. Figure 4. TAS5424 COMMON-MODE REJECTION RATIO vs FREQUENCY CROSSTALK vs FREQUENCY 0 −20 −40 −40 Crosstalk − dBV −50 −60 −70 −60 −80 −100 −80 −90 10 −120 100 1k 10k 20k −140 10 100 1k 10k 20k f − Frequency − Hz f − Frequency − Hz G004 G003 Figure 5. 12 10k 20k f − Frequency − Hz −30 CMRR − Common−Mode Rejection Ratio − dBV 14.4 VDC, 2 Ω 0.1 0.001 10 100 200 PO − Output Power − W 1 Figure 6. Submit Documentation Feedback TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS (continued) IMD SMPTE 19 kHz, 20 kHz 1:1 NOISE FFT −60 −70 −20 −80 −40 Voltage − dBV IMD SMPTE 19 kHz, 20 kHz 1:1 − dBV 0 −60 −90 −80 −100 −100 −110 −120 10 100 1k 10k −120 10 30k 100 f − Frequency − Hz 1k 10k 30k f − Frequency − Hz G005 G006 Figure 7. Figure 8. EFFICIENCY, FOUR CHANNELS AT 4 Ω EACH DEVICE POWER DISSIPATION FOUR CHANNELS AT 4 Ω EACH 100 12 90 10 80 Power Dissipation − W Efficiency − % 70 60 50 40 30 20 8 6 4 2 10 0 0 0 4 8 12 16 20 24 28 32 0 P − Power Per Channel − W G007 Figure 9. 5 10 15 20 P − Power Per Channel − W G008 Figure 10. Submit Documentation Feedback 13 TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS (continued) DC DETECT VOLTAGE vs REGISTER 0E VALUES 20 18 DC Detect Voltage − V 16 14 PVDD = 20 V PVDD = 14.4 V 12 10 8 PVDD = 8 V 6 4 2 0 65 6a 6f 74 79 7e 83 88 8d 92 97 9c a1 Register 0E − Hex a6 ab b0 b5 ba bf c4 c9 G009 Figure 11. DC DETECT VOLTAGE vs REGISTER 0F VALUES 0 −2 DC Detect Voltage − V −4 PVDD = 8 V −6 −8 PVDD = 14.4 V −10 −12 −14 PVDD = 20 V −16 −18 −20 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c Register 0F − Hex 41 46 4b 50 55 5a 5f 64 G010 Figure 12. 14 Submit Documentation Feedback TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 DESCRIPTION OF OPERATION OVERVIEW The TAS5414 and TAS5424 are single-chip, four-channel, analog-input audio amplifiers for use in the automotive environment. The design uses an ultra-efficient class-D technology developed by Texas Instruments, but with changes needed by the automotive industry. This technology allows for reduced power consumption, reduced heat, and reduced peak currents in the electrical system. The TAS5414 and TAS5424 realize an audio sound system design with smaller size and lower weight than traditional class-AB solutions. The TAS5414 and TAS5424 are composed of eight elements: • Preamplifier • PWM • Gate drive • Power FETs • Diagnostics • Protection • Power supply • I2C serial communication bus Preamplifier The preamplifier of the TAS5414 and TAS5424 is a high-input-impedance, low-noise, low-offset-voltage input stage with adjustable gain. The high input impedance of the TAS5414 and TAS5424 allows the use of low-cost 1-μF input capacitors while still achieving extended low-frequency response. The preamplifier is powered by a dedicated, internally regulated supply, which gives it excellent noise immunity and channel separation. Also included in the preamp are: 1. Mute Pop-and-Click Control—An audio input signal is reshaped and amplified as a step when a mute is applied at the crest or trough of the signal. Such a step is perceived as a loud click. This is avoided in the TAS5414 and TAS5424 by ramping the gain gradually when a mute or play command is received. Another form of click and pop can be caused by the start or stopping of switching in a class-D amplifier. The TAS5414 and TAS5424 incorporate a patented method to reduce the pop energy during the switching startup and shutdown sequence. Fault conditions require rapid protection response by the TAS5414 and the TAS5424, which do not have time to ramp the gain down in a pop-free manner. The device transitions into Hi-Z mode when an OV, UV, OC, OT, or DC fault is encountered. Also, activation of the STANDBY pin may not be pop-free. 2. Gain Control—The four gain settings are set in the preamplifier via I2C control registers. The gain is set outside of the global feedback resistors of the TAS5414 and the TAS5424, thus allowing for stability in the system under all load conditions and gain settings. 3. DC Offset Reduction Circuitry—Circuitry has been incorporated to reduce the dc offset. DC offset in high-gain amplifiers can produce audible clicks and pops when the amplifier is started or stopped. The offset reduction circuitry can be disabled or enabled via I2C. Pulse-Width Modulator (PWM) The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is the critical stage that defines the class-D architecture. In the TAS5414 and TAS5424, the modulator is an advanced design with high bandwidth, low noise, low distortion, excellent stability, and full 0–100% modulation capability. The patented PWM uses clipping recovery circuitry to eliminate the deep saturation characteristic of PWMs when the input signal exceeds the modulator waveform. Gate Drive The gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge, power FET stage. The TAS5414 and TAS5424 use patent-pending techniques to avoid shoot-through and are optimized for EMI and audio performance. Submit Documentation Feedback 15 TAS5414 TAS5424 www.ti.com SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 DESCRIPTION OF OPERATION (continued) Power FETs The BTL output for each channel comprises four rugged N-channel 30-V FETs, each of which has an RDSon of 75 mΩ for high efficiency and maximum power transfer to the load. These FETs are designed to handle large voltage transients during load dump. Load Diagnostics The TAS5414 and TAS5424 incorporate load diagnostic circuitry designed to help pinpoint the nature of output misconnections during installation. The TAS5414 and the TAS5424 include functions for detecting and determining the status of output connections. The following diagnostics are supported: • Short to GND • Short to PVDD • Short across load (R < 1 Ω, typical) • Open load (R > 800 Ω, typical) • Tweeter detection The presence of any of the short or open conditions is reported to the system via I2C register read. The tweeter detect status can be read from the CLIP_OTW pin when properly configured. 1. Output Short and Open Diagnostics—The TAS5414 and TAS5424 contain circuitry designed to detect shorts and open conditions on the outputs. The load diagnostic function can only be invoked when the output is in the Hi-Z mode. There are four phases of test during load diagnostics and two levels of test. In the full level, all channels must be in the Hi-Z state. All four phases are tested on each channel, all four channels at the same time. When fewer than four channels are in Hi-Z, the reduced level of test is the only available option. In the reduced level, only short to PVDD and short to GND can be tested. Load diagnostics can occur at power up before the amplifier is moved out of Hi-Z mode. If the amplifier is already in play mode, it must Mute and then Hi-Z before the load diagnostic can be performed. By performing the mute function, the normal pop- and click-free transitions occur before the diagnostics begin. The diagnostics are performed as shown in Figure 13. Figure 14 shows the impedance ranges for the open-load and shorted-load diagnostics. The results of the diagnostic are read from the diagnostic register for each channel via I2C. Note: Do not send a command via I2C to register 0x0C during the load diagnostic test. Hi-Z Channel Synchronization Playback / Mute OUT1_M Phase1 Phase2 Phase3 Phase4 S2G S2P OL SL OUT1_P VSpeaker (OUT1_P – OUT1_M) 100 ms ~50 ms ~50 ms ~50 ms ~50 ms 100 ms 150 ms ~50 ms ~50 ms ~50 ms ~50 ms 150 ms