TAS5514BTDKDRQ1

TAS5514B-Q1 www.ti.com SLOS768 – JUNE 2012 FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIER Check for Samples: TAS5514B-Q1 FEATURES 1 • • • • • • • • • • • • • Single-Ended Input Four-Channel Digital Power Amplifier Four Analog Inputs, Four BTL Power Outputs Typical Output Power at 10% THD+N – 28 W/Ch Into 4 Ω at 14.4 V – 50 W/Ch Into 2 Ω at 14.4 V – 79 W/Ch Into 4 Ω at 24 V – 150 W/Ch Into 2 Ω at 24 V (PBTL) Channels Can Be Paralleled (PBTL) for HighCurrent Applications THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω Patented Pop- and Click-Reduction Technology – Soft Muting With Gain Ramp Control – Common-Mode Ramping Patented AM Interference Avoidance Patented Cycle-by-Cycle Current Limit 75-dB PSRR Master/Slave Capability to Synchronize Clocks Load Diagnostic Functions: – Output Open and Shorted Load – Output-to-Power and -to-Ground Shorts Protection and Monitoring Functions: – Short-Circuit Protection – Load-Dump Protection to 50 V – Fortuitous Open-Ground and -Power Tolerant – Patented Output DC Level Detection While Music Playing – Overtemperature Protection – Over- and Undervoltage Conditions – Clip Detection • • • • • 36-Pin PSOP3 (DKD) Power SOP Package With Heat Slug Designed for Automotive EMC Requirements Qualified According to AEC-Q100 ISO9000:2002 TS16949 Certified –40°C to 105°C Ambient Temperature Range APPLICATIONS OEM/Retail Head Units and Amplifier Modules Where Feature Densities and System Configurations Require Reduction in Heat From the Audio Power Amplifier DESCRIPTION The TAS5514B-Q1 is a four-channel digital audio amplifier designed for use in automotive head units and external amplifier modules. It provides four channels at 23 W continuously into 4 Ω at less than 1% THD+N from a 14.4-V supply. Each channel can also deliver 38 W into 2 Ω at 1% THD+N. The digital PWM topology of the device provides dramatic improvements in efficiency over traditional linear amplifier solutions. This reduces the power dissipated by the amplifier by a factor of ten under typical music playback conditions. The device incorporates all the functionality needed to perform in the demanding OEM applications area. The TAS5514B-Q1 has builtin load diagnostic functions for detecting and diagnosing misconnected outputs to help to reduce test time during the manufacturing process. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 SLOS768 – JUNE 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM 2 Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 www.ti.com SLOS768 – JUNE 2012 PIN ASSIGNMENTS AND FUNCTIONS The pin assignments are shown as follows. Copyright © 2012, Texas Instruments Incorporated 3 TAS5514B-Q1 SLOS768 – JUNE 2012 www.ti.com Table 1. PIN FUNCTIONS PIN DKD PACKAGE NAME TYPE DESCRIPTION TAS5514B-Q1 NO. A_BYP 13 PBY Bypass pin for the AVDD analog regulator CLIP_OTW 9 DO Reports CLIP, OTW, or both. It also reports tweeter detection during tweeter mode. Open-drain CP 28 CP Top of main storage capacitor for charge pump (bottom goes to PVDD) CPC_BOT 27 CP Bottom of flying capacitor for charge pump CPC_TOP 29 CP Top of flying capacitor for charge pump D_BYP 8 PBY Bypass pin for DVDD regulator output FAULT 5 DO Global fault output (open-drain): UV, OV, OTSD, OCSD, DC 10, 11, 23, 26, 32 GND CS 2 AI Chip select IN1_P 14 AI Non-inverting analog input for channel 1 IN2_P 15 AI Non-inverting analog input for channel 2 IN3_P 17 AI Non-inverting analog input for channel 3 IN4_P 18 AI Non-inverting analog input for channel 4 IN_M 16 ARTN MUTE 6 AI OSC_SYNC 1 DI/DO OUT1_M 34 PO – polarity output for bridge 1 OUT1_P 33 PO + polarity output for bridge 1 OUT2_M 31 PO – polarity output for bridge 2 OUT2_P 30 PO + polarity output for bridge 2 OUT3_M 25 PO – polarity output for bridge 3 OUT3_P 24 PO + polarity output for bridge 3 OUT4_M 22 PO – polarity output for bridge 4 OUT4_P 21 PO + polarity output for bridge 4 PVDD 19, 20, 35, 36 PWR REXT 12 AI Precision resistor pin to set analog reference RESERVED 3, 4 DI Active-low STANDBY pin. Standby (low), power up (high) GND STANDBY 4 7 Ground Signal return for the four analog channel inputs Gain ramp control: mute (low), play (high) Oscillator input from master or output to slave amplifiers PVDD supply Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 www.ti.com SLOS768 – JUNE 2012 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) PVDD DC supply-voltage range Relative to GND PVDDMAX Pulsed supply-voltage range t ≤ 100 ms exposure PVDDRAMP VALUE UNIT –0.3 to 30 V –1 to 50 V Supply-voltage ramp rate 15 V/ms IPVDD Externally imposed dc supply current per PVDD or GND pin ±12 A IPVDD_MAX Pulsed supply current per PVDD pin (one shot) IO Maximum allowed dc current per output pin IO_MAX (1) t < 100 ms Pulsed output current per output pin (single pulse) (2) 17 A ±13.5 A ±17 A DC or pulsed ±1 mA DC or pulsed ±20 mA 7 mA t < 100 ms IIN_MAX Maximum current, all digital and analog input pins IMUTE_MAX Maximum current on MUTE pin IIN_ODMAX Maximum sink current for open-drain pins VLOGIC Input voltage range for pin relative to GND (SCL, SDA, CS pins) Supply voltage range: 6V < PVDD < 24 V –0.3 to 6 V VMUTE Voltage range for MUTE pin relative to GND Supply voltage range: 6 V < PVDD < 24 V –0.3 to 7.5 V VSTANDBY Input voltage range for STANDBY pin Supply voltage range: 6 V < PVDD < 24 V –0.3 to 5.5 V VOSC_SYNC Input voltage range for OSC_SYNC pin relative to GND Supply voltage range: 6 V < PVDD < 24 V –0.3 to 3.6 V VGND Maximum voltage between GND pins ±0.3 V VAIN_AC_MAX_5514 Maximum ac-coupled input voltage for TAS5514B-Q1 (2), analog input pins 1.9 Vrms TJ Maximum operating junction temperature range –55 to 150 °C Tstg Storage temperature range –55 to 150 °C (1) (2) Supply voltage range: 6 V < PVDD < 24 V Pulsed current ratings are maximum survivable currents externally applied to the device. High currents may be encountered during reverse battery, fortuitous open-ground, and fortuitous open-supply fault conditions. See Application Information section for information on analog input voltage and ac coupling. THERMAL CHARACTERISTICS PARAMETER VALUE (Typical) RθJC Junction-to-case (heat slug) thermal resistance, DKD package 1 RθJC Junction-to-case (heat slug) thermal resistance, PHD package 1.2 RθJA Junction-to-ambient thermal resistance Exposed pad dimensions, DKD package Copyright © 2012, Texas Instruments Incorporated UNIT °C/W This device is not intended to be used without a heatsink. Therefore, RθJA is not specified. See the Thermal Information section. 13.8 × 5.8 mm 5 TAS5514B-Q1 SLOS768 – JUNE 2012 www.ti.com ELECTROSTATIC DISCHARGE (ESD) PARAMETER Human-body model (HBM) AEC-Q100-002 Package All DKD/DKE Charged-device model (CDM) AEC-Q100-011 PHD Machine model (MM) AEC-Q100-003 Pins VALUE (Typical) All 3000 Corner pins excluding OSC_SYNC 1000 All other pins (including OSC_SYNC) except CP pin 500 CP pin (non-corner Pin) 400 Corner pins excluding SCL 750 All pins (including SCL) except CP and CP_TOP 600 CP and CP_TOP pins 400 DKD/DKE 150 PHD 100 UNIT V RECOMMENDED OPERATING CONDITIONS (1) PVDDOP VAIN_5514 DC supply-voltage range relative to GND (2) TA Analog audio input signal level (TAS5514B-Q1) AC-coupled input voltage Ambient temperature An adequate heat sink is required to keep TJ within the specified range. MIN TYP MAX 6 14.4 24 UNIT V 0 0.25–1 (3) –40 105 °C –40 115 °C Vrms TJ Junction temperature RL Nominal speaker load impedance 2 4 VPU Pullup voltage supply (for open-drain logic outputs) 3 3.3 or 5 5.5 V RPU_I2C I2C pullup resistance on SDA and SCL pins 1 4.7 10 kΩ RCS Total resistance of voltage divider for I2C address slave 1 or slave 2, connected between D_BYP and GND pins 50 kΩ RREXT External resistance on REXT pin 20.2 kΩ CD_BYP , CA_BYP External capacitance on D_BYP and A_BYP pins 120 nF COUT External capacitance to GND on OUT_X pins 150 680 nF CIN External capacitance to analog input pin in series with input signal 0.47 CFLY Flying capacitor on charge pump CP Charge pump capacitor CMUTE MUTE pin capacitor COSCSYNC_MAX Allowed loading capacitance on OSC_SYNC pin (1) (2) (3) 6 10 1% tolerance required 19.8 20 10 50 V needed for load dump Ω μF 0.47 1 1.5 μF 0.47 1 1.5 μF 100 220 1000 nF 75 pF The Recommended Operating Conditions table specifies only that the device is functional in the given range. See the Electrical Characteristics table for specified performance limits. Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB Maximum recommended input voltage is determined by the gain setting. Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 www.ti.com SLOS768 – JUNE 2012 ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ, AES17 Filter, default I2C settings, master mode operation (see application diagram) PARAMETER TEST CONDITIONS MIN TYP MAX 170 220 UNIT OPERATING CURRENT IPVDD_IDLE IPVDD_Hi-Z IPVDD_STBY PVDD idle current PVDD standby current All four channels in MUTE mode All four channels in Hi-Z mode 93 STANDBY mode, TJ ≤ 85°C 2 10 mA μA OUTPUT POWER 4 Ω, PVDD = 14.4 V, THD+N ≤ 1%, 1 kHz, Tc = 75°C 23 4 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C 25 28 4 Ω, PVDD = 24 V, THD+N = 10%, 1 kHz, Tc = 75°C 63 79 2 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, Tc = 75°C POUT Output power per channel 2 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C 38 40 PBTL 2-Ω operation, PVDD = 24 V, THD+N = 10%, 1 kHz, Tc = 75°C 150 PBTL 1-Ω operation, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C EFFP Power efficiency W 50 90 4 channels operating, 23-W output power/ch, L = 10 μH, TJ ≤ 85°C 90% AUDIO PERFORMANCE VNOISE Noise voltage at output Zero input, and A-weighting 60 100 μV 2 Crosstalk Channel crosstalk P = 1W, f = 1 kHz, enhanced crosstalk enabled via I C (reg 0x10) 70 PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz 60 THD+N Total harmonic distortion + noise P = 1W, f = 1 kHz fS Switching frequency Switching frequency selectable for AM interference avoidance RAIN Analog input resistance Internal shunt resistance on each input pin VIN_CM Common-mode input voltage AC-coupled common-mode input voltage (zero differential input) VCM_INT Internal common-mode input bias voltage Internal bias applied to IN_M pin G Voltage gain (VO/VIN) Source impedance = 0 Ω, gain measurement taken at 1 W of power per channel GCH Channel-to-channel variation Any gain commanded 85 dB 75 dB 0.02% 0.1% 336 357 378 392 417 442 470 500 530 63 85 106 1.3 kHz kΩ Vrms 3.3 V 11 12 13 19 20 21 25 26 27 31 32 33 –1 0 1 dB dB PWM OUTPUT STAGE RDSon FET drain-to-source resistance Not including bond wire resistance, TJ = 25°C VO_OFFSET Output offset voltage Zero input signal, G = 26 dB 65 90 mΩ ±10 ±50 mV PVDD OVERVOLTAGE (OV) PROTECTION VOV_SET PVDD overvoltage shutdown set 24.6 26.4 28.2 VOV_CLEAR PVDD overvoltage shutdown clear 24.4 25.9 27.4 V PVDD UNDERVOLTAGE (UV) PROTECTION VUV_SET PVDD undervoltage shutdown set 4.9 5.3 5.6 V VUV_CLEAR PVDD undervoltage shutdown clear 6.2 6.6 7.0 V AVDD VA_BYP A_BYP pin voltage 6.5 V VA_BYP_UV_SET A_BYP UV voltage 4.8 V VA_BYP_UV_CLEAR Recovery voltage A_BYP UV 5.3 V D_BYP pin voltage 3.3 V DVDD VD_BYP Copyright © 2012, Texas Instruments Incorporated 7 TAS5514B-Q1 SLOS768 – JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ, AES17 Filter, default I2C settings, master mode operation (see application diagram) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER-ON RESET (POR) VPOR PVDD voltage for POR VPOR_HY PVDD recovery hysteresis voltage for POR State machine active above this voltage 3.5 V 0.1 V 1.27 V REXT VREXT Rext pin voltage CHARGE PUMP (CP) VCPUV_SET CP undervoltage 4.8 V VCPUV_CLEAR Recovery voltage for CP UV 4.9 V OVERTEMPERATURE (OT) PROTECTION TOTW_CLEAR TOTW_SET TOTSD_CLEAR Junction temperature for overtemperature warning TOTSD Junction temperature for overtemperature shutdown TFB Junction temperature for overtemperature foldback Per channel 96 112 128 °C 106 122 138 °C 126 142 158 °C 136 152 168 °C 130 150 170 °C CURRENT LIMITING PROTECTION ILIM Current limit (load current) Level 1 5.5 7.3 9 Level 2 (default) 10.6 12.7 15 Level 2 (default), Any short to supply, ground, or other channels 11.9 14.8 17.7 A OVERCURRENT (OC) SHUTDOWN PROTECTION IMAX Maximum current (peak output current) A STANDBY MODE VIH_STBY STANDBY input voltage for logic-level high VIL_STBY STANDBY input voltage for logic-level low ISTBY_PIN STANDBY pin current 2 V 0.1 0.7 V 0.2 μA MUTE MODE GMUTE Output attenuation MUTE pin ≤ 0.5 V + 200mS 100 dB 25 % DC DETECT VTH_DC_TOL DC detect threshold tolerance tDCD DC detect step response time for four channels 5.3 s CLIP_OTW REPORT VOH_CLIPOTW CLIP_OTW pin output voltage for logic level high (open-drain logic output) VOL_CLIPOTW CLIP_OTW pin output voltage for logic level low (open-drain logic output) tDELAY_CLIPDET CLIP_OTW signal delay when output clipping detected 2.4 V External 47-kΩ pullup resistor to 3 V–5.5 V 0.5 V 20 μs FAULT REPORT VOH_FAULT VOL_FAULT FAULT pin output voltage for logic-level high (open-drain logic output) FAULT pin output voltage for logic-level low (open-drain logic output) 2.4 External 47-kΩ pullup resistor to 3 V–5.5 V V 0.5 OPEN/SHORT DIAGNOSTICS RS2P, RS2G Maximum resistance to detect a short from OUT pin(s) to PVDD or ground ROPEN_LOAD Minimum load resistance to detect open circuit Including speaker wires 300 RSHORTED_LOAD Maximum load resistance to detect short circuit Including speaker wires 0.5 8 200 Ω 740 1300 Ω 1 1.5 Ω Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 www.ti.com SLOS768 – JUNE 2012 ELECTRICAL CHARACTERISTICS (continued) Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ, AES17 Filter, default I2C settings, master mode operation (see application diagram) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Chip Select DECODER tLATCH_CS VCS Time delay to latch CS after POR μs 300 Voltage on CS pin for address 0 Connect to GND 0% 0% 15% Voltage on CS pin for address 1 Voltage on CS pin for address 2 External resistors in series between D_BYP and GND as a voltage divider 25% 35% 45% 55% 65% 75% Voltage on CS pin for address 3 Connect to D_BYP 85% 100% 100% VD_BYP OSCILLATOR VOH_OSCSYNC OSC_SYNC pin output voltage for logiclevel high VOL_OSCSYNC OSC_SYNC pin output voltage for logiclevel low VIH_OSCSYNC OSC_SYNC pin input voltage for logic-level high VIL_OSCSYNC OSC_SYNC pin input voltage for logic-level low fOSC_SYNC OSC_SYNC pin clock frequency Copyright © 2012, Texas Instruments Incorporated 2.4 V CS pin set to MASTER mode 0.5 2 V V CS pin set to SLAVE mode CS pin set to MASTER mode, fS = 417 kHz 3.13 3.33 0.8 V 3.63 MHz 9 TAS5514B-Q1 SLOS768 – JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS 10 THD+N vs BTL OUTPUT POWER at 1kHz THD+N vs PBTL OUTPUT POWER at 1kHz Figure 1. Figure 2. THD+N vs FREQUENCY at 1 Watt TAS5524B-Q1 COMMON-MODE REJECTION RATIO vs FREQUENCY Figure 3. Figure 4. Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 www.ti.com SLOS768 – JUNE 2012 TYPICAL CHARACTERISTICS (continued) CROSSTALK vs FREQUENCY NOISE FFT Figure 5. Figure 6. EFFICIENCY, FOUR CHANNELS AT 4 Ω EACH DEVICE POWER DISSIPATION FOUR CHANNELS AT 4 Ω EACH 100 12 90 10 80 Power Dissipation − W Efficiency − % 70 60 50 40 30 20 8 6 4 2 10 0 0 0 4 8 12 16 20 24 28 32 P − Power Per Channel − W G007 Figure 7. Copyright © 2012, Texas Instruments Incorporated 0 5 10 15 20 P − Power Per Channel − W G008 Figure 8. 11 TAS5514B-Q1 SLOS768 – JUNE 2012 www.ti.com DESCRIPTION OF OPERATION OVERVIEW The TAS5514B-Q1 is a single-chip, four-channel, analog-input audio amplifier for use in the automotive environment. The design uses an ultra-efficient class-D technology developed by Texas Instruments, but with changes needed by the automotive industry. This technology allows for reduced power consumption, reduced heat, and reduced peak currents in the electrical system. The device realizes an audio sound system design with smaller size and lower weight than traditional class-AB solutions. There are eight core design blocks: • Preamplifier • PWM • Gate drive • Power FETs • Diagnostics • Protection • Power supply • State machine Preamplifier The preamplifier is a high-input-impedance, low-noise, low-offset-voltage input stage with adjustable gain. The high input impedance allows the use of low-cost input capacitors while still achieving extended low-frequency response. The preamplifier is powered by a dedicated, internally regulated supply, which gives it excellent noise immunity and channel separation. Also included in the preamplifier is Mute Pop-and-Click Control—The device ramps the gain gradually when a mute or play command is received. Another form of click and pop can be caused by the start or stopping of switching in a class-D amplifier. The TAS5514B-Q1 incorporates a patented method to reduce the pop energy during the switching startup and shutdown sequences. Fault conditions require rapid protection response by the TAS5514B-Q1, which do not have time to ramp the gain down in a pop-free manner. The device transitions into Hi-Z mode when an OV, UV, OC, OT, or dc fault is encountered. Pulse-Width Modulator (PWM) The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is the critical stage that defines the class-D architecture. In the TAS5514B-Q1, the modulator is an advanced design with high bandwidth, low noise, low distortion, excellent stability, and full 0–100% modulation capability. The patented PWM uses clipping recovery circuitry to eliminate the deep saturation characteristic of PWMs when the input signal exceeds the modulator waveform. Gate Drive The gate driver accepts the low-voltage PWM signal and level-shifts it to drive a high-current, full-bridge, power FET stage. The device uses proprietary techniques to optimize EMI and audio performance. Power FETs The BTL output for each channel comprises four rugged N-channel 30-V 65-mΩ FETs for high efficiency and maximum power transfer to the load. These FETs are designed to handle large voltage transients during load dump. Load Diagnostics The device incorporates load diagnostic circuitry designed to help pinpoint the nature of output misconnections or faulty loads. The TAS5514B-Q1 includes functions for detecting and determining the status of output connections. The following diagnostics are performed when the device transitions from standby to play mode. • Short to GND • Short to PVDD • Short across load 12 Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 www.ti.com • SLOS768 – JUNE 2012 Open load The presence of any of the short or open conditions does not allow the channel with the fault to transition to play mode. Only an open load is allowed to transition to play mode. Output Short and Open Diagnostics—The device contains circuitry designed to detect shorts and open conditions on the outputs. There are four phases of test during load diagnostics and two levels of test. All four phases are tested on each channel, all four channels at the same time. The diagnostics are performed as shown in Figure 9. Figure 10 shows the impedance ranges for the open-load and shorted-load diagnostics. With the default value of the MUTE capacitor the S2G and S2P phase take approximately 20 ms each, the OL phase takes approximately 100 ms, and the SL phase takes approximately 230 ms. Figure 9. Load Diagnostics Sequence of Events Figure 10. Open- and Shorted-Load Detection Copyright © 2012, Texas Instruments Incorporated 13 TAS5514B-Q1 SLOS768 – JUNE 2012 www.ti.com Protection and Monitoring • • • • • • • Cycle-By-Cycle Current Limit (CBC)—The CBC current-limiting circuit terminates each PWM pulse to limit the output current flow when the average current limit (ILIM) threshold is exceeded. The overall effect on the audio in the case of a current overload is quite similar to a voltage-clipping event, where power is temporarily limited at the peaks of the musical signal and normal operation continues without disruption when the overload is removed. The TAS5514B-Q1 does not prematurely shut down in this condition. All four channels continue in play mode and pass signal. Overcurrent Shutdown (OCSD)—Under severe short-circuit events, such as a short to PVDD or ground, a peak-current detector is used, and the affected channel shuts down in 200 μs to 390 μs if the conditions are severe enough. The shutdown speed depends on a number of factors, such as the impedance of the short circuit, supply voltage, and switching frequency. Only the shorted channels are shut down in such a scenario. An OCSD event activates the fault pin, and the affected channel(s) are placed in Hi-Z mode. Normal operation is restored 1 second after the short is removed. If the supply or ground short is strong enough to exceed the peak current threshold but not severe enough to trigger the OCSD, the peak current limiter prevents excess current from damaging the output FETs, and operation returns to normal after the short is removed. DC Detect—This circuit detects a dc offset continuously during normal operation at the output of the amplifier. If the dc offset reaches the trip level for 1 second, the circuit triggers and latches off the output. The FAULT pin is asserted. The only method to recover is to cycle the device into standby mode and back to play mode. If the dc offset is still present, it latches off again after 1 second. Clip Detect—The clip detect circuit alerts the user to the presence of a 100% duty-cycle PWM due to a clipped waveform. When this occurs, a signal is passed to the CLIP_OTW pin, and this pin is asserted until the 100% duty-cycle PWM signal is no longer present. All four channels are connected to the same CLIP_OTW pin. Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD), and Thermal Foldback—By default, the CLIP_OTW pin is set to indicate an OTW. The CLIP_OTW pin is asserted when the die temperature reaches the warning level as shown in the electrical characteristics. The device still functions until the temperature reaches the OTSD threshold, at which time the outputs are placed into Hi-Z mode and the FAULT pin is asserted. After the OTSD recovers at the OTSD clear value, the device automatically returns to play mode. The OTW is still indicated until the temperature drops below warning level value. The thermal foldback decreases the channel gain. Undervoltage (UV) and Power-On-Reset (POR)—The undervoltage (UV) protection detects low voltages on PVDD, AVDD, and CP. In the event of an undervoltage, the FAULT pin is asserted. Power-on-reset (POR) occurs when PVDD drops low enough. Recovery from a POR event is the same as a transition from standby to play mode. Overvoltage (OV) and Load Dump—The OV protection detects high voltages on PVDD. If PVDD reaches the overvoltage threshold, the FAULT pin is asserted. The device can withstand 50-V load-dump voltage spikes. Also depicted in this graph are the voltage thresholds for normal operation region, overvoltage operation region, and load-dump protection region. Figure 9 shows the regions of operating voltage and the profile of the load dump event. Power Supply The power for the device is most commonly provided by a car battery that can have a large voltage range. PVDD is a filtered battery voltage, and it is the supply for the output FETS and the low-side FET gate driver. The highside FET gate driver is supplied by a charge pump (CP) supply. The charge pump supplies the gate-drive voltage for all four channels. The analog circuitry is powered by AVDD, which is provided by an internal linear regulator. A 0.1-μF/10V external bypass capacitor is needed at the A_BYP pin for this supply. It is recommended that no external components except the bypass capacitor be attached to this pin. The digital circuitry is powered by DVDD, which is provided by an internal linear regulator. A 0.1-μF/10V external bypass capacitor is needed at the D_BYP pin. It is recommended that no external components except the bypass capacitor and CS encoding resistors be attached to this pin. The TAS5514B-Q1 can withstand fortuitous open-ground and power conditions. Fortuitous open ground usually occurs when a speaker wire is shorted to ground, allowing for a second ground path through the body diode in the output FETs. The diagnostic capability allows the speakers and speaker wires to be debugged, eliminating the need to remove the amplifier to diagnose the problem. 14 Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 www.ti.com SLOS768 – JUNE 2012 Oscillator Master/Slave Operation The TAS5514B includes a single pin that allows for multiple devices to work together in a system with no additional hardware required for synchronization. The CS pin sets the device in master or slave mode. Connect the CS pin to GND for master mode, but no clock is on available on the OSC_SYNC pin. Connect the CS pin to 1.2 Vdc for a master mode with a clock on the OSC_SYNC pin, and to D_BYP for slave mode. In slave mode, the OSC_SYNC pin accepts a clock signal from a master device or external clock. The outputs cease to switch if an oscillator is not present on the OSC_SYNC pin while in slave mode. Table 2. Table 7. CS Pin Connection DESCRIPTION CS PIN CONNECTION TAS5514B-Q1 (master without clock) To SGND pin TAS5514B-Q1 (master with clock) 35% DVDD (resistive voltage divider between D_BYP pin and SGND pin) (1) TAS5514B-Q1 (slave) To D_BYP pin (1) RCS with 5% or better tolerance is recommended. Hardware Control Pins There are four discrete hardware pins for real-time control and indication of device status. FAULT pin: This active-low open-drain output pin indicates the presence of a fault condition that requires the device to go into the Hi-Z mode or standby mode. When this pin is asserted, the device has protected itself and the system from potential damage. However, the fault is still indicated due to the fact that the FAULT pin is asserted. When the fault is removed, the device transitions from standby mode to play mode. CLIP_OTW pin: This active-low open-drain pin is configured to indicate both overtemperature warning and the detection of clipping. MUTE pin: This active-low pin is used for hardware control of the mute/unmute function for all four channels. Capacitor CMUTE is used to control the time constant for the gain ramp needed to produce a pop- and clickfree mute function. The use of a hard mute with an external transistor does not ensure pop- and click-free operation, and is not recommended unless an emergency hard mute function is required. The CMUTE capacitor may not be shared between multiple devices. STANDBY pin: When this active-low pin is asserted, the device goes into a complete shutdown, and current draw is limited to 2 μA, typical. It can be used to shut down the device rapidly. If all channels are in Hi-Z, the device enters standby in approximately 1 ms, and if not, a quick rampdown occurs that takes approximately 20 ms. The outputs are ramped down quickly if not already in Hi-Z, so externally biasing the MUTE pin prevents the device from entering standby. EMI Considerations Automotive-level EMI performance depends on both careful integrated circuit design and good system-level design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the design. The design has minimal parasitic inductances due to the short leads on the package. This dramatically reduces the EMI that results from current passing from the die to the system PCB. Each channel also operates at a different phase to reduce EMI caused by high-current switching. The design also incorporates circuitry that optimizes output transitions that cause EMI. Operating Modes and Faults The operating modes and faults are depicted in the following tables. Copyright © 2012, Texas Instruments Incorporated 15 TAS5514B-Q1 SLOS768 – JUNE 2012 www.ti.com Table 3. Operating Modes STATE NAME OUTPUT FETS CHARGE PUMP OSCILLATOR AVDD and DVDD STANDBY Hi-Z, floating Stopped Stopped OFF Hi-Z Hi-Z, weak pulldown Active Active ON Mute Switching at 50% Active Active ON Normal operation Switching with audio Active Active ON Table 4. Global Faults and Actions FAULT/ EVENT FAULT/EVENT CATEGORY MONITORING MODES REPORTING METHOD ACTION TYPE ACTION RESULT LATCHED/ SELFCLEARING POR Voltage fault All FAULT pin Hard mute (no ramp) Standby Self-clearing Hi-Z, mute, normal FAULT pin Hi-Z All FAULT pin Standby UV CP UV OV Load dump OTW Thermal warning Hi-Z, mute, normal CLIP_OTW pin None None OTSD Thermal fault Hi-Z, mute, normal FAULT pin Hard mute (no ramp) Standby Table 5. Channel Faults and Actions FAULT/ EVENT FAULT/EVENT CATEGORY MONITORING MODES REPORTING METHOD ACTION TYPE ACTION RESULT LATCHED/ SELFCLEARING Open/short diagnostic Diagnostic at turnon Hi-Z Channel does not play None None Self-clearing Play CLIP_OTW pin Clipping Warning CBC load current limit Online protection OC fault Output channel fault FAULT pin DC detect OT Foldback 16 Warning CLIP_OTW pin None None Current Limit Start OC timer Hard mute Hi-Z Hard mute Hi-Z Latched Reduce Gain None Self-clearing Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 www.ti.com SLOS768 – JUNE 2012 Audio Shutdown and Restart Sequence The gain ramp of the filtered output signal corresponds to the MUTE pin voltage during the ramping process. The length of time that the MUTE pin takes to complete its ramp is dictated by the value of the external capacitor on the MUTE pin. With the default 220-nF capacitor, the turnon common-mode ramp takes approximately 26ms and the gain ramp takes approximately 76 ms. Figure 11. Click- and Pop-Free Shutdown and Restart Sequence Timing Diagram Fault Shutdown and Restart Sequence Control Figure 12. Global Fault Shutdown and Restart Diagram (UV Shutdown and Auto-Recovery) Copyright © 2012, Texas Instruments Incorporated 17 TAS5514B-Q1 SLOS768 – JUNE 2012 www.ti.com Figure 13. Channel-Fault Shutdown and Individual Channel Restart Diagram 18 Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 www.ti.com SLOS768 – JUNE 2012 APPLICATION INFORMATION Figure 14. TAS5514B-Q1 Typical Application Schematic Copyright © 2012, Texas Instruments Incorporated 19 TAS5514B-Q1 SLOS768 – JUNE 2012 www.ti.com Parallel Operation (PBTL) The device can drive more current paralleling BTL channels on the load side of the LC output filter. For parallel operation, identical I2C settings are required for any two paralleled channels in order to have reliable system performance and even power dissipation on multiple channels. For smooth power up, power down, and mute operation, the same control commands (such as mute, play, Hi-Z, etc.) should be sent to the paralleled channels at the same time. Load diagnostic is also supported for parallel connection. Paralleling on the device side of the LC output filter is not supported, and can result in device failure. When paralleling channels, it is important to monitor channels for thermal foldback and lower the system gain for paralleled channels. Input Filter Design The input filter for the TAS5514B-Q1 IN_M pin should have an impedance to GND that is equivalent to the parallel combination of the input impedances of all IN_P channels combined, including any source impedance from the previous stage in the system design. For example, if each of the four IN_P channels has a 1-µF dc blocking capacitor, 1 kΩ of series resistance due to an input RC filter, and 1 kΩ of source resistance from the DAC supplying the audio signal, then the IN_M channel should have a 4-µF capacitor in series with a 500-Ω resistor to GND (4 × 1 µF in parallel = 4 µF; 4 × 2 kΩ in parallel = 500 Ω). Demodulation Filter Design The amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. These transistors are either fully off or on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. It is recommended that a second-order LC filter be used to recover the audio signal. The main purpose of the demodulation filter is to attenuate the high-frequency components of the output signals that are out of the audio band. Design of the demodulation filter significantly affects the audio performance of the power amplifier. Therefore, to meet the system THD+N needs, the selection of the inductors used in the output filter should be carefully considered. The rule is that the inductance should stay above 10% of the inductance value within the range of peak current seen at maximum output power in the system design. Line Driver Applications In many automotive audio applications, the end user would like to use the same head unit to drive either a speaker (with several ohms of impedance) or an external amplifier (with several kilohms of impedance). The design is capable of supporting both applications; however, the output filter and system must be designed to handle the expected output load conditions. Thermal Information The thermally augmented package is designed to interface directly to heat sinks using a thermal interface compound (for example, Arctic Silver or Ceramique thermal compound). The heat sink then absorbs heat from the ICs and couples it to the local air. If proper thermal management is applied, a proper operating temperature can be maintained the heat can be continually removed from the ICs. Because of the device efficiency, heat sinks can be smaller than those required for linear amplifiers of equivalent performance. RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the following components: • RθJC (the thermal resistance from junction to case, or in this case the heat slug) • Thermal grease thermal resistance • Heat sink thermal resistance The thermal grease thermal resistance can be calculated from the exposed heat slug area and the thermal grease manufacturer's area thermal resistance (expressed in °C-in2/W or °C-mm2/W). The area thermal resistance of the example thermal grease with a 0.001-inch (0.0254-mm) thick layer is about 0.007°C-in2/W (4.52°C-mm2/W). The approximate exposed heat slug size is as follows: 36-pin PSOP3 20 0.124 in2 (80 mm2) Copyright © 2012, Texas Instruments Incorporated TAS5514B-Q1 www.ti.com SLOS768 – JUNE 2012 Dividing the example thermal grease area resistance by the area of the heat slug gives the actual resistance through the thermal grease for both parts: 36-pin PSOP3 0.06°C/W The thermal resistance of thermal pads is generally considerably higher than that of a thin thermal grease layer. Thermal tape has an even higher thermal resistance and should not be used at all. Heat sink thermal resistance generally is predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD) model, or measured. Thus, for a single monaural channel in the IC, the system RθJA = RθJC + thermal grease resistance + heat sink resistance. The following table indicates modeled parameters for one device on a heat sink. The junction temperature is set at 115°C while delivering 20 Wrms per channel into 4-Ω loads with no clipping. It is assumed that the thermal grease is about 0.001 inches (0.0254 mm) thick. Device 36-Pin PSOP3 Ambient temperature 25°C Power to load 20 W × 4 Power dissipation 1.90 W × 4 ΔT inside package 7.6°C ΔT through thermal grease 0.46°C Required heatsink thermal resistance 10.78°C/W Junction temperature 115°C System RθJA 11.85°C/W RθJA × power dissipation 90°C Electrical Connection of Heat Slug and Heat Sink The heat sink connected to the heat slug of the device should be connected to GND or left floating. The heat slug should not be connected to any other electrical node. Copyright © 2012, Texas Instruments Incorporated 21 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) TAS5514BTDKDRQ1 LIFEBUY HSSOP DKD 36 500 RoHS & Green NIPDAU Level-3-245C-168 HR -40 to 105 TAS5514BQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of