TAS5518PAG

TAS5518 8 Channel Digital Audio PWM Processor Data Manual Literature Number: SLES115 August 2004 TM TAS5518 8 Channel Digital Audio PWM Processor Data Manual 2004 DAV−Digital Audio/Speaker SLES115 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Applications amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright © 2004, Texas Instruments Incorporated Contents Contents Section 1 2 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 TAS5518 System Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 TAS5518 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Audio Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 PWM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3 Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 TAS5518 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Clock, PLL, and Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 I2C Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Device Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.5 Digital Audio Processor (DAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 TAS5518 DAP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 TAS5518 DAP Architecture Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 I2C Coefficient Number Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Input Crossbar Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Biquad Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 Bass and Treble Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Volume, Auto Mute, and Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.1 Auto Mute and Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 Loudness Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.1 Loudness Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11.2 Compression/Expansion Coefficient Computation Engine Parameters . . . . . . . . . . 1.12 Output Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.13 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.13.1 DC Blocking (High Pass Enable/ Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.13.2 De-Emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.13.3 Power Supply Volume Control (PSVC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.13.4 AM Interference Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TAS5518 Controls and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 I2C Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 General Status Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Error Status Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 TAS5518 Pin Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Power Down (PDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Backend Error (BKND_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Speaker / Headphone Selector (HP_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Mute (MUTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . July 2004 SLES115 1 2 3 3 3 4 4 5 5 5 5 8 8 8 9 9 9 11 11 14 18 19 19 20 21 21 23 26 29 29 30 30 30 31 33 33 33 33 33 33 35 35 36 36 iii Contents 2.3 3 4 5 iv Device Configuration Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Channel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Headphone Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Audio System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 Recovery from Clock Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 Power Supply Volume Control Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 Volume and Mute Update Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.7 Modulation Index Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.8 Inter-channel Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Master Clock and Serial Data Rate Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Bank Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 Manual Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Automatic Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 Bank Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Bank Switch Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.5 Bank Switching Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.6 Bank Switching Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Dynamic Performance (At Recommended Operating Conditions at 25°C) . . . . . . . . . . . . . . . . 3.3 Recommended Operating Conditions (over 0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . 3.5 PWM Operation at Recommended Operating Conditions Over 0°C to 70°C . . . . . . . . . . . . . . . 3.6 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Clock Signals Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . 3.6.2 Serial Audio Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 I2C Serial Control Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.4 Reset Timing (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.5 Power-Down (PDN) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.6 Backend Error (BKND_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.7 MUTE Timing—MUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.8 Headphone Select (HP_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.9 Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Serial Audio Interface Control and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 I2S Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 Left Justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 Right Justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Serial Control Interface (Slave Address 0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 General I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Single and Multiple Byte Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Single Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Multiple Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Incremental Multiple Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Single Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Multiple Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control I2C Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLES115 36 37 38 38 39 39 40 40 41 41 42 42 42 42 43 43 43 44 45 45 45 45 46 46 46 46 47 48 49 49 50 50 51 52 52 52 53 54 55 55 55 56 56 56 57 57 59 July 2004 Contents 6 7 Serial Control Interface Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Clock Control Register (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 General Status Register 0 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Error Status Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 System Control Register 1 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 System Control Register 2 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Channel Configuration Control Register (0x05−X0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Headphone Configuration Control Register (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Serial Data Interface Control Register (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 Soft Mute Register (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Automute Control Register(0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 Automute PWM Threshold and Backend Reset Period (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 Modulation Index Limit Register (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 Interchannel Channel Delay Registers (0x1B − 0x22) and Offset Register (0x23) . . . . . . . . . . 6.14 Bank Switching Command (0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15 Input Mixer Registers (0x41 – 0x48, Channels 1 − 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16 Bass Management Registers (0x49 – 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17 Biquad Filters Register (0x51 – 0x88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 Bass and Treble Bypass Register (0x89 – 0x90, Channels 1 − 8) . . . . . . . . . . . . . . . . . . . . . . . . 6.19 Loudness Registers (0x91 – 0x95) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20 DRC1 Control (0x96, Channels 1−7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21 DRC2 Control (0x97, Channel 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.22 DRC1 Data Registers (0x98 – 0x9C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.23 DRC2 Data Registers (0x9D – 0xA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24 DRC Bypass Registers (0xA2 – 0xA9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.25 8x2 Output Mixer Registers (0xAA – 0xAF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.26 8x3 Output Mixer Registers (0xB0 – 0xB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.27 Volume Biquad Register (0xCF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.28 Volume Treble and Bass Slew Rates (0xD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29 Volume Registers (0xD1 − 0xD9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30 Bass Filter Set Register (0xDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31 Bass Filter Index Register (0xDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32 Treble Filter Set Register (0xDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33 Treble Filter Index (0xDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.34 AM Mode Register (0xDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.35 PSVC Range Register (0xDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.36 General Control Register (0xE0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.37 Incremental Multiple Write Append Register (0xFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TAS5518 Example Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . July 2004 SLES115 65 65 65 65 66 66 66 67 67 68 68 69 70 70 71 72 75 75 76 76 77 77 78 79 80 80 81 83 83 83 84 85 86 87 88 88 89 89 91 v List of Illustrations List of Illustrations Figure Title Page 1−1. TAS5518 Functional Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2. Typical TAS5518 Application (DVD Receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3. Recommended TAS5518 + TAS5121 Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4. TAS5518 DAP Architecture With I2C Registers (Fs 3 96 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5. TAS5518 Architecture With I2C Registers (Fs = 176.4 kHz or Fs = 192 kHz) . . . . . . . . . . . . . . . . . . . 1−6. TAS5518 Detailed Channel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−7. 5.23 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−8. Conversion Weighting Factors—5.23 Format to Floating Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−9. Alignment of 5.23 Coefficient in 32-Bit I2C Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−10. 25.23 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−11. Alignment of 5.23 Coefficient in 32-Bit I2C Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−12. Alignment of 25.23 Coefficient in Two 32-Bit I2C Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−13. TAS5518 Digital Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−14. Input Crossbar Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−15. Biquad Filter Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−16. Auto Mute Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−17. Loudness Compensation Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−18. Loudness Example Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−19. DRC Positioning in TAS5518 Processing Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−20. Dynamic Range Compression (DRC) Transfer Function Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−21. Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−22. De-emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−23. Power Supply and Digital Gains (Log Space) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−24. Power Supply and Digital Gains (Linear Space) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−25. Block Diagrams of Typical Systems Requiring TAS5518 Automatic AM Interference Avoidance Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1. Slave Mode Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2. SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3. Start and Stop Conditions Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5. Power-Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6. Error Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7. Mute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8. HP_SEL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9. I2S Format 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10. Left Justified 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11. Right Justified 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1. Typical I2C Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2. Single Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3. Multiple Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4. Single Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2 12 13 14 15 15 15 16 16 17 17 18 19 21 22 23 25 25 29 30 31 31 4−5. Multiple Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 vi SLES115 32 47 48 48 49 49 50 50 51 52 53 54 55 56 56 57 July 2004 List of Tables List of Tables Table Title Page 1−1. Serial Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2. TAS5518 Audio Processing Feature Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass) . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4. Bass and Treble Filter Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5. Linear Gain Step Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−6. Default Loudness Compensation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−7. Loudness Function Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−8. DRC Recommended Changes From TAS5518 Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1. Device Outputs During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2. Values Set During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3. Device Outputs During Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4. Device Outputs During Backend Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5. Description of the Channel Configuration Registers (0x05 to 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−6. Recommended TAS5518 Configurations for Texas Instruments Power Stages . . . . . . . . . . . . . . . . . 2−7. Audio System Configuration (General Control Register 0xE0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−8. Volume Ramp Rates in ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−9. Inter-Channel Delay Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1. Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2. General Status Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3. Error Status Register (0X02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−4. System Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−5. System Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−6. Channel Configuration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7. Headphone Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−8. Serial Data Interface Control Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−9. Soft Mute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−10. Automute Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−11. Automute PWM Threshold and Backend Reset Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−12. Modulation Index Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−13. Interchannel Channel Delay Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−14. Channel Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−15. Bank Switching Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−16. Input Mixer Registers Format (0x41 – 0x48, Channels 1 − 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−17. Bass Management Registers Format (0x49 – 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−18. Biquad Filters Registers Format (0x51 – 0x88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−19. Contents of One 20-Byte Biquad Filter Register Format (Default = All-pass) . . . . . . . . . . . . . . . . . . 6−20. Bass and Treble Bypass Register Format (0x89−0x90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−21. Loudness Registers Format (0x91 – 0x95) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−22. DCR1 Control (0x96, Channels 1−7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−23. DRC2 Control (0x97, Channel 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−24. DRC1 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−25. DRC2 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−26. DRC Bypass Registers Format (0xA2−0xA9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−27. Output Mixer Control Register Format (Upper 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−28. Output Mixer Control (Lower 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−29. Output Mixer Control (Upper 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−30. Output Mixer Control (Middle 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . July 2004 SLES115 9 11 19 20 20 22 23 24 33 34 35 36 37 38 38 40 41 65 65 65 66 66 66 67 67 68 68 69 70 70 70 71 72 75 75 76 76 76 77 77 78 79 80 80 81 81 82 vii List of Tables 6−31. 6−32. 6−33. 6−34. 6−35. 6−36. 6−37. 6−38. 6−39. 6−40. 6−41. 6−42. 6−43. 6−44. 6−45. 6−46. 6−47. 6−48. 6−49. 6−50. 6−51. 6−52. 6−53. viii Output Mixer Control (Lower 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Volume Biquad Register Format (Default = All-pass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Volume Gain Update Rate (Slew Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Treble and Bass Gain Step Size (Slew Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Volume Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master and Individual Volume Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 8 Sub Woofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration Right and Left Surround in Eight Channel Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 4 and 3 (Right and Left Rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 7, 2, 1 (Center, Right Front, and Left Front) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bass Filter Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bass Filter Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 8 Sub Woofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration or Right and Left Surround in Eight Channel Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 4 and 3 (Right and Left Rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 7, 2, 1 (Center, Right Front, and Left Front) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Treble Filter Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Treble Filter Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AM Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE) . . . . . . . . . . . . . . . . . . . . . . . AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE) . . . . . . . . . . . . . . . . . . . . . PSVC Range Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLES115 82 83 83 83 83 84 84 85 85 85 85 86 86 86 87 87 87 87 88 88 88 88 89 July 2004 Introduction 1 Introduction The TAS5518 is an eight channel digital pulse width a modulator (PWM) that provides superior dynamic range performance and a high level of system integration. The typical dynamic range in a well-designed system is 110 dB and the power supply volume control (PSVC) feature provides up to 24 dB of additional dynamic range at normal listening levels. The TAS5518 is designed to interface seamlessly with most audio digital signal processors. This device automatically adjusts control configurations in response to clock and data rate changes and idle conditions. This enables the TAS5518 to provide an easy to use control interface with relaxed timing requirements. The TAS5518 can drive eight channels of H-bridge power stages. Texas Instruments H-bridge devices TAS5111, TAS5112, and TAS5182 + FETs are designed to work seamlessly with the TAS5518. The TAS5518 supports both single-ended or bridge-tied load configurations. It also provides a high-performance differential output to drive an external differential input analog headphone amplifier (such as the TPA112). The TAS5518 uses an AD modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data. The 8x over sampling, combined with a 5th-order noise shaper, provides a broad flat noise floor and excellent dynamic range from 20 Hz to 20 kHz. VR_PLL AVDD_PLL AVSS_PLL AVDD_REF VBGAP VRA_PLL VRD_PLL DVDD DVSS AVDD AVSS The TAS5518 is a clock slave-only device. It receives MCLK, SCLK, and LRCLK from other system components. It accepts master clock rates of 128, 192, 256, 384, 512, and 768 Fs and a 64-Fs bit clock. Power Supply RESET PDN PWM Control MUTE HP_SEL BKND_ERR Loud DRC Comp DC De Interpo SRC NS PWM Block Emph late 0 7 Soft Soft Det Biquads Tone Vol Loud DRC Comp DC De Interpo SRC NS PWM Block Emph late 0 7 Soft Soft Det Biquads Tone Vol Loud DRC Comp 0 7 Soft Soft Det Biquads Tone Vol Loud DRC Comp 0 7 Soft Soft Det Biquads Tone Vol Loud DRC Comp 0 7 Soft Soft Det Biquads Tone Vol Loud DRC Comp 0 7 Soft Soft Det Biquads Tone Vol Loud DRC Comp DC De Interpo SRC NS PWM Block Emph late 0 7 Soft Soft Det Biquads Tone Vol Loud DRC Comp DC De Interpo SRC NS PWM Block Emph late 8 8 9 4 Volume Control 8 2 DC De Interpo SRC NS PWM Block Emph late DC De Interpo SRC NS PWM Block Emph late DC De Interpo SRC NS PWM Block Emph late PWM AP& AM1 L Front PWM AP& AM2 R Front Output Control 0 7 Soft Soft Det Biquads Tone Vol 8 x 2 Crossbar Mixer 8 x 8 Crossbar Mixer SCL Serial Control IF DAP Control SDA Control System Control SDIN1 SDIN2 SDIN3 SDIN4 Clock, PLL, and Serial Data I/F MCLK XTL_ OUT XTL_ IN PLL_FLTM PLL_FLTP OSC CAP SCLK LRCLK PWM_HPP& MR PWM_HPP & ML PWM Section Digital Audio Processor DC De Interpo SRC NS PWM Block Emph late 8 PWM AP& AM3 L Rear PWM AP& AM4 R Rear PWM AP& Am7 Center PWM AP& AM8 Sub woofer PWM AP& AM5 L Surround PWM L Line Out PWM AP& AM6 R Surround PWM R Line Out 8 VALID 2 PSVC PSVC Figure 1−1. TAS5518 Functional Structure SLES115 — August 2004 TAS5518 1 Introduction 1.1 TAS5518 System Diagrams Typical applications for the TAS5518 are 6- to 8-channel audio systems such as DVD receiver or AV receiver. Figure 1−2 shows the basic system diagram of the DVD receiver. AM Texas Instruments Digital Audio Amplifier FM Power Supply Tuner TAS5518 MPEG Decoder DVD Loader Micro Front-Panel Controls Figure 1−2. Typical TAS5518 Application (DVD Receiver) Figure 1−3 shows the recommended channel configuration when using the TAS5518 with the TAS5121 power stage. Note that each channel is normally dedicated to a particular function. − TAS5121 − + TAS5121 PWM_M_1 + LEFT PWM_P_1 TAS5121 PWM_P_3 PWM_P_4 − PWM_M_2 + TAS5121 PWM_M_4 TAS5121 − RIGHT PWM_P_2 + LEFT SURROUND PWM_M_3 − + PWM_M_7 TAS5121 − RIGHT SURROUND CENTER PWM_P_7 TAS5121 + PWM_M_8 PWM_M_6 PWM_P_6 TAS5121 − + PWM_P_8 − SUBWOOFER PWM_M_5 + LEFT BACK SURROUND PWM_P_5 RIGHT BACK SURROUND TAS5518 PWM to Analog (Line Level) Headphone Out Right Headphone Out Left HW Control & Status Clocks PWM to Analog (Headphone Level) I2C Control & Status Lineout Left SDIN1,2,3,4 (8 chan. PCM) Lineout Right Figure 1−3. Recommended TAS5518 + TAS5121 Channel Configuration 2 TAS5518 SLES115 — August 2004 Introduction 1.2 TAS5518 Features 1.2.1 Audio Input / Output • Automatic Master Clock Rate and Data Sample Rate Detection • Eight Serial Audio Input Channels • Eight PWM Audio Output Channels Configurable as Six Channels With Stereo Line Out or Eight Channels • Line Output is a PWM Output to Drive an External Differential Input Operational Amplifier • Headphone PWM Output to Drive an External Differential Amplifier Like the TPA112 • PWM Outputs Support Single Ended and Bridge Tied Loads • 32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Sampling Rates • Data Formats: 16-, 20-, or 24-bit input Data Left, Right and I2S, • 64 x Fs Bit Clock Rate • 128, 192, 256, 384, 512, and 768 x Fs Master Clock Rates (Up to a Maximum of 50 MHz) 1.2.2 Audio Processing • 48-Bit Processing Architecture With 76 bits of Precision for Most Audio Processing Features • Volume Control Range +36 dB to – 127 dB − Master Volume Control Range of +18 dB to –100 dB − Eight Individual Channel Volume Control Range of +18-dB to −127-dB • Programmable Soft Volume and Mute Update Rates • Four Bass and Treble Tone Controls with ±18-dB Range, Selectable Corner Frequencies, and 2nd Order Slopes − L, R, and C − LS, RS − LR, RR − Sub • Configurable Loudness Compensation • Two Dynamic Range Compressors With Two Thresholds, Two Offsets, and Three Slopes • Seven Bi-quads Per Channel • Full 8x8 Input Crossbar Mixer. Each Signal Processing Channel Input Can Be Any Ratio of the Eight Input Channels • 8x2 Output Mixer – Channels 1−6. Each Output Can Be Any Ratio of Any Two Signal Processed Channels • 8x3 Output mixer – Channels 7 and 8. Each Output can be Any Ratio of Any Three Signal Processed Channels • Three Coefficient Sets Stored on the Device Can be Selected Manually or Automatically (Based on Specific Data Rates) • DC Blocking Filters • Able to Support a Variety of Bass Management Algorithms SLES115 — August 2004 TAS5518 3 Introduction 1.2.3 PWM Processing • 32-Bit Processing PWM Architecture With 40 Bits of Precision • 8x Oversampling With 5th Order Noise Shaping at 32 – 48 kHz, 4x Oversampling at 88.2 kHz, and 96 kHz and 2x Oversampling at 176.4 kHz and 192 kHz • >110-dB Dynamic Range • THD+N < 0.1% • 20 – 20-kHz Flat Noise Floor for 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Data Rates • Digital De-emphasis for 32-, 44.1-, and 48-kHz Data Rates • Flexible Automute Logic With Programmable Threshold and Duration for Noise Free Operation • Intelligent AM Interference Avoidance System Provides Clear AM Reception • Power Supply Volume Control (PSVC) Support for Enhanced Dynamic Range in High Performance Applications • Adjustable Modulation Limit 1.2.4 General Features 4 • Automated Operation With an Easy to Use Control Interface • I2C Serial Control Slave Interface • Integrated AM Interference Avoidance Circuitry • Single 3.3-V Power Supply • 64-Pin TQFP Package • 5-V Tolerant Inputs TAS5518 SLES115 — August 2004 Introduction 1.3 Physical Characteristics 1.3.1 Terminal Assignments RESERVED MCLK PWM_HPPR PWM_HPMR PWM_HPPL PWM_HPML PWM_P_6 PWM_M_6 PWM_P_5 PWM_M_5 DVDD_PWM DVSS_PWM PWM_P_8 PWM_M_8 PWM_P_7 PWM_M_7 TQFP PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VRA_PLL PLL_FLT_RET PLL_FLTM PLL_FLTP AVSS AVSS VRD_PLL AVSS_PLL AVDD_PLL VBGAP RESET HP_SEL PDN MUTE DVDD DVSS 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 VR_PWM PWM_P_4 PWM_M_4 PWM_P_3 PWM_M_3 PWM_P_2 PWM_M_2 PWM_P_1 PWM_M_1 VALID DVSS BKND_ERR DVDD DVSS DVSS VR_DIG VR_DPLL OSC_CAP XTL_OUT XTL_IN RESERVED RESERVED RESERVED SDA SCL LRCLK SCLK SDIN4 SDIN3 SDIN2 SDIN1 PSVC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1.3.2 Ordering Information TA PLASTIC 64-PIN PQFP (PN) 0°C to 70°C TAS5518PAG 1.3.3 Terminal Descriptions TERMINAL NO. NAME I/O 5-V TOLERANT TERMINATION DESCRIPTION 1 VRA_PLL 2 PLL_FLT_RET AO PLL external filter return 3 PLL_FLTM AO PLL negative input. Connected to PLL_FLT_RTN via an RC network 4 PLL_FLTP AI PLL positive input. Connected to PLL_FLT_RTN via an RC network 5 AVSS P Analog ground 6 AVSS P Analog ground SLES115 — August 2004 Voltage reference for PLL analog supply 1.8 V. A pin-out of the internally regulated 1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices. TAS5518 5 Introduction TERMINAL NO. 6 NAME I/O 5-V TOLERANT TERMINATION DESCRIPTION 7 VRD_PLL P Voltage reference for PLL digital supply 1.8 V. A pin-out of the internally regulated 1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices. 8 AVSS_PLL P Analog ground for PLL. This terminal should reference the same ground as power terminal DVSS, but to achieve low PLL jitter; ground noise at this terminal must be minimized. The availability of the AVSS terminal allows a designer to use optimizing techniques such as star ground connections, separate ground planes, or other quiet ground distribution techniques to achieve a quiet ground reference at this terminal. 9 AVDD_PLL P 3.3-V analog power supply for PLL This terminal can be connected to the same power source used to drive power terminal DVDD, but to achieve low PLL jitter, this terminal should be bypassed to AVSS_PLL with a 0.1-µF low-ESR capacitor. 10 VBGAP P Band gap voltage reference. A pin-out of the internally regulated 1.2-V reference. Typically has a 1-nF low ESR capacitor between VBGAP and AVSS_PLL. This terminal must not be used to power external devices. 11 RESET DI 5V Pull up System reset input, active low. A system reset is generated by applying a logic low to this terminal. RESET is an asynchronous control signal that restores the TAS5518 to its default conditions, sets the valid output low, and places the PWM in the hard mute (M) state. Master volume is immediately set to full attenuation. Upon the release of RESET, if PDN is high, the system performs a 4−5 ms. device initialization and set the volume at mute. 12 HP_SEL DI 5V Pull up Headphone in/out selector. When a logic low is applied, the headphone is selected (speakers are off). When a logic high is applied, speakers are selected – headphone is off. 13 PDN DI 5V Pull up Power down, active low. PDN powers down all logic and stops all clocks whenever a logic low is applied. The internal parameters are preserved through a power down cycle, as long as a RESET is not active. The duration for system recovery from power down is 100 ms. 14 MUTE DI 5V Pull up Soft mute of outputs, active low (Muted signal = a logic low, normal operation = a logic high) The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume. 15 DVDD P Digital power 3.3-V supply for digital core and most of I/O buffers 16 DVSS P Digital ground for digital core and most of I/O buffers 17 VR_DPLL P Voltage reference for digital PLL supply 1.8 V. A pin-out of the internally regulated 1.8-V power used by digital PLL logic. A 0.1−µF low ESR capacitor should be connected between this terminal and DVSS_CORE. This terminal must not be used to power external devices. 18 OSC_CAP AO Oscillator capacitor 19 XTL_OUT AO XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They provide a reference clock for the TAS5518 via use of an external fundamental mode crystal. XTL_OUT is the 1.8-V output drive to the crystal. See Note 4 for the recommended crystal type. 20 XTL_IN AI XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They provide a reference clock for the TAS5518 via use of an external fundamental mode crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. See Note 4 for the recommended crystal type. 21 RESERVED Connect to digital ground 22 RESERVED Connect to digital ground 23 RESERVED 24 SDA DIO 5V I2C serial control data interface input / output 25 SCL DI 5V I2C serial control clock input output 26 LRCLK DI 5V Serial audio data left / right clock (sampling rate clock) 27 SCLK DI 5V Serial audio data clock (shift clock) SCLKIN is the serial audio port (SAP) input data bit clock that is supplied to the serial bit clock to other I2S bus. TAS5518 Connect to digital ground SLES115 — August 2004 Introduction TERMINAL NO. NAME I/O 5-V TOLERANT TERMINATION DESCRIPTION 28 SDIN4 DI 5V Pulldown Serial audio data 4 input is one of the serial data input ports. SDIN4 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs. 29 SDIN3 DI 5V Pulldown Serial audio data 3 input is one of the serial data input ports. SDIN3 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs. 30 SDIN2 DI 5V Pulldown Serial audio data 2 input is one of the serial data input ports. SDIN2 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs. 31 SDIN1 DI 5V Pulldown Serial audio data 1 input is one of the serial data input ports. SDIN1 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs. 32 PSVC O Power supply volume control PWM output 33 VR_DIG P Voltage reference for digital core supply 1.8 V. A pin-out of the internally regulated 1.8-V power used by digital core logic. A 0.47-µF low ESR capacitor should be connected between this terminal and DVSS. This terminal must not be used to power external devices 34 DVSS P Digital ground 35 DVSS P Digital ground 36 DVDD P 3.3-V digital power supply 37 BKND_ERR DI 38 DVSS P 39 VALID DO Output indicating validity of PWM outputs active high 40 PWM_M_1 DO PWM 1 output (differential −) 41 PWM_P_1 DO PWM 1 output (differential +) 42 PWM_M_2 DO PWM 2 output (differential −) 43 PWM_P_2 DO PWM 2 output (differential +) 44 PWM_M_3 DO PWM 3 output (differential −) 45 PWM_P_3 DO PWM 3 output (differential +) 46 PWM_M_4 DO PWM 4 output (differential −) 47 PWM_P_4 DO PWM 4 output (differential +) 48 VR_PWM P 49 PWM_M_7 DO PWM 7 (Line out L) output (differential −) 50 PWM_P_7 DO PWM 7 (Line out L) output (differential +) 51 PWM_M_8 DO PWM 8 (Line out R) output (differential −) 52 PWM_P_8 DO PWM 8 (Line out R) output (differential +) 53 DVSS_PWM 54 DVDD_PWM 55 PWM_M_5 DO PWM 5 output (differential −) 56 PWM_P_5 DO PWM 5 output (differential +) 57 PWM_M_6 DO PWM 6 output (differential −) 58 PWM_P_6 DO PWM 6 output (differential +) 59 PWM_HPML DO PWM left channel headphone (differential −) 60 PWM_HPPL DO PWM left channel headphone (differential +) 61 PWM_HPMR DO PWM right channel headphone (differential −) 62 PWM_HPPR DO PWM right channel headphone (differential +) SLES115 — August 2004 Pull up Active low. A backend error sequence is generated by applying logic low to this terminal. The BKND_ERR results in all system parameters unaffected, while all H-bridge drive signals going to a hard mute (M) state. Digital ground Voltage reference for digital PWM core supply 1.8 V. A pin-out of the internally regulated 1.8-V power used by digital PWM core logic. A 0.1-µF low ESR capacitor should be connected between this terminal and DVSS_PWM. This terminal must not be used to power external devices. P Digital ground for PWM P 3.3-V digital power supply for PWM TAS5518 7 Introduction TERMINAL NO. NAME 63 MCLK 64 RESERVED I/O 5-V TOLERANT TERMINATION DI 5V Pulldown DESCRIPTION MCLK is a 3.3-V clock master clock input. The input frequency of this clock can range from 4 MHz to 50 MHz. Connect to digital ground NOTES: 1. Type: A = analog; D = 3.3-V digital; P = power / ground / decoupling; I = input; O = output 2. All pullups are 200-µA weak pullups and all pulldowns are 200-µA weak pull downs. The pullups and pulldowns are included to assure proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive inputs with pull ups must be able to sink 200 µA, while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must be able to source 200 µA, while maintaining a logic ‘1’ drive level. 3. If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing parallel resonance circuits that have been observed when paralleling capacitors of different values. 4. 13.5-MHz crystal (HCM49) 1.4 TAS5518 Functional Description Figure 1−4 shows the TAS5518 functional structure. The next sections describe the TAS5518 functional blocks: • Power Supply • Clock, PLL, and Serial Data Interface • Serial Control Interface • Device Control • Digital Audio Processor (DAP) • Pulse Width Modulation (PWM) Processor 1.4.1 Power Supply The power supply section contains supply regulators that provide analog and digital regulated power for various sections of the TAS5518. The analog supply supports the analog PLL, while digital supplies support the digital PLL, the digital audio processor (DAP), the pulse width modulator (PWM), and the output control (reclocker). The regulators can also be turned off when terminals RESET and PDN are both low. 1.4.2 Clock, PLL, and Serial Data Interface The TAS5518 is a clock slave only device and it requires the use of an external 13.5 MHz crystal. It accepts MCLK, SCLK, and LRCLK as inputs only. The TAS5518 uses the external crystal to provide a time base for: • Continuous data and clock error detection and management • Automatic data rate detection and configuration • Automatic MCLK rate detection and configuration (automatic bank switching) • Supporting I2C operation/ communication while MCLK is absent The TAS5518 automatically handles clock errors, data rate changes, and master clock frequency changes without requiring intervention from an external system controller. This feature significantly reduces system complexity and design. 8 TAS5518 SLES115 — August 2004 Introduction 1.4.2.1 Serial Audio Interface The TAS5518 operates as a slave only / receive only serial data interface in all modes. The TAS5518 has four PCM serial data interfaces to permit eight channels of digital data to be received though the SDIN1, SDIN2, SDIN3, and SDIN4 inputs. The serial audio data is in MSB first, two’s complement format. The serial data input interface of the TAS5518 can be configured in right justified, I2S, or left-justified modes. The serial data interface format is specified using the I2C data interface control register. The supported formats and word lengths are shown in Table 1−1. Table 1−1. Serial Data Formats RECEIVE SERIAL DATA INTERFACE FORMAT WORD LENGTHS Right justified 16 Right justified 20 Right justified 24 I2S 16 I2S 20 I2S 24 Left Justified 16 Left Justified 20 Left Justified 24 Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5518 accepts 32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 20-, or 24-bit data in left, right, and I2S serial data formats using a 64-Fs SCLK clock and a 128, 192, 256, 384, 512, or 768 x Fs MCLK rates (up to a maximum of 50 MHz). The parameters of this clock and serial data interface are I2C configurable. 1.4.3 I 2C Serial Control Interface The TAS5518 has an I2C serial control slave interface (address 0x36) to receive commands from a system controller. The serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz) operations without wait states. Since the TAS5518 has a crystal time base, this interface operates even when MCLK is absent. The serial control interface supports both single byte and multi-byte read / write operations for status registers and the general control registers associated with the PWM. However, for the DAP data processing registers, the serial control interface also supports multiple byte (4 byte) write operations. The I2C supports a special mode which permits I2C write operations to be broken up into multiple data write operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte ... etc write operations that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data. This permits the system to incrementally write large register values without blocking other I2C transactions. In order to use this feature, the first chunk of data is written to the target I2C address and each subsequent chunk of data is written to a special append register (0xFE) until all the data is written and a stop bit is sent. An incremental read operation is not supported. 1.4.4 Device Control The TAS5518 control section provides the control and sequencing for the TAS5518. The device control provides both high and low level control for the serial control interface, clock and serial data interfaces, digital audio processor, and pulse width modulator sections. 1.4.5 Digital Audio Processor (DAP) The DAP arithmetic unit is used to implement all audio processing functions – soft volume, loudness compensation, bass and treble processing, dynamic range control, channel filtering, input and output mixing. Figure 1−6 shows the TAS5518 DAP architecture. SLES115 — August 2004 TAS5518 9 Introduction The DAP accepts 24-bit data signal from the serial data interface and outputs 32-bit data to the PWM section. The DAP supports two configurations, one for 32-kHz – 96-kHz data and one for 176.4-kHz to 192-kHz data. 1.4.5.1 TAS5518 Audio Processing Configurations The 32 − 96 kHz configuration supports eight channels of data processing that can be configured as eight channels or six channels with two channels for separate stereo line outputs. The 176.4 − 192 kHz configuration supports three channels of signal processing with five channels passed though (or derived from the three processed channels). To efficiently support the processing requirements of both multi-channel 32 – 96-kHz data and the two channel 176.4 and 192-kHz data, the TAS5518 supports separate audio processing features for 32 –96-kHz data rates and for 176.4 and 192 kHz. See Table 2 for a summary of TAS5518 processing feature sets. 1.4.5.2 TAS5518 Audio Signal Processing Functions The DAP provides 10 primary signal processing functions. 1. The data processing input has a full 8x8 input crossbar mixer. This enables each input to be any ratio of the eight input channels. 2. Two I2C programmable threshold detectors in each channel support auto mute. 3. Seven biquads per channel 4. Four soft bass and treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd order slopes. In 8-channel mode, bass and treble controls are normally configured as follows: − Bass and Treble 1: Channel 1 (Left), Channel 2 (Right), and Channel 7 (Center) − Bass and Treble 2: Channel 3 (Left Surround) and Channel 4 (Right Surround) − Bass and Treble 3: Channel 5 (Left Back Surround) and Channel 6 (Right Back Surround) − Bass and Treble 4: Channel 8 (Subwoofer) 5. Individual channel and master volume controls. Each control provides an adjustment range of +18 dB to –127 dB. This permits a total volume device control range of +36 dB to –127 dB plus mute. The master volume control can be configured to control six or eight channels. The DAP soft volume and mute update interval is I2C programmable. The update is performed at a fixed rate regardless of the sample rate. 6. Programmable loudness compensation that is controlled via the combination of the master and individual volume settings. 7. Two dual-threshold dual-rate dynamic range compressors (DRCs). The volume gain values are provided used as input parameters using the maximum RMS (master volume x individual channel volume). 8. 8x2 output mixer (channels 1−6). Each output can be any ratio of any two signal processed channels. 9. 8x3 output mixer (channels 7 and 8). Each output can be any ratio of any three signal processed channels. 10. The DAP maintains three sets of coefficient banks that are used to maintain separate sets of sample rate dependent parameters for the biquad, tone controls, loudness, and DRC in RAM. These can be set to be automatically selected for one or more data sample rates or can be manually selected under I2C program control. This feature enables coefficients for different sample rates to be stored in the TAS5518 and then select when needed. 10 TAS5518 SLES115 — August 2004 Introduction Table 1−2. TAS5518 Audio Processing Feature Sets FEATURE Signal processing channels 32 − 96 kHz 8 CHANNEL FEATURE SET 32 − 96 kHz 6 + 2 LINE OUT FEATURE SET 176.4- AND 192-kHz FEATURE SET 8 6+2 3 Pass through channels Master volume N/A 1 for eight channels Individual channel volume controls Bass and treble tone controls 5 1 for six channels 8 3 Four Bass and Treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd order slopes Four Bass and Treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd order slopes L, R and C (Ch 1, 2, and 7) L, R and C (Ch 1, 2, and 7) Two Bass and Treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd order slopes LS, RS (Ch 3 and 4) LS, RS (Ch 3 and 4) L and R (Ch 1 and 2) LBS, RBS (Ch 5 and 6) Sub, (Ch 8) Sub (Ch 8) Sub (Ch 8) Line L and R (Ch 5 and 6) Biquads Dynamic range compressors Input output mapping/mixing 1 for three channels 56 DRC1 for seven satellites and DRC2 for sub 21 DRC1 for five satellites and DRC2 for sub (Ch 5 and 6 Uncompressed) Each of the eight signal-processing channels input can be any ratio of the eight input channels. Each of the eight outputs can be any ratio of any two processed channels. DRC1 for two satellites and DRC2 for sub Each of the three signal-processing channels or the five pass-though channels inputs can be any ratio of the eight input channels. Each of the eight outputs can be any ratio of any of the three processed or five bypass channels. DC blocking filters Eight channels (Implemented in PWM Section) Digital de-emphasis (Implemented in PWM Section) Loudness Eight channels for 32 kHz, 44.1 kHz, and 48 kHz Six channels for 32 kHz, 44.1 kHz, and 48 kHz N/A Eight channels Six channels Three channels Number of Coefficient sets Stored 1.5 Three additional coefficient sets can be stored in memory TAS5518 DAP Architecture 1.5.1 TAS5518 DAP Architecture Diagrams Figure 1−4 shows the TAS5518 DAP architecture for Fs = 96 kHz. Note the TAS5518 bass management architecture shown in channels 1, 2, 7, and 8. Note that the I2C registers are shown to help the designer configure the TAS5518. Figure 1−5 shows the TAS5518 architecture for Fs = 176.4 kHz or Fs = 192 kHz. Note that only channels 1, 2, and 8 contain all the features. Channels 3−7 are pass-through except for master volume control. Figure 1−6 shows TAS5518 detailed channel processing. The output mixer is 8X2 for channels 1−6 and *X3 for channels 7 and 8. SLES115 — August 2004 TAS5518 11 Introduction Default input is BOLD SDIN1−L(L) SDIN1−R (R) SDIN2−L (LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L(L) SDIN1−R(R) SDIN2−L (LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L(L) SDIN1−R(R) SDIN2−L(LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L(L) SDIN1−R(R) SDIN2−L(LS) SDIN2−R(RS) SDIN3−L (LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L(L) SDIN1−R(R) SDIN2−L(LS) SDIN2−R (RS) SDIN3−L(LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L(L) SDIN1−R(R) SDIN2−L(LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R(RBS) SDIN4−L (C) SDIN4−R (LFE) Master Vol (0xD9) A A B B C C IP Mixer 1 D D (I2C 0x41) E E F G F H G H 7 DAP1 BQ (0x51− 0x57) A A B B C C IP Mixer 2 D D E (I2C 0x42) E F G F H G H 7 DAP2 BQ (0x58− 0x5E) Bass & Treble 1 (0xDA− 0xDD) Bass & Treble 1 (0xDA− 0xDD) DAP1 Volume (0xD1) 7 DAP3 Bass & BQ Treble 2 (0x5F− (0xDA− 0x65) A A B B C C IP Mixer 4 D D E (I2C 0x44) E F G F H G H 7 DAP4 BQ (0x66− 0x6C) A A B B C C IP Mixer 5 D D E (I2C 0x45) E F G F H G H 0xDD) Bass & Treble 2 (0xDA− 0xDD) 7 DAP5 Bass & BQ Treble 3 (0x6D− (0xDA− 0x73) A A B B C C IP Mixer 6 D D E (I2C 0x46) E F G F H G H 7 DAP6 BQ (0x74− 0x7A) 0xDD) Bass & Treble 3 (0xDA− 0xDD) Loud− ness (0x91− 0x95) Master Vol (0xD9) Max Vol DAP2 Loud− ness (0x91− Volume (0xD2) Master Vol (0xD9) A A B B C C IP Mixer 3 D D E (I2C 0x43) E F G F H G H Max Vol DAP3 Volume (0xD3) 0x95) Loud− ness (0x91− 0x95) Max Vol DAP4 Loud− ness (0x91− (0xD4) 0x95) Master Vol (0xD9) Max Vol DAP5 Loud− ness (0x91− Volume (0xD5) 0x95) Master Vol (0xD9) Max Vol DAP6 Loud− ness (0x91− Volume (0xD6) DRC1 OP Mixer 2 (I2C 0xAB) R to 0x9C) 8X2 Output PWM2 Mixer (0x96− Max Vol Master Vol (0xD9) Volume DRC1 OP Mixer 1 (I2C 0xAA) L to 0x9C) 8X2 Output PWM1 Mixer (0x96− 0x95) DRC1 OP Mixer 3 (I2C 0xAC) LS to 0x9C) 8X2 Output PWM3 Mixer (0x96− DRC1 OP Mixer 4 (I2C 0xAD) RS to 0x9C) 8X2 Output PWM4 Mixer (0x96− DRC1 OP Mixer 5 (I2C 0xAE) LBS to 0x9C) 8X2 Output PWM5 Mixer (0x96− DRC1 OP Mixer 6 (I2C 0xAF) RBS to 0x9C) 8X2 Output PWM6 Mixer (0x96− Coeff = 0 (lin) (I2C 0x4E) Coeff = 0 (lin) (I2C 0x4B) Coeff = 1 (lin) SDIN1−L(L) SDIN1−R(R) SDIN2−L(LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R(RBS) SDIN4−L(C) SDIN4−R (LFE) A A B B C C IP Mixer 7 D D E (I2C 0x47) E F G F H G H (I2C 0x4D) 5 DAP7 Bass & BQ Treble 1 (0x7D− (0xDA− 2 DAP7 BQ (0x7B− 0x7C) 0x81) 0xDD) Master Vol (0xD9) Max Vol DAP7 Loud− ness (0x91− Volume (0xD7) 0x95) DRC1 OP Mixer 7 (I2C 0xB0) C to 0x9C) 8X3 Output PWM7 Mixer (0x96− Coeff = 0 (lin) (I2C 0x4C) Coeff = 0 (lin) (I2C 0x49) Coeff = 0 (lin) (I2C 0x4A) SDIN1−L(L) SDIN1−R(R) SDIN2−L(LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R(RBS) SDIN4−L (C) SDIN4−R(LFE) A A B B C C IP Mixer 8 D D E (I2C 0x48) E F G F H G H (I2C 0x50) Coeff = 1 (lin) 2 DAP8 BQ (0x82− 0x83) 5 DAP8 Bass & BQ Treble 4 (0x84− (0xDA− 0x88) 0xDD) Master Vol (0xD9) Max Vol DAP8 Loud− ness (0x91− Volume (0xD8) 0x95) DRC2 OP Mixer 8 (I2C 0xB1) Sub to 0xA1) 8X3 Output PWM8 Mixer (0x9D− Coeff = 0 (lin) (I2C 0x4F) Figure 1−4. TAS5518 DAP Architecture With I2C Registers (Fs ≤ 96 kHz) 12 TAS5518 SLES115 — August 2004 Introduction Default input is BOLD Master Vol (0xD9) A IP Mixer 1 A B B C C (I2C 0x41) D D 8X8 E E F Crossbar G F H G Input Mixer H SDIN1−L (L) SDIN1−R (R) SDIN2−L (LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L (L) 7 DAP1 BQ (0x51− 0x57) SDIN2−L (LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L (L) SDIN1−R (R) 0xDD) 7 DAP2 BQ (0x58− 0x5E) Bass & Treble 1 (0xDA− 0xDD) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L (L) SDIN1−R (R) SDIN2−L (LS) SDIN3−L (LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L (L) SDIN1−R (R) SDIN2−L (LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L (L) SDIN1−R (R) SDIN2−L (LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R (RBS ) SDIN4−L (C) SDIN4−R (LFE) SDIN4−L (C) SDIN4−R (LFE) SDIN1−L (L) SDIN1−R (R) SDIN2−L (LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R (RBS) SDIN4−L (C) SDIN4−R (LFE) (I2C 0xAA) 8X2 Output Mixer L to PWM1 Max Vol Loud− ness (0x91− 0x95) DRC1 (0x96− 0x9C) OP Mixer 2 (I2C 0xAB) 8X2 Output Mixer R to PWM2 LS to PWM3 Master Vol (0xD9) OP Mixer 4 (I2C 0xAD) 8X2 Output Mixer RS to PWM4 Master Vol (0xD9) A A IP Mixer 5 B B C C (I2C 0x45) D D 8X8 E E F Crossbar G F H G Input Mixer H OP Mixer 5 (I2C 0xAE) 8X2 Output Mixer LBS to PWM5 Master Vol (0xD9) A IP Mixer 6 A B B C C (I2C 0x46) D D 8X8 E E F Crossbar G F H G Input Mixer H A IP Mixer 8 A B B C C (I2C 0x48) D D 8X8 E E F Crossbar G F H G Input Mixer H (0xD2) 0x9C) OP Mixer 1 (I2C 0xAC) 8X2 Output Mixer OP Mixer 6 (I2C 0xAF) 8X2 Output Mixer RBS to PWM6 Master Vol (0xD9) A IP Mixer 7 A B B C C (I2C 0x47) D D 8X8 E E F Crossbar G F H G Input Mixer H SDIN1−L (L) SDIN1−R (R) SDIN2−L (LS) SDIN2−R (RS) SDIN3−L (LBS) SDIN3−R (RBS) DAP2 Volume 0x95) DRC1 (0x96− OP Mixer 3 A IP Mixer 4 A B B C (I2C 0x44) C D D 8X8 E E F G Crossbar F H G Input Mixer H SDIN2−R (RS) (0xD1) Loud− ness (0x91− Master Vol (0xD9) A IP Mixer 3 A B B C (I2C 0x43) C D D 8X8 E E F Crossbar G F H G Input Mixer H SDIN2−L (LS) DAP1 Volume Master Vol (0xD9) A IP Mixer 2 A B B (I2C 0x42) C C D D 8X8 E E F Crossbar G F H G Input Mixer H SDIN1−R (R) Bass & Treble 1 (0xDA− Max Vol OP Mixer 7 (I2C 0xB0) 8X3 Output Mixer Master Vol (0xD9) 2 DAP8 BQ (0x82− 0x83) 5 DAP8 BQ (0x84− 0x88) Bass & Treble 4 (0xDA− 0xDD) DAP8 Volume (0xD8) C to PWM7 Max Vol Loud− ness (0x91− 0x95) DRC2 (0x9D− 0xA1) OP Mixer 8 (I2C 0xB1) 8X3 Output Mixer Sub to PWM8 Figure 1−5. TAS5518 Architecture With I2C Registers (Fs = 176.4 kHz or Fs = 192 kHz) SLES115 — August 2004 TAS5518 13 Introduction Master Volume A_to_ipmix Left SDIN1 A Channel Volume Bass and Treble Bypass B Right B_to_ipmix C_to_ipmix Left SDIN2 E F Right F_to_ipmix G_to_ipmix Left SDIN4 Right Output Gain Input Mixer D_to_ipmix E_to_ipmix Left DRC Bypass Loudness C Right D SDIN3 Max Volume 7 Biquads in Series Bass and Treble Bass and Treble PreIn-Line Volume PostVolume DRC DRC In-Line Output Mixer Sums Any Two Channels 1 Other Channel Output From 7 Available 32−Bit PWM Trunc Proc Volume G H H_to_ipmix Figure 1−6. TAS5518 Detailed Channel Processing 1.5.2 I 2C Coefficient Number Formats The architecture of the TAS5518 is contained in ROM resources within the TAS5518 and cannot be altered. However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I2C bus interface, provide a user with the flexibility to set the TAS5518 to a configuration that achieves the system level goals. The firmware is executed in a 48-bit signed fixed-point arithmetic machine. The most significant bit of the 48-bit data path is a sign bit, and the 47 lower bits are data bits. Mixer gain operations are implemented by multiplying a 48-bit signed data value by a 28-bit signed gain coefficient. The 76-bit signed output product is then truncated to a signed 48-bit number. Level offset operations are implemented by adding a 48-bit signed offset coefficient to a 48-bit signed data value. In most cases, if the addition results in overflowing the 48-bit signed number format, saturation logic is used. This means that if the summation results in a positive number that is greater than 0x7FFF_FFFF_FFFF (the spaces are used to ease the reading of the hexadecimal number), the number is set to 0x7FFF_FFFF_FFFF. If the summation results in a negative number that is less than 0x8000_0000_0000 0000, the number is set to 0x8000_0000_0000 0000. 14 TAS5518 SLES115 — August 2004 PWM Output Introduction 1.5.2.1 28-Bit 5.23 Number Format All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23 numbers means that there are 5 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown in the Figure 1−7. 2−23 Bit 2−4 Bit 2−1 Bit 20 Bit 23 Bit Sign Bit S_xxxx.xxxx_xxxx_xxxx_xxxx_xxx Figure 1−7. 5.23 Format The decimal value of a 5.23 format number can be found by following the weighting shown in Figure 1−8. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 1−8 applied to obtain the magnitude of the negative number. 23 Bit 22 Bit 20 Bit 2−1 Bit 2−4 Bit 2−23 Bit (1 or 0) x 23 + (1 or 0) x 22 + … + (1 or 0) x 20 + (1 or 0) x 2−1 + … + (1 or 0) x 2−4 + … + (1 or 0) x 2−23 Figure 1−8. Conversion Weighting Factors—5.23 Format to Floating Point Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 1−9. Fraction Digit 6 Sign Bit Integer Digit 1 u u u u Coefficient Digit 8 S x x x Coefficient Digit 7 Fraction Digit 1 x. x x x Coefficient Digit 6 Fraction Digit 2 x x x x Coefficient Digit 5 Fraction Digit 3 x x x x Coefficient Digit 4 Fraction Digit 4 x x x x Coefficient Digit 3 Fraction Digit 5 x x x x Coefficient Digit 2 0 x x x x Coefficient Digit 1 u = unused or don’t care bits Digit = hexadecimal digit Figure 1−9. Alignment of 5.23 Coefficient in 32-Bit I2C Word As Figure 1−9 shows, the hex value of the integer part of the gain coefficient cannot be concatenated with the hex value of the fractional part of the gain coefficient to form the 32-bit I2C coefficient. The reason is that the 28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient occupies all of one hex digit and the most significant bit of the second hex digit. In the same way, the fractional part occupies the lower 3 bits of the second hex digit, and then occupies the other five hex digits (with the eighth digit being the zero-valued most significant hex digit). SLES115 — August 2004 TAS5518 15 Introduction 1.5.2.2 48-Bit 25.23 Number Format All level adjustment and threshold coefficients are 48-bit coefficients using a 25.23 number format. Numbers formatted as 25.23 numbers means that there are 25 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown in Figure 1−10. 2−23 Bit 2−10 Bit 2−1 Bit 20 Bit 216 Bit 222 Bit 223 Bit Sign Bit S_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx Figure 1−10. 25.23 Format Figure 1−11 shows the derivation of the decimal value of a 48-bit 25.23 format number. 223 Bit 222 Bit 20 Bit 2−1 Bit 2−23 Bit (1 or 0) x 223 + (1 or 0) x 222 + … + (1 or 0) x 20 + (1 or 0) x 2−1 + … + (1 or 0) x 2−23 Figure 1−11. Alignment of 5.23 Coefficient in 32-Bit I2C Word Two 32-bit words must be sent over the I2C bus to download a level or threshold coefficient into the TAS5518. The alignment of the 48-bit, 25.23 formatted coefficient in the 8-byte (two 32-bit words) I2C word is shown in Figure 1−12. 16 TAS5518 SLES115 — August 2004 Introduction Integer Digit 4 (Bits 23 − 21) Sign Bit Integer Digit 1 u u u u Coefficient Digit 16 u u u u u Coefficient Digit 15 u u u Coefficient Digit 14 u u u u Coefficient Digit 13 S x x x Coefficient Digit 12 Integer Digit 2 x x x x Coefficient Digit 11 Integer Digit 3 x x x x Coefficient Digit 10 x x x Coefficient Digit 9 Integer Digit 4 (Bit 20) Fraction Digit 6 Integer Digit 5 x x Word 1 (Most Significant Word) x x x Coefficient Digit 8 Integer Digit 6 x x x x Fraction Digit 1 x. x Coefficient Digit 7 x x Coefficient Digit 6 Fraction Digit 2 x x x x Coefficient Digit 5 Fraction Digit 3 x x x x Coefficient Digit 4 Fraction Digit 4 x x x x Coefficient Digit 3 Fraction Digit 5 x x x x Coefficient Digit 2 0 x x x x Word 2 (Least Significant Word) Coefficient Digit 1 u = unused or don’t care bits Digit = hexadecimal digit Figure 1−12. Alignment of 25.23 Coefficient in Two 32-Bit I2C Words 1.5.2.3 TAS5518 Audio Processing The TAS5518 digital audio processing is designed such that noise produced by filter operations is maintained below the smallest signal amplitude of interest, as shown in Figure 1−13. The TAS5518 achieves this by increasing the precision of the signal representation substantially above the number of bits that are absolutely necessary to represent the input signal. Ideal Input Possible Outputs Maximum Signal Amplitude Overflow Filter Operation Signal bits input Desired Output Values retained by overflow bits Reduced SNR signal output Signal bits output Noise Floor with no additional precision Noise Floor as a result of additional precision Figure 1−13. TAS5518 Digital Audio Processing SLES115 — August 2004 TAS5518 17 Introduction Similarly, the TAS5518 carries additional precision in the form of overflow bits to permit the value of intermediate calculations to exceed the input precision without clipping. The TAS5518 advanced digital audio processor achieves both of these important performance capabilities by using a high performance digital audio processing architecture with a 48-bit data path, 28-bit filter coefficients, and a 76-bit accumulator. 1.6 Input Crossbar Mixer The TAS5518 has a full 8x8 input crossbar mixer. This mixer permits each signal processing channel input to be any ratio of any of the eight input channels. The control parameters for the input crossbar mixer are programmable via the I2C interface. See the Input Mixer Register (0x41−0x48, channels 1−8) section. Gain Coefficient 28 Input 1 48 Gain Coefficient 28 48 Input 2 48 48 Gain Coefficient 28 SUM 48 Input 8 48 Figure 1−14. Input Crossbar Mixer 18 TAS5518 SLES115 — August 2004 Introduction 1.7 Biquad Filters For 32-kHz to 96-kHz data, the TAS5518 provides 56 biquads across the eight channels (seven per channel) For 176.4-kHz and 192-kHz data, the TAS5518 has 21 biquads across the three channels (seven per channel). All of the biquad filters are second order direct form I structure. The direct form I structure provides a separate delay element and mixer (gain coefficient) for each node in the biquad filter. Each mixer output is a signed 76-bit product of a signed 48-bit data sample (25.23 format number) and a signed 28-bit coefficient (5.23 format number). The 76-bit ALU in the TAS5518 allows the 76-bit resolution to be retained when summing the mixer outputs (filter products). The five 28-bit coefficients for the each of the 56 biquads are programmable via the I2C interface. See Table 1−3. b0 48 X b1 Z−1 48 48 28 X b2 Z−1 28 28 X 76 ∑ 76 48 Magnitude Truncation a1 76 76 X a2 76 76 28 X 28 Z−1 48 Z−1 48 Figure 1−15. Biquad Filter Structure All five coefficients for one biquad filter structure are written to one I2C register containing 20 bytes (or five 32-bit words). The structure is the same for all biquads in the TAS5518. Registers 0x51 – 0x88 show all the biquads in the TAS5518. Note that u(31:28) bits are unused and default to 0x0. Table 1−3. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass) DESCRIPTION REGISTER FIELD CONTENTS DECIMAL HEX bo Coefficient u(31:28), b0(27:24), b0(23:16), b0(15:8), b0(7:0) 1.0 0x00, 0x80, 0x00, 0x00 b1 Coefficient u(31:28), b1(27:24), b1(23:16), b1(15:8), b1(7:0) 0.0 0x00, 0x00, 0x00, 0x00 b2 Coefficient u(31:28), b2(27:24), b2(23:16), b2(15:8), b2(7:0) 0.0 0x00, 0x00, 0x00, 0x00 a1 Coefficient u(31:28), a1(27:24), a1(23:16), a1(15:8), a1(7:0) 0.0 0x00, 0x00, 0x00, 0x00 a2 Coefficient u(31:28), a2(27:24), a2(23:16), a2(15:8), a2(7:0) 0.0 0x00, 0x00, 0x00, 0x00 1.8 INITIALIZATION GAIN COEFFICIENT VALUE Bass and Treble Controls From 32-kHz to 96-kHz data, the TAS5518 has four Bass and Treble tone controls. Each control has a ±18-dB control range with selectable corner frequencies and 2nd order slopes. These controls operate four channel groups: • L, R & C (Channels 1, 2, and 7) • LS, RS (Channels 3 and 4) • LBS, RBS (or alternately called L and R Lineout.) (Channels 5 and 6) • Sub (Channel 8) SLES115 — August 2004 TAS5518 19 Introduction For 176.4 kHz and 192 kHz data, the TAS5518 has two Bass and Treble tone controls. Each control has a ±18-dB I2C control range with selectable corner frequencies and 2nd order slopes. These controls operate two channel groups: • L&R • Sub The bass and treble filters utilize a soft update rate that does not produce artifacts during adjustment. Table 1−4. Bass and Treble Filter Selections FS (kHz) 3-dB CORNER FREQUENCIES FILTER SET 1 FILTER SET 1 FILTER SET 2 FILTER SET 2 FILTER SET 3 FILTER SET 3 FILTER SET 4 FILTER SET 4 FILTER SET 5 FILTER SET 5 BASS TREBLE BASS TREBLE BASS TREBLE BASS TREBLE BASS TREBLE 32 42 917 83 1833 125 3000 146 3667 167 4333 38 49 1088 99 2177 148 3562 173 4354 198 5146 44.1 57 1263 115 2527 172 4134 201 5053 230 5972 48 63 1375 125 2750 188 4500 219 5500 250 6500 88.2 115 2527 230 5053 345 8269 402 10106 459 11944 96 125 2750 250 5500 375 9000 438 11000 500 13000 176.4 230 5053 459 10106 689 16538 804 20213 919 23888 192 250 5500 500 11000 750 18000 875 22000 1000 26000 The I2C registers that control Bass and Treble are: 1.9 • Bass and Treble By-Pass Register (0x89 – 0x90, channels 1−8) • Bass and Treble Slew Rates (0xD0) • Bass Filter Sets 1−5 (0xDA) • Bass Filter Index (0xDB) • Treble Filter Sets 1−5 (0xDC) • Treble Filter Index (0xDD) Volume, Auto Mute, and Mute The TAS5518 provides individual channel and master volume controls. Each control provides an adjustment range of +18.0618 dB to –100 dB in 0.25 dB increments. This permits a total volume device control range of +36 dB to –100 dB plus mute. The master volume control can be configured to control six or eight channels. The TAS5518 has a master soft mute control that can be enabled by a terminal or I2C command. The device also has individual channel soft mute controls that can are enabled via I2C. The soft volume and mute update rates are programmable. The soft adjustments are performed using a soft gain linear update with an I2C programmable linear step size at a fixed temporal rate. The linear soft gain step size can be varied from 0.5 to 0.003906. Table 1−5. Linear Gain Step Size 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.007813 0.003906 Time to go from 36.124 db to −127 dB in ms STEP SIZE (GAIN) 10.67 21.33 42.67 85.34 170.67 341.35 682.70 1365.4 Time to go from 18.062 db to −127 dB in ms 1.33 2.67 5.33 10.67 21.33 42.67 85.33 170.67 Time to go from 0 db to −127 dB in ms 0.17 0.33 0.67 1.33 2.67 5.33 10.67 21.33 20 TAS5518 SLES115 — August 2004 Introduction 1.9.1 Auto Mute and Mute The TAS5518 has individual channel automute controls that are enabled via the I2C interface. There are two separate detectors used to trigger the automute: • Input Auto Mute: All channels are muted when all 8 inputs to the TAS5518 are less in magnitude than the input threshold value for a programmable amount of time. • Output Auto Mute: A single channel is muted when the output of the DAP section is less in magnitude than the input threshold value for a programmable amount of time. The detection period and thresholds for these two detectors are the same. This time interval is selectable via I2C to be from 1 ms. to 110 ms. The increments of time are 1, 2, 3, 4, 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. This interval is independent of the sample rate. The default value is mask programmable. The input threshold value is an unsigned magnitude that is expressed as a bit position. This value is adjustable via I2C. The range of the input threshold adjustment is from below the LSB (bit position 0) to below bit position 12 in a 24 bit input data word (bit positions 8 to 20 in the DSPE). This provides an input threshold that can be adjusted for 12 to 24 bits of data. The default value is mask programmable. DVD Data Range CD Data Range 24-Bit Input 32-Bit in DSPE Representation 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Threshold Range Figure 1−16. Auto Mute Threshold The auto mute state is exited when the TAS5518 receives one sample that is greater that the output threshold. The output threshold can be one of two values: • Equal to the input threshold • 6 dB (one bit position) greater than the input threshold The value for the output threshold is selectable via I2C. The default value is mask programmable. The system latency enables the data value that is above the threshold to be preserved and output. A mute command initiated by automute, master mute, individual I2C mute, the AM interference mute sequence, or the bank switch mute sequence overrides an unmute command or a volume command. While a mute command is activated, the commanded channels transition to the mute state. When a channel is unmuted, it goes to the last commanded volume setting that has been received for that channel. 1.10 Loudness Compensation The loudness compensation function compensates for the Fletcher-Munson loudness curves. The TAS5518 loudness implementation tracks the volume control setting to provide spectral compensation for weak low or high frequency response at low volume levels. For the volume tracking function both linear and log control laws can be implemented. Any biquad filter response can be used to provide the desired loudness curve. The control parameters for the loudness control are programmable via the I2C interface. SLES115 — August 2004 TAS5518 21 Introduction The TAS5518 has a single set of loudness controls for the eight channels. In 6-channel mode loudness is available to the six speaker outputs and also the line outputs. The loudness control input uses the Maximum individual master volume (V) to control the loudness that is applied to all channels. In 192-kHz and 176.4-kHz modes, the loudness function is active only for channels 1, 2, and 8. V + Audio In x Loudness Biquad H(Z) x Audio Out x Loudness Function = f (V) V Figure 1−17. Loudness Compensation Functional Block Diagram Loudness Function = f (V) = G x [2 [(Log V) x LG + LO]] + O or alternatively, Loudness Function = f (V) = G x [V LG x 2LO] + O For example, for the default values LG = −0.5, LO = 0.0, G = 1.0, and O = 0.0 then: Loudness Function = 1 / SQRT (V) which is the recommended transfer function for loudness. So, Audio Out = (Audio In) x V + H (Z) x SQRT (V). Other transfer functions are possible. Table 1−6. Default Loudness Compensation Parameters LOUDNESS TERM 22 DESCRIPTION USAGE DATA FORMAT I2C SUB-ADD SUB ADD RESS DEFAULT HEX FLOAT V Max volume Gains audio 5.23 NA NA NA Log V Log2 (max volume) Loudness function 5.23 NA 00000000 0.0 H (Z) Loudness biquad Controls shape of Loudness curves 5.23 0x95 b0 = 0000D513 b1 = 00000000 b2 = 0FFF2AED a1 = 00FE5045 a2 = 0F81AA27 b0 = 0.006503 b1 = 0 b2 = −0.006503 a1 = 1.986825 a2 = −0.986995 LG Gain (log space) Loudness function 5.23 0x91 FFC00000 −0.5 LO Offset (log space) Loudness function 25.23 0x92 00000000 0 G Gain Switch to enable Loudness (ON = 1, OFF = 0) 5.23 0x93 00000000 0 O Offset Provides offset 25.23 0x94 00000000 0 TAS5518 SLES115 — August 2004 Introduction 1.10.1 Loudness Example Problem: Due to the Fletcher-Munson phenomena, we want to compensate for low frequency attenuation near 60 Hz. The TAS5518 provides a loudness transfer function with EQ gain = 6, EQ center frequency = 60 Hz, and EQ bandwidth = 60 Hz. Solution: Using Texas Instruments ALE TAS5518 DSP tool, Matlab, or other signal-processing tool, develop a loudness function with following parameters: Table 1−7. Loudness Function Parameters EXAMPLE VALUES DATA FORMAT I2C SUBADDRESS HEX FLOAT 5.23 0x95 b0 = 00008ACE b1 = 00000000 b2 = FFFF7532 a1 = FF011951 a2 = 007EE914 b0 = 0.004236 b1 = 0 b2 = −0.004236 a1 = −1.991415 a2 = 0.991488 Loudness function 5.23 0x91 FFC00000 −0.5 Loudness function 25.23 0x92 00000000 0 Gain Switch to Enable Loudness (ON = 1, OFF = 0) 5.23 0x93 00800000 1 Offset Offset 25.23 0x94 00000000 0 LOUDNESS TERM DESCRIPTION USAGE H (Z) Loudness Biquad Controls shape of loudness curves LG Loudness Gain LO Loudness Offset G O See Figure 1−18 for the resulting loudness function at different gains. Figure 1−18. Loudness Example Plots SLES115 — August 2004 TAS5518 23 Introduction 1.11 Dynamic Range Control (DRC) The DRC provides both compression and expansion capabilities over three separate and definable regions of audio signal levels. Programmable threshold levels set the boundaries of the three regions. Within each of the three regions a distinct compression or expansion transfer function can be established and the slope of each transfer function is determined by programmable parameters. The offset (boost or cut) at the two boundaries defining the three regions can also be set by programmable offset coefficients. The DRC implements the composite transfer function by computing a 5.23 format gain coefficient from each sample output from the rms estimator. This gain coefficient is then applied to a mixer element, whose other input is the audio data stream. The mixer output is the DRC-adjusted audio data. There are two distinct DRC blocks in the TAS5518. DRC1 services channels 1−7 in the 8-channel mode and channels 1−4, and 7 in the 6-channel mode. This DRC computes rms estimates of the audio data streams on all channels that it controls. The estimates are then compared on a sample-by-sample basis and the larger of the estimates is used to compute the compression/expansion gain coefficient. The gain coefficient is then applied to appropriate channels audio stream. DRC2 services only channel 8. This DRC also computes an rms estimate of the signal level on channel 8 and this estimate is used to compute the compression/expansion gain coefficient applied to the channel 8 audio stream. All of the TAS5518 default values for DRC can be used except for the DRC1 decay and DRC2 decay. Table 1−8 shows the recommended time constants and their HEX values. If the user wants to implement other DRC functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE) tool available from Texas Instruments. The ALE tool allows the user to select the DRC transfer function graphically. It will then output the TAS5518 hex coefficients for download to the TAS5518. Table 1−8. DRC Recommended Changes From TAS5518 Defaults I2C SUBADDRESS 0x98 REGISTER FIELDS RECOMMENDED TIME CONSTANT (MS) DRC1 energy 5 RECOMMENDED HEX VALUE DRC1 (1 – energy) 0x9C DRC1 attack 5 DRC1 (1 – attack) DRC1 decay 2 DRC1 (1 – decay) 0x9D DRC2 energy 5 DRC2 (1 – energy) 0xA1 DRC2 attack 5 DRC2 (1 – attack) DRC2 decay 2 DRC2 (1 – decay) DEFAULT HEX 0000883F 0000883F 007F77C0 007F77C0 0000883F 0000883F 007F77C0 007F77C0 0001538F 000000AE 007EAC70 007FFF51 0000883F 0000883F 007F77C0 007F77C0 0000883F 0000883F 007F77C0 007F77C0 0001538F 000000AE 007EAC70 007FFF51 Recommended DRC set-up flow if the defaults are used: • After power up, load the recommended hex value for DRC1 and DRC2 decay and (1 – decay). See Table 1−8. • Enable either the pre-volume or post-volume DRC Recommended DRC set-up flow if the DRC design uses values different from the defaults: • After power up, load all DRC coefficients per the DRC design. • Enable either the pre-volume or post-volume DRC Figure 1−19 shows the positioning of the DRC block in the TAS5518 processing flow. As seen, the DRC input can come from either before or after soft volume control and loudness processing. 24 TAS5518 SLES115 — August 2004 Introduction Master Volume Channel Volume Max Volume DRC By-Pass Bass & Treble By-Pass Loudness From Input Mixer 7 Biquads in Series To Output Mixer Bass and Treble Bass & Treble In-Line DRC PreVolume PostVolume In-Line DRC Figure 1−19. DRC Positioning in TAS5518 Processing Flow Figure 1−20 illustrates a typical DRC transfer function. DRC − Compensated Output Region 0 Region 1 Region 2 k2 k1 1:1 Transfer Function Implemented Transfer Fucntion k0 O2 O1 T1 T2 DRC Input Level Figure 1−20. Dynamic Range Compression (DRC) Transfer Function Structure The three regions shown in Figure 1−20 are defined by three sets of programmable coefficients: • Thresholds T1 and T2—define region boundaries. • Offsets O1 and O2—define the DRC gain coefficient settings at thresholds T1 and T2 respectively. • Slopes k0, k1, and k2—define whether compression or expansion is to be performed within a given region. The magnitudes of the slopes define the degree of compression or expansion to be performed. The three sets of parameters are all defined in logarithmic space and adhere to the following rules: • The maximum input sample into the DRC is referenced at 0 dB. All values below this maximum value then have negative values in logarithmic (dB) space. • The samples input into the DRC are 32-bit words and consist of the upper 32 bits of the 48-bit word format used by the digital audio processor (DAP). The 48-bit DAP word is derived from the 32-bit serial data received at the serial audio receive port by adding 8 bits of headroom above the 32-bit word and 8 bits of computational precision below the 32-bit word. If the audio processing steps between the SAP input and the DRC input result in no accumulative boost or cut, the DRC would operate on the 8 bits of headroom and the 24 MSBs of the audio sample. Under these conditions, a 0-dB (maximum value) audio sample (0x7FFFFFFF) is seen at the DRC input as a –48-dB sample (8 bits x −6.02 dB/bit = −48 dB). SLES115 — August 2004 TAS5518 25 Introduction • Thresholds T1 and T2 define, in dB, the boundaries of the three regions of the DRC, as referenced to the rms value of the data into the DRC. Zero valued threshold settings reference the maximum valued rms input into the DRC and negative valued thresholds reference all other rms input levels. Positive valued thresholds have no physical meaning and are not allowed. In addition, zero valued threshold settings are not allowed. Although the DRC input is limited to 32-bit words, the DRC itself operates using the 48-bit word format of the DAP. The 32-bit samples input into the DRC are placed in the upper 32 bits of this 48-bit word space. This means that the threshold settings must be programmed as 48-bit (25.23 format) numbers. CAUTION: Zero valued and positive valued threshold settings are not allowed and cause unpredictable behavior if used. • Offsets O1 and O2 define, in dB, the attenuation (cut) or gain (boost) applied by the DRC-derived gain coefficient at the threshold points T1 and T2 respectively. Positive offsets are defined as cuts, and thus boost or gain selections are negative numbers. Offsets must be programmed as 48-bit (25.23 format) numbers. • Slopes k0, k1, and k2 define whether compression or expansion is to be performed within a given region, and the degree of compression or expansion to be applied. Slopes are programmed as 28-bit (5.23 format) numbers. 1.11.1 DRC Implementation The three elements comprising the DRC: (1) an rms estimator, (2) a compression/expansion coefficient computation engine, and (3) an attack/decay controller. • RMS estimator—This DRC element derives an estimate of the rms value of the audio data stream into the DRC. For the DRC block shared by CH1 and CH2, two estimates are computed—an estimate of the CH1 audio data stream into the DRC, and an estimate of the CH2 audio data stream into the DRC. The outputs of the two estimators are then compared, sample-by-sample, and the larger valued sample is forwarded to the compression/expansion coefficient computation engine. Two programmable parameters, ae and (1 – ae), set the effective time window over which the rms estimate is made. For the DRC block shared by CH1 and CH2, the programmable parameters apply to both rms estimators. The time window over which the rms estimation is computed can be determined by: t window + *1 F ȏn(1 * ae) S • Compression/expansion coefficient computation—This DRC element converts the output of the rms estimator to a logarithmic number, determines the region that the input resides, and then computes and outputs the appropriate coefficient to the attack/decay element. Seven programmable parameters—T1, T2, O1, O2, k0, k1, and k2—define the three compression/expansion regions implemented by this element. • Attack/decay control—This DRC element controls the transition time of changes in the coefficient computed in the compression/expansion coefficient computation element. Four programmable parameters define the operation of this element. Parameters ad and 1 − ad set the decay or release time constant to be used for volume boost (expansion). Parameters aa and 1 − aa set the attack time constant to be used for volume cuts. The transition time constants can be determined by: ta + 1.11.2 *1 F ȏn(1 * aa) S *1 t + d F ȏn(1 * ad) S Compression/Expansion Coefficient Computation Engine Parameters There are seven programmable parameters assigned to each DRC block: two threshold parameters - T1 and T2, two offset parameters - O1 and O2, and three slope parameters - k0, k1, and k2. The threshold parameters establish the three regions of the DRC transfer curve, the offsets anchor the transfer curve by establishing known gain settings at the threshold levels, and the slope parameters define whether a given region is a compression or an expansion region. 26 TAS5518 SLES115 — August 2004 Introduction The audio input stream into the DRC must pass through DRC-dedicated programmable input mixers. These mixers are provided to scale the 32-bit input into the DRC to account for the positioning of the audio data in the 48-bit DAP word and the net gain or attenuation in signal level between the SAP input and the DRC. The selection of threshold values must take the gain (attenuation) of these mixers into account. The DRC implementation examples that follow illustrate the effect these mixers have on establishing the threshold settings. T2 establishes the boundary between the high-volume region and the mid-volume region. T1 establishes the boundary between the mid-volume region and the low-volume region. Both thresholds are set in logarithmic space, and which region is active for any given rms estimator output sample is determined by the logarithmic value of the sample. Threshold T2 serves as the fulcrum or pivot point in the DRC transfer function. O2 defines the boost (> 0 dB) or cut (< 0 dB) implemented by the DRC-derived gain coefficient for an rms input level of T2. If O2 = 0 dB, the value of the derived gain coefficient is 1.0 (0x00, 80, 00, 00 in 5.23 format). k2 is the slope of the DRC transfer function for rms input levels above T2 and k1 is the slope of the DRC transfer function for rms input levels below T2 (and above T1). The labeling of T2 as the fulcrum stems from the fact that there cannot be a discontinuity in the transfer function at T2. The user can, however, set the DRC parameters to realize a discontinuity in the transfer function at the boundary defined by T1. If no discontinuity is desired at T1, the value for the offset term O1 must obey the following equation. O1 No Discontinuity + |T1 * T2| k1 ) O2 For ( |T1| w |T2| ) T1 and T2 are the threshold settings in dB, k1 is the slope for region 1, and O2 is the offset in dB at T2. If the user chooses to select a value of O1 that does not obey the above equation, a discontinuity at T1 is realized. Going down in volume from T2, the slope k1 remains in effect until the input level T1 is reached. If, at this input level, the offset of the transfer function curve from the 1:1 transfer curve does not equal O1, there is a discontinuity at this input level as the transfer function is snapped to the offset called for by O1. If no discontinuity is wanted, O1 and/or k1 must be adjusted so that the value of the transfer curve at the input level T1 is offset from the 1:1 transfer curve by the value O1. The examples that follow illustrate both continuous and discontinuous transfer curves at T1. Going down in volume from T1, starting at the offset level O1, the slope k0 defines the compression/expansion activity in the lower region of the DRC transfer curve. 1.11.2.1 Threshold Parameter Computation For thresholds, TdB = −6.0206TINPUT = −6.0206TSUB_ADDRESS_ENTRY If, for example, it is desired to set T1 = -64 dB, then the subaddressaddress entry required to set T1 to -64 dB is: T1 SUB_ADDRESS_ENTRY + *64 + 10.63 *6.0206 T1 is entered as a 48-bit number in 25.23 format. Therefore: T1 = 10.63 = 0_1010.1010_0001_0100_0111_1010_111 = 0x00000550A3D7 in 25.23 format SLES115 — August 2004 TAS5518 27 Introduction 1.11.2.2 Offset Parameter Computation The offsets set the boost or cut applied by the DRC-derived gain coefficient at the threshold point. An equivalent statement is that offsets represent the departure of the actual transfer function from a 1:1 transfer at the threshold point. Offsets are 25.23 formatted 48-bit logarithmic numbers. They are computed by the following equation. O INPUT + O ) 24.0824 dB DESIRED 6.0206 Gains or boosts are represented as negative numbers; cuts or attenuation are represented as positive numbers. For example, to achieve a boost of 21 dB at threshold T1, the I2C coefficient value entered for O1 must be: O1 INPUT + –21 dB ) 24.0824 dB + 0.51197555 6.0206 + 0.1000_0011_0001_1101_0100 + 0x00000041886A in 25.23 format More examples of offset computations are included in the following examples. 1.11.2.3 Slope Parameter Computation In developing the equations used to determine the subaddress of the input value required to realize a given compression or expansion within a given region of the DRC, the following convention is adopted. DRC Transfer = Input Increase : Output Increase If the DRC realizes an output increase of n dB for every dB increase in the rms value of the audio into the DRC, a 1:n expansion is being performed. If the DRC realizes a 1 dB increase in output level for every n dB increase in the rms value of the audio into the DRC, a n:1 compression is being performed. For 1:n expansion, the slope k can be found by: k=n−1 For n:1 compression, the slope k can be found by: k + 1 n –1 In both expansion (1:n) and compression (n:1), n is implied to be greater than 1. Thus, for expansion: k = n −1 means k > 0 for n > 1. Likewise, for compression, k + 1 n –1 means −1 < k < 0 for n > 1. Thus, it appears that k must always lie in the range k > −1. The DRC imposes no such restriction and k can be programmed to values as negative as −15.999. To determine what results when such values of k are entered, it is first helpful to note that the compression and expansion equations for k are actually the same equation. For example, a 1:2 expansion is also a 0.5:1 compression. 0.5 Compression å k + 1 –1 + 1 0.5 1 : 2 Expansion å k + 2–1 + 1 As can be seen, the same value for k is obtained either way. The ability to choose values of k less than −1 allows the DRC to implement negative slope transfer curves within a given region. Negative slope transfer curves are usually not associated with compression and expansion operations, but the definition of these operations can be expanded to include negative slope transfer functions. For example, if k = −4 1 Compression Equation : k + *4 + 1 n *1 å n + – 3 å *0.3333 : 1 compression Expansion Equation : k + *4 + n–1 å n + –3 å 1 : *3 expansion With k = −4, the output decreases 3 dB for every 1 dB increase in the rms value of the audio into the DRC. As the input increases in volume, the output decreases in volume. 28 TAS5518 SLES115 — August 2004 Introduction 1.12 Output Mixer The TAS5518 provides an 8x2 output mixer for channels 1, 2, 3, 4, 5, and 6. For channels 7 and 8 the TAS5518 provides an 8x3 output mixer. These mixers allow each output to be any ratio of any two (three) signal processed channels. The control parameters for the output crossbar mixer are programmable via the I2C interface. Gain Coefficient 28 Select Output N 48 Gain Coefficient 28 Select Output N 48 Output 1, 2, 3, 4, 7 or 8 Output 5 or 6 48 48 Gain Coefficient 28 Select Output N 48 Gain Coefficient 28 Select Output N 48 48 48 Gain Coefficient 28 Select Output N 48 48 Figure 1−21. Output Mixers 1.13 PWM The TAS5518 has eight channels of high performance digital PWM Modulators that are designed to drive switching output stages (backends) in both single-ended (SE) and H-bridge (bridge tied load) configuration. The TAS5518 device uses noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The TAS5518 uses an AD1 PWM modulation combined with a 5th order noise shaper to provide a 110-dB SNR from 20 to 20 kHz. The PWM section accepts 32-bit PCM data from the DAP and outputs eight PWM audio output channels configurable as either: • Six channels to drive power stages + two channels to drive a differential input active filter to provide a separately controllable stereo line out • Eight channels to drive power stages The TAS5518 PWM section output supports both single-ended and bridge-tied loads. The PWM section provides a headphone PWM output to drive an external differential amplifier like the TPA112. The headphone circuit uses the PWM modulator for channels 1 and 2. The headphone will not operate while the six or eight backend drive channels are operating. The headphone will be enabled via a headphone select terminal or I2C command. The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff frequency is less than 1 Hz. The PWM section has individual channel de-emphasis filters for 32, 44.1, and 48 kHz that can be enabled and disabled. The PWM section also contains the power supply volume control (PSVC) PWM. SLES115 — August 2004 TAS5518 29 Introduction The interpolator, noise shaper, and PWM sections provide a PWM output with the following features: • Up to 8x over sampling. − 8x at FS = 44.1 kHz, 48 kHz, 32 kHz, 38 kHz − 4x at FS = 88.2 kHz, 96 kHz − 2x at FS = 176.4 kHz, 192 kHz • 5th • 110-dB dynamic range 0 – 20 kHz (TAS5518 + TAS5182 system measured at speaker terminals) • THD < 0.01% • Adjustable maximum modulation limit of 93.8% to 99.2% • 3.3-V digital signal 1.13.1 order noise shaping DC Blocking (High Pass Enable/ Disable) Each input channel incorporates a first order digital high-pass filter to block potential dc components. The filter –3 dB point is approximately 0.89-Hz at 44.1-kHz sampling rate. The high-pass filter can be enabled and disabled via the I2C interface. 1.13.2 De-Emphasis Filter For audio sources that have been pre-emphasized, a precision 50 µs/15 µs de-emphasis filter is provided to support the sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. Figure 1−22 shows a graph of the de-emphasis filtering characteristics. De-emphasis is set using two bits in the system control register. Response − dB 0 −10 3.18 (50 µs) 10.6 (15 µs) Frequency − kHz Figure 1−22. De-emphasis Filter Characteristics 1.13.3 Power Supply Volume Control (PSVC) The TAS5518 supports volume control by both conventional digital gain / attenuation and by a combination of digital and analog gain / attenuation. Varying the H-bridge power supply voltage performs the analog volume control function. The benefits of using powers supply volume control (PSVC) are reduced idle channel noise, improved signal resolution at low volumes, increased dynamic range, and reduced radio frequency emissions at reduced power levels. The power supply volume control (PSVC) is enabled via I2C. When enabled the PSCV provides a PWM output that is filtered to provide a reference voltage for the power supply. The power supply adjustment range can be set for −12.04, −18.06, or −24.08 dB, to accommodate a range of variable power supply designs. Figure 1−23 and Figure 1−24 show how power supply and digital gains can be used together. The volume biquad (0xCF) can be used to implement a low-pass filter in the digital volume control to match the PSVC volume transfer function. 30 TAS5518 SLES115 — August 2004 Introduction Power Supply Volume Control Digital & Power Supply Gain − dB 30 20 10 0 Digital Gain −10 −20 Power Supply Gain −30 −40 −50 30 20 10 0 −10 −20 −30 −40 −50 −60 −70 −80 −60 Desired Gain − dB Figure 1−23. Power Supply and Digital Gains (Log Space) Power Supply Volume Control Digital & Power Supply Gain 100 10 1 Digital Gain 0.1 Power Supply Gain 0.01 0.001 0.0001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 Desired Gain (Linear) Figure 1−24. Power Supply and Digital Gains (Linear Space) 1.13.4 AM Interference Avoidance Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments patented AM interference avoidance circuit provides a flexible system solution for a wide variety of digital audio architectures. During AM reception, the TAS5518 adjusts the radiated emissions to provide an emission clear zone for the tuned AM frequency. The inputs to the TAS5518 for this operation are the tuned AM frequency, the IF frequency, and the sample rate. The sample rate is automatically detected. SLES115 — August 2004 TAS5518 31 Introduction Analog Receiver ADC PCM1802 Audio DSP TAS5518 TAS5111 TAS5111 TAS5111 Audio DSP provides the master and bit clocks TAS5111 TAS5111 TAS5111 TAS5111 TAS5111 Digital Receiver Audio DSP TAS5518 TAS5111 TAS5111 TAS5111 TAS5111 The Digital Receiver or the Audio DSP provides the Master and Bit clocks TAS5111 TAS5111 TAS5111 TAS5111 Figure 1−25. Block Diagrams of Typical Systems Requiring TAS5518 Automatic AM Interference Avoidance Circuit 32 TAS5518 SLES115 — August 2004 TAS5518 Controls and Status 2 TAS5518 Controls and Status The TAS5518 provides control and status information from both the I2C registers and device pins. This section describes some of these controls and status functions. The I2C summary and detailed register descriptions are contained in sections at the end of this document. 2.1 I2C Status Registers The TAS5518 has two status registers that provide general device information. These are the General Status Register 0 (0x01) and the Error Status Register (0x02). 2.1.1 General Status Register (0x01) • • • Device identification code Clip indicator – The TAS5518 has a clipping indicator. Writing to the register clears the indicator. Bank switching is busy 2.1.2 Error Status Register (0x02) 2.2 • No internal errors (the valid signal is high) • A clock error has occurred – These are sticky bits that are cleared by writing to the register. − LRCLK error – When the number of MCLKs per LRCLK is incorrect − SCLK error – When the number of SCLKS per LRCLK is incorrect − Frame slip – When the number of MCLKs per LRCLK changes by more than 10 MCLK cycles − PLL phase-lock error • This error status register is normally used for system development only. TAS5518 Pin Controls The TAS5518 provide a number of terminal controls to manage the device operation. These controls are: • • • • • RESET PDN BKND_ERR HP_SEL MUTE 2.2.1 Reset (RESET) The TAS5518 is placed in the reset mode by setting the RESET terminal low or by the power up reset circuitry when power is applied. RESET is an asynchronous control signal that restores the TAS5518 to the hard mute state (M). Master volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset without an MCLK input. As long as the RESET terminal is held low, the device is in the reset state. During reset, all I2C and serial data bus operations are ignored. Table 2−1 shows the device output signals while RESET is active. Table 2−1. Device Outputs During Reset SIGNAL SLES115 — August 2004 SIGNAL STATE Valid Low PWM P-outputs Low (M-State) PWM M-outputs Low (M-State) SDA Signal Input (not driven) TAS5518 33 TAS5518 Controls and Status Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading edge) of RESET cannot be avoided. However, the transition from the hard mute state (M) to the operational state is performed using a quiet start up sequence to minimize noise. This control uses the PWM reset and unmute sequence to shut down and start up the PWM. A detailed description of these sequences is contained in the PWM section. If a completely quiet reset or power down sequence is desired, MUTE should be applied before applying RESET. The rising edge of the reset pulse begins device initialization before the transition to the operational mode. During device initialization, all controls are reset to their initial states. Table 2−2 shows the default control settings following a reset. Table 2−2. Values Set During Reset CONTROL 34 TAS5518 SETTING Clock register Not valid High pass Disabled Unmute from clock error Hard unmute PSVC high Z Disabled Post DAP detection automute Enabled Eight Ch PreDAP detection automute Enabled De−emphasis De-emphasis disabled Channel configuration control Configured for the default setting Headphone configuration control Configured for the default setting Serial data interface format I2S 24 bit Individual channel mute No channels are muted Automute delay 5 ms Automute threshold 1 < 8 bits Automute threshold 2 Same as automute threshold 1 Modulation limit Maximum modulation limit of 97.7% Six (or eight – low) channel configuration Eight channels Slew rate limit Disengaged for all channels Interchannel delay −32, 0, –16, 16, –24, 8, –8, −24 Shutdown PWM on error Enabled Volume and mute update rate Volume ramp 85 ms Treble and bass slew rate Update every 1.31 ms Bank switching Manual bank selection is enabled Auto bank switching map All channels use Bank 1 Biquad coefficients (5508) Set to All pass Input mixer coefficients Input N −> Channel N, no attenuation Output mixer coefficients Channel N −> Output N, no attenuation Subwoofer sum into Ch1 and 2 (5508) Gain of 0 Ch1 and 2 sum in subwoofer (5508) Gain of 0 Bass and treble bypass Gain of 1 Bass and treble Inline Gain of 0 DRC bypass (5508) Gain of 1 DRC inline (5508) Gain of 0 DRC (5508) DRC disabled, default values Master volume Mute Individual channel volumes 0 dB All bass and treble Indexes 0x12 neutral Treble filter sets Filter Set 3 SLES115 — August 2004 TAS5518 Controls and Status CONTROL SETTING Bass filter sets Filter Set 3 Loudness (5508) Loudness disabled, default values AM interference enable Disabled AM interference IF 455 AM interference select sequence 1 Tuned freq and mode 0000 , BCD Subwoofer PSVC control Enabled PSVC and PSVC range Disabled / 0 dB After the initialization time, the TAS5518 starts the transition to the operational state with the Master volume set at mute. Since the TAS5518 has an external crystal time base, following the release of RESET, the TAS5518 sets the MCLK and data rates and perform the initialization sequences. The PWM outputs are held at a mute state until the master volume is set to a value other than mute via I2C. 2.2.2 Power Down (PDN) TheTAS5518 can be placed into the power down mode by holding the PDN terminal low. When power down mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation (there is no ramp down). This control uses the PWM mute sequence that provides a low click and pop transition to the hard mute state (M). A detailed description of the PWM mute sequence is contained in the PWM section. Power down is an asynchronous operation that does not require MCLK to go into the power down state. To initiate the power-up sequence requires MCLK to be operational and the TAS5518 to receive 5 MCLKs prior to the release of PDN. As long as the PDN terminal is held low the device is in the power down state with the PWM outputs in a hard mute (M) state. During power down, all I2C and serial data bus operations are ignored. Table 2−3 shows the device output signals while PDN is active. Table 2−3. Device Outputs During Power Down SIGNAL SIGNAL STATE Valid Low PWM P-outputs M-state = low PWM M-outputs M-state = low SDA Signal input PSVC M-state = low Following the application of PDN, the TAS5518 does not perform a quiet shutdown to prevent clicks and pops produced during the application (the leading edge) of this command. The application of PDN immediately performs a PWM stop. A quiet stop sequence can be performed by first applying MUTE before PDN. When PDN is released, the system goes to the end state specified by MUTE and BKND_ERR pins and the I2C register settings. The crystal time base allows the TAS5518 to determine the CLK rates. Once these rates are determined, the TAS5518 unmutes the audio. 2.2.3 Backend Error (BKND_ERR) Backend error is used to provide error management for backend error conditions. Backend error is a level sensitive signal. Backend error can be initiated by bringing the BKND_ERR terminal low for a minimum 5 MCLK cycles. When BKND_ERR is brought low, the PWM sets either six or eight channels into the PWM backend error state. This state is described in the PWM section. Once the backend error sequence is initiated, a delay of 5 ms is performed before the system starts the output re−initialization sequence. After the initialization time, the TAS5518 begins normal operation. Backend error does not affect other PWM modulator operations SLES115 — August 2004 TAS5518 35 TAS5518 Controls and Status The number of channels that are affected by the BKND_ERR signal is dependent upon the 6-channel configuration signal. If the I2C setting 6-channel configuration is false, the TAS5518 places all eight PWM outputs in the PWM backend error state, while not affecting any other internal settings or operations. If the I2C setting six configuration is true, the TAS5518 brings the PWM outputs 1−6 to a backend error state, while not affecting any other internal settings or operations. Table 2−4 shows the device output signal states during backend error. Table 2−4. Device Outputs During Backend Error SIGNAL SIGNAL STATE Valid Low PWM P-outputs M-State − low PWM M-outputs M-State − low HPPWM P-outputs M-State − low HPPWM M-outputs M-State − low SDA Signal Input (not driven) 2.2.4 Speaker / Headphone Selector (HP_SEL) The HP_SEL terminal enables the headphone output or the speaker outputs. The headphone output receives the processed data output from DAP and PWM channels 1 and 2. In 6-channel configuration this feature does not affect the two lineout channels. When low, the headphone output is enabled. In this mode the speaker outputs are disabled. When high, the speaker outputs are enabled and the headphone is disabled. Changes in the pin logic level results in a state change sequence using soft mute to the hard mute (M) state for both speaker and headphone followed by a soft unmute. When HP_SEL is low, the configuration of channels 1 and 2 are defined by the headphone configuration register. When HP_SEL is high, the channel 1 and 2 configuration registers define the configuration of channels 1 and 2. 2.2.5 Mute (MUTE) The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume. The TAS55508 has both a master and individual channel mute commands. A terminal is also provided for the master MUTE. The low active master Mute I2C register and the MUTE terminal are logically Or’ed together. If either is set to low, a mute on all channels is performed. The master mute command operates on all channels regardless on whether the system is in six or eight channel configuration. When MUTE is invoked, the PWM output stops switching and then goes to an idle state. The master Mute terminal is used to support a variety of other operations in the TAS5518, such as setting the inter-channel delay, the biquad coefficients, the serial interface format, and the clock rates. A mute command by the master mute terminal, individual I2C mute, the AM interference mute sequence, the bank switch mute sequence, or automute overrides an unmute command or a volume command. While a mute is active, the commanded channels will be placed in a mute state. When a channel is unmuted, it goes to the last commanded volume setting that has been received for that channel. 2.3 Device Configuration Controls The TAS5518 provides a number of system configuration controls that are set at initialization and following a reset. • • • 36 Channel Configuration Headphone Configuration Audio System Configurations TAS5518 SLES115 — August 2004 TAS5518 Controls and Status • • • • • • • Recovery from Clock Error Power Supply Volume Control Enable Volume and Mute Update Rate Modulation Index Limit Inter-channel Delay Master Clock and Data Rate Controls Bank Controls 2.3.1 Channel Configuration Registers In order for the TAS5518 to have full control of the power stages, registers 0x05 to 0x0C must be programmed to reflect the proper power stage and how each one should be controlled. Channel configuration registers consist of eight registers, one for each channel. The primary reason for using these registers is that different power stages require different handling during start up, mute/unmute, shutdown, and error recovery. The TAS5518 must select the sequence that gives the best click and pop performance and insure that the bootstrap capacitor is charged correctly during start up. This sequence depends on which power stage is present at the TAS5518 output. Table 2−5. Description of the Channel Configuration Registers (0x05 to 0x0C) BIT DESCRIPTION D7 Enable/disable error recovery sequence. In case the BKND_RECOVERY pin is pulled low, this register determines if this channel is to follow the error recovery sequence or to continue with no interruption. D6 Determines if the power stage needs the TAS5518 VALID pin to go low to reset the power stage. Some power stages can be reset by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power stages. This provides better control of each power stage. D5 Determines if the power stage needs the TAS5518 VALID pin to go low to mute the power stage. Some power stages can be muted by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power stages. This provides better control of each power stage. D4 Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin are opposite the TAS5518 PWM pinout. This makes routing on the PCB easier. To keep the phase of the output the speaker terminals must also be inverted. D3 The power stage TAS5182 has a special PWM input. To ensure that the TAS5518 has full control in all occasions, the PWM output must be remapped. D2 Can be used to handle click and pop for some applications. D1 This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation of both speaker outputs to be low. This bit sets the PWM outputs high-high during mute. D0 Not used SLES115 — August 2004 TAS5518 37 TAS5518 Controls and Status Table 2−6 lists the optimal setting for each output stage configuration. Note that the default value is applicable in all configurations except the TAS5182 SE/BTL configuration. Table 2−6. Recommended TAS5518 Configurations for Texas Instruments Power Stages DEVICE ERROR RECOVERY CONFIGURATION D7 D6 D5 D4 D3 D2 D1 D0 Default RES BTL 1 1 1 0 0 0 0 0 BTL 1 1 1 0 0 0 0 0 SE 1 1 1 0 0 0 0 0 BTL 0 1 1 0 0 0 0 0 RES TAS5111 AUT RES TAS5112 AUT TAS5182 RES SE 0 1 1 0 0 0 0 0 BTL 1 1 0 0 0 0 0 0 SE 1 1 0 0 0 0 0 0 BTL 0 1 0 0 0 0 0 0 SE 0 1 0 0 0 0 0 0 BTL 1 1 1 0 1 0 0 0 SE 1 1 1 0 1 0 0 0 RES: The output stage requires VALID to go low to recover from a shutdown. AUT: The power stage can auto recover from a shutdown. BTL: Bridge tied load configuration SE: Single-ended configuration 2.3.2 Headphone Configuration Registers The headphone configuration controls are identical to the speaker configuration controls. The headphone configuration control settings are used in place of the speaker configuration control settings for channels 1 and 2 when the headphones are selected. In reality however, there is only one used configuration setting for headphones and that is the default setting. 2.3.3 Audio System Configurations The TAS5518 can be configured to comply with various audio systems: 5.1-channel system, 6-channel system, 7.1-channel system and 8-channel system. The audio system configuration is set in the General Control Register (0xE0). Bits D31 – D4 must be zero and D0 is don’t care. D3 Determines if SUB is to be controlled by PSVC (D3 is a write-only bit) D2 Enable/Disable power supply volume control D1 Sets number of speakers in the system, including possible line outputs D3−D1 must be configured as the following according to the audio system in the application: Table 2−7. Audio System Configuration (General Control Register 0xE0) 38 TAS5518 AUDIO SYSTEM D31−D4 D3 D2 D1 D0 DEFAULT 0 0 0 0 X 6 channel or 5.1 NOT using PSVC 0 0 0 1 X 6 channel using PSVC 0 0 1 1 X 5.1 system using PSVC 0 1 1 1 X 8 channel or 7.1 NOT using PSVC 0 0 0 0 X 8 channel using PSVC 0 0 1 0 X 7.1 system using PSVC 0 1 1 0 X SLES115 — August 2004 TAS5518 Controls and Status 2.3.3.1 Using Line Outputs in 6-Channel Configurations The audio system can be configured for a 6-channel configuration (with 2 line outs) by writing a 1 to bit D1 of register 0xE0 (General Control Register). In this configuration, channel 5 and 6 processing are exactly the same as the other channels, except that Master Volume has no effect. Note that in 6-channel configuration, channels 5 and 6 are unaffected by backend error (BKND_ERR goes low). To use channels 5 and 6 as dry unprocessed line outs, the following setup should be done: • Channel 5 volume and channel 6 volume should be set for a constant output such as 0 dB. • Bass and Treble for channels 5 and 6 can be used if desired. • DRC1 should be by-passed for channels 5 and 6. • If enabled, the loudness function shapes the response of channels 5 and 6. However, the amplitude of 5 and 6 are not used in determining the loudness response. • If a down mix is desired on the channel 5 and 6 as line out, the down mixing can be performed using the channel 5 and channel 6 input mixers. • The operation of the channel 5 and 6 biquads is unaffected by the 6/8 channel configuration setting. 2.3.4 Recovery from Clock Error The TAS5518 can be set to either perform a volume ramp up during the recovery sequence of a clock error or to simply come up in the last state (or desired state if a volume or tone update was in progress). This feature is enabled via I2C system control register 0x03. 2.3.5 Power Supply Volume Control Enable The power supply volume control (PSVC) can be enabled and disabled via I2C register 0xE0. The subwoofer PWM output can configured to be controlled by the PSVC or digitally attenuated when PSVC is enabled (for powered subwoofer configurations). Note that PSVC cannot be simultaneously enabled along with unmute outputs after clock error feature. SLES115 — August 2004 TAS5518 39 TAS5518 Controls and Status 2.3.6 Volume and Mute Update Rate The TAS5518 has fixed soft volume and mute ramp durations. The ramps are linear. The soft volume and mute ramp rates are adjustable by programming the I2C register 0xD0 for the appropriate number of steps to be 512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate. • In normal speed, the update rate is 1 step every 4 / Fs seconds. • In double speed, the update is 1 step every 8 / Fs seconds. • In quad speed, the update is 1 step every 16 / Fs seconds. Because of processor loading, the update rate can increase for some increments by +1/Fs to +3/Fs. However, the variance of the total time to go from +18 dB to mute is less than 25%. Table 2−8. Volume Ramp Rates in ms NUMBER OF STEPS SAMPLE RATE (KHZ) 44.1, 88.2, 176.4 32, 48, 96, 192 42.67 ms 512 46.44 ms 1024 92.88 ms 85.33 ms 2048 185.76 ms 170.67 ms 2.3.7 Modulation Index Limit PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is 50%. When the audio signal increases towards full scale, the PWM modulation increases towards 100%. For negative signals, the PWM modulations fall below 50% towards 0%. However, there is a limit to the maximum modulation possible. During the off-time period, the power stage connected to the TAS5518 output needs to get ready for he next on-time period. The maximum possible modulation is then set by the power stage requirements. All Texas Instruments power stages needs maximum modulation to be 97.7%. This is also the default setting of the TAS5518. Default settings can be changed in the Modulation Index Register (0x16). Note that no change should be made to this register when using Texas Instruments power stages. 40 TAS5518 SLES115 — August 2004 TAS5518 Controls and Status 2.3.8 Inter-channel Delay An 8-bit value can be programmed to each of the eight PWM inter-channel delay registers to add a delay per channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK. The default values are shown in Table 2−9. Table 2−9. Inter-Channel Delay Default Values I2C SUB-ADDRESS CHANNEL INTER-CHANNEL DELAY DEFAULT (DCLK PERIODS) 0x1B 1 −24 0x1C 2 0 0x1D 3 −16 0x1E 4 +16 0x1F 5 −24 0x20 6 +8 0x21 7 −8 0x22 8 +24 This delay is generated in the PWM and can be changed at any time through the serial control interface I2C registers 0x1B – 0x22. The absolute offset for channel 1 is set in I2C sub-address 0x23. NOTE:If used correctly, setting the PWM channel delay can optimize the performance of a pure path digital amplifier system. The setting is based upon the type of backend power device that is used and the layout. These values are set during initialization using the I2C serial interface. Unless otherwise noted, use the default values given in Table 2−9. 2.4 Master Clock and Serial Data Rate Controls The TAS5518 function only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK (left/right clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz external crystal allows the TAS5518 to automatically detect MCLK and the data rate. The MCLK frequency can be 64 x Fs, 128 x Fs, 196 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, or 768 x Fs. The TAS5518 operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK. However, there is no constraint as to the phase relationship of these signals. The TAS5518 accepts a 64 x Fs SCLK rate and a 1 x Fs LRCLK. If the phase of SCLK or LRCLK drifts more than ±10 MCLK cycles since the last RESET, the TAS5518 performs a clock error and resynchronize the clock timing. The clock and serial data interface have several control parameters: • MCLK Ratio 64 Fs, 128 Fs, 196 Fs, 256 Fs, 384 Fs, 512 Fs, or 768 Fs) − I2C parameter • Data Rate 32, 38, 44.1,48, 88.2, 96, 176.4, 192 kHz − I2C parameter • AM Mode Enable / Disable − I2C parameter During AM interference avoidance, the clock control circuitry utilizes three other configuration inputs: • Tuned AM Frequency (for AM interference avoidance) (550 − 1750 kHz) − I2C parameter • Frequency Set Select (1−4) − I2C parameter • Sample Rate − I2C parameter or auto detected SLES115 — August 2004 TAS5518 41 TAS5518 Controls and Status 2.4.1 PLL Operation The TAS5518 uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL (DPLL) and the analog PLL (APLL). The analog PLL provides the reference clock for the PWM. The digital PLL provides the reference clock for the digital audio processor and the control logic. The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz crystal provides the input reference clock for the digital PLL. The crystal provides a time base to support a number of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions. The crystal time base provides a constant rate for all controls and signal timing. Even if MCLK is not present, the TAS5518 can receive and store I2C commands and provide status. 2.5 Bank Controls The TAS5518 permits the user to specify and assign sample rate dependent parameters for Biquad, Loudness, DRC, and Tone in one of three banks that can be manually selected or selected automatically based upon the data sample rate. Each bank can be enabled for one or more specific sample rates via I2C bank control register 0x40. Each bank set holds the following values: • Coefficients for Seven Biquads (7X5 = 35 coefficients) for Each of the Eight Channels (Registers 0X51 – 0x88) • Coefficients for One Loudness Biquad (Register 0x95) • DRC1 Energy and (1 – Energy) Values (Register 0x98) • DRC1 Attack, (1 − Attack), Decay, (1 – Decay) Values (Register 0x9C) • DRC2 Energy and (1 – Energy) Values (Register 0x9D) • DRC2 Attack, (1 − Attack), Decay, (1 – Decay) Values (Register 0xA1) • Five Bass Filter-Set Selections (Register 0xDA) • Five Treble Filter-Set Selections (Register 0xDC) The default selection for bank control is manual bank with bank 1 selected. Note that if bank switching is used, Bank 2 and Bank 3 must be programmed on power−up since the default values are all zeroes. If bank switching is used and Bank 2 and Bank 3 are not programmed correctly, then the output of the TAS5518 could be muted when switching to those banks. 2.5.1 Manual Bank Selection The three bank selection bits of the bank control register allow the appropriate bank to be manually selected (000 = Bank 1, 001 = Bank 2, 010 = Bank 3). In the manual mode, when a write occurs to the Biquad, DRC, or Loudness coefficients, the current selected bank is updated. If audio data is streaming to the TAS5518, during a manual bank selection, the TAS5518 first performs a mute sequence, then performs the bank switch, and finally restores the volume using an un−mute sequence. A mute command initiated by the bank switch mute sequence overrides an un−mute command or a volume command. While a mute is active, the commanded channels are muted. When a channel is unmated, the volume level goes to the last commanded volume setting that has been received for that channel. If MCLK or SCLK is stopped, the TAS5518 performs a bank switch operation. If the clocks should start up once the manual bank switch command has been received, the bank switch operation is performed during the 5−ms silent start sequence. 2.5.2 Automatic Bank Selection To enable automatic bank selection, a value of 3 is written into in the bank selection bits of the bank control register. Banks are associated with one or more sample rates by writing values into the Bank 1 or Bank 2 data rate selection registers. The automatic base selection is performed when a frequency change is detected according to the following scheme: 42 TAS5518 SLES115 — August 2004 TAS5518 Controls and Status 1. The system scans Bank 1 data rate associations to see if the Bank 1 is assigned for that data rate. 2. If Bank 1 is assigned, then the Bank 1 coefficients will be loaded. 3. If it is not then, the system scans the bank 2 to see if Bank 1 is assigned for that data rate. 4. If Bank 2 is assigned, then the Bank 2 coefficients will be loaded. 5. If it is not then, the system loads the Bank 3 coefficients. The default is that all frequencies are enabled for Bank 1. This default is expressed as a value of all 1s in the Bank 1 auto-selection byte and all 0s in the bank 2 auto−section byte. 2.5.2.1 Coefficients Write Operations While Automatic Bank Switch Is Enabled In automatic mode if a write occurs to the Tone, EQ, DRC, or Loudness coefficients, the bank that is written to is the current bank. 2.5.3 Bank Set Bank set is used to provide a secure way to update the bank coefficients in both the manual and automatic switching modes without causing a bank switch to occur. Bank set mode does not alter the current bank register mapping. It simply enables any bank’s coefficients to be updated while inhibiting any bank switches from taking place. In manual mode, this enables the coefficients to be set without switching banks. In automatic mode this prevents a clock error or data rate change from corrupting a bank coefficient write. To update the coefficients of a bank, a value of 4, 5, or 6 is written into in the bank selection bits of the bank control register. This enables the Tone, EQ, DRC, and Loudness coefficient values of bank 1, 2, or 3 to be respectively updated. Once the coefficients of the bank have been updated, the bank selection bits are then returned to the desired manual or automatic bank selection mode. 2.5.4 Bank Switch Timeline After a bank switch is initiated (manual or automatic), no I2C writes to the TAS5518 should occur before a minimum of 186 ms. This value is determined by the volume ramp rates for a particular sample rate. 2.5.5 Bank Switching Example 1 Problem: The audio unit containing a TAS5518 needs to handle different audio formats with different sample rates. Format #1 requires Fs = 32 kHz, Format #2 requires Fs = 44.1 kHz, and Format #3 requires Fs = 48 kHz. The sample-rate dependent parameters in the TAS5518 require different coefficients and data depending on the sample rate. Strategy: Use the TAS5518 bank switching feature to allow for managing and switching three banks associated with the three sample rates, 32 kHz (Bank 1), 44.1 kHz (Bank 2), and 48 kHz (Bank 3). One possible algorithm is to generate, load, and automatically manage bank switching for this problem: • Generate bank-related coefficients (see above) for sample rates 32 kHz, 44.1 kHz, and 48 kHz and include the same in the micro-based TAS5518 I2C firmware. • On TAS5518 power up or reset, the micro runs the following TAS5518 Initialization code: − Update Bank 1 (Write 0x00048040 to register 0x40). − Write bank-related I2C registers with appropriate values for Bank 1. − Write Bank 2 (Write 0x00058040 to register 0x40). − Load bank-related I2C registers with appropriate values for Bank 2. − Write Bank 3 (Write 0x00068040 to register 0x40). − Load bank-related I2C registers with appropriate values for Bank 3. − Select automatic bank switching (write 0x00038040 to register 0x40) SLES115 — August 2004 TAS5518 43 TAS5518 Controls and Status • Now when the audio media changes, the TAS5518 automatically detects the incoming sample rate and automatically switches to the appropriate bank. In this example any sample rates other then 32 kHz and 44.1 kHz will use Bank 3. If other sample rates are used, then the banks need to be set−up differently. 2.5.6 Bank Switching Example 2 Problem: The audio system uses all of the sample rates supported by the TAS5518. How can the automatic bank switching be set up to handle this situation? Strategy: Use the TAS5518 bank switching feature to allow for managing and switching three banks associated with sample rates as follows: • Bank 1: Coefficients for 32 kHz, 38 kHz, 44.1 kHz, and 48 kHz • Bank 2: Coefficients for 88.2kHz and 96 kHz • Bank 3: Coefficients for 176.4 kHz and 192 kHz One possible algorithm is to generate, load, and automatically manage bank switching for this problem: • Generate bank-related coefficients for sample rates 48 kHz (Bank 1), 96 kHz (Bank 2), and 192 kHz (Bank 3) and include the same in the micro-based TAS5518 I2C firmware. • On TAS5518 power−up or reset, the micro runs the following TAS5518 Initialization code: • 44 − Update Bank 1 (Write 0x0004F00C to register 0x40). − Write bank-related I2C registers with appropriate values for Bank 1. − Write Bank 2 (Write 0x0005F00C to register 0x40). − Load bank-related I2C registers with appropriate values for Bank 2. − Write Bank 3 (Write 0x0006F00C to register 0x40). − Load bank-related I2C registers with appropriate values for Bank 3. − Select automatic bank switching (Write 0x0003F00C to register 0x40) Now when the audio media changes, the TAS5518 automatically detects the incoming sample rate and automatically switches to the appropriate bank. TAS5518 SLES115 — August 2004 Electrical Specifications 3 Electrical Specifications 3.1 Absolute Maximum Ratings{ UNITS Supply voltage, DVDD and DVD_PWM −0.3 V to 3.6 V Supply voltage, AVDD_PLL −0.3 V to 3.6 V 3.3-V digital input −0.5 V to DVDD + 0.5 V 5 V tolerant(2) digital input Input voltage −0.5 V to 6 V 1.8 V LVCMOS(3) −0.5 V to VREF(1) + 0.5 V Input clamp current, IIK (VI < 0 or VI > 1.8 V ±20 mA Output clamp current, IOK (VO < 0 or VO > 1.8 V) ±20 mA Operating free air temperature 0°C to 70°C Storage temperature range, Tstg −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. VREF is a 1.8-V supply derived from regulators internal to the TAS5518 chip. VREF is on terminals VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, and VR_PWM. These terminals are provided to permit use of external filter capacitors, but should not be used to source power to external devices. 2. 5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL. 3. VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, VR_PWM DISSIPATION RATING TABLE (High-k Board, 1055C Junction) 3.2 PACKAGE TA ≤ 255C POWER RATING DERATING FACTOR ABOVE TA = 255C TA = 705C POWER RATING PAG 1869 mW 23.36 mW/°C 818 mW Dynamic Performance (At Recommended Operating Conditions at 255C) PARAMETER Dynamic range Total harmonic distortion Frequency response 3.3 TEST CONDITIONS MIN TAS5518 + TAS5182 EVM A-weighted (FS = 48 kHz) NOM MAX 110 TAS5182 A at 1 W UNITS dB 0.1% TAS5518 ouput 0.01% 32-kHz to 96-kHz sample rates ±0.1 176.4, 192-kHz sample rates ±0.2 dB Recommended Operating Conditions (over 05C to 705C) Digital supply voltage, DVDD and DVDD_PWM Analog supply voltage, AVDD_PLL High-level High level input voltage, VIH MIN NOM MAX 3 3.3 3.6 V 3 3.3 3.6 V 3.3 V 2 5-V tolerant(4) 2 1.8-V LVCMOS (XTL_IN) V 1.26 3.3 V Low-level Low level input voltage, VIL 5-V UNITS 0.8 tolerant(4) 0.8 1.8-V (XTL_IN) V 0.54 Operating ambient air temperature range, TA −20 Operating junction temperature range, TJ −20 25 70 °C 105 °C NOTE 4: 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4. SLES115 — August 2004 TAS5518 45 Electrical Specifications 3.4 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER VOH High level output voltage High-level VOL Low level output voltage Low-level IOZ High-impedance output current IIL Low-level Low level input current High-level High level input current TYP MAX 1.8-V LVCMOS (XTL_OUT) IOH = − 0.55 mA 3.3-V TTL and 5 V(6) tolerant IOL = 4 mA 0.5 1.8-V LVCMOS (XTL_OUT) IOL = 0.75 mA 0.5 2.4 ±20 3.3-V TTL VI = VIL ±1 1.8-V LVCMOS (XTL_IN) VI = VIL ±1 VI = 0 V DVDD = 3 V ±1 3.3-V TTL VI = VIH ±1 1.8-V LVCMOS (XTL_IN) VI = VIH ±1 5 V tolerant(5) VI = 5.5 V DVDD = 3 V ±1 tolerant(5) Input supply current voltage AVDD Analog supply voltage, UNITS V 1.44 3.3-V TTL Digital supply voltage, voltage DVDD IDD MIN IOH = −4 mA 5V IIH TEST CONDITIONS 3.3 V TTL and 5 V(6) tolerant Fs = 48 kHz 140 Fs = 96 kHz 150 Fs = 192kHz 155 Power down 8 Normal 6 Power down 1 V µA µA µA mA mA NOTES: 5. 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4. 6. 5-V tolerant outputs are SCL and SDA 3.5 PWM Operation at Recommended Operating Conditions Over 05C to 705C PARAMETER Output sample rate 1X – 8 x over sampled 3.6 TEST CONDITIONS MODE VALUE UNITS 384 kHz 8, 4, and 2 x sample rate 352.8 kHz 8, 4, and 2 x sample rate 384 kHz 32-kHz data rate ±4% 12 x sample rate 44.1-, 88.2-, 176.4-kHz data rate ±4% 48, 96, 192 kHz data rate ±4% Switching Characteristics 3.6.1 Clock Signals Over Recommended Operating Conditions (Unless Otherwise Noted) 3.6.1.1 PLL Input Parameters and External Filter Components{ PARAMETER TEST CONDITIONS MIN fXTALI Frequency, XTAL IN fMCLKI Frequency, MCLK (1 / tcyc2) Only use 13.5-MHz crystal ≤1000 ppm 2 MCLK duty cycle duty cycle 40% TYP MAX 13.5 MHz 50 50% UNITS MHz 60% MCLK minimum high time ≥2-V MCLK = 49.152 MHz, Within the min and max duty cycle constraints 5 ns MCLK minimum low time ≤0.8-V MCLK = 49.152 MHz, Within the min and max duty cycle constraints 5 ns LRCLK allowable drift before LRCLK reset 10 MCLKs External PLL filter cap C1 SMD 0603 Y5V 100 nF External PLL filter cap C2 SMD 0603 Y5V External PLL filter resistor R SMD 0603, metal film 10 nF 200 Ω External VRA_PLL decoupling SMD, Y5V 100 nF See the TAS5518 Example Application Schematic section. 46 TAS5518 SLES115 — August 2004 Electrical Specifications 3.6.2 Serial Audio Port 3.6.2.1 Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN CL = 30 pF TYP 2.048 MAX Frequency, SCLK 64 x fs tsu1 Setup time, LRCLK to SCLK rising edge 10 ns th1 Hold time, LRCLK from SCLK rising edge 10 ns tsu2 Setup time, SDIN to SCLK rising edge 10 ns th2 Hold time, SDIN from SCLK rising edge 10 LRCLK frequency 32 48 192 SCLK duty cycle 40% 50% 60% LRCLK duty cycle 40% 50% 60% MHz ns kHz 64 64 SCLK edges −1/4 1/4 SCLK period SCLK rising edges between LRCLK rising edges LRCLK clock edge with respect to the falling edge of SCLK 12.288 UNITS fSCLKIN SCLK (Input) th1 tsu1 LRCLK (Input) th2 tsu2 SDIN1 SDIN2 SDIN3 Figure 3−1. Slave Mode Serial Data Interface Timing SLES115 — August 2004 TAS5518 47 Electrical Specifications 3.6.3 I 2C Serial Control Port Operation 3.6.3.1 Timing Characteristics for I2C Interface Signals Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN fSCL Frequency, SCL No wait states tw(H) Pulse duration, SCL high 0.6 tw(L) Pulse duration, SCL low 1.3 tr Rise time, SCL and SDA tf Fall time, SCL and SDA tsu1 Setup time, SDA to SCL th1 Hold time, SCL to SDA t(buf) tsu2 MAX UNITS 400 kHz µs µs 300 ns 300 ns 100 ns 0 ns Bus free time between stop and start condition 1.3 µs Setup time, SCL to start condition 0.6 µs th2 Hold time, start condition to SCL 0.6 µs tsu3 Setup time, SCL to stop condition 0.6 CL Load capacitance for each bus line µs 400 tw(L) tw(H) tr pF tf SCL tsu1 th1 SDA Figure 3−2. SCL and SDA Timing SCL th2 t(buf) tsu2 tsu3 Start Condition Stop Condition SDA Figure 3−3. Start and Stop Conditions Timing 48 TAS5518 SLES115 — August 2004 Electrical Specifications 3.6.4 Reset Timing (RESET) 3.6.4.1 Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER tr(DMSTATE) Time to M-STATE low tw(RESET) Pulse duration, RESET active tr(I2C_ready) Time to enable I2C tr(run) Device startup time MIN TYP 400 MAX UNITS 370 ns None 3 10 RESET ns ms ms Earliest time that M-State could be exited tw(RESET) M-State tr(I2C_ready) tr(run) tr(DMSTATE) = ~ < 300 ns Determine SCLK rate and MCLK ratio Enable I2C Start system Figure 3−4. Reset Timing Since a crystal time base is used, the system determines the CLK rates. Once the data rate and master clock ratio is determined, the system outputs audio if a master volume command is issued. 3.6.5 Power-Down (PDN) Timing 3.6.5.1 Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER tp(DMSTATE) MIN Number of MCLKs preceding the release of PDN tsu TYP Time to M-STATE low MAX UNITS 300 µs 5 Device startup time 120 ms PDN M-State tp(DMSTATE) = ~ < 300 µs tsu Figure 3−5. Power-Down Timing SLES115 — August 2004 TAS5518 49 Electrical Specifications 3.6.6 Backend Error (BKND_ERR) 3.6.6.1 Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER tw(ER) MIN Pulse duration, BKND_ERR active 350 tp(valid_low) tp(valid_high) I2C programmable to be between 1 to 10 ms TYP MAX UNITS None ns