TAS5548DCAR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TAS5548 SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 TAS5548 8-Channel HD Compatible Audio Processor with ASRC and PWM Output 3 Description The TAS5548 is an 8-channel Digital Pulse Width Modulator (PWM) with Digital Audio Processing and Sample Rate Converter that provides both advanced performance and a high level of system integration. TAS5548 is designed to support DTS-HD specification Blu-ray HTiB applications. The ASRC consists of two separate modules which handle 4 channels each. Therefore, it is possible to support up to two different input sampling rates. Texas Instruments Power Stages are designed to work seamlessly with the TAS5548. The TAS5548 also provides a high-performance, differential output to drive an external, differential-input, analog headphone amplifier. The TAS5548 supports AD, BD, and ternary modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data. The external crystal used must be 12.288 MHz. The TAS5548 also features power-supply-volume-control (PSVC), which improves dynamic range at lower power level and can be used as part of a Class G power supply when used with closed-loop PWM input power stages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TAS5548 HTSSOP (56) 14.00 mm x 6.10 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Block Diagram SDIN1 SDIN2 SCLK LRCLK SDIN2-1 SDIN2-2 SCLKO /SCLKIN_2 LRCLKO / LRCKIN_2 Serial Audio Receiver 2x Stereo Serial Audio Receiver 2x Stereo Fixed Flow Digital Audio Processor (DAP) 4ch ASRC 8ch PWM Generator 10ch input 8ch Processor 8ch Output Mixer 4ch ASRC PWM_x_1 through 8 + Headphone (PWM) Bypass /BKND_ERR VALID PWM_HPM_L&R PWM_HPP_L&R /MUTE /PDN DVSS2 DVSS1 DVDD2 I2C Control DVDD1 MCU Power AVSS_PWM AVSS AVDD VR_DIG VR_ANA VR_PWM SCL AVDD_PWM SDA Energy Manager (EMO) /HP_SEL RESET TEST 12.288 ASEL_EMO2 Clocks (Osc, PLL etc) ASEL_EMO2 Serial Audio Transciever Stereo Power Supply Volume Control (PSVC) PSVC/MCLKO SDOUT/SDIN5 MCLK • Interface Seamlessly with Most Digital Audio Decoders EMO1 • 2 Applications OSCRES • General Features – 8ch Asynchronous Sample Rate Converter – 8 Channel Audio Processing for 32-192 kHz (ARSC to 96kHz) – 4 Channel Native Audio Processing at 192kHZ – 30 kHz Audio Bandwidth for DTS-HD Compatibility – Energy Manager for Overall System Power Control – Power Supply Volume Control Audio Input or Output – Up to Five Synchronous Serial Audio Inputs (10 Channels) – Up to One Synchronous Serial Audio Outputs (2 Channels) – I2S Master Mode When Used With External Crystal – Slave Mode 32-192KHz With Auto/Manual Sample Rate Detection – Eight Differential PWM Output That can Support AD or BD Modulation – Two Differential PWM Headphone Outputs – I2S Out for External Wireless Sub – PWM Output Supports Single Ended (S.E.) or Bridge Tied Load (BTL) Audio Processing – Volume Control Range 18 dB to –127 dB (Master and Eight Channel Volume) – Bass and Treble Tone Controls With ±18-dB Range, Selectable Corner Frequencies – Configurable Loudness Compensation – Two Dynamic Range Compressors With Two Thresholds, Two Offsets, and Three Slopes – Seven Biquads Per Channel PWM Processing – >105-dB Dynamic Range – THD+N < 0.1% (0–40 kHz) – 20-Hz–40-kHz, Flat Noise Floor for 32KHz 192KHz – Flexible Automute Logic With Programmable Threshold and Duration for Noise-Free Operation – Power-Supply Volume Control (PSVC) in HighPerformance Applications PLL_FLTP • 1 – Adjustable Modulation Limit PLL_FLTM 1 Features 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TAS5548 SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 7 1 1 1 2 3 6 Absolute Maximum Ratings ..................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Dynamic Performance ............................................. 7 SRC Performance ..................................................... 7 Timing I2C Serial Control Port Operation.................. 8 Reset Timing (RESET) ............................................. 8 Power-Down (PDN) Timing..................................... 8 Back-End Error (BKND_ERR) ............................... 8 Mute Timing (MUTE).............................................. 9 Headphone Select (HP_SEL) ................................ 9 Switching Characteristics - Clock Signals............... 9 Switching Characteristics - Serial Audio Port ....... 9 Volume Control .................................................... 10 Typical Characteristics .......................................... 13 Detailed Description ............................................ 14 7.1 7.2 7.3 7.4 7.5 7.6 8 14 14 16 25 48 53 Application and Implementation ........................ 95 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... Application Information............................................ 95 Typical Applications ................................................ 95 Do’s and Don’ts..................................................... 102 Initialization Set Up ............................................... 102 Power Supply Recommendations.................... 103 9.1 Power Supply ........................................................ 103 9.2 Energy Manager.................................................... 103 9.3 Programming Energy Manager ............................. 104 10 Layout................................................................. 105 10.1 Layout Guidelines ............................................... 105 10.2 Layout Example .................................................. 106 11 Device and Documentation Support ............... 108 11.1 11.2 11.3 11.4 Documentation Support ...................................... Trademarks ......................................................... Electrostatic Discharge Caution .......................... Glossary .............................................................. 108 108 108 108 12 Mechanical, Packaging, and Orderable Information ......................................................... 108 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (November 2012) to Revision A Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 • Added the Thermal Information table ..................................................................................................................................... 6 • Updated Figure 23 ............................................................................................................................................................... 29 • Updated Figure 24................................................................................................................................................................ 30 • Updated Table 12 ................................................................................................................................................................. 46 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5548 TAS5548 www.ti.com SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 5 Pin Configuration and Functions TAS5548 DCA Package 56-Pin HTSSOP Top View PWM_HPM_L PWM_HPP_L PWM_HPM_R PWM_HPP_R AVSS PLL_FLTM PLL_FLTP VR_ANA AVDD ASEL_EMO2 XTALI XTALO DVSS2 DVDD2 EMO1 RESET HP_SEL PDN MUTE SDA SCL LRCLK SCLK SDIN1 SDIN2 SDIN2_1 (SDIN3) SDIN2_2 (SDIN4) VR_DIG 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 PWM_P_6 PWM_M_6 PWM_P_5 PWM_M_5 VR_PWM AVSS_PWM AVDD_PWM PWM_P_8 PWM_M_8 PWM_P_7 PWM_M_7 PWM_P_4 PWM_M_4 PWM_P_3 PWM_M_3 PWM_P_2 PWM_M_2 PWM_P_1 PWM_M_1 VALID DVSS1 DVDD1 BKND_ERR PSVC/MLCK TEST LRCLKO (LRCK#2) SCLKO (SCLK#2) SDOUT (SDIN5) Pin Functions PIN NAME ASEL_EMO2 NO. TYPE 5-V TOLERANT TERMINATION DESCRIPTION Pullup I2C Address Select. Address will 0X34/0X36 with the value of pin being "0' or "1" during de-assertion of reset. Can be programmed to be an output (as energy manager output for subwoofer) 10 DIO AVDD 9 P Analog supply (3.3 V) for PLL. AVDD_PWM 50 P 3.3-V analog power supply for PWM. This terminal can be connected to the same power source used to drive power terminal DVDD; but to achieve low PLL jitter, this terminal should be bypassed to AVSS_PWM with a 0.1-μF low-ESR capacitor. AVSS 5 P Analog ground AVSS_PWM 51 P Analog ground for PWM. Must have direct return Cu path to analog 3.3V supply for optimized performance. BKND_ERR 34 DI DVDD1 35 P 3.3-V digital power supply. (It is recommended that decoupling capacitors of 0.1 μF and 10 μF be mounted close to this pin). DVDD2 14 P 3.3-V digital power supply for PWM. (It is recommended that decoupling capacitors of 0.1 μF and 10 μF be mounted close to this pin). DVSS1 36 P Digital ground 1 DVSS2 13 P Digital ground 2 EMO1 15 DO Pullup Active-low. A back-end error sequence is generated by applying logic low to this terminal. The BKND_ERR results in no change to I2C parameters, with all Hbridge drive signals going to a hard-mute state (Non PWM Switching). Energy Manger Output interrupt - Asserted high when threshold is exceeded. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5548 3 TAS5548 SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 www.ti.com Pin Functions (continued) PIN NAME NO. TYPE 5-V TOLERANT TERMINATION DESCRIPTION DI 5V Pullup Headphone/speaker selector. When a logic low is applied, the headphone is selected (speakers are off). When a logic high is applied, speakers are selected (headphone is off). HP_SEL 17 LRCLK 22 DI 5V Pulldown Serial-audio data left/right clock (sampling-rate clock) LRCLKO / LRCKIN_2 31 DIO 5V Pulldown LRCLK for I2S OUT. Can also be used as LRCKIN_2 (I2S Input for SDIN2_x and SRC Bank 2) XTALI 11 DI 1.8 V MUTE 19 DI 5V Pullup XTALO 12 DO PDN 18 DI 5V Pullup PLL_FLTM 6 AIO PLL negative filter. PLL_FLTP 7 AIO PLL positive filter. PSVC/MCLKO 33 DO Power-supply volume control PWM output or MCKO for external ADC (SDIN5 Source) PWM_HPM_L 1 DO PWM left-channel headphone (differential –) PWM_HPM_R 3 DO PWM right-channel headphone (differential –) PWM_HPP_L 2 DO PWM left-channel headphone (differential +) PWM_HPP_R 4 DO PWM right-channel headphone (differential +) PWM_M_1 38 DO PWM 1 output (differential –) PWM_M_2 40 DO PWM 2 output (differential –) PWM_M_3 42 DO PWM 3 output (differential –) PWM_M_4 44 DO PWM 4 output (differential –) PWM_M_5 53 DO PWM 5 output (lineout L) (differential –) PWM_M_6 55 DO PWM 6 output (lineout R) (differential –) PWM_M_7 46 DO PWM 7 output (differential –) PWM_M_8 48 DO PWM 8 output (differential –) PWM_P_1 39 DO PWM 1 output (differential +) PWM_P_2 41 DO PWM 2 output (differential +) PWM_P_3 43 DO PWM 3 output (differential +) PWM_P_4 45 DO PWM 4 output (differential +) PWM_P_5 54 DO PWM 5 output (lineout L) (differential +) PWM_P_6 56 DO PWM 6 output (lineout R) (differential +) PWM_P_7 47 DO PWM 7 output (differential +) PWM_P_8 49 DO PWM 8 output (differential +) RESET 16 DI 5V SCL 21 DI 5V SCLK 23 DI 5V Pulldown Serial-audio data clock (shift clock) input SCLKO / SCLKIN_2 30 DIO 5V Pulldown Serial data clock out. I2S bit clock out. Can also be used as SCLKIN_2 (I2S Input for SDIN2_x and SRC Bank 2) SDA 20 DIO 5V SDIN1 24 DI 5V Pulldown Serial-audio data bank 1 input 1 is one of the serial-data input ports and goes into the 1st SRC Bank. Four discrete (stereo) data formats and is capable of inputting data at 64 fS. SDIN2 25 DI 5V Pulldown Serial-audio data bank 1 input 2 is one of the serial-data input ports and goes into the 1st SRC Bank. Four discrete (stereo) data formats and is capable of inputting data at 64 fS. 4 XTAL input. Connect to external 12.288 MHz XTAL Soft mute of outputs, active-low (muted signal = a logic low, normal operation = a logic high). The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume. XTAL input. Connect to external 12.288 MHz XTAL Pullup Power down, active-low. PDN powers down all logic and stops all clocks whenever a logic low is applied. The I2C parameters are preserved through a power-down cycle, as long as RESET is not active. System reset input, active-low. A system reset is generated by applying a logic low to this terminal. RESET is an asynchronous control signal that restores the TAS5548 to its default conditions, sets the valid output low, and places the PWM in the hard-mute state (Non PWM Switching). Master volume is immediately set to full attenuation. On the release of RESET, if PDN is high, the system performs a 4- to 5-ms device initialization and sets the volume at mute. I2C serial-control clock input/output I2C serial-control data-interface input/output Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5548 TAS5548 www.ti.com SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 Pin Functions (continued) PIN NAME NO. TYPE 5-V TOLERANT TERMINATION DESCRIPTION SDIN2-1 26 DI 5V Pulldown Serial-audio data bank 2 input 1 is one of the serial-data input ports and goes into the 2nd SRC Bank. Four discrete (stereo) data formats and is capable of inputting data at 64 fS. SDIN2-2 27 DI 5V Pulldown Serial-audio data bank 2 input 2 is one of the serial-data input ports and goes into the 2nd SRC Bank. Four discrete (stereo) data formats and is capable of inputting data at 64 fS. SDOUT / SDIN5 29 TEST 32 DI Test mode active high. In normal mode tie this to digital ground. VALID 37 DO Output indicating validity of PWM outputs, active-high VR_DIG 28 P Voltage reference for 1.8-V digital core supply. A pinout of the internally regulated 1.8-V power used by digital core logic. A 4.7-μF low-ESR capacitor should be connected between this terminal and DVSS. This terminal must not be used to power external devices. VR_PWM 52 P Voltage reference for 1.8-V digital PLL supply. A pinout of the internally regulated 1.8-V power used by digital PLL logic. A 0.1-μF low-ESR capacitor should be connected between this terminal and DVSS_CORE. This terminal must not be used to power external devices. VR_ANA 8 P Voltage reference for 1.8-V PLL analog supply. A pinout of the internally regulated 1.8-V power used by PLL logic. A 0.1-µF low-ESR capacitor should be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices. I2S data out or SDIN5 (must be sync'd to post SRC rate). Usually used for Microphone ADC Input Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5548 5 TAS5548 SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) MIN MAX UNIT Supply voltage, DVDD1 and DVDD2 –0.3 3.9 V Supply voltage, AVDD and AVDD_PWM –0.3 3.9 V 3.3-V digital input –0.5 DVDD + 0.5 V 5-V tolerant (2) digital input –0.5 6 Input voltage IIK Input clamp current (VI < 0 or VI > 1.8 V IOK Output clamp current (VO < 0 or VO > 1.8 V) TSTG Storage temperature range (1) (2) –65 ±20 μA ±20 μA 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5-V tolerant signals are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±250 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over 0°C to 85°C MIN NOM MAX Digital supply voltage, DVDD1 and DVDD2 3 3.3 3.6 V Analog supply voltage, AVDD and AVDD_PWM 3 3.3 3.6 V 3.3 V VIH High-level input voltage 2 5-V tolerant 2 1.8-V LVCMOS (XTL_IN) V 1.26 3.3 V VIL Low-level input voltage UNIT 0.8 5-V tolerant 0.8 1.8-V (XTL_IN) V 0.54 TA Operating ambient-air temperature 0 TJ Operating junction temperature 0 25 85 °C 105 °C 6.4 Thermal Information TAS5548 THERMAL METRIC (1) DCA (HTSSOP) UNIT 56 PINS RθJA Junction-to-ambient thermal resistance 26.1 RθJCtop Junction-to-case (top) thermal resistance 13.0 RθJB Junction-to-board thermal resistance 8.0 ψJT Junction-to-top characterization parameter 0.4 ψJB Junction-to-board characterization parameter 7.9 RθJCbot Junction-to-case (bottom) thermal resistance 0.4 (1) 6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5548 TAS5548 www.ti.com SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 6.5 Electrical Characteristics At recommended operating conditions - 25 °C Operating Temp, 3.3V Power Supplies with 48kHz input data unless otherwise specified PARAMETER VOH High-level output voltage VOL Low-level output voltage IOZ High-impedance output current IIL Low-level input current IIH High-level input current TEST CONDITIONS MAX 1.8-V LVCMOS (XTL_OUT) IOH = –0.55 mA 3.3-V TTL and 5-V tolerant IOL = 4 mA 0.5 1.8-V LVCMOS (XTL_OUT) IOL = 0.75 mA 0.5 2.4 ±20 3.3-V TTL VI = VIL ±1 1.8-V LVCMOS (XTL_IN) VI = VIL ±1 5-V tolerant (1) VI = 0 V, DVDD = 3 V ±1 3.3-V TTL VI = VIH ±1 1.8-V LVCMOS (XTL_IN) VI = VIH ±1 5-V tolerant (1) VI = 5.5 V, DVDD = 3 V ±1 Input fS = 48 kHz Input supply current UNIT V 1.44 3.3-V TTL Analog supply voltage, AVDD (1) TYP IOH = –4 mA Digital supply voltage, DVDD IDD MIN 3.3-V TTL and 5-V tolerant V μA μA μA 220 Power down 9 Input fS = 48 kHz 8 Power down 8 mA 5-V tolerant signals are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL. 6.6 Dynamic Performance At recommended operating conditions at (25°C, 3.3V Power Supplies with 48kHz input data) unless otherwise noted. PARAMETER TEST CONDITIONS MIN Dynamic range TAS5548 A-weighted (Test Range: 20Hz to 20kHz. fS = 96 kHz). Total harmonic distortion TAS5548 output (1kHz at -1dBFS) Frequency response NOM MAX 105 UNIT dB 0.01% 32-kHz to 96-kHz sample rates (Test Range 20Hz 20kHz) ±0.1 176.4, 192-kHz sample rates (Test Range 20Hz 20kHz) ±0.2 dB 6.7 SRC Performance ATTRIBUTE VALUE SRC Latency 102.53125/FSin + 36.46875/FSout THD+N at 1kHz Pass Band Ripple (worst case) ±0.05dB SRC Channel Gain