TAS5601DCAR

TAS5601 www.ti.com....................................................................................................................................... SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008 20W STEREO (BTL) DIGITAL AMPLIFIER POWER STAGE • FEATURES 1 • Supports Multiple Output Configurations – 2×20-W into a 8-Ω BTL Load at 18 V – 4×10-W into a 4-Ω SE Load at 18 V – 2×10W (SE) + 1×20W (BTL) at 18 V • Thermally Enhanced Package – DCA (56-pin HTTSOP) • Wide Voltage Range: 10V–26V – No Separate Supply Required for Gate Drive • Efficient Class-D Operation Eliminates Need for Heat Sinks • Closed Loop Power Stage Architecture – Improved PSRR Reduces Power Supply Performance Requirements – High Damping Factor Provides for Tighter, More Accurate Sound With Improved Bass Response – Constant Output Power Over Variation in Supply Voltage • Differential Inputs 2 Integrated Self-Protection Circuits Including Overvoltage, Undervoltage, Overtemperature, and Short Circuit With Error Reporting APPLICATIONS • Flat-Panel, Rear-Projection, and CRT TV DESCRIPTION The TAS5601 is a 20-W (per channel) efficient, stereo digital amplifier power stage for driving 4 single-ended speakers, 2 bridge-tied speakers, or combination of single and bridge-tied loads. The TAS5601 can drive a speaker with an impedance as low as 4Ω. The high efficiency, >90% into 8-Ω loads, of the TAS5601 eliminates the need for an external heat sink. A simple interface to a digital audio PWM processor is shown below. The TAS5601 is fully protected against faults with short-circuit protection and thermal protection as well as overvoltage and undervoltage protection. Faults are reported back to the processor to prevent devices from being damaged during overload conditions. SIMPLIFIED APPLICATION CIRCUIT 3 - 4.2 V Digital PWM Processor 10 - 26 V DVDD DGND I2S TAS5602 DVDD DGND OUTA_P PWM_AP OUTA_N PWM_AN OUTB_P PWM_BP OUTB_N PVCC AVCC BSA OUTA OUTB LC Filter PWM_BN BSB Control Inputs OUTC_P PWM_CP OUTC_N PWM_CN OUTD_P PWM_DP OUTD_N PWM_DN BSC OUTC OUTD LC Filter BSD VCLAMP_AB VALID ERROR GPIO RESET VCLAMP_CD FAULT BYPASS THERM_WARN AGND SE/BLT PGND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TAS5601 SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008....................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PINOUT DCA PACKAGE (TOP VIEW) PGNDA PGNDA PGNDA PVCCA PVCCA PVCCA NC DVDD DGND PWM_AP PWM_AN PWM_BP PWM_BN PWM_CP PWM_CN PWM_DP PWM_DN RESET FAULT SE/BTL THERM_WARN NC PVCCD PVCCD PVCCD PGNDD PGNDD PGNDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OUTA OUTA PGNDB PGNDB PGNDB OUTB OUTB PVCCB PVCCB BSB VCLAMP_AB BSA NC AVCC AGND BYPASS BSD VCLAMP_CD BSC PVCCC PVCCC OUTC OUTC PGNDC PGNDC PGNDC OUTD OUTD TERMINAL FUNCTIONS TERMINAL NO. 2 I/O DESCRIPTION NAME 40 BSD I/O 39 VCLAMP_CD – 38 BSC I/O 43 AVCC – 42 AGND Bootstrap I/O for channel D high-side FET Internally generated voltage supply for channel C and D bootstrap. Not to be used as a supply or connected to any component other than the decoupling capacitor. Bootstrap I/O for channel C high-side FET Analog power supply Analog ground 8 DVDD I Digital supply (3V–4.2V). Supply for PWM input signal conditioning, FAULT and RST I/O buffers 9 DGND I Ground reference input for PWM and digital inputs 10 PWM_AP I Positive audio signal PWM input for channel A (Must be the complement of PWM_AN) 11 PWM_AN – Negative audio signal PWM input for channel A (Must be the complement of PWM_AP) 12 PWM_BP I Positive audio signal PWM input for channel B (Must be the complement of PWM_BN) 13 PWM_BN – Negative audio signal PWM input for channel B (Must be the complement of PWM_BP) 14 PWM_CP I Positive audio signal PWM input for channel C (Must be the complement of PWM_CN) 15 PWM_CN – Negative audio signal PWM input for channel C (Must be the complement of PWM_CP) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5601 TAS5601 www.ti.com....................................................................................................................................... SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NO. NAME 16 PWM_DP I Positive audio signal PWM input for channel D (Must be the complement of PWM_DN) 17 PWM_DN – Negative audio signal PWM input for channel D (Must be the complement of PWM_DP) 18 RESET I Enable/Disable pin RESET = High, normal operation RESET = Low, held in reset mode 19 FAULT O Short circuit fault FAULT = High, normal operation FAULT = Low, short circuit at output detected. FAULT will latch if short circuit detected and will be reset if the RESET pin is pulled low or the VCC power supplies are turned off. Thermal fault will not be reported by the FAULT pin. 20 SE/BTL I Single-ended or Bridge-tied output select terminal. If any output is configured as a single-ended load, this pin should be connected to DVDD. For 2-channel, BTL operation, connect to GND. 21 THERM_WARN O Thermal warning output flag. THERM_WARN = HIGH, normal operation. THERM_WARN = LOW, die temperature has reached 125 deg. C. Automatically resets when temperature falls back to normal range. TTL compatible push-pull output. 41 BYPASS O VCC/8 reference for analog cells 47 BSB I/O Bootstrap I/O for channel B high-side FET 46 VCLAMP_AB – 45 BSA I/O Bootstrap I/O for channel A high-side FET Internally generated voltage supply for channel A and B bootstrap. Not to be used as a supply or connected to any component other than the decoupling capacitor. 4–6 PVCCA – Positive power supply for channel A output 55, 56 OUTA O Channel A 1/2 H-bridge output 1–3 PGNDA – Power ground reference for channel A output 48, 49 PVCCB – Positive power supply for channel B output 52–54 PGNDB – Power ground reference for channel B output 50, 51 OUTB O Channel B 1/2 H-bridge output 34, 35 OUTC O Channel C 1/2 H-bridge output 31–33 PGNDC – Power ground reference for channel C output 36, 37 PVCCC – Positive power supply for channel C output 26–28 PGNDD – Power ground reference for channel D output 29, 30 OUTD O Channel D 1/2 H-bridge output 23–25 PVCCD – Positive power supply for channel D output 7, 22, 44 NC – No internal connection. – Thermal Pad Connect to PGNDx Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5601 3 TAS5601 SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008....................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply Voltage Input Voltage VALUE UNIT DVDD –0.3 to 5 V AVCC, PVCC –0.3 to 30 –0.3 to DVDD + 0.3 V Operating free-air temperature, TA RESET, SE/BTL, PWM_xP, PWM_xN –40 to 85 °C Operating junction temperature range, TJ –40 to 150 °C Storage temperature range, Tstg –65 to 150 °C 260 °C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C DCA (56 pin HTSSOP) 5.5 W 44 mW/°C 3.52 W 2.86 W RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN Supply voltage, VCC 10 26 PVCCx, AVCC (output is fully protected from shorts with no inductance between short and terminal) 10 20 DVDD 3 High-level input voltage, VIH PWM_xx, RESET, SE/ BTL 2 Low-level input voltage, VIL PWM_xx, RESET, SE/ BTL High-level output voltage, VOH FAULT, THERM_WARN, IOH = 10 µA Low-level output voltage, VOL FAULT, THERM_WARN, IOL = –10 µA PWM input frequency, fPWM PWM_xx Load Impedance RL(PBTL) UNIT V V V DVDD–0.4V V V DGND+0.4V 6.0 8 3.2 4 V 400 kHz 85 °C Ω 3.2 Lo(BTL) Output-filter Inductance Minimum output inductance under short-circuit condition Lo (PBTL) 4 4.2 0.8 –40 Output filter: L= 22 µH, C = 680 nF Lo (SE) 3.3 200 Operating free-air temperature, TA RL(SE) MAX PVCCx, AVCC (minimum series inductance of 5uH for full output short circuit protection) Digital reference voltage RL(BTL) NOM 10 µH 10 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5601 TAS5601 www.ti.com....................................................................................................................................... SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008 DC ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN | VOS | Class-D output offset voltage (measured with respect to VCC/2 for SE and output-to-output for BTL) 50% duty cycle PWM at PWM_xx inputs VBYPASS VCC/8 reference for analog section No load IIH High-level input current PWM_xx, RESET, SE/BTL, VI = DVDD, DVDD = 5 V IIL Low-level input current PWM_xx, RESET, SE/BTL, VI = 0, DVDD = 5 V IDVDD DVDD supply current RESET = 2.0 V, DVDD = 3.3 V, No load ICC Quiescent supply current RESET = 2.0 V No load, PVCC = 18 V ICC(RESET) Quiescent supply current in reset mode RDS(on) TON TOFF MAX 26 80 mV 5 µA 5 µA VCC/8 19 RESET = 0.8 V, No load, PVCC = 18 V Drain-source on-state resistance TYP VCC = 24 V, Io = 500 mA, TJ = 25°C UNIT V 11 22 µA 35 60 mA 64 216 µA High side 360 Low side 330 Total 690 Turn-on time (SE mode), voltage on BYPASS pin reaches final value of PVCC/8 C(BYPASS) = 1µF, RESET = 2 V, SE/BTL = 2V Turn-on time (BTL mode) , voltage on BYPASS pin reaches final value of PVCC/8 C(BYPASS) = 1µF, RESET = 2 V, SE/BTL = 0.8 V 30 Turn-off time (SE mode), voltage on BYPASS pin reaches final value of PVCC/8 C(BYPASS) = 1 µF, RESET = 0.8 V, SE/BTL = 2 V 500 Turn-off time (BTL mode) , voltage on BYPASS pin reaches final value of PVCC/8 C(BYPASS) = 1 µF, RESET= 0.8 V, SE/BTL = 0.8 V mΩ 500 ms ms 1 DC ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS | VOS | Class-D output offset voltage (measured with respect to VCC/2 for SE and output-to-output for BTL) 50% duty cycle PWM at PWM_xx inputs VBYPASS VCC/8 reference for analog section No load IDVDD DVDD supply current RESET = 2.0 V, DVDD = 3.3 V, No load ICC Quiescent supply current RESET = 2.0 V, No load ICC(RESET) Quiescent supply current in reset mode RESET = 0.8 V, No load RDS(on) TON TOFF Drain-source on-state resistance VCC = 12 V, Io = 500 mA, TJ = 25°C MIN TYP MAX 26 80 mV 22 µA 28 51 mA 64 216 µA VCC/8 11 14 High side 360 Low side 330 Total 690 Turn-on time (SE mode), voltage on BYPASS pin reaches final value of PVCC/8 C(BYPASS) = 1µF, RESET = 2 V, SE/BTL = 2V Turn-on time (BTL mode), voltage on BYPASS pin reaches final value of PVCC/8 C(BYPASS) = 1µF, RESET = 2 V, SE/BTL = 0.8 V 30 Turn-off time (SE mode), voltage on BYPASS pin reaches final value of PVCC/8 C(BYPASS) = 1 µF, RESET = 0.8 V, SE/BTL = 2 V 500 Turn-off time (BTL mode), voltage on BYPASS pin reaches final value of PVCC/8 C(BYPASS) = 1 µF, RESET= 0.8 V, SE/BTL = 0.8 V V Product Folder Link(s): TAS5601 mΩ 500 1 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated UNIT ms ms 5 TAS5601 SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008....................................................................................................................................... www.ti.com AC ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = 24 V, RL = 8Ω (unless otherwise noted) PARAMETER KSVR PO THD+N Vn SNR TEST CONDITIONS Supply Ripple Rejection MIN 200 mVpp ripple at 20 Hz–20 kHz, BTL 50% duty cycle PWM at inputs Continuous output power TYP MAX –60 BTL – RL = 8Ω, THD+N = 7%, f = 1 kHz, VCC = 18 V 20 SE – RL = 4Ω, THD+N = 10%, f = 1 kHz, VCC = 24 V 19 UNIT dB W Total Harmonic Distortion + Noise (SE) VCC = 24 V, f = 1 kHz, Po = 10 W 0.08% Total Harmonic Distortion + Noise (BTL) Vcc = 18 V, Rl = 8Ω, f = 1 kHz, Po = 10 W (half-power) 0.04% Output Integrated Noise 20 Hz to 22 kHz, A-weighted filter, GD modulation Crosstalk Po = 1 W, f = 1 kHz Signal-to-noise ratio Max. Output at THD+N 1.9V). For shutdown and power-down, the PWM inputs should remain switching for the “turn-off” time specified in the DC Electrical Characteristics table. For SE mode, this is approximately 500ms. For BTL mode, the time is much faster, at 30ms. This ensures the best “pop” performance in the system. POWER SUPPLIES To allow simplified system design, the TAS5601 requires only a single supply (PVCC) for the the power blocks and a 3.3 V (DVDD) supply for PWM input blocks. In addition, the high-side gate drive is provided by built-in bootstrap circuits requiring only an external capacitor for each half-bridge. In order for the bootstrap circuit to function properly, it is necessary to connect a small ceramic capacitor from each bootstrap pin (BS_) to the corresponding output pin (OUT_). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate drive. DEVICE PROTECTION SYSTEM The TAS5601 contains a complete set of protection circuits carefully designed to make system design efficient as well as to protect the device against any kind of permanent failures due to short circuits, overload, overtemperature, and undervoltage. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5601 13 TAS5601 SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008....................................................................................................................................... www.ti.com Protection Mechanisms in the TAS5601 • • • • SCP (short-circuit protection, OCP) protects against shorts across the load, to GND, and to PVCC. OTP turns off the device if Tdie (typical) > 150°C. UVP turns off the device if PVCC (typical) < 8.4 V OVP turns off the device if PVCC (typical) > 27.5 V Single-Ended Output Capacitor, CO In single-ended (SE) applications, the dc blocking capacitor forms a high-pass filter with the speaker impedance. The frequency response rolls of with decreasing frequency at a rate of 20 dB/decade. The cutoff frequency is determined by fc = 1/2πCOZL Table 1 shows some common component values and the associated cutoff frequencies: Table 1. Common Filter Responses CSE – DC Blocking Capacitor (µF) Speaker Impedance (Ω) fc = 60 Hz (–3 dB) fc = 40 Hz (–3 dB) fc = 20 Hz (–3 dB) 4 680 1000 2200 8 330 470 1000 Output Filter and Frequency Response For the best frequency response, a flat-passband output filter (second-order Butterworth) may be used. The output filter components consist of the series inductor and capacitor to ground at the output pins. There are several possible configurations, depending on the speaker impedance and whether the output configuration is single-ended (SE) or bridge-tied load (BTL). Table 2 lists the recommended values for the filter components. It is important to use a high-quality capacitor in this application. A rating of at least X7R is required. Table 2. Recommended Filter Output Components Output Configuration Speaker Impedance (Ω) Filter Inductor (µH) Filter Capacitor (nF) 4 22 680 8 47 390 4 10 1500 8 22 680 Single Ended (SE) Bridge Tied Load (BTL) OUTA Lfilter OUTA Lfilter Cfilter Cfilter OUTB Lfilter Cfilter Figure 17. BTL Filter Configuration Figure 18. SE Filter Configuration Power-Supply Decoupling, CS The TAS5601 is a high-performance CMOS audio amplifier that requires adequate power-supply decoupling to 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5601 TAS5601 www.ti.com....................................................................................................................................... SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008 ensure that the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power-supply leads. For higher-frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF to 1 µF, placed as close as possible to the device VCC lead works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µF or greater placed near the audio power amplifier is recommended. The 220-µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220-µF or larger capacitor should be placed on each PVCC terminal. A 10-µF capacitor on the AVCC terminal is adequate. These capacitors must be properly derated for voltage and ripple-current rating to ensure reliability. BSN and BSP Capacitors The half H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. The bootstrap capacitors connected between the BSx pins and their corresponding outputs function as a floating power supply for the high-side N-channel power MOSFET gate-drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. VCLAMP Capacitor To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, one internal regulator clamps the gate voltage. One 1-µF capacitor must be connected from each VCLAMP (terminal) to ground and must be rated for at least 16 V. The voltages at the VCLAMP terminal may vary with VCC and may not be used for powering any other circuitry. VBYP Capacitor Selection The scaled supply reference (BYPASS) nominally provides an AVCC/8 internal bias for the preamplifier stages. The external capacitor for this reference (CBYP) is a critical component and serves several important functions. During start-up or recovery from shutdown mode, CBYP determines the rate at which the amplifier starts. The start up time is proportional to 0.5 s per microfarad in single-ended mode (SE/BTL = DVDD). Thus, the recommended 1-µF capacitor results in a start-up time of approximately 500 ms (SE/BTL = DVDD). The second function is to reduce noise produced by the power supply caused by coupling with the output drive signal. This noise could result in degraded power-supply rejection and THD+N. The circuit is designed for a CBYP value of 1 µF for best pop performance. The input capacitors should have the same value. A ceramic or tantalum low-ESR capacitor is recommended. RESET OPERATION The TAS5601 employs a RESET mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The RESET input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling RESET low causes the outputs to amp to GND and the amplifier to enter a low-current state. Never leave RESET unconnected, because amplifier operation would be unpredictable. For the best power-up pop performance, place the amplifier in the RESET mode prior to applying the power-supply voltage. USING LOW-ESR CAPACITORS Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5601 15 TAS5601 SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008....................................................................................................................................... www.ti.com SHORT-CIRCUIT PROTECTION The TAS5601 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts and output-to-GND shorts after the filter and output capacitor (at the speaker terminal.) Directly at the device terminals, the protection circuitry prevents damage to device during output-to-output, output-to-ground, and output-to-supply. When a short circuit is detected on the outputs, the part immediately disables the output drive. This is latched fault and is cleared by cycling the RESET pin. Normal operation is restored when the fault is removed. The FAULT will transition low when a short is detected. The FAULT pin will be cleared after RESET is cycled. THERMAL PROTECTION Thermal protection on the TAS5601 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 20°C. The device begins normal operation at this point with no external system interaction. Thermal protection fault is NOT reported on the FAULT terminal. A THERM_WARN terminal can be used to monitor when the internal device temperature reaches 125°C. The terminal will transition low at this point and transition back high after the device cools approximately 20°C. It is not necessary to cycle RESET to clear this warning flag. PRINTED-CIRCUIT BOARD (PCB) LAYOUT Because the TAS5601 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit board (PCB) should be optimized according to the following guidelines for the best possible performance. • Decoupling capacitors—The high-frequency 0.1-µF decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. The BYPASS capacitor and VCLAMP_XX capacitors should also be placed as close to the device as possible. Large (220-µF or greater) bulk power-supply decoupling capacitors should be placed near the TAS5601 on the PVCCx terminals. For single-ended operation, a 220 µF capacitor should be placed on each PVCC pin. For Bridge-tied operation, a single 220 µF, capacitor can be shared between A and B or C and D. • Grounding—The AVCC decoupling capacitor and BYPASS capacitor should each be grounded to analog ground (AGND). The PVCCx decoupling capacitors and VCLAMP_xx capacitors should each be grounded to power ground (PGND). Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TAS5601. • Output filter—The reconstruction LC filter should be placed as close to the output terminals as possible for the best EMI performance. The capacitors should be grounded to power ground. • Thermal pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land are described in the mechanical section at the back of the data sheet. See TI Technical Briefs SLMA002 and SLOA120 for more information about using the thermal pad. For recommended PCB footprints, see figures at the end of this data sheet. For an example layout, see the TAS5601 Evaluation Module (TAS5601EVM) User Manual, (SLOU189). Both the EVM user manual and the thermal pad application note are available on the TI Web site at http://www.ti.com. BASIC MEASUREMENT SYSTEM This section focuses on methods that use the basic equipment listed below: • Audio analyzer or spectrum analyzer • Digital multimeter (DMM) • Oscilloscope • Twisted-pair wires • Signal generator • Power resistor(s) • Linear regulated power supply • Filter components 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5601 TAS5601 www.ti.com....................................................................................................................................... SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008 • EVM or other complete audio circuit Figure 19 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine wave is normally used as the input signal because it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the audio power amplifier (APA) output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two™ audio measurement system (AP-II) by Audio Precision™ includes the signal generator and analyzer in one package. The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the analyzer input impedance should be high. The output resistance, ROUT, of the APA is normally in the hundreds of milliohms and can be ignored for all but the power-related calculations. Figure 19(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal output. This amplifier circuit can be directly connected to the AP-II or other analyzer input. This is not true of the class-D amplifier system shown in Figure 19(b), which requires low-pass filters in most cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers. Power Supply Signal Generator APA RL Analyzer 20 Hz - 20 kHz (a) Basic Class-AB Power Supply Lfilt Signal Generator Class-D APA Cfilt RL Analyzer 20 Hz - 20 kHz (b) Traditional Class-D Figure 19. Audio Measurement Systems Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5601 17 TAS5601 SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008....................................................................................................................................... www.ti.com SE Input and SE Output (TAS5601 Stereo Configuration) The SE input and output configuration is used with class-AB amplifiers. A block diagram of a fully SE measurement circuit is shown in Figure 20. SE inputs normally have one input pin per channel. In some cases, two pins are present; one is the signal and the other is ground. SE outputs have one pin driving a load through an output ac-coupling capacitor and the other end of the load is tied to ground. SE inputs and outputs are considered to be unbalanced, meaning one end is tied to ground and the other to an amplifier input/output. The generator should have unbalanced outputs, and the signal should be referenced to the generator ground for best results. Unbalanced or balanced outputs can be used when floating, but they may create a ground loop that affects the measurement accuracy. The analyzer should have balanced inputs to cancel out any common-mode noise in the measurement. Evaluation Module Audio Power Amplifier Generator Analyzer CIN VGEN RIN RGEN Lfilt CL Cfilt Twisted-Pair Wire RL RANA CANA RANA CANA Twisted-Pair Wire Figure 20. SE Input—SE Output Measurement Circuit The following general rules should be followed when connecting to APAs with SE inputs and outputs: • Use an unbalanced source to supply the input signal. • Use an analyzer with balanced inputs. • Use twisted-pair wire for all connections. • Use shielding when the system environment is noisy. • Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see Table 3). 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5601 TAS5601 www.ti.com....................................................................................................................................... SLAS585A – FEBRUARY 2008 – REVISED SEPTEMBER 2008 DIFFERENTIAL INPUT AND BTL OUTPUT (TAS5601 Mono Configuration) Many of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied-load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180° out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output power to the load and eliminating a dc-blocking capacitor. A block diagram of the measurement circuit is shown in Figure 21. The differential input is a balanced input, meaning the positive (+) and negative (–) pins have the same impedance to ground. Similarly, the BTL output equates to a balanced output. Evaluation Module Audio Power Amplifier Generator Analyzer CIN RGEN VGEN Lfilt RIN Cfilt CIN RGEN RL Lfilt RIN Cfilt Twisted-Pair Wire RANA CANA RANA CANA Twisted-Pair Wire Figure 21. Differential Input, BTL Output Measurement Circuit The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in the circuit and providing the most accurate measurement. The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs: • Use a balanced source to supply the input signal. • Use an analyzer with balanced inputs. • Use twisted-pair wire for all connections. • Use shielding when the system environment is noisy. • Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see Table 3). Table 3 shows the recommended wire size for the power supply and load cables of the APA system. The real concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch (30.5-cm)-long wire with a 20-kHz sine-wave signal at 25°C. Table 3. Recommended Minimum Wire Size for Power Cables DC POWER LOSS (mW) AWG Size AC POWER LOSS (mW) POUT (W) RL(Ω) 10 4 18 22 16 40 18 42 2 4 18 22 3.2 8 3.7 8.5 1 8 22 28 2 8 2.1 8.1 < 0.75 8 22 28 1.5 6.1 1.6 6.2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5601 19 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TAS5601DCA ACTIVE HTSSOP DCA 56 35 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TAS5601 TAS5601DCAR ACTIVE HTSSOP DCA 56 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TAS5601 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of