TAS5622ADDVR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TAS5622A SLAS845A – MAY 2012 – REVISED MARCH 2015 TAS5622A 125-W Stereo and 250-W Stereo PurePath™ HD Digital-Input Class-D Power Stage 1 Features 3 Description • The TAS5622A device is a thermally enhanced version of the class-D power amplifier based on the TAS5612A using large MOSFETs for improved power efficiency and a novel gate drive scheme for reduced losses in idle and at low output signals leading to reduced heat sink size. 1 • • • • • • • • PurePath™ HD Integrated Feedback Provides: – 0.025% THD at 1 W into 4 Ω – > 65-dB PSRR (No Input Signal) – > 105 dB (A weighted) SNR Preclipping Output for Control of a Class-G Power Supply Reduced Heat Sink Size Due to Use of 40mΩ Output MOSFET With > 90% Efficiency at Full Output Power Output Power at 10%THD+N – 125-W and 4-Ω BTL Stereo Configuration – 250-W and 2-Ω PBTL Mono Configuration Output Power at 1%THD+N – 105-W and 4-Ω BTL Stereo Configuration – 210-W and 2-Ω PBTL Mono Configuration Click and Pop Free Start-up Error Reporting Self-Protected Design With UVP, Overtemperature, and Short-Circuit Protection EMI Compliant When Used With Recommended System Design 44-Pin HTSSOP (DDV) Package for Reduced Board Size The TAS5622A uses constant voltage gain. The internally matched gain resistors ensure a high Power Supply Rejection Ratio giving an output voltage only dependent on the audio input voltage and free from any power supply artifacts. The high integration of the TAS5622A makes the amplifier easy to use; and, using TI’s reference schematics and PCB layouts leads to fast design in time. The TAS5622A is available in the space-saving, surface-mount, 44-pin HTSSOP package. Device Information(1) PART NUMBER TAS5622A PACKAGE BODY SIZE (NOM) HTSSOP (44) 14.00 mm × 6.10 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • The unique preclipping output signal can be used to control a class-G power supply. This combined with the low idle loss and high power efficiency of the TAS5622A leads to industry-leading levels of efficiency ensuring a super “green” system. Blu-ray™ and DVD Receivers High-Power Sound Bars Powered Subwoofer and Active Speakers Mini Combo Systems Typical TAS5622A Application Block Diagram PurePath HDTM TAS 5630 TAS5622A TASxxxx DIGITAL AUDIO INPUT Digital Audio Processor +12V 18V-32.5V PurePath HDTM Class G Power Supply Ref design +3.3V REG. 105VAC → 240VAC 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TAS5622A SLAS845A – MAY 2012 – REVISED MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7 1 1 1 2 3 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Audio Specification Stereo (BTL).............................. 8 Audio Specification 4 Channels (SE) ........................ 8 Audio Specification Mono (PBTL) ............................ 9 Typical Characteristics ............................................ 10 Detailed Description ............................................ 13 7.1 Overview ................................................................. 13 7.2 Functional Block Diagrams ..................................... 14 7.3 Feature Description................................................. 16 7.4 Device Functional Modes........................................ 19 8 Application and Implementation ........................ 20 8.1 Application Information............................................ 20 8.2 Typical Applications ................................................ 21 9 Power Supply Recommendations...................... 30 9.1 Boot Strap Supply ................................................... 30 10 Layout................................................................... 30 10.1 Layout Guidelines ................................................. 30 10.2 Layout Example .................................................... 33 11 Device and Documentation Support ................. 35 11.1 Trademarks ........................................................... 35 11.2 Electrostatic Discharge Caution ............................ 35 11.3 Glossary ................................................................ 35 12 Mechanical, Packaging, and Orderable Information ........................................................... 35 4 Revision History Changes from Original (May 2012) to Revision A • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A TAS5622A www.ti.com SLAS845A – MAY 2012 – REVISED MARCH 2015 5 Pin Configuration and Functions DDV Package 44-Pin HTSSOP Top View GVDD_AB VDD OC_ADJ RESET INPUT_A INPUT_B C_START DVDD GND BST_A BST_B GND GND OUT_A OUT_A PVDD_AB PVDD_AB PVDD_AB OUT_B GND GND GND AVDD INPUT_C INPUT_D FAULT OTW CLIP M1 GND GND OUT_C PVDD_CD PVDD_CD PVDD_CD OUT_D OUT_D GND GND BST_C BST_D M2 M3 GVDD_CD Pin Functions PIN I/O/P (1) DESCRIPTION NAME NO. AVDD 13 P Internal voltage regulator, analog section BST_A 44 P Bootstrap pin, A-side BST_B 43 P Bootstrap pin, B-side BST_C 24 P Bootstrap pin, C-side BST_D 23 P Bootstrap pin, D-side CLIP 18 O Clipping warning; open drain; active low C_START 7 O Start-up ramp DVDD 8 P Internal voltage regulator, digital section FAULT 16 O Shutdown signal, open drain; active low 9, 10, 11, 12, 25, 26, 33, 34, 41, 42 P Ground GVDD_AB 1 P Gate-drive voltage supply; AB-side GVDD_CD 22 P Gate-drive voltage supply; CD-side INPUT_A 5 I PWM Input signal for half-bridge A INPUT_B 6 I PWM Input signal for half-bridge B INPUT_C 14 I PWM Input signal for half-bridge C INPUT_D 15 I PWM Input signal for half-bridge D M1 19 I Mode selection 1 (LSB) M2 20 I Mode selection 2 M3 21 I Mode selection 3 (MSB) OC_ADJ 3 O Over-Current threshold programming pin GND (1) I = Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A 3 TAS5622A SLAS845A – MAY 2012 – REVISED MARCH 2015 www.ti.com Pin Functions (continued) PIN NAME I/O/P (1) NO. OTW DESCRIPTION 17 O Over-temperature warning; open drain; active low OUT_A 39, 40 O Output, half-bridge A OUT_B 35 O Output, half-bridge B OUT_C 32 O Output, half-bridge C OUT_D 27, 28 O Output, half-bridge D PVDD_AB 36, 37, 38 P PVDD supply for half-bridge A and B PVDD_CD 29, 30, 31 P PVDD supply for half-bridge C and D RESET 4 I Device reset Input; active low VDD 2 P Input power supply PowerPAD™ – P Ground, connect to grounded heat sink Mode Selection Pins MODE PINS OUTPUT CONFIGURATION INPUT A 0 2N + 1 2 x BTL 1 1N + 1 (2) 2 x BTL 0 2N + 1 M2 M1 0 0 0 0 0 1 (1) (2) (3) 4 PWM INPUT (1) M3 1N + 1 (2) INPUT B INPUT C INPUT D MODE PWMa PWMb PWMa Unused PWMc PWMd AD mode PWMc Unused 2 x BTL PWMa AD mode PWMb PWMc PWMd BD mode 0 1 1 1 x BTL + 2 x SE PWMa Unused PWMc PWMd AD mode 1 0 0 2N + 1 1 x PBTL PWMa PWMb 0 0 AD mode 1 0 0 1N + 1 (2) 1 x PBTL PWMa Unused 0 1 AD mode 1 0 0 2N + 1 1 x PBTL PWMa PWMb 1 0 BD mode 1 0 1 1N + 1 4 x SE (3) PWMa PWMb PWMc PWMd AD mode The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode. Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals. The 4xSE mode can be used as 1xBTL + 2xSE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD for improved DC offset accuracy Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A TAS5622A www.ti.com SLAS845A – MAY 2012 – REVISED MARCH 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range unless otherwise noted (1) VDD to GND, GVDD_X (2) to GND PVDD_X (2) to GND (3) (3) , OUT_X to GND , BST_X to GVDD_X (2) (3) MIN MAX UNIT –0.3 13.2 V –0.3 50 V BST_X to GND (3) (4) –0.3 62.5 V DVDD to GND –0.3 4.2 V AVDD to GND –0.3 8.5 V OC_ADJ, M1, M2, M3, C_START, INPUT_X to GND –0.3 4.2 V RESET, FAULT, OTW, CLIP, to GND –0.3 4.2 V 9 mA 0 150 °C 260 °C 150 °C Maximum continuous sink current (FAULT, OTW, CLIP) Maximum operating junction temperature, TJ Lead temperature Storage temperature, Tstg (1) (2) (3) (4) –40 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. GVDD_X and PVDD_X represents a full bridge gate drive or power supply. GVDD_X is GVDD_AB or GVDD_CD, PVDD_X is PVDD_AB or PVDD_CD These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions. Maximum BST_X to GND voltage is the sum of maximum PVDD to GND and GVDD to GND voltages minus a diode drop. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN NOM MAX UNIT PVDD_X Full-bridge supply DC supply voltage 12 32.5 34 V GVDD_X Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V 2.5 4.0 1.5 3.0 1.5 2.0 BTL RL Load impedance SE PBTL Output filter: L = 10 uH, 1 µF. Output AD modulation, switching frequency > 350 kHz. Minimum inductance at overcurrent limit, including inductor tolerance, temperature and possible inductor saturation Ω μH LOUTPUT Output filter inductance 5 FPWM PWM frame rate 352 384 CPVDD PVDD close decoupling capacitors 0.44 1 BTL and PBTL configuration C_START Start-up ramp capacitor ROC Overcurrent programming resistor Resistor tolerance = 5% 24 ROC_LATCHED Overcurrent programming resistor Resistor tolerance = 5% 47 TJ Junction temperature SE and 1xBTL+2xSE configuration 0 500 μF 100 nF 1 μF 62 33 kΩ 68 kΩ 125 °C Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A kHz 5 TAS5622A SLAS845A – MAY 2012 – REVISED MARCH 2015 www.ti.com 6.4 Thermal Information TAS5622A THERMAL METRIC (1) DDV (HTSSOP) UNIT 44 PINS RθJH Junction-to-heat sink thermal resistance 1.9 RθJC(top) Junction-to-case (top) thermal resistance 0.6 RθJB Junction-to-board thermal resistance 1.7 ψJT Junction-to-top characterization parameter 0.6 ψJB Junction-to-board characterization parameter 1.7 (1) 6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A TAS5622A www.ti.com SLAS845A – MAY 2012 – REVISED MARCH 2015 6.5 Electrical Characteristics PVDD_X = 32.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX 3.0 3.3 3.6 UNIT INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION DVDD Voltage regulator, only used as a reference node VDD = 12 V AVDD Voltage regulator, only used as a reference node VDD = 12 V 7.8 IVDD VDD supply current Operating, 50% duty cycle 20 Idle, reset mode 20 IGVDD_X Gate-supply current per full-bridge 50% duty cycle 12 IPVDD_X Full-bridge idle current Reset mode V mA mA 3 50% duty cycle without load 12 RESET low 1.7 VDD and GVDD_X at 0V V mA 0.35 OUTPUT-STAGE MOSFETs RDS(on), LS Drain-to-source resistance, low side (LS) RDS(on), HS Drain-to-source resistance, high side (HS) TJ = 25°C, excludes metallization resistance, GVDD = 12 V 40 mΩ 40 mΩ 8.5 V 0.7 V 8.5 V 0.7 V 8.5 V I/O PROTECTION Vuvp,GVDD Vuvp,GVDD, hyst (1) Vuvp,VDD Vuvp,VDD, hyst (1) Vuvp,PVDD Vuvp,PVDD,hyst (1) OTW (1) OTWhyst Undervoltage protection limit, GVDD_X Undervoltage protection limit, VDD Undervoltage protection limit, PVDD_X 0.7 Overtemperature warning (1) 115 Temperature drop needed below OTW temperature for OTW to be inactive after OTW event. 125 V 135 25 °C °C OTE (1) Overtemperature error OTE-OTWdifferential (1) OTE-OTW differential 30 °C A device reset is needed to clear FAULT after an OTE event 25 °C OTEHYST (1) OLPC 145 155 165 °C Overload protection counter fPWM = 384 kHz 2.6 ms IOC Overcurrent limit protection Resistor – programmable, nominal peak current in 1Ω load, ROC = 24 kΩ 15 A IOC_LATCHED Overcurrent limit protection, latched Resistor – programmable, nominal peak current in 1Ω load, ROC = 62 kΩ 15 A IOCT Overcurrent response time Time from application of short condition to Hi-Z of affected half bridge 150 ns IPD Internal pulldown resistor at output of each half bridge Connected when RESET is active to provide bootstrap charge. Not used in SE mode. 3 mA STATIC DIGITAL SPECIFICATIONS VIH High level input voltage VIL Low level input voltage LEAKAGE Input leakage current INPUT_X, M1, M2, M3, RESET 1.9 V 0.8 V 100 μA 33 kΩ OTW / SHUTDOWN (FAULT) RINT_PU Internal pullup resistance, OTW, CLIP, FAULT to DVDD VOH High level output voltage Internal pullup resistor VOL Low level output voltage IO = 4mA FANOUT Device fanout OTW, FAULT, CLIP No external pullup (1) 20 3 26 3.3 3.6 V 200 500 mV 30 devices Specified by design. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A 7 TAS5622A SLAS845A – MAY 2012 – REVISED MARCH 2015 www.ti.com 6.6 Audio Specification Stereo (BTL) Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and a TAS5622A power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C,Output Filter: LDEM = 10 μH, CDEM = 1 µF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX RL = 3 Ω, 10% THD+N 150 RL = 4 Ω, 10% THD+N 125 RL = 3 Ω, 1% THD+N 140 UNIT PO Power output per channel THD+N Total harmonic distortion + noise 1 W, 1 kHz signal Vn Output integrated noise A-weighted, AES17 measuring filter VOS Output offset voltage No signal SNR Signal-to-noise ratio (1) A-weighted, AES17 measuring filter 105 dB DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD+N) 105 dB Pidle Power dissipation due to Idle losses (IPVDD_X) PO = 0, channels switching (2) 0.8 W RL = 4 Ω, 1% THD+N (1) (2) W 105 0.025% μV 180 10 20 mV SNR is calculated relative to 1% THD-N output level. Actual system idle losses also are affected by core losses of output inductors. 6.7 Audio Specification 4 Channels (SE) Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and a TAS5622A power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C,Output Filter: LDEM = 10 μH, CDEM = 1 µF, CDCB = 470 µF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX RL = 3 Ω, 10% THD+N 43 RL = 3 Ω, 1% THD+N 35 UNIT PO Power output per channel THD+N Total harmonic distortion + noise 1 W, 1 kHz signal Vn Output integrated noise A-weighted, AES17 measuring filter 180 μV A-weighted, AES17 measuring filter 102 dB A-weighted, –60 dBFS (rel 1% THD+N) 102 dB 0.8 W (1) SNR Signal-to-noise ratio DNR Dynamic range Pidle Power dissipation due to Idle losses (IPVDD_X) (1) (2) 8 PO = 0, channels switching W 0.025% (2) SNR is calculated relative to 1% THD-N output level. Actual system idle losses also are affected by core losses of output inductors. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A TAS5622A www.ti.com SLAS845A – MAY 2012 – REVISED MARCH 2015 6.8 Audio Specification Mono (PBTL) Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and a TAS5622A power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 μF, unless otherwise noted. PARAMETER PO Power output per channel TEST CONDITIONS MIN TYP MAX RL = 1.5 Ω, 10%, THD+N 330 RL = 2 Ω, 10% THD+N 250 RL = 4 Ω, 10% THD+N 130 RL = 1.5 Ω, 1% THD+N 270 RL = 2 Ω, 1% THD+N 210 RL = 4 Ω, 1% THD+N 105 UNIT W THD+N Total harmonic distortion + noise 1 W, 1 kHz signal Vn Output integrated noise A-weighted, AES17 measuring filter VOS Output offset voltage No signal SNR Signal to noise ratio (1) A-weighted, AES17 measuring filter 105 dB DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD) 105 dB Pidle Power dissipation due to idle losses (IPVDD_X) 0.8 W (1) (2) PO = 0, All channels switching 0.025% 10 (2) μV 180 20 mV SNR is calculated relative to 1% THD-N output level. Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A 9 TAS5622A SLAS845A – MAY 2012 – REVISED MARCH 2015 www.ti.com 6.9 Typical Characteristics 6.9.1 Typical Characteristics, BTL Configuration Measurement conditions are: 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted. 220 3Ω 4Ω 8Ω 3Ω 4Ω 8Ω 200 180 160 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 0.1 140 120 100 80 60 40 0.01 TC = 75°C THD+N at 10% 20 TC = 75°C 0.005 0.02 0.1 1 10 0 100 200 PO − Output Power − W Figure 1. Total Harmonic + Noise vs Output Power, 1 kHz 15 20 25 PVDD − Supply Voltage − V 30 35 G003 Figure 2. Output Power vs Supply Voltage vs Distortion + Noise = 10% 180 10 1W 10 W 80 W 3Ω 4Ω 8Ω 160 140 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 G001 0.1 0.01 120 100 80 60 40 20 TC = 75°C 0.001 20 100 1k Frequency − Hz 10k TC = 75°C 0 20k 10 15 20 25 PVDD − Supply Voltage − V 30 35 G002 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 G004 Figure 4. Output Power vs Supply Voltage, vs Distortion + Noise = 1% 45 35 30 25 20 15 10 3Ω 4Ω 8Ω 5 TC = 75°C TC = 75°C 0 0 100 200 300 Total Output Power − W 400 Figure 5. System Efficiency vs Output Power 0 100 200 300 Total Output Power − W 400 G006 G005 10 3Ω 4Ω 8Ω 40 Power Loss − W Efficiency − % Figure 3. Total Harmonic Distortion + Noise vs Frequency, 4Ω Figure 6. System Power Loss vs Output Power Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A TAS5622A www.ti.com SLAS845A – MAY 2012 – REVISED MARCH 2015 Typical Characteristics, BTL Configuration (continued) 200 180 140 Noise Amplitude − dB PO − Output Power − W 160 120 100 80 60 40 3Ω 4Ω 8Ω 20 0 −10 0 10 THD+N at 10% 20 30 40 50 60 70 80 90 100 110 TC − Case Temperature − °C 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 TC = 75°C VREF = 20.5 V Sample Rate = 48kHz FFT Size = 16384 0 2k 4k 6k 4Ω 8k 10k 12k 14k 16k 18k 20k 22k 24k f − Frequency − Hz G007 G008 Figure 7. Output Power vs Temperature Figure 8. Noise Amplitude vs Frequency 6.9.2 Typical Characteristics, SE Configuration Measurement conditions are: 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, CDCB = 470 µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted. 80 2Ω 3Ω 4Ω 2Ω 3Ω 4Ω 60 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 0.1 40 20 TC = 75°C THD+N at 10% 0.01 TC = 75°C 0.005 0.02 0.1 1 10 PO − Output Power − W 0 100 G009 Figure 9. Total Harmonic Distortion + Noise vs Output Power 10 15 20 25 PVDD − Supply Voltage − V 30 35 G010 Figure 10. Output Power vs Supply Voltage Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A 11 TAS5622A SLAS845A – MAY 2012 – REVISED MARCH 2015 www.ti.com 6.9.3 Typical Characteristics, PBTL Configuration Measurement conditions are: 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted. 340 2Ω 3Ω 4Ω 300 280 260 1 0.1 240 220 200 180 160 140 120 100 80 60 40 0.01 0.005 0.02 0.1 1 10 PO − Output Power − W 100 TC = 75°C THD+N at 10% 20 TC = 75°C 0 400 G011 Figure 11. Total Harmonic Distortion + Noise vs Output Power 12 2Ω 3Ω 4Ω 320 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 10 15 20 25 PVDD − Supply Voltage − V 30 35 G012 Figure 12. Output Power vs Supply Voltage Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A TAS5622A www.ti.com SLAS845A – MAY 2012 – REVISED MARCH 2015 7 Detailed Description 7.1 Overview TAS5622A is a PWM input, audio PWM (class-D) amplifier. The output of the TAS5622A can be configured for single-ended, BTL (Bridge-Tied Load) or parallel BTL (PBTL) output. It requires two rails for power supply, PVDD and 12 V (GVDD and VDD). The following block diagram shows typical connections for BTL outputs. Detailed schematic can be viewed in TAS5622A EVM User's Guide (SLAU376). Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A 13 TAS5622A SLAS845A – MAY 2012 – REVISED MARCH 2015 www.ti.com 7.2 Functional Block Diagrams Capacitors for External Filtering & Startup/Stop System microcontroller /AMP RESET C_START /CLIP *NOTE1 /OTW TASxxxx PWM Modulator /FAULT I2C /RESET VALID BST_A BST_B LeftChannel Output PWM_A INPUT_A PWM_B INPUT_B OUT_A Input H-Bridge 1 Output H-Bridge 1 OUT_B Bootstrap Capacitors nd 2 Order L-C Output Filter for each H-Bridge 2-CHANNEL H-BRIDGE BTL MODE nd PWM_C INPUT_C PWM_D INPUT_D PVDD 32.5V Output H-Bridge 2 OUT_D PVDD OC_ADJ DVDD AVDD VDD M3 2 Order L-C Output Filter for each H-Bridge BST_C GND M2 GVDD_AB, CD M1 Power Supply Decoupling SYSTEM Power Supplies GVDD, VDD, & VREG Power Supply Decoupling BST_D Bootstrap Capacitors Hardwire OverCurrent Limit GND GND 12V Input H-Bridge 2 GND Hardwire Mode Control OUT_C PVDD_AB, CD RightChannel Output GVDD (12V)/VDD (12V) VAC (1) Logic AND is inside or outside the microprocessor. Figure 13. Typical System Block Diagram 14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A TAS5622A www.ti.com SLAS845A – MAY 2012 – REVISED MARCH 2015 Functional Block Diagrams (continued) /CLIP /OTW /FAULT BST_X GVDD_X AVDD DVDD UVP /RESET PROTECTION & I/O LOGIC MODE1-3 AVDD AVDD VDD DVDD DVDD POWER-UP RESET TEMP SENSE CB3C OVERLOAD PROTECTION STARTUP CONTROL C_START BST_A PVDD_AB INPUT_A PWM RECEIVER ANALOG LOOP FILTER + - PWM & TIMING CONTROL GATE-DRIVE OUT_A GND GVDD_AB BST_B PVDD_AB INPUT_B PWM RECEIVER ANALOG LOOP FILTER + - PWM & TIMING CONTROL GATE-DRIVE OUT_B GND BST_C PVDD_CD INPUT_C PWM RECEIVER ANALOG LOOP FILTER + - PWM & TIMING CONTROL GATE-DRIVE OUT_C GND GVDD_CD BST_D PVDD_CD INPUT_D PWM RECEIVER ANALOG LOOP FILTER + - PWM & TIMING CONTROL GATE-DRIVE OUT_D GND Figure 14. Functional Block Diagram Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A 15 TAS5622A SLAS845A – MAY 2012 – REVISED MARCH 2015 www.ti.com 7.3 Feature Description 7.3.1 System Power-Up and Power-Down Sequence 7.3.1.1 Powering Up The TAS5622A does not require a power-up sequence. The outputs of the H-bridges remain in a highimpedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see Electrical Characteristics). Although not specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. 7.3.1.2 Powering Down The TAS5622A does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see Electrical Characteristics). Although not specifically required, it is a good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks. 7.3.2 Start-up and Shutdown Ramp Sequence The integrated start-up and stop sequence ensures a click and pop free startup and shutdown sequence of the amplifier. The start-up sequence uses a voltage ramp with a duration set by the CSTART capacitor. The sequence uses the input PWM signals to generate output PWM signals, hence input idle PWM should be present during both start-up and shut down ramping sequences. VDD, GVDD_X and PVDD_X power supplies must be turned on and with settled outputs before starting the start-up ramp by setting RESET high. During start-up and shutdown ramp the input PWM signals should be in muted condition with the PWM processor noise shaper activity turned off (50% duty cycle). The duration of the start-up and shutdown ramp is 100 ms + X ms, where X is the CSTART capacitor value in nF. It is recommended to use 100nF CSTART in BTL and PBTL mode and 1 µF in SE mode configuration. This results in ramp times of 200 ms and 1.1s respectively. The longer ramp time in SE configuration allows charge and discharge of the output AC coupling capacitor without audible artifacts. Ramp Start Ramp Start Ramp End Ramp End 3.3V /RESET 0V INPUT_X OUT_X INPUT_X IS SWITCHING (MUTE) NOISE SHAPER OFF (UNMUTED) INPUT_X IS SWITCHING (MUTE) NOISE SHAPER OFF OUT_X IS SWITCHING (MUTE) (UNMUTED) OUT_X IS SWITCHING (MUTE) 3.3V Hi-Z 0V PVDD_X Hi-Z 0V VI_CM DC_RAMP 0V 50% PVDD_X/2 0V tStartup Ramp tStartup Ramp INPUT_X IS SWITCHING (MUTE) NOISE SHAPER ON Figure 15. Start-up/Shutdown Ramp 16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5622A TAS5622A www.ti.com SLAS845A – MAY 2012 – REVISED MARCH 2015 Feature Description (continued) 7.3.3 Unused Output Channels If all available output channels are not used, it is recommended to disable switching of unused output nodes to reduce power consumption. Furthermore by disabling unused output channels the cost of unused output LC demodulation filters can be avoided. Disabling a channel is done by leave the bootstrap capacitor (BST) unstuffed and connecting the respective input to GND. The unused output pin(s) can be left floating. Please note that the PVDD decoupling capacitors still need to be mounted. Table 1. Unused Output Channels Operating Mode PWM Input 000 2N + 1 001 1N + 1 010 2N + 1 101 Output Configuration Unused Channel INPUT_A INPUT_B INPUT_C INPUT_D Unstuffed Component 2 x BTL AB CD GND PWMa GND PWMb PWMc GND PWMd GND BST_A & BST_B capacitor BST_C & BST_D capacitor A GND PWMb PWMc PWMd BST_A capacitor B PWMa GND PWMc PWMd BST_B capacitor C PWMa PWMb GND PWMd BST_C capacitor D PWMa PWMb PWMc GND BST_D capacitor 1N + 1 4 x SE 7.3.4 Device Protection System The TAS5622A contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5622A responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been removed, that is, the supply voltage has increased. The device will function on errors, as shown in the following table. Table 2. Device Protection BTL Mode PBTL Mode SE Mode Channel Fault Turns Off Channel Fault Turns Off Channel Fault Turns Off A A+B A A+B+C+D A A+B B C C+D D B B C C D D C+D Bootstrap UVP does not shutdown according to the table, it shuts down the respective high-side FET. 7.3.5 Pin-to-Pin Short Circuit Protection (PPSC) The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is shorted to GND or PVDD_X. For comparison, the OC protection system detects an overcurrent after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at start-up, that is, when VDD is supplied, consequently a short to either GND or PVDD_X after system start-up will not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the start-up sequence and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no shorts from OUT_X to GND, the second step tests that there are no shorts from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is 2.6ms) OC shutdown Channel FAULT Pin Latched Toggle RESET Hi-Z Latched OC (ROC >47k) OC shutdown Channel FAULT Pin Latched Toggle RESET Hi-Z Flip state, cycle by cycle at fs/2 Fault/Event PVDD_X UVP VDD UVP GVDD_X UVP AVDD UVP CBC (24k