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TAS5630B
SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
TAS5630B 300-W Stereo and 400-W Mono PurePath™ HD Analog-Input Power Stage
1 Features
3 Description
•
The TAS5630B device is a high-performance analoginput class-D amplifier with integrated closed-loop
feedback technology (known as PurePath HD
technology) with the ability to drive up to 300 W (1)
stereo into 4-Ω to 8-Ω speakers from a single 50-V
supply.
1
•
•
•
•
•
•
PurePath™ HD Enabled Integrated Feedback
Provides:
– Signal Bandwidth up to 80 kHz for HighFrequency Content From HD Sources
– Ultralow 0.03% THD at 1 W into 4 Ω
– Flat THD at All Frequencies for Natural Sound
– 80-dB PSRR (BTL, No Input Signal)
– > 100-dB (A-weighted) SNR
– Click- and Pop-Free Start-up
Multiple Configurations Possible on the Same
PCB With Stuffing Options:
– Mono Parallel Bridge-Tied Load (PBTL)
– Stereo Bridge-Tied Load (BTL)
– 2.1 Single-Ended Stereo Pair and BTL
Subwoofer
– Quad Single-Ended Outputs
Total Output Power at 10% THD+N
– 400 W in Mono PBTL Configuration
– 300 W per Channel in Stereo BTL
Configuration
– 145 W per Channel in Quad Single-Ended
Configuration
High-Efficiency Power Stage (> 88%) With 60-mΩ
Output MOSFETs
Two Thermally Enhanced Package Options:
– PHD (64-Pin QFP)
– DKD (44-Pin PSOP3)
Self-Protection Design (Including Undervoltage,
Overtemperature, Clipping, and Short-Circuit
Protection) With Error Reporting
EMI Compliant When Used With Recommended
System Design
PurePath HD technology enables traditional ABamplifier performance (< 0.03% THD) levels while
providing the power efficiency of traditional class-D
amplifiers.
Unlike traditional class-D amplifiers, the distortion
curve does not increase until the output levels move
into clipping.
PurePath HD technology enables lower idle losses,
making the device even more efficient. When coupled
with TI’s class-G power-supply reference design for
TAS563x, industry-leading levels of efficiency can be
achieved.
Device Information(1)
PART NUMBER
TAS5630B
Mini Combo System
AV Receivers
DVD Receivers
Active Speakers
BODY SIZE (NOM)
HSSOP (44)
15.90 mm × 11.00 mm
HTQFP (64)
14.00 mm × 14.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical TAS5630B Application Block Diagram
3 ´ OPA1632
♫♪
TM
ANALOG
AUDIO
INPUT
PurePath HD
TAS5630B
(2.1 Configuration)
♫♪
♫♪
±15 V
12 V
25 V–50 V
TM
PurePath HD
Class-G Power Supply
Ref. Design
2 Applications
•
•
•
•
PACKAGE
110 VAC ® 240 VAC
(1)
Achievable output power levels are dependent on the thermal
configuration of the target application. A high-performance
thermal interface material between the exposed package heat
slug and the heat sink should be used to achieve high output
power levels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5630B
SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Audio Characteristics (BTL) .................................... 10
Audio Specification (Single-Ended Output) ............ 10
Audio Specification (PBTL) .................................... 11
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28
11 Device and Documentation Support ................. 30
11.1 Trademarks ........................................................... 30
11.2 Electrostatic Discharge Caution ............................ 30
11.3 Glossary ................................................................ 30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
Changes from Revision C (September 2012) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed Thermal Information table data. .............................................................................................................................. 8
Changes from Revision B (November 2011) to Revision C
Page
•
Changed Analog comparator reference node, VI_CM Vlaues From: MIN = 1.5 TYP = 1.75 MAX = 1.9 To: MIN =
1.75 TYP = 2 MAX = 2.15 ...................................................................................................................................................... 8
•
Changed ANALOG INPUTS - VIN TYP value From 3.5 to 5 VPP............................................................................................ 8
•
Changed the VIH and VIL Test Conditions From: INPUT_X, M1, M2, M3, RESET To: M1, M2, M3, RESET ........................ 9
•
Deleted - RL = 2 Ω, 1% THD+N, unclipped output signal From PO in the Audio Specification (PBTL) table....................... 11
Changes from Revision A (November 2011) to Revision B
Page
•
Changed the RINT_PU parameters from /OTW1 to VREG, /OTW2 to VREG, /SD to VREG to /OTW, /OTW1, /OTW2,
/CLIP, READY, /SD to VRE.................................................................................................................................................... 9
•
Added text to the PHD Package section. ............................................................................................................................. 17
•
Added text to the DKD Package section .............................................................................................................................. 17
Changes from Original (November 2010) to Revision A
Page
•
Changed Title From: 600-W MONO To: 400-W MONO......................................................................................................... 1
•
Changed Feature From: 600 W per Channel in Mono PBTL Configuration To: 400 W per Channel in Mono PBTL
Configuration .......................................................................................................................................................................... 1
•
Changed the Pin One Location Package image .................................................................................................................... 5
•
Changed RL(PBTL) Load Impedance Min value From: 1.6 Ω To: 2.4 Ω, and Typ value From 2 To: 3 Ω ............................. 7
•
Added footnotes to the ROC table ......................................................................................................................................... 7
•
Added ROCP information to the ROC Table ............................................................................................................................ 8
2
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SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
•
Changed the IOC Typical Value From: 19 A To: 15 A............................................................................................................. 9
•
Deleted - RL = 2 Ω, 10%, THD+N, clipped input signal From PO in the Audio Specification (PBTL) table.......................... 11
•
Replaced the TYPICAL CHARACTERISTICS, PBTL CONFIGURATION graphs ............................................................... 12
•
Added section - Click and Pop in SE-Mode ......................................................................................................................... 18
•
Added section - PBTL Overload and Short Circuit ............................................................................................................... 18
•
Replaced the PACKAGE HEAT DISSIPATION RATINGS table with the THERMAL INFORMATION table....................... 18
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SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
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5 Pin Configuration and Functions
DKD Package
44 Pins HSSOP
Top View
AGND
VREG
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IOSD
OTW
READY
M1
M2
M3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44 pins PACKAGE
(TOP VIEW)
PSU_REF
VDD
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
GVDD_AB
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_CD
64-pins QFP package
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
OTW2
CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IOSD
OTW1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
PHD Package
64 Pins HTQFP
Top View
4
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SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
Electrical Pin 1
Pin 1 Marker
White Dot
Figure 1. Pin One Location PHD Package
Pin Functions
PIN
NAME
FUNCTION (1)
DESCRIPTION
HTQFP
HSSOP
AGND
8
10
P
Analog ground
BST_A
54
43
P
HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_A required.
BST_B
41
34
P
HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_B required.
BST_C
40
33
P
HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_C required.
BST_D
27
24
P
HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_D required.
CLIP
18
—
O
Clipping warning; open drain; active-low
C_STARTUP
3
5
O
Start-up ramp requires a charging capacitor of 4.7 nF to AGND in BTL mode
FREQ_ADJ
12
14
I
PWM frame-rate-programming pin requires resistor to AGND
7, 23, 24, 57,
58
9
P
Ground
GND_A
48, 49
38
P
Power ground for half-bridge A
GND_B
46, 47
37
P
Power ground for half-bridge B
GND_C
34, 35
30
P
Power ground for half-bridge C
GND_D
32, 33
29
P
Power ground for half-bridge D
GVDD_A
55
—
P
Gate-drive voltage supply requires 0.1-μF capacitor to GND_A
GVDD_B
56
—
P
Gate drive voltage supply requires 0.1-μF capacitor to GND_B
GVDD_C
25
—
P
Gate drive voltage supply requires 0.1-μF capacitor to GND_C
GVDD_D
26
—
P
Gate drive voltage supply requires 0.1-μF capacitor to GND_D
GVDD_AB
—
44
P
Gate drive voltage supply requires 0.22-μF capacitor to GND_A/GND_B
GVDD_CD
—
23
P
Gate drive voltage supply requires 0.22-μF capacitor to GND_C/GND_D
INPUT_A
4
6
I
Input signal for half-bridge A
INPUT_B
5
7
I
Input signal for half-bridge B
INPUT_C
10
12
I
Input signal for half-bridge C
INPUT_D
11
13
I
Input signal for half-bridge D
M1
20
20
I
Mode selection
M2
21
21
I
Mode selection
M3
22
22
I
Mode selection
NC
59–62
–
—
GND
(1)
No connect; pins may be grounded.
I = Input, O = Output, P = Power
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Pin Functions (continued)
PIN
NAME
FUNCTION (1)
DESCRIPTION
HTQFP
HSSOP
OC_ADJ
1
3
O
Analog overcurrent-programming pin requires resistor to AGND. 64-pin
package (PHD) = 22 kΩ. 44-pin PSOP3 (DKD) = 24 kΩ
OSC_IO+
13
15
I/O
Oscillator master/slave output/input
OSC_IO–
14
16
I/O
Oscillator master/slave output/input
OTW
—
18
O
Overtemperature warning signal, open-drain, active-low
OTW1
16
—
O
Overtemperature warning signal, open-drain, active-low
OTW2
17
—
O
Overtemperature warning signal, open-drain, active-low
OUT_A
52, 53
39, 40
O
Output, half-bridge A
OUT_B
44, 45
36
O
Output, half-bridge B
OUT_C
36, 37
31
O
Output, half-bridge C
OUT_D
28, 29
27, 28
O
Output, half-bridge D
63
1
P
PSU reference requires close decoupling of 330 pF to AGND.
PVDD_A
50, 51
41, 42
P
Power-supply input for half-bridge A requires close decoupling of 0.01-μF
capacitor in parallel with 2.2-μF capacitor to GND_A.
PVDD_B
42, 43
35
P
Power-supply input for half-bridge B requires close decoupling of 0.01-μF
capacitor in parallel with 2.2-μF capacitor to GND_B.
PVDD_C
38, 39
32
P
Power-supply input for half-bridge C requires close decoupling of 0.0- μF
capacitor in parallel with 2.2-μF capacitor to GND_C.
PVDD_D
30, 31
25, 26
P
Power-supply input for half-bridge D requires close decoupling of 0.01-μF
capacitor in parallel with 2.2-μF capacitor to GND_D.
READY
19
19
O
Normal operation; open-drain; active-high
RESET
2
4
I
Device reset input; active-low
SD
15
17
O
Shutdown signal, open-drain, active-low
VDD
64
2
P
Power supply for digital voltage regulator requires a 10-μF capacitor in parallel
with a 0.1-μF capacitor to GND for decoupling.
VI_CM
6
8
O
Analog comparator reference node requires close decoupling of 1 nF to
AGND.
VREG
9
11
P
Regulator supply filter pin requires 0.1-μF capacitor to AGND.
PSU_REF
6
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted
(1)
MIN
MAX
UNIT
VDD to AGND
–0.3
13.2
V
GVDD to AGND
–0.3
13.2
V
PVDD_X to GND_X (2)
–0.3
69
V
OUT_X to GND_X (2)
–0.3
69
V
BST_X to GND_X (2)
–0.3
82.2
V
BST_X to GVDD_X (2)
–0.3
69
V
VREG to AGND
–0.3
4.2
V
GND_X to GND
–0.3
0.3
V
GND_X to AGND
–0.3
0.3
V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP, PSU_REF to AGND
–0.3
4.2
V
INPUT_X
–0.3
7
V
RESET, SD, OTW1, OTW2, CLIP, READY to AGND
–0.3
7
V
9
mA
0
150
°C
–40
150
°C
Continuous sink current (SD, OTW1, OTW2, CLIP, READY)
Operating junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage
25
50
52.5
V
GVDD_x
Supply for logic regulators and gate-drive circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator supply voltage
DC supply voltage
10.8
12
13.2
V
3.5
4
1.8
2
2.4
3
7
10
7
15
7
10
Nominal
385
400
415
AM1
315
333
350
AM2
260
300
335
RL(BTL)
RL(SE)
(2)
RL(PBTL)
Load impedance
Output filter according to schematics in the
application information section
(1)
(2)
LOUTPUT(BTL)
LOUTPUT(SE)
(2)
LOUTPUT(PBTL)
Output filter inductance
(1)
Minimum output inductance at IOC
(2)
PWM frame rate selectable for AM interference
avoidance; 1% resistor tolerance.
fPWM
Nominal; master mode
RFREQ_ADJ
(1)
(2)
PWM frame-rate-programming resistor
Ω
μH
9.9
10
10.1
AM1; master mode
19.8
20
20.2
AM2; master mode
29.7
30
30.3
kHz
kΩ
Values are for actual measured impedance over all combinations of tolerance, current and temperature and not simply the component
rating.
See additional details for SE and PBTL in System Design Considerations.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
Voltage on FREQ_ADJ pin for slave mode
operation
VFREQ_ADJ
Overcurrent-protection-programming resistor,
cycle-by-cycle mode
ROCP
Overcurrent-protection-programming resistor,
latching mode
TJ
NOM
Slave mode
MAX
UNIT
3.3
V
64-pin QFP package (PHD)
22
33
44-Pin PSOP3 package (DKD)
24
33
PHD or DKD
47
68
0
125
Junction temperature
kΩ
°C
6.4 Thermal Information
TAS5630B
THERMAL METRIC
(1)
PHD (HTQFP)
DKD (HSSOP)
64 PINS
44 PINS
RθJA
Junction-to-ambient thermal resistance
8.6
8.8
RθJC(top)
Junction-to-case (top) thermal resistance
0.3
0.4
RθJB
Junction-to-board thermal resistance
2.1
3.0
ψJT
Junction-to-top characterization parameter
0.4
0.4
ψJB
Junction-to-board characterization parameter
2.1
3.0
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
6.5 Electrical Characteristics
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference
node, VREG
VI_CM
Analog comparator reference node, VI_CM
IVDD
VDD supply current
IGVDD_X
GVDD_x gate-supply current per half-bridge
IPVDD_X
Half-bridge supply current
VDD = 12 V
3
3.3
3.6
V
1.75
2
2.15
V
Operating, 50% duty cycle
22.5
Idle, reset mode
22.5
50% duty cycle
12.5
Reset mode
mA
mA
1.5
50% duty cycle with recommended output
filter
13.3
mA
Reset mode, No switching
870
μA
33
kΩ
5
VPP
ANALOG INPUTS
RIN
Input resistance
VIN
Maximum input voltage with symmetrical
output swing
READY = HIGH
IIN
Maximum input current
342
μA
G
Voltage gain (VOUT/VIN)
23
dB
OSCILLATOR
Nominal, master mode
fOSC_IO+
AM1, master mode
FPWM × 10
AM2, master mode
VIH
High level input voltage
VIL
Low level input voltage
8
3.85
4
3.15
3.33
4.15
3.5
2.6
3
3.35
1.86
V
1.45
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V
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Electrical Characteristics (continued)
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
OUTPUT-STAGE MOSFETs
RDS(on)
Drain-to-source resistance, low side (LS)
Drain-to-source resistance, high side (HS)
TJ = 25°C, excludes metallization
resistance, GVDD = 12 V
60
100
60
100
mΩ
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
VDD
Vuvp,G
Vuvp,hyst (1)
9.5
V
0.6
V
(1)
Overtemperature warning 1
95
100
105
°C
OTW2 (1)
Overtemperature warning 2
115
125
135
°C
OTWhyst (1)
Temperature drop needed below OTW
temperature for OTW to be inactive after
OTW event
OTW1
OTE (1)
25
Overtemperature error
145
155
OTE-OTW differential
30
OTEhyst (1)
A reset must occur for SD to be released
following an OTE event.
25
OLPC
Overload protection counter
°C
165
°C
°C
fPWM = 400 kHz
2.6
Resistor – programmable, nominal peak
current in 1-Ω load,
64-pin QFP package (PHD)
ROCP = 22 kΩ
15
Resistor – programmable, nominal peak
current in 1-Ω load,
44-pin PSOP3 package (DKD),
ROCP = 24 kΩ
15
Overcurrent limit protection, latched
Resistor – programmable, nominal peak
current in 1-Ω load,
ROCP = 47 kΩ
15
IOCT
Overcurrent response time
Time from switching transition to flip-state
induced by overcurrent
150
ns
IPD
Internal pulldown resistor at output of each
half-bridge
Connected when RESET is active to
provide bootstrap charge. Not used in SE
mode
3
mA
Overcurrent limit protection
IOC
ms
A
STATIC DIGITAL SPECIFICATIONS
VIH
High-level input voltage
VIL
Low-level input voltage
Ilkg
Input leakage current
M1, M2, M3, RESET
2
V
0.8
V
100
μA
kΩ
OTW/SHUTDOWN (SD)
RINT_PU
Internal pullup resistance, OTW, OTW1,
OTW2, CLIP, READY, SD to VREG
VOH
High-level output voltage
VOL
Low-level output voltage
IO = 4 mA
FANOUT
Device fanout OTW, OTW1, OTW2, SD,
CLIP, READY
No external pullup
(1)
Internal pullup resistor
External pullup of 4.7 kΩ to 5 V
20
26
32
3
3.3
3.6
4.5
V
5
200
30
500
mV
devices
Specified by design.
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6.6 Audio Characteristics (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 μH, CDEM = 680 nF,
MODE = 010, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
MIN
TYP MAX
RL = 4 Ω, 10% THD+N, clipped output signal
300
RL = 6 Ω, 10% THD+N, clipped output signal
210
RL = 8 Ω, 10% THD+N, clipped output signal
160
RL = 4 Ω, 1% THD+N, unclipped output signal
240
RL = 6 Ω, 1% THD+N, unclipped output signal
160
RL = 8 Ω, 1% THD+N, unclipped output signal
UNIT
W
125
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, input capacitor
grounded
|VOS|
Output offset voltage
Inputs ac-coupled to AGND
SNR
Signal-to-noise ratio (1)
A-weighted, AES17 filter
100
dB
DNR
Dynamic range
A-weighted, AES17 filter
100
dB
2.7
W
Pidle
(1)
(2)
Power dissipation due to idle losses (IPVDD_X)
0.03%
20
PO = 0, four channels switching
μV
270
(2)
50
mV
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses also are affected by core losses of output inductors.
6.7 Audio Specification (Single-Ended Output)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 15 μH, CDEM = 470 μF,
MODE = 100, unless otherwise noted.
PARAMETER
PO
Power output per channel
TEST CONDITIONS
MIN
TYP MAX
RL = 2 Ω, 10% THD+N, clipped output signal
145
RL = 3 Ω, 10% THD+N, clipped output signal
100
RL = 4 Ω, 10% THD+N, clipped output signal
75
RL = 2 Ω, 1% THD+N, unclipped output signal
110
RL = 3 Ω, 1% THD+N, unclipped output signal
75
RL = 4 Ω, 1% THD+N, unclipped output signal
UNIT
W
55
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, input capacitor grounded
340
μV
SNR
Signal-to-noise ratio (1)
A-weighted, AES17 filter
93
dB
DNR
Dynamic range
A-weighted, AES17 filter
93
dB
Pidle
Power dissipation due to idle losses
(IPVDD_X)
PO = 0, four channels switching (2)
2
W
(1)
(2)
10
0.07%
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
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6.8 Audio Specification (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 3 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 μH, CDEM = 1.5 μF,
MODE = 101-10, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
RL = 3 Ω, 10% THD+N, clipped output signal
400
RL = 4 Ω, 10% THD+N, clipped output signal
300
RL = 3 Ω, 1% THD+N, unclipped output signal
310
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted
260
μV
SNR
Signal to noise ratio (1)
A-weighted
100
dB
DNR
Dynamic range
A-weighted
100
dB
Pidle
Power dissipation due to idle losses (IPVDD_X) PO = 0, four channels switching (2)
2.7
W
RL = 4 Ω, 1% THD+N, unclipped output signal
(1)
(2)
W
230
0.05%
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses are affected by core losses of output inductors.
6.9 Typical Characteristics
6.9.1 BTL Configuration
340
10
THD+N − Total Harmonic Distortion + Noise − %
4Ω
6Ω
8Ω
4Ω
6Ω
8Ω
320
300
280
260
PO − Output Power − W
1
0.1
240
220
200
180
160
140
120
100
80
60
40
0.01
0.005
20m
100m
1
10
100
0
400
PO − Output Power − W
4Ω
6Ω
8Ω
200
Efficiency − %
PO − Output Power − W
220
180
160
140
120
100
80
60
40
20
TC = 75°C
25
30
35
40
PVDD − Supply Voltage − V
35
40
PVDD − Supply Voltage − V
45
50
G001
240
0
30
Figure 3. Output Power vs Supply Voltage
300
260
25
G001
Figure 2. Total Harmonic + Noise vs Output Power
280
TC = 75°C
THD+N at 10%
20
TC = 75°C
45
50
G001
Figure 4. Unclipped Output Power vs Supply Voltage
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
4Ω
6Ω
8Ω
0
100
TC = 25°C
THD+N at 10%
200
300
400
500
2 Channel Output Power − W
600
700
G001
Figure 5. System Efficiency vs Output Power
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100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
340
4Ω
6Ω
8Ω
320
300
280
260
PO − Output Power − W
Power Loss − W
BTL Configuration (continued)
240
220
200
180
160
140
120
100
80
60
0
100
200
300
400
500
2 Channel Output Power − W
600
4Ω
6Ω
8Ω
40
TC = 25°C
THD+N at 10%
20
0
−10
700
0
10
THD+N at 10%
20
30
40
50
60
70
80
90 100 110
TC − Case Temperature − °C
G001
Figure 6. System Power Loss vs Output Power
G001
Figure 7. Output Power vs Case Temperature
0
TC = 75°C
VREF = 35.36 V
Sample Rate = 48kHz
FFT Size = 16384
−10
−20
−30
4Ω
Noise Amplitude − dB
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
0
2k
4k
6k
8k 10k 12k 14k 16k 18k 20k 22k
f − Frequency − Hz
G001
Figure 8. Noise Amplitude vs Frequency
6.9.2 SE Configuration
1 Channel Driven
170
2Ω
3Ω
4Ω
150
140
130
1
0.1
120
110
100
90
80
70
60
50
40
30
20
0.01
0.005
20m
100m
1
10
PO − Output Power − W
TC = 75°C
THD+N at 10%
10
TC = 75°C
0
100 200
G001
Figure 9. Total Harmonic Distortion + Noise vs Output
Power
12
2Ω
3Ω
4Ω
160
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
10
25
30
35
40
PVDD − Supply Voltage − V
45
50
G001
Figure 10. Output Power vs Supply Voltage
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SE Configuration (continued)
180
170
160
150
140
PO − Output Power − W
130
120
110
100
90
80
70
60
50
40
30
2Ω
3Ω
4Ω
20
10
0
−10
0
10
THD+N at 10%
20
30
40
50
60
70
80
90 100 110
TC − Case Temperature − °C
G001
Figure 11. Output Power vs Case Temperature
6.9.3 PBTL Configuration
500
3Ω
4Ω
6Ω
8Ω
3Ω
4Ω
6Ω
8Ω
450
400
1
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
10
0.1
350
300
250
200
150
100
50
0.01
TC = 75°C
THD+N at 10%
TC = 75°C
0.005
20m
100m
1
10
100
0
700
PO − Output Power − W
25
30
G001
35
40
PVDD − Supply Voltage − V
45
50
G001
Figure 12. Total Harmonic Distortion + Noise vs Output
Power
Figure 13. Output Power vs Supply Voltage
500
450
PO − Output Power − W
400
350
300
250
200
150
100
3Ω
4Ω
6Ω
8Ω
50
0
−10
0
10
THD+N at 10%
20
30
40
50
60
70
80
90 100 110
TC − Case Temperature − °C
G001
Figure 14. Output Power vs Case Temperature
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7 Detailed Description
7.1 Overview
TAS5630B is an analog input, audio PWM (class-D) amplifier. The output of the TAS5630B can be configured for
single-ended, bridge-tied load (BTL) or parallel BTL (PBTL) output. It requires two rails for power supply, PVDD
and 12 V (GVDD and VDD). The following functional block diagram shows interconnections of internal supplies,
control logic, gate drives and power amplifiers. Detailed schematic can be viewed in TAS5630B EVM User's
Guide (SLAU287).
7.2 Functional Block Diagram
/CLIP
READY
/OTW1
/OTW2
/SD
PROTECTION & I/O LOGIC
M1
M2
M3
/RESET
C_STARTUP
VDD
POWER-UP
RESET
UVP
VREG
VREG
AGND
TEMP
SENSE
STARTUP
CONTROL
GVDD_A
GVDD _C
GVDD_B
OVER-LOAD
PROTECTION
GND
GVDD_D
CURRENT
SENSE
CB3C
OC_ADJ
OSC_SYNC_IO+
OSC_SYNC_IO-
4
OSCILLATOR
PPSC
FREQ_ADJ
4
4
PVDD_X
OUT_X
GND_X
GVDD_A
PWM
ACTIVITY
DETECTOR
4
PSU_REF
BST_A
PVDD_A
PVDD_X
PSU_FF
VI_CM
GND
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND_A
GVDD_B
INPUT_A
ANALOG
LOOP FILTER
BST_B
+
PVDD_B
+
INPUT_D
ANALOG
LOOP FILTER
-
+
ANALOG COMPARATOR MUX
INPUT_C
ANALOG
LOOP FILTER
ANALOG INPUT MUX
INPUT_B
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
GND_B
GVDD_C
BST_C
PVDD_C
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
+
ANALOG
LOOP FILTER
OUT_B
OUT_C
GND_C
-
GVDD_D
BST_D
PVDD_D
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND_D
14
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7.3 Feature Description
7.3.1 Power Supplies
To facilitate system design, the TAS5630B needs only a 12-V supply in addition to the (typical) 50-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and
output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the
same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see Typical Application for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See SLAU287 for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 400 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2-μF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5630B reference design. For additional information on recommended power
supply and required components, see Typical Application.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V powerstage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit. Moreover, the TAS5630B is fully protected against erroneous
power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within
the specified range (see Recommended Operating Conditions).
7.3.2 System Power-Up and Power-Down Sequence
7.3.2.1 Powering Up
The TAS5630B does not require a power-up sequence. The outputs of the H-bridges remain in a highimpedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see Electrical Characteristics). Although not specifically required, it is
recommended to hold RESET in a low state while powering up the device. This allows an internal circuit to
charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
7.3.2.2 Powering Down
The TAS5630B does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see Electrical Characteristics). Although not specifically required, it is a good practice to hold RESET
low during power down, thus preventing audible artifacts including pops or clicks.
7.3.3 Error Reporting
The SD, OTW, OTW1, and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
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Feature Description (continued)
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see Table 1).
Table 1. Error Reporting
SD
OTW1
OTW2,
OTW
0
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
0
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
warning)
0
1
1
Overload (OLP) or undervoltage (UVP)
1
0
0
Junction temperature higher than 125°C (overtemperature warning)
1
0
1
Junction temperature higher than 100°C (overtemperature warning)
1
1
1
Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
DESCRIPTION
Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, for example, turning down the volume to prevent further heating of the device resulting in
device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see Electrical
Characteristics for further specifications).
7.3.4 Device Protection System
The TAS5630B contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5630B responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, that is, the supply voltage has increased.
The device functions on errors, as shown in the following table.
Table 2. Device Protection System
BTL Mode
Local error in
A
B
C
D
PBTL Mode
Turns Off or in
A+B
C+D
Local error in
Turns Off or in
A
B
C
SE Mode
Local error in
Turns Off or in
A
A+B+C+D
D
B
C
D
A+B
C+D
Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge.
16
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7.3.5 Pin-to-Pin Short-Circuit Protection (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup, that is, when VDD is supplied; consequently, a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the
startup sequence and starts switching. The detection is controlled globally by a two-step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC
filter. The typical duration is
