TAS5706A is Not Recommended for New Designs
TAS5706A
TAS5706B
www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009
20-W Stereo Digital Audio Power Amplifier with EQ and DRC
FEATURES
1
• Audio Input/Output
– 20-W into an 8-Ω Load From an 18-V Supply
– Two Serial Audio Inputs (Four Audio
Channels)
• TAS5706A Supports:
– 2-Ch Bridged Outputs (20 W × 2)
• TAS5706B Supports:
– 2-Ch Bridged Outputs (20 W × 2)
– 4-Ch Single-Ended Outputs (10 W × 4)
– 2-Ch Single-Ended + 1-Ch Bridged (2.1
Mode) (10 W × 2 + 20 W)
• Supports 32-kHz–192-kHz Sample Rates
(LJ/RJ/I2S)
• Closed Loop Power Stage Architecture
– Improved PSRR Reduces Power Supply
Performance Requirements
– Higher Damping Factor Provides for
Tighter, More Accurate Sound With
Improved Bass Response
– Constant Output Power Over Variation in
Supply
• Wide PVCC Range From (10 V to 26 V)
– No Separate Supply Required for Gate
Drive
• Headphone PWM Outputs
• Subwoofer PWM Outputs
• AM Interference Avoidance Support
• Audio/PWM Processing
– Independent Channel Volume Controls With
48-dB to –79-dB Range—Soft Mute (50%
Duty Cycle)
– Programmable Dynamic Range Control
– 7 Programmable Biquads for Speaker
Equalization for Left and Right Channels
– 4 Programmable Biquads for Bass
23
•
Processing
– Adaptive Biquad Coefficients for EQ and
DRC Filters
– Programmable Input and Output Mixers
– Automatic Sample-Rate Detection and
Coefficient Banking
General Features
– Serial Control Interface Operational Without
MCLK
– Factory-Trimmed Internal Oscillator Avoids
the Need for External Crystal
– Surface Mount, 64-Terminal, 10-mm ×
10-mm HTQFP Package
– Thermal and Short-Circuit Protection
DESCRIPTION
The TAS5706A/B is a 20-W, efficient, digital audio
power amplifier for driving stereo bridged-tied
speakers. Two serial data inputs allow processing of
up to four discrete audio channels and seamless
integration to most digital audio processors and
MPEG decoders, accepting a wide range of input
data and clock rates. A fully programmable data path
allows these channels to be routed to the internal
speaker drivers or output via the subwoofer or
headphone PWM outputs.
The TAS5706A/B is a slave-only device receiving all
clocks from external sources. The TAS5706A/B
operates at a 384-kHz switching rate for 32-, 48-, 96-,
and 192-kHz data, and at a 352.8 kHz switching rate
for 44.1-, 88.2-, and 176.4-kHz data. The 8×
oversampling combined with the fourth-order noise
shaper provides a flat noise floor and excellent
dynamic range from 20 Hz to 20 kHz.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TAS5706A
TAS5706B
TAS5706A is Not Recommended for New Designs
SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED APPLICATION DIAGRAMS
Bridge-Tied Load (BTL) Mode (TAS5706A/TAS5706B)
3.3 V
10 V–26 V
DVDD/AVDD
AVCC/PVCC
OUT_A
LRCLK
SCLK
Digital
Audio
Source
BST_A
MCLK
SDIN1
LCBTL*
Left
LCBTL*
Right
BST_B
SDIN2
OUT_B
2
SDA
I C
Control
OUT_C
SCL
BST_C
BST_D
MUTE
HPSEL
Control
Inputs
OUT_D
RESET
10 V–26 V
TAS5602
PDN
SUB_PWM+
PWM_AP
OUT_A
PWM_AN
PLL_FLTP
SUB_PWM–
PWM_BP
BST_A
LCBTL*
Subwoofer
BST_B
Loop
Filter
PWM_BN
PLL_FLTM
BKND_ERR
FAULT
VALID
RESET
OUT_B
HPR_PWM
HPL_PWM
RC
Filter
TPA6110A2
(HP Amplifier)
* Refer to TI Application Note (SLOA119) on LC filter design for BTL (AD/BD mode) configuration.
2
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TAS5706A
TAS5706B
www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009
2 Single-Ended (SE) + 1 BTL Mode (TAS5706B Only)
3.3 V
10 V–26 V
DVDD/AVDD
AVCC/PVCC
OUT_A
LCSE*
LRCLK
SCLK
Digital
Audio
Source
BST_A
MCLK
SDIN1
SDIN2
BST_B
OUT_B
2
LCSE*
SDA
I C
Control
SCL
MUTE
OUT_C
HPSEL
Control
Inputs
RESET
PDN
BST_C
LCBTL*
BST_D
OUT_D
PLL_FLTP
Loop
Filter
SUB_PWM+
PLL_FLTM
SUB_PWM–
BKND_ERR
VALID
HPR_PWM
HPL_PWM
RC
Filter
TPA6110A2
(HP Amplifier)
* Refer to TI Application Note (SLOA119) on LC filter design for SE or BTL configuration.
B0264-05
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TAS5706A
TAS5706B
TAS5706A is Not Recommended for New Designs
SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com
Single-Ended (SE) 4.0 Mode (TAS5706B Only)
3.3 V
10 V–26 V
DVDD/AVDD
AVCC/PVCC
OUT_A
LCSE*
LRCLK
SCLK
Digital
Audio
Source
BST_A
MCLK
SDIN1
SDIN2
2
BST_B
OUT_B
LCSE*
OUT_C
LCSE*
SDA
I C
Control
SCL
MUTE
HPSEL
Control
Inputs
RESET
BST_C
PDN
BST_D
OUT_D
LCSE*
PLL_FLTP
Loop
Filter
SUB_PWM+
PLL_FLTM
SUB_PWM–
BKND_ERR
VALID
HPR_PWM
HPL_PWM
RC
Filter
TPA6110A2
(HP Amplifier)
* Refer to TI Application Note (SLOA119) on LC filter design for SE configuration.
B0264-04
4
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TAS5706A
TAS5706B
www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009
FUNCTIONAL VIEW
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TAS5706A
TAS5706B
TAS5706A is Not Recommended for New Designs
SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com
64-PIN, HTQFP PACKAGE (TOP VIEW)
PIN FUNCTIONS
PIN
NAME
AGND
TYPE
NO.
57
58
AVCC
(1)
5-V
TOLERANT
TERMINATION
DESCRIPTION
(2)
P
Analog ground for power stage
P
Analog power supply for power stage. Connect externally to same
potential as PVCC.
AVDD
10
P
3.3-V analog power supply
AVSS
11
P
Analog 3.3-V supply ground
BKND_ERR
35
DI
(1)
(2)
6
Pullup
Active-low. A back-end error sequence is generated by applying logic
LOW to this terminal. This terminal is connected to an external power
stage. If no external power stage is used, connect this terminal directly
to DVDD.
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
All pullups are 20-µA weak pullups and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 µA while maintaining a logic-1 drive level.
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TAS5706A
TAS5706B
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PIN FUNCTIONS (continued)
PIN
NAME
TYPE
NO.
(1)
5-V
TOLERANT
TERMINATION
DESCRIPTION
(2)
BST_A
59
P
High-side bootstrap supply for half-bridge A
BST_B
61
P
High-side bootstrap supply for half-bridge B
BST_C
53
P
High-side bootstrap supply for half-bridge C
BST_D
55
P
High-side bootstrap supply for half-bridge D
BYPASS
56
O
Nominally equal to VCC/8. Internal reference voltage for analog cells
DVDD
15,
33
P
3.3-V digital power supply
DVSS
20,
26
P
Digital ground
HPL_PWM
37
DO
Headphone left-channel PWM output.
HPR_PWM
38
DO
Headphone right-channel PWM output.
HPSEL
30
DI
5-V
Headphone select, active high. When a logic HIGH is applied, device
enters headphone mode and speakers are HARD MUTED. When a
logic LOW is applied, device is in speaker mode and headphone
outputs become line outputs or are disabled.
LRCLK
22
DI
5-V
Input serial audio data left/right clock (sampling rate clock)
MCLK
34
DI
5-V
MCLK is the clock master input. The input frequency of this clock can
range from 4.9 MHz to 49 MHz.
5-V
Performs a soft mute of outputs, active-low. A logic low on this
terminal sets the outputs equal to 50% duty cycle. A logic high on this
terminal allows normal operation. The mute control provides a
noiseless volume ramp to silence. Releasing mute provides a
noiseless ramp to previous volume.
MUTE
21
DI
OSC_RES
19
AO
OUT_A
4, 5
O
Output, half-bridge A
OUT_B
1, 64
O
Output, half-bridge B
OUT_C
49,
50
O
Output, half-bridge C
OUT_D
45,
46
O
Output, half-bridge D
Power down, active-low. PDN powers down all logic, stops all clocks,
and outputs stops switching. When PDN is released, the device
powers up all logic, starts all clocks, and performs a soft start that
returns to the previous configuration determined by register settings.
Pullup
Oscillator trim resistor. Connect an 18.2-kΩ resistor to GND.
PDN
17
DI
5-V
Pullup
PGND_A
6, 7
P
Power ground for half-bridge A
PGND_B
2, 3
P
Power ground for half-bridge B
PGND_C
47,
48
P
Power ground for half-bridge C
PGND_D
43,
44
P
Power ground for half-bridge D
PLL_FLTM
12
AO
PLL negative input
PLL_FLTP
13
AI
PLL positive input
PVCC_A
8, 9
P
Power supply input for half-bridge output A
PVCC_B
62,
63
P
Power supply input for half-bridge output B
PVCC_C
51,
52
P
Power supply input for half-bridge output C
PVCC_D
41,
42
P
Power supply input for half-bridge output D
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TAS5706B
TAS5706A is Not Recommended for New Designs
SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com
PIN FUNCTIONS (continued)
PIN
NAME
TYPE
NO.
(1)
5-V
TOLERANT
TERMINATION
(2)
DESCRIPTION
Pullup
Reset, active-low. A system reset is generated by applying a logic low
to this terminal. RESET is an asynchronous control signal that
restores the DAP to its default conditions, sets the VALID outputs low,
and places the PWM in the hard-mute state (stops switching). Master
volume is immediately set to full attenuation. Upon the release of
RESET, if PDN is high, the system performs a 4- to 5-ms device
initialization and sets the volume at mute.
RESET
16
DI
5-V
SCL
29
DI
5-V
I2C serial control clock input
SCLK
23
DI
5-V
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
SDA
28
DIO
5-V
I2C serial control data interface input/output
SDIN1
25
DI
5-V
Serial audio data-1 input is one of the serial data input ports. SDIN1
supports three discrete (stereo) data formats.
SDIN2
24
DI
5-V
Serial audio data-2 input is one of the serial data input ports. SDIN2
supports three discrete (stereo) data formats.
STEST
31
DI
Test terminal. Connect directly to GND.
SUB_PWM–
39
DO
Subwoofer negative PWM output
SUB_PWM+
40
DO
Subwoofer positive PWM output
TEST2
32
DI
Test terminal. Connect directly to DVDD.
VALID
36
DO
Output indicating validity of ALL PWM channels, active-high. This
terminal is connected to an external power stage. If no external power
stage is used, leave this terminal floating.
VCLAMP_AB
60
P
Internally generated voltage supply for channels A and B gate drive.
Not to be used as a supply or connected to any component other than
the decoupling capacitor
VCLAMP_CD
54
P
Internally generated voltage supply for channels C and D gate drive.
Not to be used as a supply or connected to any component other than
the decoupling capacitor
VR_ANA
14
P
Internally regulated 1.8-V analog supply voltage. This terminal must
not be used to power external devices.
VR_DIG
27
P
Internally regulated 1.8-V digital supply voltage. This terminal must not
be used to power external devices.
VREG_EN
18
DI
Pulldown
Voltage regulator enable. Connect directly to GND.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Input voltage
(1)
VALUE
UNIT
DVDD, AVDD
–0.3 to 3.6
V
PVCC
-0.3 to 30
V
3.3-V digital input
–0.5 to DVDD + 0.5
V
5-V tolerant (2) digital input
–0.5 to DVDD + 2.5
V
±20
mA
Input clamp current, IIK (VI < 0 or VI > 1.8 V
Output clamp current, IOK (VO < 0 or VO > 1.8 V
±20
mA
Operating free-air temperature
0 to 85
°C
Operating junction temperature range
0 to 150
°C
–40 to 125
°C
Storage temperature range, Tstg
(1)
(2)
8
Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDA, SCL, and HPSEL.
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TAS5706A is Not Recommended for New Designs
www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009
DISSIPATION RATINGS
PACKAGE (1)
DERATING FACTOR
TA = 25°C
POWER RATING
TA = 45°C
POWER RATING
TA = 70°C
POWER RATING
10-mm × 10-mm QFP
29 mW/°C
2.89 W
2.31 W
1.59 W
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
Digital/analog supply voltage
DVDD
Half-bridge supply voltage
PVCC_xx
VIH
High-level input voltage
3.3-V TTL, 5-V tolerant
VIL
Low-level input voltage
3.3-V TTL, 5-V tolerant
TA
Operating ambient temperature range
TJ
Operating junction temperature range
MAX
3
3.3
3.6
V
26
V
2
0
RL (PBTL)
6.0
8
3.2
4
3.2
4
LO (BTL)
UNIT
V
0.8
V
85
°C
150
°C
0
Output filter: L = 22 µH, C = 680 nF.
Load impedance
NOM
10
RL (BTL)
RL (SE)
MIN
Ω
10
LO (SE)
Minimum output inductance under
short-circuit condition
Output-filter inductance
µH
10
LO (PBTL)
10
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER
Output sample rate 2×–1×
oversampled
TEST CONDITIONS
MODE
32–kHz data rate ±2%
12× sample rate
VALUE
44.1-, 88.2-, 176.4-kHz data rate ±2%
48-, 96-, 192-kHz data rate ±2%
UNITS
384
kHz
8×, 4×, and 2× sample rates
352.8
kHz
8×, 4×, and 2× sample rates
384
kHz
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER
fMCLKI
TEST CONDITIONS
MIN
Frequency, MCLK (1 / tcyc2)
TYP
4.9
MCLK duty cycle
40%
50%
MAX
UNIT
49
MHz
60%
MCLK minimum high time
≥ 2-V MCLK = 49.152 MHz, within the
min and max duty cycle constraints
8
ns
MCLK minimum low time
≤ 0.8-V MCLK = 49.152 MHz, within the
min and max duty cycle constraints
8
ns
LRCLK allowable drift before LRCLK reset
10
External PLL filter capacitor C1
SMD 0603 Y5V
External PLL filter capacitor C2
External PLL filter resistor R
MCLKs
47
nF
SMD 0603 Y5V
4.7
nF
SMD 0603, metal film
470
Ω
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TAS5706A is Not Recommended for New Designs
SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS
DC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
3.3-V TTL and 5-V tolerant
(1)
IOH = –4 mA
VOL
Low-level output voltage
3.3-V TTL and 5-V tolerant
(1)
IOL = 4 mA
| VOS |
Class-D output offset voltage
VBYPASS
PVCC/8 reference for analog section
IIL
Low-level input current
IIH
High-level input current
MIN
TYP MAX
2.4
V
0.5
±26
No load
2.2
2.26
VI = VIL
±2
5-V tolerant (1)
VI = 0 V, DVDD = 3 V
±2
3.3-V TTL
VI = VIH
5-V tolerant
VI = 5.5 V, DVDD = 3 V
Supply voltage (DVDD, AVDD)
±2
Power down
(PDNZ = LOW)
V
mV
2.3
3.3-V TTL
Normal mode
UNIT
±20
43
65
80
2
8
16
33
V
µA
µA
IDD
Input supply current
Reset (RESET = LOW)
11
23
ICC
Quiescent supply current
No load
14
33
57
mA
ICC(RESET)
Quiescent supply current in reset mode
No load
58
176
µA
ICC(PDNZ)
Quiescent supply current in power down mode
No load
58
176
µA
PSRR
DC power-supply rejection ratio
PVCC = 17.5 V to 18.5 V
60
Drain-source on-state resistance, high-side
RDS(on)
tON
tOFF
(1)
10
240
Total
480
Turnon time (SE mode) (Set Reg 0x1A bit 7 to 1)
500
Turnon time (BTL mode) (Set Reg 0x1A bit 7 to 0)
Turnoff time (SE mode) (Set Reg 0X1A bit 7 to 1)
Turnoff time (BTL mode) (Set Reg 0X1A bit 7 to 0)
dB
240
VCC = 18 V , IO = 500 mA,
TJ = 25°C
Low-side
mA
C(BYPASS) = 1 µF,
Time required for the
C(BYPASS) to reach its final
value
30
500
30
mΩ
850
ms
ms
5-V tolerant pins are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDA, SCL, and HPSEL.
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TAS5706A is Not Recommended for New Designs
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AC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, AVDD, DVDD = 3.3 V, RL = 8 Ω (unless
otherwise noted) (1)
PARAMETER
KSVR
Supply ripple rejection
Continuous output
power
PO
THD+N
Vn
TEST CONDITIONS
MIN
TYP
MAX
100-mVPP ripple at 20 Hz–20 kHz, BTL, 50%
duty cycle PWM
–60
dB
BTL (RL = 8 Ω, THD+N = 10%, f = 1 kHz,
PVCC = 18 V)
20.6
W
BTL (RL = 8 Ω, THD+N = 7%, f = 1 kHz,
PVCC = 18 V)
19.3
W
SE (RL = 4 Ω, THD+N = 10%, f = 1 kHz,
PVCC = 24 V)
18.1
W
SE (RL = 4 Ω, THD+N = 7%, f = 1 kHz,
PVCC = 24 V)
17.3
W
Total harmonic distortion VCC = 24 V, RL = 4 Ω, f = 1 kHz, PO = 10 W
+ noise (SE)
(half-power)
0.08%
Total harmonic distortion VCC = 18 V, RL = 8 Ω, f = 1 kHz, PO = 10 W
+ noise (BTL)
(half-power)
0.05%
Output integrated noise
UNIT
20 Hz to 22 kHz (BD mode)
115
µV
A-weighted filter; MUTE = LOW
–82
dBV
Crosstalk
PO = 1 W, f = 1 kHz
–69
dB
SNR
Maximum output at THD+N < 1%, f = 1 kHz,
A-weighted
99
dB
Thermal trip point
(output shutdown,
unlatched fault)
150
°C
Thermal hysteresis
15
°C
(1)
Signal-to-noise ratio
All measurement in AD mode.
AC Characteristics, TA = 25°C, PVCC_X, AVCC = 12 V, AVDD, DVDD = 3.3 V, RL = 8 Ω (unless
otherwise noted) (1)
PARAMETER
KSVR
PO
Supply ripple rejection
Continuous output power
THD+N
Total harmonic distortion
+ noise (BTL)
Vn
Output integrated noise
Crosstalk
SNR
Signal-to-noise ratio
TEST CONDITIONS
TYP
MAX
UNIT
–60
dB
BTL (RL = 8 Ω, THD+N = 10%, f = 1 kHz)
9.2
W
BTL (RL = 8 Ω, THD+N = 7%, f = 1 kHz)
8.7
W
SE (RL = 4 Ω, THD+N = 10%, f = 1 kHz)
4.5
W
SE (RL = 4 Ω, THD+N = 7%, f = 1 kHz)
4.2
W
VCC = 12 V, RL = 8 Ω, f = 1 kHz,
PO = 5 W (half-power)
0.07%
20 Hz to 22 kHz (BD mode)
115
µV
A-weighted filter
–82
dBV
PO = 1 W, f = 1 kHz
–75
dB
96
dB
150
°C
15
°C
Maximum output at THD+N < 1%,
f = 1 kHz, A-weighted
Thermal trip point (output
shutdown, unlatched fault)
Thermal hysteresis
(1)
MIN
100-mVPP ripple at 20 Hz–20 kHz, BTL,
50% duty cycle PWM
All measurement in AD mode.
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SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
TYP
1.024
MAX
UNIT
12.288
MHz
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
CL = 30 pF
MIN
Hold time, SDIN from SCLK rising edge
10
LRCLK frequency
32
48
192
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
32
64
SCLK
edges
–1/4
1/4
SCLK
period
SCLK rising edges between LRCLK rising edges
t(edge)
LRCLK clock edge with respect to the falling edge of SCLK
ns
kHz
Figure 1. Slave Mode Serial Data Interface Timing
12
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I2C SERIAL CONTROL PORT OPERATION
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fSCL
Frequency, SCL
No wait states
tw(H)
Pulse duration, SCL high
0.6
1.3
MAX
UNIT
400
kHz
µs
µs
tw(L)
Pulse duration, SCL low
tr
Rise time, SCL and SDA
300
ns
tf
Fall time, SCL and SDA
300
ns
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
t(buf)
tsu2
100
ns
0
ns
Bus free time between stop and start condition
1.3
µs
Setup time, SCL to start condition
0.6
µs
µs
th2
Hold time, start condition to SCL
0.6
tsu3
Setup time, SCL to stop condition
0.6
CL
Load capacitance for each bus line
µs
400
tw(H)
tw(L)
pF
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 2. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 3. Start and Stop Conditions Timing
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RESET TIMING (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
td(VALID_LOW)
Time to assert VALID (reset to power stage) low
tw(RESET)
Pulse duration, RESET active
td(I2C_ready)
Time to enable I2C
td(run)
Device start-up time (after start-up command via I2C)
TYP
MAX
ns
1
ms
3.5
ms
10
RESET
UNIT
300
ms
Earliest time
that hard mute
could be exited
tw(RESET)
VALID
td(I2C_ready)
td(run)
td(VALID_LOW)
System initialization.
Start system
2
Enable via I C.
T0029-05
NOTE: On power up, it is recommended that the TAS5706A/B RESET be held LOW for at least 100 µs after DVDD has
reached 3.0 V. RESET assertion is ignored if applied while part is powered down
Figure 4. Reset Timing
POWER-DOWN (PDN) TIMING
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
td(VALID_LOW)
Time to assert VALID (reset to power stage) low
725
µs
td(STARTUP)
Device startup time
120
ms
tw
Minimum pulse duration required
800
ns
PDN
tw
VALID
td(STARTUP)
td(VALID_LOW)
T0030-04
NOTE: PDNZ assertion is ignored if applied when part is in RESET
Figure 5. Power-Down Timing
14
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BACK-END ERROR (BKND_ERR)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
tw(ER)
Pulse duration, BKND_ERR active (active-low)
tp(valid_high)
Programmable. Time to stay in the OUT_x low state. After tp(valid_high), the TAS5706A
attempts to bring the system out of the OUT_x low state if BKND_ERR is high. Refer
Reg 0x1C
tp(valid_low)
TYP
MAX
UNIT
350
None
ns
ms
350
Time TAS5706A takes to bring OUT_x low after BKND_ERR assertion.
ns
tw(ER)
BKND_ERR
VALID
Normal
Operation
Normal
Operation
tp(valid_high)
tp(valid_low)
T0031-04
Figure 6. Error Recovery Timing
MUTE TIMING (MUTE)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
td(VOL)
(1)
MIN
Volume ramp time. Ramp Time = Number of Steps (programmable number of steps, refer
register 0x0E) × Stepsize (1)
TYP
MAX
1024
UNIT
steps
Stepsize = 4 LRCLKs (for 32–48 kHz sample rate); 8 LRCLKs (for 88.2–96 kHz sample rate); 16 LRCLKs (for 176.4–192 kHz sample
rate)
MUTE
VOLUME
Normal
Operation
Normal
Operation
td(VOL)
td(VOL)
50-50
Duty Cycle
T0032-03
Figure 7. Mute Timing
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HEADPHONE SELECT (HPSEL)
PARAMETER
tw(MUTE)
Pulse duration, HPSEL active
td(VOL)
Soft volume update time
t(SW)
Switch-over time
(1)
MIN
MAX
350
None
See
(1)
0.2
UNIT
ns
ms
1
ms
Defined by rate setting. See the Volume Configuration Register section.
Figure 8 and Figure 9 show functionality when bit 4 in HP configuration register is set to DISABLE line output from HP_PWM outputs. If
bit 4 is not set, than the HP PWM outputs are not disabled when HPSEL is brought low.
HPSEL
Spkr Volume
td(VOL)
HP Volume
td(VOL)
t(SW)
VALID
T0267-01
Figure 8. HPSEL Timing for Headphone Insertion
HPSEL
HP Volume
td(VOL)
Spkr Volume
td(VOL)
t(SW)
VALID
T0268-01
Figure 9. HPSEL Timing for Headphone Extraction
16
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 12 V
RL = 8 Ω
P=5W
1
P = 2.5 W
0.1
0.01
P = 0.5 W
0.001
20
100
1k
VCC = 18 V
RL = 8 Ω
P = 10 W
1
P=5W
0.1
0.01
P=1W
0.001
20
10k 20k
100
1k
f − Frequency − Hz
10k 20k
f − Frequency − Hz
G001
G002
Figure 10.
Figure 11.
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 24 V
RL = 8 Ω
P = 10 W
1
P=5W
0.1
0.01
P=1W
0.001
20
100
1k
10k 20k
VCC = 12 V
RL = 8 Ω
1
f = 10 kHz
f = 1 kHz
0.1
0.01
f = 20 Hz
0.001
0.01
f − Frequency − Hz
G003
Figure 12.
0.1
1
10
PO − Output Power − W
40
G004
Figure 13.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 18 V
RL = 8 Ω
1
f = 10 kHz
f = 1 kHz
0.1
0.01
f = 20 Hz
0.001
0.01
0.1
1
10
PO − Output Power − W
VCC = 24 V
RL = 8 Ω
1
f = 10 kHz
f = 1 kHz
0.1
0.01
f = 20 Hz
0.001
0.01
40
0.1
1
G005
Figure 15.
EFFICIENCY
vs
OUTPUT POWER
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
3.0
RL = 8 Ω
90
2.5
VCC = 18 V
70
VCC = 24 V
VCC = 18 V
60
ICC − Supply Current − A
80
Efficiency − %
40
G006
Figure 14.
100
VCC = 12 V
50
40
30
2.0
VCC = 12 V
1.5
1.0
VCC = 24 V
20
0.5
10
RL = 8 Ω
0.0
0
0
5
10
15
20
25
PO − Output Power (Per Channel) − W
30
0
5
10
15
20
25
30
PO − Total Output Power − W
G007
Figure 16.
18
10
PO − Output Power − W
35
40
G008
Figure 17.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
OUTPUT POWER
vs
SUPPLY VOLTAGE
PSRR
vs
PVCC
40
0
RL = 8 Ω
35
−10
−20
−30
THD+N = 10%
25
PSRR − dB
PO − Output Power − W
30
20
15
THD+N = 1%
−40
−50
−60
−70
10
−80
5
−90
0
10
12
14
16
18
20
22
24
12
14
16
18
20
22
24
26
PVCC − V
G009
G010
Figure 18.
Figure 19.
A-WTD NOISE
vs
PVCC
CROSSTALK
vs
FREQUENCY
−75
−40
−76
−50
−77
−60
−78
−70
Right to Left
Crosstalk − dB
A-Wtd Noise − dBV
VCC − Supply Voltage − V
−100
10
26
−79
−80
−81
−80
−90
−100
−82
−110
−83
−120
−84
−130
−85
10
12
14
16
18
20
22
24
−140
20
26
Left to Right
RL = 8 Ω
VCC = 12 V
100
PVCC − V
G011
Figure 20.
1k
10k 20k
f − Frequency − Hz
G012
Figure 21.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
−40
−40
−50
−50
−60
−60
Right to Left
−80
Left to Right
−90
−100
−110
−140
20
Left to Right
−80
−90
−100
−110
−120
−130
Right to Left
−70
Crosstalk − dB
Crosstalk − dB
−70
−120
RL = 8 Ω
VCC = 18 V
100
RL = 8 Ω
VCC = 24 V
−130
1k
−140
20
10k 20k
100
1k
f − Frequency − Hz
10k 20k
f − Frequency − Hz
G013
G014
Figure 22.
Figure 23.
TYPICAL CHARACTERISTICS, SE CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
OUTPUT POWER
10
PO = 1 W
RL = 4 Ω
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
1
VCC = 12 V
0.1
VCC = 24 V
0.01
VCC = 18 V
0.001
20
100
1k
10k 20k
f = 1 kHz
RL = 4 Ω
1
VCC = 12 V
0.1
VCC = 24 V
0.01
VCC = 18 V
0.001
0.01
f − Frequency − Hz
G015
Figure 24.
20
0.1
1
PO − Output Power − W
10
40
G016
Figure 25.
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TYPICAL CHARACTERISTICS, SE CONFIGURATION (continued)
EFFICIENCY
vs
OUTPUT POWER
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
2.0
100
RL = 4 Ω
90
VCC = 18 V
80
1.5
VCC = 24 V
VCC = 18 V
ICC − Supply Current − A
Efficiency − %
70
60
VCC = 12 V
50
40
30
VCC = 12 V
1.0
VCC = 24 V
0.5
20
10
RL = 4 Ω
0.0
0
0
5
10
15
20
0
25
5
10
15
20
25
30
35
PO − Total Output Power − W
PO − Output Power (Per Channel) − W
G017
Figure 26.
40
G018
Figure 27.
OUTPUT POWER
vs
SUPPLY VOLTAGE
20
RL = 4 Ω
18
PO − Output Power − W
16
14
12
THD+N = 10%
10
8
THD+N = 1%
6
4
2
0
10
12
14
16
18
20
22
24
VCC − Supply Voltage − V
26
G019
Figure 28.
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DETAILED DESCRIPTION
POWER SUPPLY
The digital portion of the chip requires 3.3 V, and the power stages can work from 10 V to 26 V.
CLOCK, AUTO DETECTION, AND PLL
The TAS5706A DAP is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the clock control register.
The TAS5706A checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1
× fS LRCLK. The timing relationship of these clocks to SDIN1/2 is shown in subsequent sections. The clock
section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce the internal
clock.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for the frequencies of
32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed (176.4 kHz or
192 kHz). The automatic sample rate detection can be disabled and the values set via I2C in the clock control
register.
The DAP also supports an AM interference-avoidance mode during which the clock rate is adjusted, in concert
with the PWM sample rate converter, to produce a PWM output at 7 × fS, 8 × fS, or 6 × fS.
The sample rate must be set manually during AM interference avoidance and when de-emphasis is enabled.
SERIAL DATA INTERFACE
Serial data is input on SDIN1/2. The PWM outputs are derived from SDIN1/2. The TAS5706A DAP accepts 32-,
44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 18-, 20-, or 24-bit data in left-justified, right-justified,
and I2S serial data formats.
PWM Section
The TAS5706A DAP device uses noise-shaping and sophisticated error correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper that
has >100-dB SNR performance from 20 Hz to 20 kHz. The PWM section accepts 24-bit PCM data from the DAP
and outputs four PWM audio output channels. TAS5706A PWM section output supports bridge-tied loads.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual channel de-emphasis filters for 32-, 44.1-, and 48-kHz are included and
can be enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
I2C COMPATIBLE SERIAL CONTROL INTERFACE
The TAS5706A DAP has an I2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multi-byte read and write operations for status registers
and the general control registers associated with the PWM.
The I2C interface supports a special mode which permits I2C write operations to be broken up into multiple-data
write operations that are multiples of 4 data bytes. These are 6-, 10-, 14-, 18-, ... etc., -byte write operations that
are composed of a device address, read/write bit, subaddress, and any multiple of 4 bytes of data. This permits
the system to write large register values incrementally without blocking other I2C transactions.
22
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SDIN2
SDIN1
SDI
0x04
SDIN1L
SDIN1R
SDIN2L
SDIN2R
6
4
3
2
1
0x20
R'
Down Mix
0x21
L'
SUB
2
BQ
7
BQ
7
BQ
0x21
(L'+R')/2
0x21
Bass
Management
RS
LS
RF
LF
0x21
Vol6
0x0D
Vol 4
0x0B
Vol 3
0x0A
Vol 2
0x09
Vol1
0x08
DRC2
drc2_ coeff
Drc2_en
drc1_ coeff
Drc1_en
Drc2_dis
drc1_ coeff
Drc1_en
drc1_ coeff
Drc1_en
DRC1
drc1_ coeff
Drc1_en
Drc1_dis
Noise
Shaper
AD/BD
B
T
L
PWM3
0x13
0x20
PWM2
0x12
PWM1
0x11
Sub+
B
T
L
0x20
Sub–
B
T
L
PWM6
0x16
PWM5
0x15
PWM4
0x14
0x20
RF–
RF+
LF–
LF+
0x20
Noise
Shaper
AD
Noise
Shaper
AD
Noise
Shaper
AD/BD
0x20
Noise
Shaper
AD/BD
0x20
6
6
6
6
6
6
6
6
0x25
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B0263-01
HPR
HPL
Sub+
Sub–
Out_D
Out_C
Out_B
Out_A
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BQ (0x24)
Loudness (0x23)
Master Volume 0x07
Figure 29. TAS5706A DAP Data Flow Diagram With I2C Registers
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I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 30. I2S 64-fS Format
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2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
MSB
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
0
LSB
23 22
17 16
9
8
5
4
19 18
13 12
5
4
1
0
15 14
9
1
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
8
8
T0092-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 31. I2S 48-fS Format
2
2-Channel I S (Philips Format) Stereo Input
LRCLK
16 Clks
16 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
MSB
LSB
11 10
9
8
5
4
3
2
1
0
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
T0266-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 32. I2S 32-fS Format
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Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 33. Left-Justified 64-fS Format
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2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
21
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
1
0
MSB
LSB
21
17 16
9
8
5
4
19 18 17
13 12
5
4
1
0
15 14 13
9
1
0
23 22
1
0
20-Bit Mode
19 18 17
16-Bit Mode
15 14 13
8
8
T0092-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 34. Left-Justified 48-fS Format
2-Channel Left-Justified Stereo Input
16 Clks
16 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
MSB
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
T0266-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 35. Left-Justified 32-fS Format
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Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks
unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 36. Right Justified 64-fS Format
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2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
MSB
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
20-Bit Mode
16-Bit Mode
T0092-03
Figure 37. Right Justified 48-fS Format
Figure 38. Right Justified 32-fS Format
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I2C SERIAL CONTROL INTERFACE
The TAS5706A DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations.
This is a slave only device that does not support a multimaster bus environment or wait state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
General I2C Operation
The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is high to indicate a start and stop
conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal
data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 39.
The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5706A holds SDA low during the acknowledge
clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the
sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible
devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor
must be used for the SDA and SCL signals to set the high level for the bus.
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
2
Figure 39. Typical I C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 39.
The 7-bit address for TAS5706A is 0011 011 (0x36).
Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for status registers
and the general control registers associated with the PWM. However, for the DAP data processing registers, the
serial control interface supports only multiple-byte (4-byte) read/write operations.
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. If a write command is received for a biquad subaddress, the DAP
expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop
command (or another start command) is received, the data received is discarded. Similarly, if a write command is
received for a mixer coefficient, the DAP expects to receive one 32-bit word.
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Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5706A also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by
data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place,
and the data for all 16 subaddresses is successfully received by the TAS5706A. For I2C sequential write
transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted,
before a stop or start is transmitted, determines how many subaddresses are written. As was true for random
addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data
is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is
accepted; only the incomplete data is discarded.
Single-Byte Write
As shown in Figure 40, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device
address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the
address byte or bytes corresponding to the TAS5706A internal memory address being accessed. After receiving
the address byte, the TAS5706A again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5706A
again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 40. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 41. After receiving each data byte, the
TAS5706A responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
A6
A5
A4
A3
Subaddress
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-02
Figure 41. Multiple-Byte Write Transfer
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Single-Byte Read
As shown in Figure 42, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5706A address
and the read/write bit, TAS5706A responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the TAS5706A
address and the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After
receiving the address and the read/write bit, the TAS5706A again responds with an acknowledge bit. Next, the
TAS5706A transmits the data byte from the memory address being read. After receiving the data byte, the
master device transmits a not acknowledge followed by a stop condition to complete the single byte data read
transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
A5
A4
A0 ACK
A6
A5
A1
A0 R/W ACK D7
D6
2
Subaddress
I C Device Address and
Read/Write Bit
Not
Acknowledge
Acknowledge
D1
D0 ACK
Stop
Condition
Data Byte
I C Device Address and
Read/Write Bit
T0036-03
Figure 42. Single-Byte Read Transfer
Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5706A to the master device as shown in Figure 43. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
2
A0 R/W ACK A7
I C Device Address and
Read/Write Bit
Acknowledge
A6
A5
Subaddress
A6
A0 ACK
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 43. Multiple Byte Read Transfer
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Dynamic Range Control (DRC)
The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the
left/right channels and one DRC for the subwoofer channel.
DRC-Compensated Output
The DRC input/output diagram is shown in Figure 44.
k
1:1 Transfer Function
Implemented Transfer Function
T
DRC Input Level
M0091-01
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• One DRC for left/right and one DRC for subwoofer
• Each DRC has adjustable threshold, offset, and compression levels
• Programmable energy, attack, and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 44. Dynamic Range Control
Energy
Filter
Compression
Control
Attack
and
Decay
Filters
a, w
T, K, O
aa, wa / ad, wd
DRC1
0x3A
0x40, 0x41, 0x42
0x3B / 0x3C
DRC2
0x3D
0x43, 0x44, 0x45
0x3E / 0x3F
Audio Input
DRC Coefficient
Alpha Filter Structure
S
a
w
–1
Z
NOTE:
a=a
w=1–a
B0265-01
Figure 45. DRC Structure
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Loudness Function
The TAS5706A provides a direct form I biquad for loudness on the subwoofer channel. The first biquad is
contained in a gain-compensation circuit that maintains the overall system gain at 1 or less to prevent clipping at
loud volume settings. This gain compensation is shown in Figure 46
1 if Vol £ 1/G
0 if Vol ³ 1/G + 1/Scale
1 - Scale (Vol - 1/G) otherwise
From
Input
Mux
To
Output
Mux
Loudness
Biquad (0x23)
Gain = G
Volume
Biquad (0x24)
Scale = 1/(1 - 1/G)
0 if Vol £ 1/G
1 if Vol ³ 1/G + 1/Scale
Scale (Vol - 1/G) otherwise
B0273-01
Figure 46. Biquad Gain Control Structure
Table 1. Loudness Table Example for Gain = 4, 1/G = 0.25, Scale = 1.33
Volume
0.125
0.25
0.375
0.5
0.625
0.75
0.875
1
1.125
1.25
1.375
1.5
1.625
1.75
1.875
2
Biquad path
1
1
0.833
0.666
0.5
0.333
0.166
0
0
0
0
0
0
0
0
0
Direct path
0
0
0.166
0.333
0.5
0.666
0.833
1
1
1
1
1
1
1
1
1
Total gain
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The biquads are implemented in a direct form-I architecture. The direct form-I structure provides a separate delay
element and mixer (gain coefficient) for each node in the biquad filter.
The five 26-bit (3.23) coefficients for the biquad are programmable via the I2C interface.
The following steps are involved in using a loudness biquad with the volume compensation feature:
1. Program the biquad with a loudness filter.
2. Program 0x26 (1/G) and 0x28 (scale).
3. Enable volume compensation in register 0x0E.
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b0
x(n)
S
b1
z
a1
–1
z
b2
z
y(n)
Magnitude
Truncation
–1
a2
–1
z
–1
M0012-02
Figure 47. Biquad Filter
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BANK SWITCHING
The TAS5706A uses an approach called bank switching together with automatic sample-rate detection. All
processing features that must be changed for different sample rates are stored internally in the TAS5706A. The
TAS5706A has three full banks storing information, one for 32 kHz, one for 44.1/48 kHz, and one for all other
data rates. Combined with the clock-rate autodetection feature, bank switching allows the TAS5706A to detect
automatically a change in the input sample rate and switch to the appropriate bank without any MCU
intervention.
The TAS5706A supports three banks of coefficients to be updated during the initialization. One bank is for 32
kHz , a second bank is for 44.1/48 kHz, and a third bank is for all other sample rates. An external controller
updates the three banks (see the I2C register mapping table for bankable locations) during the initialization
sequence.
If the autobank switch is enabled (register 0x50, bits 2:0) , then the TAS5706A automatically swaps the
coefficients for subsequent sample rate changes, avoiding the need for any external controller intervention for a
sample rate change.
By default, bits 2:0 have the value 000; that means the bank switch is disabled. In that state, any update to
locations 0x29–0x3F go into the DAP. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the
system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any
subsequent write to locations 0x29-0x3F updates the coefficient banks stored outside the DAP. After updating all
the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes
the system state to automatic bank update. In automatic bank update, the TAS5706A automatically swaps banks
based on the sample rate.
In the headphone mode, speaker equalization and DRC are disabled, and they are restored upon returning to the
speaker mode.
Command sequences for initialization can be summarized as follows:
1. Enable factory trim for internal oscillator: Write to register 0x1B with a value 0x00.
2. Update coefficients: Coefficients can be loaded into DAP RAM using the manual bank mode.
OR
Use automatic bank mode.
a. Enable bank-1 mode: Write to register 0x50 with 0x01. Load the 32-kHz coefficients. TI ALE
can generate coefficients.
b. Enable bank-2 mode: Write to register 0x50 with 0x02. Load the 48-kHz coefficients.
c. Enable bank-3 mode: Write to register 0x50 with 0x03. Load the other coefficients.
d. Enable automatic bank switching by writing to register 0x50 with 0x04.
3. Bring the system out of all-channel shutdown: Write 0 to bit 6 of register 0x05.
4. Issue master volume: Write to register 0x07 with the volume value (0 db = 0x30).
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APPLICATION INFORMATION
Recovery From Error
Protection Mechanisms in the TAS5706A/B
• SCP (short-circuit protection, OCP) protects against shorts across the load, to GND, and to PVCC.
• OTP turns off the device if Tdie (typical) > 150°C.
• UVP turns off the device if PVCC (typical) < 8.4 V
• OVP turns off the device if PVCC (typical) > 27.5 V
A short-circuit condition can be detected also by an external controller. The SCP error from the external power
stage is also fed into TAS5706A/B. The VALID pin goes low in the event of a short circuit. The VALID pin can be
monitored by an external µC. The TAS5706A/B initiates a back-end error sequence by itself to recover from the
error, which involves settling VALID low for a programmable amount of time and then retrying to check whether
the SCP condition still exists.
• OTP turns on the device back when Tdie(typical) < 135°C.
• UVP turns on the device if PVCC (typical) is > 8.5 V.
• OVP turns on the device if PVCC (typical) is < 27.2 V.
Interchannel Delay (ICD) Settings
Recommended ICD Settings
Mode
Description
ICD1
ICD2
ICD3
ICD4
ICD5
ICD6
2.0 ch BD BTL
2 BTL channels, internal
power stage only, BD
mode
A(L+) = 19
(0x4C)
C(R+) = 13
(0x34)
B(L–) = 7
(0x1C)
D(R–) = 25
(0x64)
SM(S–) = –12 SP(S+) = –28
(0xD0)
(0x90)
2.1 ch AD BTL
2 internal BTL channels,
1 external BTL channel
using PBTL TAS5601,
AD mode
A(L+) = 23
(0x5C)
C(R+) = 9
(0x24)
B(L–) = 21
(0x54)
D(R–) = 11
(0x2C)
SM(S–) = –23 SP(S+) = –21
(0xA4)
(0xAC)
2.1 ch AD SE
2 internal SE channels (2
unused), 1 external BTL A(L+) = 15
channel using PBTL
(0x3C)
TAS5601, AD mode
B(R–) = –15
(0xC4)
B(0) = 0
(0x00)
D(0) = 0
(0x00)
SM(S–) = –30 SP(S+) = –32
(0x88)
(0x80)
2.1 ch BD BTL
2 internal BTL channels,
1 external BTL channel
using PBTL TAS5601,
BD mode
A(L+) = 19
(0x4C)
C(R+) = 13
(0x34)
B(L–) = 7
(0x1C)
D(R–) = 25
(0x64 )
SM(S–) = –12 SP(S+) = –28
(0xD0)
(0x90)
2 internal SE channels +
3.0 ch AD 2SE +
1 internal BTL channel,
1 BTL
AD mode
A(L+) = 15
(0x3C)
B(R–) = –16
(0xC0)
SM(0) = 0
(0x00)
SP(0) = 0
(0x00)
D(S–) = 0
(0x00)
C(S+) = 2
(0x08)
4.0 ch AD SE
4 internal SE channels
A(L1+) = 8
(=0x20)
B(R1–) = –24
(0xA0)
C(L2+) = –8
(0xE0)
D(R2–) = 24
(0x60)
SM(0) = 1
(0x04)
SP(0) = –1
(0xFC)
4.1 ch AD SE
4 internal SE channels +
1 external BTL channel,
using PBTL TAS5601,
AD mode.
A(L1+) = 8
(0x20)
B(R1–) = –24
(0xA0)
C(L2+) = –8
(xE0)
D(R2–)= 24
(0x60)
SM(S–) = 1
(0x04)
SP(S+) = –1
(0xFC)
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Calculation of Output Signal Level of TAS5706A/B Feedback Power Stage
(Gain Is independent of PVCC)
The gain of the TAS5706A/B is the total digital gain of the controller multiplied by the gain of the power stage.
For a half-bridge channel of the TAS5706A/B power stage, the gain is simply:
Power stage gain = 13 × VRMS / Modulation Level
Modulation level = fraction of full-scale modulation of the PWM signal at the input of the power stage.
VRMS = Audio voltage level at the output of the power stage = 13 × Modulation Level
For the TAS5706A/B controller, the gain is the programmed digital gain multiplied by a scaling factor, called the
maximum modulation level. The maximum modulation level is derived from the modulation limit programmed in
the controller, which limits duty cycle to a set number of percent above 0% and below 100%. Setting the
modulation limit to 97.7% (default) limits the duty cycle between 2.3% and 97.7%.
Controller gain = digital gain × maximum modulation level × (modulation level/digital FFS)
Digital FFS = digital input fraction of full scale
Modulation limit = 97.7%
Maximum modulation level = 2 × modulation limit – 1 = 0.954
The output signal level of the TAS5706A/B can now be calculated.
VRMS = digital FFS × digital gain × maximum modulation level × 13
With the modulation limit set at the default level of 97.7%, this becomes:
VRMS = digital FFS × digital gain × 12.4
(Single-ended)
VRMS = digital FFS × digital gain × 24.8
(BTL)
Example: Input = –20 dbFS; volume = 0 dB; biquads = ALL PASS; modulation index = 97.7%; mode = BTL
Output VRMS = 24.8 × 0.1 × 1 = 2.48 V
38
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I2C SERIAL CONTROL COMMAND CHARACTERISTICS
The DAP has two groups of I2C commands. One set is commands that are designed specifically to be operated
while audio is streaming and that have built-in mechanisms to prevent noise, clicks, and pops. The other set
does not have this built-in protection.
Commands that are designed to be adjusted while audio is streaming:
• Master volume
• Master mute
• Individual channel volume
• Individual channel mute
Commands that are normally issued as part of initialization:
• Serial data interface format
• De-emphasis
• Sample-rate conversion
• Input multiplexer
• Output multiplexer
• Biquads
• Down mix
• Channel delay
• Enable/disable dc blocking
• Hard/soft unmute from clock error
• Enable/disable headphone outputs
Start-up sequence for correct device operation
This sequence must be followed to ensure proper operation.
1. Hold ALL logic inputs low. Power up AVDD/DVDD and wait for the inputs to settle in the allowed range.
2. Drive PDN = 1, MUTE = 1, and drive other logic inputs to the desired state.
3. Provide a stable MCLK, LRCLK, and SCLK (clock errors must be avoided during the initialization sequence) .
4. After completing step 3, wait 100 µs, then drive RESET = 1, and wait 13.5 ms after RESET goes high.
5. Trim the internal oscillator (write 0x00 to register 0x1B).
6. Wait 50 ms while the part acquires lock.
7. Configure the DAP via I2C, e.g.:
– Downmix control (0x21)
– Biquads (0x23–0x24 and 0x29–0x38)
– DRC parameters and controls (0x3A–0x46)
– Bank select (0x50)
NOTE: User may not issue any I2C reads or writes to the above registers after this step is complete.
8. Configure remaining I2C registers, e.g.:
– Shutdown group
– De-emphasis
– Input multiplexers
– Output multiplexers
– Channel delays
– DC blocking
– Hard/soft unmute from clock error
– Serial data interface format
– Clock register (manual clock mode only)
NOTE: The BKND_ERR register (0x1C) can only be written once with a value that is not reserved (00
and 01 are reserved values).
9. Exit all-channel shutdown (write 0 to bit 6 of register 0x05).
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10. This completes the initialization sequence. From this step on, no further constraints are imposed on PDN,
MUTE, and clocks.
11. During normal operation the user may do the following:
a. Write to the master or individual-channel volume registers.
b. Write to the soft-mute register.
c. Write to the clock and serial data interface format registers (in manual clock mode only).
d. Write to bit 6 of register 0x05 to enter/exit all-channel shutdown. No other bits of register 0x05 may be
altered. After issuing the all-channel shutdown command, no further I2C transactions that address this
device are allowed for a period of at least: 1 ms + 1.3 × (period specified in start/stop register 0x1A) .
e. PDN may be asserted (low) at any time. Once PDN is asserted, no I2C transactions that address this
device may be issued until PDN has been deasserted and the part has returned to active mode.
NOTE: When the device is in a powered down state (initiated via PDN), the part is not reset if RESET
is asserted.
NOTE: Once RESET is asserted, and as long as the part is in a reset state, the part does not power
down if PDN is asserted. For powering the part down, a negative edge on PDN must be issued when
RESET is high and the part is not in a reset state.
NOTE: No registers besides those explicitly listed in Steps a.–d. should be altered during normal
operation (i.e., after exiting all-channel shutdown).
NOTE: No registers should be read during normal operation (i.e., after exiting all-channel shutdown) .
12. To reconfigure registers:
a. Return to all-channel shutdown (observe the shutdown wait time as specified in Step 11.d.).
b. Drive PDN = 1, and hold MUTE stable.
c. Provide a stable MCLK, LRCLK, and SCLK.
d. Repeat configuration starting from step (6).
Table 2. Serial Control Interface Register Summary
SUBADDRESS
NO. OF
BYTES
REGISTER NAME
(1)
INITIALIZATION
VALUE
CONTENTS
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x2A
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface
register
1
Description shown in subsequent section
0x05
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Channel 3 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0B
Channel 4 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0C
HP volume
1
Description shown in subsequent section
0x30 (0 dB)
0x0D
Channel 6 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0E
Volume configuration
register
1
Description shown in subsequent section
0x91
1
Reserved (2)
0x0F
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0x4C
(1)
(2)
Biquad definition is given in Figure 47.
Reserved registers should not be accessed.
40
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Table 2. Serial Control Interface Register Summary (continued)
SUBADDRESS
NO. OF
BYTES
REGISTER NAME
0x12
IC delay channel 2
1
Description shown in subsequent section
0x34
0x13
IC delay channel 3
1
Description shown in subsequent section
0x1C
0x14
IC delay channel 4
1
Description shown in subsequent section
0x64
0x15
IC delay channel 5
1
Description shown in subsequent section
0xB0
0x16
IC delay channel 6
1
Description shown in subsequent section
0x90
0x17
Offset register
1
Reserved
0x00
1
Reserved (2)
0x18
0x19
PWM shutdown group
register
1
0x30
0x1A
Start/stop period register
1
0x0A
0x1B
Oscillator trim register
1
0x82
0x1C
BKND_ERR register
1
0x1D–0x1F
0x02
Reserved
(2)
0x20
Input MUX register
4
Description shown in subsequent section
0x0089 777A
0x21
Downmix input MUX
register
4
Description shown in subsequent section
0x0000 4203
0x22
AM tuned frequency
4
Description shown in subsequent section
0x0000 0000
0x23
ch6_bq[2] (Loudness BQ)
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
Description shown in subsequent section
0x0102 1345
u[31:26], x[25:0]
0x0080 0000
0x24
ch6_bq[3] (post volume
BQ)
0x25
PWM MUX register
0x26
1/G register
20
4
0x27
(3)
1
Reserved
0x28
Scale register
4
u[31:26], x[25:0]
0x0080 0000
0x29
ch1_bq[0]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x2A
0x2B
(3)
INITIALIZATION
VALUE
CONTENTS
ch1_bq[1]
20
ch1_bq[2]
20
Reserved registers should not be accessed.
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Table 2. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
42
REGISTER NAME
ch1_bq[3]
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
ch2_bq[0]
ch2_bq[1]
ch2_bq[2]
ch2_bq[3]
ch2_bq[4]
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
CONTENTS
INITIALIZATION
VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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Table 2. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x35
0x36
0x37
0x38
NO. OF
BYTES
REGISTER NAME
ch2_bq[5]
20
ch2_bq[6]
20
ch6_bq[0]
20
ch6_bq[1]
20
0x39
0x3A
DRC1 ae
0x3B
DRC1 aa
0x3D
DRC2 ae
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x0080 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
u[31:26], (1 – ad)[25:0]
0x0000 0000
u[31:26], ae[25:0]
0x0080 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
8
8
DRC 2 (1 – ae)
8
DRC2 (1 – aa)
8
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
0x3F
DRC2 ad
u[31:26], (1 – ad)[27::0]
0x0000 0000
0x40
DRC1-T
4
T1[31:0]
0xFDA2 1490
0x41
DRC1-K
4
u[31:26], k1[25:0]
0x0384 2109
0x42
DRC1-O
4
u[31:24], O[23:16], O1[15:0]
0x0008 4210
0x43
DRC2-T
4
T2[31:0]
0xFDA2 1490
0x44
DRC2-K
4
u[31:24], k2'[22:0]
0x0384 2109
0x45
DRC2-O
4
u[31:24], O2[25:0]
0x0008 4210
0x46
DRC control
DRC2 (1 – ad)
4
u[31:2], ch6[1], ch1_5[0]
0x0000 0000
0x47–0x49
4
Reserved (4)
0x0000 0000
0x50
4
Bank update command register
0x0000 0000
0x51–0xFF
(4)
0x0000 0000
u[31:26], ae[25:0]
8
DRC2 aa
0x0080 0000
8
DRC1 (1 – ad)
0x3E
u[31:26], b0[25:0]
u[31:26], b1[25:0]
Reserved (4)
DRC1 (1 – aa)
DRC1 ad
INITIALIZATION
VALUE
4
DRC1 (1 – ae)
0x3C
CONTENTS
4
Reserved
(4)
0x0000 0000
Reserved registers should not be accessed.
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CLOCK CONTROL REGISTER (0x00)
In the manual mode, the clock control register provides a way for the system microprocessor to update the data
and clock rates based on the sample rate and associated clock frequencies. In the auto-detect mode, the clocks
are automatically determined by the TAS5706A. In this case, the clock control register contains the auto-detected
clock status as automatically detected (D7–D2). Bits D7–D5 selects the sample rate. Bits D4–D2 select the
MCLK frequency. Bit D0 is used in manual mode only. In this mode, when the clocks are updated a 1 must be
written to D0 to inform the DAP that the written clocks are valid.
Table 3. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
fS = 32-kHz sample rate
FUNCTION
0
0
1
–
–
–
–
–
fS = 38-kHz sample rate
0
1
0
–
–
–
–
–
fS = 44.1-kHz sample rate
0
1
1
–
–
–
–
–
fS = 48-kHz sample rate
1
0
0
–
–
–
–
–
fS = 88.2-kHz sample rate
1
0
1
–
–
–
–
–
fS = 96-kHz sample rate
1
1
0
–
–
–
–
–
fS = 176.4-kHz sample rate
1
1
1
–
–
–
–
–
fS = 192-kHz sample rate
–
–
–
0
0
0
–
–
MCLK frequency = 64 × fS (2)
–
–
–
0
0
1
–
–
MCLK frequency = 128 × fS (3)
–
–
–
0
1
0
–
–
MCLK frequency = 192 × fS
–
–
–
0
1
1
–
–
MCLK frequency = 256 × fS
(1)
(1)
(4)
–
–
–
1
0
0
–
–
MCLK frequency = 384 × fS
–
–
–
1
0
1
–
–
MCLK frequency = 512 × fS (4)
–
–
–
1
1
0
–
–
Reserved
–
–
–
1
1
1
–
–
Reserved
–
–
–
–
–
–
1
–
Bit clock (SCLK) frequency = 48 × fS (5)
–
–
–
–
–
–
0
–
Bit clock (SCLK) frequency = 64 × fS or 32 × fS (selected in register
0x04) (1)
–
–
–
–
–
–
–
0
Clock not valid (in manual mode only)
–
–
–
–
1
Clock valid (in manual mode only)
(1)
(2)
(3)
(4)
(5)
(1)
Default values are in bold.
Rate not available for 32-, 44.1-, and 48-kHz data rates
Rate not available for 32-kHz data rate
Rate not available for 176.4-kHz and 192-kHz data rates
Rate only available for 192-fS and 384-fS MCLK frequencies
DEVICE ID REGISTER (0x01)
The device ID register contains the ID code for the firmware revision.
Table 4. Device ID Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
Default
–
0
1
0
1
0
1
0
Identification code
(1)
44
FUNCTION
(1)
Default values are in bold.
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ERROR STATUS REGISTER (0x02)
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must
clear the register (write zeroes) and then read them to determine if there are any persistent errors.
Table 5. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
–
–
MCLK error
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
0
0
0
0
0
0
0
0
No errors
(1)
FUNCTION
(1)
Default values are in bold.
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must
clear the register (write zeroes) and then read them to determine if there are any persistent errors.
Table 6. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
0
0
0
0
0
0
0
0
No errors
(1)
FUNCTION
(1)
Default values are in bold.
SYSTEM CONTROL REGISTER 1 (0x03)
The system control register 1 has several functions:
Bit D7:
If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff
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