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TAS5731M
SLOS838C – JULY 2013 – REVISED AUGUST 2015
TAS5731M 2 × 30-W Digital Audio Power Amplifier With DSP and 2.1 Mode
1 Features
•
•
•
•
1
•
•
•
•
•
3 Description
The TAS5731M is a 30-W, efficient, digital-audio
stereo power amplifier for driving stereo bridge-tied
speakers. One serial data input allows processing of
up to two discrete audio channels and seamless
integration to most digital audio processors and
MPEG decoders. The device accepts a wide range of
input data and data rates. A fully programmable data
path routes these channels to the internal speaker
drivers.
2
2-Ch I S Input; 8-kHz to 48-kHz fS
30-W Stereo, 8 Ω/24 V (THD+N = 10%)
Up to 90% Efficient Operation
Wide 8-V to- 24-V Supply Range; 3.3-V Digital
Supply
Single-Device 2.1 Support (2 × SE + 1 × BTL)
80-mΩ RDS(on) Device That Can Support 2-Ω SE
and 4-Ω BTL Modes
– 12 V, 2 Ω, 8 W With SE mode
– 12 V, 4 Ω, 15 W With BTL mode
Speaker EQ (8 BQ per Channel), 2× DRCs
Pin-to-Pin Compatible With the TAS5727 and
TAS5731
Benefits:
– Direct Connect to Digital Processor
– High Output Power From a Standard Supply
– Eliminates the Need for Heat Sink
– Advanced Processing Improves Audio
Experience
The TAS5731M is a slave-only device receiving all
clocks from external sources. The TAS5731M
operates with a PWM carrier between a 384-kHz
switching rate and a 352-kHz switching rate,
depending on the input sample rate. Oversampling
combined with a fourth-order noise shaper provides a
flat noise floor and excellent dynamic range from
20 Hz to 20 kHz.
Device Information(1)
PART NUMBER
PACKAGE
TAS5731M
BODY SIZE (NOM)
HTQFP (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
LCD TV
LED TV
Sound Bar
space
Power vs Supply Voltage (2.0 BTL Mode)
Power vs Supply Voltage (PBTL Mode)
40
80
RL = 4
70
30
60
25
50
Power (W)
Power (W)
PBTL Mode
2.0 BTL Mode
RL = 8
TA = 25C
35
20
40
15
30
10
20
2 Layer Continuous Power
5
TA = 25C
2 Layer Continuous Power
10
4 Layer Continuous Power
4 Layer Continuous Power
Instantaneous Power
0
8
10
12
14
16
18
20
22
Instantaneous Power
0
24
Supply Voltage (V)
8
10
12
14
16
18
20
22
24
Supply Voltage (V)
C014
C039
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5731M
SLOS838C – JULY 2013 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6
7.1
7.2
7.3
7.4
7.5
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
PWM Operation at Recommended Operating
Conditions .................................................................. 7
7.6 DC Electrical Characteristics .................................... 8
7.7 AC Electrical Characteristics (BTL, PBTL)................ 9
7.8 Electrical Characteristics - PLL External Filter
Components............................................................... 9
7.9 Electrical Characteristic - I2C Serial Control Port
Operation ................................................................... 9
7.10 Timing Requirements - PLL Input Parameters ..... 10
7.11 Timing Requirements - Serial Audio Ports Slave
Mode ........................................................................ 10
7.12 Timing Requirements - I2C Serial Control Port
Operation ................................................................ 10
7.13 Timing Requirements - Reset (RESET)................ 10
7.14 Typical Characteristics .......................................... 13
8
9
Parameter Measurement Information ................ 21
Detailed Description ............................................ 21
9.1
9.2
9.3
9.4
9.5
9.6
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
21
21
24
34
36
41
10 Application and Implementation........................ 59
10.1 Application Information.......................................... 59
10.2 Typical Applications .............................................. 59
11 Power Supply Recommendations ..................... 69
11.1 DVDD and AVDD Supplies ................................... 69
11.2 PVDD Power Supply ............................................. 69
12 Layout................................................................... 69
12.1 Layout Guidelines ................................................. 69
12.2 Layout Examples................................................... 70
13 Device and Documentation Support ................. 73
13.1
13.2
13.3
13.4
13.5
13.6
Device Support ....................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
73
73
73
73
73
73
14 Mechanical, Packaging, and Orderable
Information ........................................................... 73
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2013) to Revision C
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision A (November 2013) to Revision B
•
2
Page
Page
Changed "2 × 20-W" to "2 × 30-W" in the Title, Features, and Description ........................................................................... 1
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5 Device Comparison Table
TAS5731M
TAS5729MD
TAS5721
TAS5717
TAS5711
Max Power to SingleEnded Load
18
Max Power to Bridge
Tied Load
37
20
15
Max Power to Parallel
Bridge Tied Load
70
40
30
40
Min Supported SingleEnded Load
2
4
4
Min Supported Bridge
Tied Load
4
4
8
Min Supported Parallel
Bridge Tied Load
2
4
4
Closed/Open Loop
Open
Open
Open
Max Speaker Outputs
3
Headphone Channels
10
TAS5707
16
10
20
4
6
20
6
4
Open
Open
Open
3
2
2
3
2
Yes
Yes
Yes
Architecture
Class D
Class D
Class D
Class D
Class D
Class D
Dynamic Range Control
(DRC)
2-Band
2-Band AGL
2-Band
2-Band AGL
2-Band
Single-Band
Biquads (EQ)
21
28
21
28
21
14
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6 Pin Configuration and Functions
PGND_CD
PGND_CD
NC
OUT_C
BST_C
NC
NC
BST_B
NC
PGND_AB
OUT_B
PGND_AB
PHP Package
48-Pin HTQFP
Top View
48 47 46 45 44 43 42 41 40 39 38 37
OUT_A
1
36
OUT_D
PVDD_AB
2
35
PVDD_CD
PVDD_AB
3
34
PVDD_CD
BST_A
4
33
BST_D
NC
5
32
GVDD_OUT
SSTIMER
6
31
VREG
30
AGND
TAS5731M
NC
7
PBTL
8
29
GND
AVSS
9
28
DVSS
PLL_FLTM
10
27
DVDD
PLL_FLTP
11
26
STEST
VR_ANA
12
25
RESET
SCL
SDA
SDIN
SCLK
PDN
LRCLK
VR_DIG
DVSSO
OSC_RES
MCLK
ADR/FAULT
AVDD
13 14 15 16 17 18 19 20 21 22 23 24
P0075-25
Pin Functions
PIN
NAME
NO.
TYPE (1)
AGND
30
P
ADR/FAULT
14
DIO
(1)
(2)
4
5-V
TERMINATION (2)
TOLERANT
DESCRIPTION
Local analog ground for power stage, which must be connected to
the system ground.
Dual function terminal which sets the LSB of the 7-bit I2C address to
"0" if pulled to GND and to "1" if pulled to DVDD. If configured to be
a fault output by the methods described in I²C Address Selection and
Fault Output, this terminal is pulled low when an internal fault occurs.
A pull-up or pull-down resistor is required, as is shown in the Typical
Application Circuit Diagrams. If pulled high (to DVDD), a 15-kΩ
resistor must be used to minimize in-rush current at power up and to
isolate the net if the pin is used as a fault output, as described
above.
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
All pullups are 20-µA weak pullups and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pull-ups → logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 µA while maintaining a logic-1 drive level.
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Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
5-V
TERMINATION (2)
TOLERANT
DESCRIPTION
AVDD
13
P
3.3-V analog power supply
AVSS
9
P
Analog 3.3-V supply ground
BST_A
4
P
High-side bootstrap supply for half-bridge A
BST_B
43
P
High-side bootstrap supply for half-bridge B
BST_C
42
P
High-side bootstrap supply for half-bridge C
BST_D
33
P
High-side bootstrap supply for half-bridge D
DVDD
27
P
3.3-V digital power supply
DVSS
28
P
Digital ground
DVSSO
17
P
Oscillator ground
GND
29
P
Analog ground for power stage
GVDD_OUT
32
P
LRCLK
20
DI
5-V
Pulldown
Input serial audio data left/right clock (sample-rate clock)
MCLK
15
DI
5-V
Pulldown
Master clock input
5, 7,
40,
41,
44, 45
–
OSC_RES
16
AO
OUT_A
1
O
Output, half-bridge A
OUT_B
46
O
Output, half-bridge B
OUT_C
39
O
Output, half-bridge C
OUT_D
36
O
PBTL
8
DI
PDN
19
DI
PGND_AB
47, 48
P
Power ground for half-bridges A and B
PGND_CD
37, 38
P
Power ground for half-bridges C and D
PLL_FLTM
10
AO
PLL negative loop-filter terminal
PLL_FLTP
11
AO
PLL positive loop-filter terminal
PVDD_AB
2, 3
P
PVDD_CD
34, 35
P
RESET
25
DI
5-V
SCL
24
DI
5-V
SCLK
21
DI
5-V
SDA
23
DIO
5-V
SDIN
22
DI
5-V
SSTIMER
6
AI
Controls ramp time of OUT_x to minimize pop. Leave this pin
floating for BD mode. Requires capacitor of 2.2 nF to GND in AD
mode. The capacitor determines the ramp time.
STEST
26
DI
Factory test pin. Connect directly to DVSS.
VR_ANA
12
P
Internally regulated 1.8-V analog supply voltage. This pin must not
be used to power external devices.
VR_DIG
18
P
Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
NC
Gate drive internal regulator output
No connect
Oscillator trim resistor. Connect an 18.2-kΩ, 1% resistor to DVSSO.
Output, half-bridge D
5-V
Pulldown
Low means BTL mode; high means PBTL mode. Information goes
directly to power stage.
Pullup
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating the PWM
stop sequence.
Power-supply input for half-bridge output A and B
Power-supply input for half-bridge output C and D
Pullup
Reset, active-low. A system reset is generated by applying a logic
low to this pin. RESET is an asynchronous control signal that
restores the DAP to its default conditions and places the PWM in the
hard-mute (high-impedance) state.
I2C serial control clock input
Pulldown
Serial audio-data clock (shift clock). SCLK is the serial-audio-port
input-data bit clock.
I2C serial control data interface input/output
Pulldown
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
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Pin Functions (continued)
PIN
NAME
NO.
VREG
TYPE (1)
31
PowerPAD™
5-V
TERMINATION (2)
TOLERANT
DESCRIPTION
P
Digital regulator output. Not to be used for powering external
circuitry.
P
Provides both electrical and thermal connection from the device to
the board. A matching ground pad must be provided on the PCB and
the device connected to it via solder. For proper electrical operation,
this ground pad must be connected to the system ground
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply
voltage
Input voltage
(1)
MIN
MAX
UNIT
DVDD, AVDD
–0.3
4.2
V
PVDD_x
–0.3
30
V
3.3-V digital input
–0.5
DVDD + 0.5
5-V tolerant (2) digital input (except MCLK)
–0.5
DVDD + 2.5 (3)
5-V tolerant MCLK input
–0.5
AVDD + 2.5 (3)
OUT_x to PGND_x
32 (4)
BST_x to PGND_x
(4)
39
V
V
V
Input clamp current, IIK
–20
20
mA
Output clamp current, IOK
–20
20
mA
Operating free-air temperature
0
85
°C
Operating junction temperature
0
150
°C
–40
125
°C
Storage temperature, Tstg
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
Maximum pin voltage must not exceed 6 V.
DC voltage + peak ac waveform measured at the pin must be below the allowed limit for all conditions.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
6
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
MIN
NOM
MAX
Digital/analog supply voltage
DVDD, AVDD
3
3.3
3.6
V
Half-bridge supply voltage
PVDD_x
8
26.4 (1)
V
VIH
High-level input voltage
5-V tolerant
2
VIL
Low-level input voltage
5-V tolerant
0.8
V
TA
Operating ambient temperature range
0
85
°C
TJ (2)
Operating junction temperature range
0
125
°C
RL (PBTL)
Load impedance
Output filter: L = 15 μH, C = 680 nF
2
Ω
RL (BTL)
Load impedance
Output filter: L = 15 μH, C = 680 nF
4
Ω
RL (SE)
Load impedance
Output filter: L = 15 μH, C = 680 nF
2
Ω
LO
Output-filter inductance
Minimum output inductance under shortcircuit condition
10
μH
(1)
(2)
UNIT
V
For operation at PVDD_x levels greater than 18 V, the modulation limit must be set to 93.8% through the control port register 0x10.
Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
7.4 Thermal Information
TAS5731M
THERMAL METRIC
(1)
PHP (HTQFP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
27.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
1.1
°C/W
RθJB
Junction-to-board thermal resistance
13
°C/W
ψJT
Junction-to-top characterization parameter
20.7
°C/W
ψJB
Junction-to-board characterization parameter
0.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 PWM Operation at Recommended Operating Conditions
PARAMETER
Output PWM switch frequency
TEST CONDITIONS
VALUE
11.025/22.05/44.1-kHz data rate ±2%
352.8
48/24/12/8/16/32-kHz data rate ±2%
384
UNIT
kHz
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7.6 DC Electrical Characteristics
TA = 25°, PVDD_x = 18 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL AD mode, fS = 48 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
ADR/FAULT and SDA
IOH = –4 mA
DVDD = 3 V
VOL
Low-level output voltage
ADR/FAULT and SDA
IOL = 4 mA
DVDD = 3 V
0.5
V
IIL
Low-level input current
VI < VIL;
DVDD = AVDD = 3.6 V
75
μA
IIH
High-level input current
VI > VIH;
DVDD = AVDD = 3.6 V
75 (1)
μA
IDD
3.3-V supply current
3.3-V supply voltage (DVDD,
AVDD)
IPVDD
Supply current
No load (PVDD_x)
Drain-to-source resistance, LS
TJ = 25°C, includes metallization resistance
80
Drain-to-source resistance, HS
TJ = 25°C, includes metallization resistance
80
6.4
rDS(on) (2)
2.4
V
Normal mode
49
68
Reset (RESET = low,
PDN = high)
23
38
Normal mode
32
50
4
8
Reset (RESET = low,
PDN = high)
mA
mA
mΩ
I/O PROTECTION
Vuvp
Undervoltage protection limit
PVDD falling
Vuvp,hyst
Undervoltage protection limit
PVDD rising
OTE (3)
Overtemperature error
OTEHYST (3)
Extra temperature drop
required to recover from error
IOC
Overcurrent limit protection
IOCT
Overcurrent response time
(1)
(2)
(3)
8
Output to output short in BTL mode
V
7.1
V
150
°C
30
°C
4.5
A
150
ns
IIH for the PBTL pin has a maximum limit of 200 µA due to an internal pulldown on the pin.
This does not include bond-wire or pin resistance.
Specified by design.
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7.7 AC Electrical Characteristics (BTL, PBTL)
PVDD_x = 18 V, BTL AD mode, fS = 48 kHz, RL = 8 Ω, CBST = 10 nF, audio frequency = 1 kHz, AES17 filter,
fPWM = 384 kHz, TA = 25°C (unless otherwise noted). All performance is in accordance with recommended operating
conditions (unless otherwise noted).
PARAMETER
PO
TEST CONDITIONS
Power output per channel
MIN
TYP
BTL mode, PVDD = 8 V, RL = 8 Ω, 7% THD
3.9
BTL mode, PVDD = 8 V, RL = 8 Ω,10% THD
4.2
BTL mode, PVDD = 12 V, RL = 8 Ω, 7% THD
8
BTL mode, PVDD = 12 V, RL = 8 Ω,10% THD
9.6
BTL mode, PVDD = 18 V, RL = 8 Ω, 7% THD
18.7
BTL mode, PVDD = 18 V, RL = 8 Ω, 10% THD
21.2
BTL mode, PVDD = 24 V, RL = 8 Ω, 7% THD
32.6
BTL mode, PVDD = 24 V, RL = 8 Ω, 10% THD
37.2
PBTL mode, PVDD = 12 V, RL = 4 Ω, 7% THD
16.5
PBTL mode, PVDD = 12 V, RL = 4 Ω, 10% THD
17.9
PBTL mode, PVDD = 18 V, RL = 4 Ω, 7% THD
Vn
PBTL mode, PVDD = 24 V, RL = 4 Ω, 10% THD
66
PBTL mode, PVDD = 24 V, RL = 4 Ω, 10% THD
69.6
SE Mode, PVDD = 12 V, RL = 4 Ω, 7% THD
4.2
SE Mode, PVDD = 12 V, RL = 4 Ω, 10% THD
4.6
SE Mode, PVDD = 18 V, RL = 4 Ω, 7% THD
9.6
SE Mode, PVDD = 18 V, RL = 4 Ω, 10% THD
10.2
SE Mode, PVDD = 24 V, RL = 4 Ω, 7% THD
17.1
SNR
(1)
0.15%
PVDD = 12 V, PO = 1 W
0.03%
PVDD = 18 V, PO = 1 W
0.04%
PVDD = 24 V, PO = 1 W
0.1%
46
μV
PO = 0.25 W, f = 1 kHz (AD Mode)
–67
dB
A-weighted, f = 1 kHz, maximum power at THD
< 1%
104
dB
A-weighted
Cross-talk
Signal-to-noise ratio
18.1
PVDD = 8 V, PO = 1 W
Output integrated noise (rms)
(1)
W
39.6
SE Mode, PVDD = 24 V, RL = 4 Ω, 10% THD
Total harmonic distortion + noise
UNIT
37
PBTL mode, PVDD = 18 V, RL = 4 Ω, 10% THD
THD+N
MAX
SNR is calculated relative to 0-dBFS input level.
7.8 Electrical Characteristics - PLL External Filter Components
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
External PLL filter capacitor C1
SMD 0603 X7R
47
nF
External PLL filter capacitor C2
SMD 0603 X7R
4.7
nF
External PLL filter resistor R
SMD 0603, metal film
470
Ω
7.9 Electrical Characteristic - I2C Serial Control Port Operation
for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
CL
TEST CONDITIONS
Load capacitance for each bus line
MIN
TYP
MAX
UNIT
400
pF
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7.10 Timing Requirements - PLL Input Parameters
PARAMETER
fMCLKI
tr/tf(MCLK)
TEST CONDITIONS
MIN
MCLK frequency
2.8224
MCLK duty cycle
40%
TYP
50%
MAX
UNIT
24.576
MHz
60%
Rise/fall time for MCLK
5
ns
LRCLK allowable drift before LRCLK reset
4
MCLKs
7.11 Timing Requirements - Serial Audio Ports Slave Mode
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
CL = 30 pF
TYP
1.024
MAX
UNIT
12.288
MHz
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
LRCLK frequency
ns
8
48
48
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
SCLK rising edges between LRCLK rising
edges
t(edge)
LRCLK clock edge with respect to the falling
edge of SCLK
tr/tf
Rise/fall time for SCLK/LRCLK
kHz
32
64
SCLK
edges
–1/4
1/4
SCLK
period
8
ns
7.12 Timing Requirements - I2C Serial Control Port Operation
for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
No wait states
MAX
UNIT
400
kHz
fSCL
Frequency, SCL
tw(H)
Pulse duration, SCL high
0.6
tw(L)
Pulse duration, SCL low
1.3
tr
Rise time, SCL and SDA
300
ns
tf
Fall time, SCL and SDA
300
ns
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
t(buf)
μs
μs
100
ns
0
ns
Bus free time between stop and start conditions
1.3
μs
tsu2
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tsu3
Setup time, SCL to stop condition
0.6
μs
7.13 Timing Requirements - Reset (RESET)
control signal parameters over recommended operating conditions (unless otherwise noted).
PARAMETER
tw(RESET)
Pulse duration, RESET active
td(I2C_ready)
Time to enable I2C
10
MIN
TYP
MAX
12
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UNIT
μs
100
ms
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tr
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 1. Slave-Mode Serial Data-Interface Timing
tw(H)
tw(L)
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 2. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 3. Start and Stop Conditions Timing
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RESET
tw(RESET)
2
2
I C Active
I C Active
td(I2C_ready)
System Initialization.
2
Enable via I C.
T0421-01
NOTES: On power up, it is recommended that the TAS5731M RESET be held LOW for at least 100 μs after DVDD has
reached 3 V.
If RESET is asserted LOW while PDN is LOW, then RESET must continue to be held LOW for at least 100 μs after
PDN is deasserted (HIGH).
Figure 4. Reset Timing
12
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7.14 Typical Characteristics
7.14.1 Typical Characteristics, 2.1 SE Configuration, 4 Ω
18
14
2.1 SE Mode
PVDD = 12V
f = 1kHz
TA = 25C
1
12
THD+N (%)
Output Power (W)
10
RL = 2î8THD+N = 1%
RL = 2î8THD+N = 10%
RL = 2î4THD+N = 1%
RL = 2î4THD+N = 10%
RL = 2î4THD+N = 1%
RL = 2î4THD+N = 10%
16
10
8
0.1
6
0.01
4
RL = 2î8
2
RL = 2î4
2.1 SE Mode
TA = 25C
RL = 2î4
0
8
10
12
14
16
18
20
22
0.001
0.01
24
0.1
Supply Voltage (V)
1
10
Output Power (W)
C016
Figure 5. Output Power vs Supply Voltage (2.1 SE Mode)
With 2 × 4ω + 4ω Load on Typical 2 Layer PCB Device
May Be Thermally Limited Above 20 V
C017
Figure 6. Total Harmonic Distortion + Noise vs Output
Power (2.1 SE Mode)
10
10
2.1 SE Mode
PVDD = 18V
f = 1kHz
TA = 25C
2.1 SE Mode
PVDD = 24V
f = 1kHz
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
RL = 2î8
RL = 2î8
RL = 2î4
RL = 2î4
RL = 2î4
RL = 2î4
0.001
1
0.001
0.01
10
0.1
Output Power (W)
1
10
Figure 7. Total Harmonic Distortion + Noise vs Output
Power (2.1 SE Mode)
C019
Figure 8. Total Harmonic Distortion + Noise vs Output
Power (2.1 SE Mode)
10
10
RL = 2î8
2.1 SE Mode
PO = 1W
PVDD = 12V
TA = 25C
RL = 2î8
2.1 SE Mode
PO = 1W
PVDD = 18V
TA = 25C
RL = 2î4
RL = 2î4
RL = 2î4
RL = 2î4
1
THD+N (%)
1
THD+N (%)
100
Output Power (W)
C018
0.1
0.01
0.1
0.01
0.001
0.001
20
200
2k
20k
20
Frequency (Hz)
200
2k
20k
Frequency (Hz)
C020
Figure 9. Total Harmonic Distortion + Noise vs Frequency
(2.1 SE Mode)
C021
Figure 10. Total Harmonic Distortion + Noise vs Frequency
(2.1 SE Mode)
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Typical Characteristics, 2.1 SE Configuration, 4 Ω (continued)
10
100
RL = 2î8
2.1 SE Mode
PO = 1W
PVDD = 24V
TA = 25C
90
RL = 2î4
RL = 2î4
80
1
2.1 SE Mode
RL = 2î8+8
TA = 25C
Efficiency (%)
THD+N (%)
70
0.1
60
50
40
30
0.01
20
PVDD = 12V
PVDD = 18V
10
PVDD = 24V
0
0.001
20
200
2k
20k
0
20
Frequency (Hz)
40
60
80
Total Output Power (W)
C022
Figure 11. Total Harmonic Distortion + Noise vs
Frequency (2.1 SE Mode)
100
0
90
±10
80
±20
2.1 SE Mode
RL = 2î4+8
TA = 25C
Right-to-Left
2.1 SE Mode
PO = 1W
PVDD = 12V
RL = 2î8+8
TA = 25C
Left-to-Right
±30
Crosstalk (dB)
70
Efficiency (%)
C023
Figure 12. Efficiency vs Total Output Power (2.1 SE Mode)
60
50
40
±40
±50
±60
±70
30
20
±80
PVDD = 12V
PVDD = 18V
10
±90
PVDD = 24V
±100
0
0
20
40
60
20
80
200
2k
C025
C024
Figure 13. Efficiency vs Total Output Power (2.1 SE Mode)
Figure 14. Crosstalk vs Frequency (2.1 SE Mode)
0
0
Right-to-Left
2.1 SE Mode
PO = 1W
PVDD = 12V
RL = 2î4+4
TA = 25C
±10
±20
±20
Left-to-Right
±30
Crosstalk (dB)
Crosstalk (dB)
Right-to-Left
2.1 SE Mode
PO = 1W
PVDD = 24V
RL = 2î8+8
TA = 25C
±10
Left-to-Right
±30
±40
±50
±60
±40
±50
±60
±70
±70
±80
±80
±90
±90
±100
±100
20
200
2k
20k
20
Frequency (Hz)
200
2k
20k
Frequency (Hz)
C026
Figure 15. Crosstalk vs Frequency (2.1 SE Mode)
14
20k
Frequency (Hz)
Total Output Power (W)
C027
Figure 16. Crosstalk vs Frequency (2.1 SE Mode)
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Typical Characteristics, 2.1 SE Configuration, 4 Ω (continued)
0
Right-to-Left
2.1 SE Mode
PO = 1W
PVDD = 24V
RL = 2î4+4
TA = 25C
±10
±20
Left-to-Right
Crosstalk (dB)
±30
±40
±50
±60
±70
±80
±90
±100
20
200
2k
20k
Frequency (Hz)
C028
Figure 17. Crosstalk vs Frequency (2.1 SE Mode)
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7.14.2 Typical Characteristics, 2.0 BTL Configuration, 8 Ω
45
10
2.0 BTL Mode
TA = 25C
40
2.0 BTL Mode
PVDD = 12V
f = 1kHz
TA = 25C
1
30
THD+N (%)
Output Power (W)
35
25
20
0.1
15
0.01
10
RL = 8THD+N = 1%
RL = 8THD+N = 10%
RL = 6THD+N = 1%
RL = 6THD+N = 10%
RL = 4THD+N = 1%
RL = 4THD+N = 10%
5
0
8
10
12
14
16
18
20
22
RL = 8
RL = 6
RL = 4
0.001
0.01
24
0.1
Supply Voltage (V)
1
10
100
Output Power (W)
C001
Figure 18. Output Power vs Supply Voltage (2.0 BTL Mode)
With 4ω Load on Typical 2 Layer PCB Device May Be
Thermally Limited Above 20 V
C002
Figure 19. Total Harmonic Distortion + Noise vs Output
Power (2.0 BTL Mode)
10
10
2.0 BTL Mode
PVDD = 18V
f = 1kHz
TA = 25C
2.0 BTL Mode
PVDD = 24V
f = 1kHz
TA = 25C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
RL = 8
RL = 8
RL = 6
RL = 6
RL = 4
0.001
0.01
0.1
1
10
RL = 4
0.001
0.01
100
0.1
Output Power (W)
1
10
Output Power (W)
C003
Figure 20. Total Harmonic Distortion + Noise vs Output
Power (2.0 BTL Mode)
C004
Figure 21. Total Harmonic Distortion + Noise vs Output
Power (2.0 BTL Mode)
10
10
RL = 4
2.0 BTL Mode
PVDD = 12V
PO = 1W
TA = 25C
RL = 8
RL = 6
RL = 8
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
0.001
0.001
20
200
2k
20k
20
Frequency (Hz)
200
2k
20k
Frequency (Hz)
C006
Figure 22. Total Harmonic Distortion vs Frequency (2.0
BTL Mode)
16
RL = 4
2.0 BTL Mode
PVDD = 18V
PO = 1W
TA = 25C
RL = 6
C007
Figure 23. Total Harmonic Distortion vs Frequency (2.0
BTL Mode)
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Typical Characteristics, 2.0 BTL Configuration, 8 Ω (continued)
10
100
RL = 4
2.0 BTL Mode
PVDD = 24V
PO = 1W
TA = 25C
RL = 6
90
RL = 8
80
1
2.0 BTL Mode
RL = 8
TA = 25C
60
Efficiency (%)
THD+N (%)
70
0.1
50
40
30
0.01
20
PVDD = 12V
PVDD = 18V
10
PVDD = 24V
0.001
0
20
200
2k
20k
0
20
Frequency (Hz)
40
60
Figure 24. Total Harmonic Distortion vs Frequency (2.0
BTL Mode)
C005
Figure 25. Efficiency vs Output Power (2.0 BTL Mode)
0
0
Right-to-Left
2.0 BTL Mode
PO = 1W
PVDD = 12V
RL = 8
TA = 25C
±10
±20
±20
Left-to-Right
±30
Crosstalk (dB)
Crosstalk (dB)
Right-to-Left
2.0 BTL Mode
PO = 1W
PVDD = 24V
RL = 8
TA = 25C
±10
Left-to-Right
±30
±40
±50
±60
±40
±50
±60
±70
±70
±80
±80
±90
±90
±100
±100
20
200
2k
20k
20
200
Frequency (Hz)
2k
20k
Frequency (Hz)
C010
Figure 26. Crosstalk vs Frequency (2.0 BTL Mode)
C011
Figure 27. Crosstalk vs Frequency (2.0 BTL Mode)
0
0
Right-to-Left
2.0 BTL Mode
PO = 1W
PVDD = 12V
RL = 4
TA = 25C
±10
±20
Right-to-Left
2.0 BTL Mode
PO = 1W
PVDD = 24V
RL = 4
TA = 25C
±10
Left-to-Right
±20
Left-to-Right
±30
Crosstalk (dB)
±30
Crosstalk (dB)
80
Total Output Power (W)
C008
±40
±50
±60
±40
±50
±60
±70
±70
±80
±80
±90
±90
±100
±100
20
200
2k
20
20k
200
2k
20k
Frequency (Hz)
Frequency (Hz)
C015
C012
Figure 28. Crosstalk vs Frequency (2.0 BTL Mode)
Figure 29. Crosstalk vs Frequency (2.0 BTL Mode)
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Typical Characteristics, 2.0 BTL Configuration, 8 Ω (continued)
40
70
2.0 BTL Mode
RL = 8
TA = 25C
35
2.0 BTL Mode
TA = 25°C
60
30
Idle Channel Noise (uV)
50
Power (W)
25
20
15
40
30
20
10
RL = 4
2 Layer Continuous Power
5
10
RL = 6
4 Layer Continuous Power
RL = 8
Instantaneous Power
0
8
10
12
14
16
18
20
22
0
24
8
Supply Voltage (V)
12
14
16
18
20
22
24
Supply Voltage (V)
C014
Figure 30. Power vs Supply Voltage (2.0 BTL Mode)
18
10
C009
Figure 31. Idle Channel Noise vs Supply Voltage (2.0 BTL
Mode)
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7.14.3 Typical Characteristics, PBTL Configuration, 8 Ω
90
10
RL = 4THD+N = 1%
RL = 4THD+N = 10%
RL = 2THD+N = 1%
RL = 2THD+N = 10%
80
PBTL Mode
PVDD = 12V
f = 1kHz
TA = 25°C
1
60
THD+N (%)
Output Power (W)
70
50
40
0.1
30
0.01
20
RL = 4
10
PBTL Mode
TA = 25C
RL = 2
0
8
10
12
14
16
18
20
22
0.001
0.01
24
0.1
Supply Voltage (V)
1
10
100
Output Power (W)
C031
Figure 32. Output Power vs Supply Voltage (PBTL Mode)
With 2ω Load on Typical 2 Layer PCB, Device May Be
Thermally Limited Above 20 V
C032
Figure 33. Total Harmonic Distortion + Noise vs Output
Power (PBTL Mode)
10
10
PBTL Mode
PVDD = 24V
f = 1kHz
TA = 25°C
PBTL Mode
PVDD = 18V
f = 1kHz
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
0.01
RL = 4
RL = 4
RL = 2
0.001
0.01
0.1
1
10
0.001
0.01
100
RL = 2
0.1
1
10
100
Output Power (W)
Output Power (W)
C029
C033
Figure 34. Total Harmonic Distortion + Noise vs Output
Power (PBTL Mode)
10
Figure 35. Total Harmonic Distortion + Noise vs Output
Power (PBTL Mode)
10
RL = 2
PBTL Mode
PO = 1W
PVDD = 12V
TA = 25C
RL = 6
RL = 4
RL = 6
1
THD+N (%)
1
THD+N (%)
RL = 2
PBTL Mode
PO = 1W
PVDD = 18V
TA = 25C
RL = 4
0.1
0.01
0.1
0.01
0.001
0.001
20
200
2k
20k
20
Frequency (Hz)
200
2k
20k
Frequency (Hz)
C037
Figure 36. Total Harmonic Distortion vs Frequency (PBTL
Mode)
C038
Figure 37. Total Harmonic Distortion vs Frequency (PBTL
Mode)
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Typical Characteristics, PBTL Configuration, 8 Ω (continued)
10
100
RL = 2
PBTL Mode
PO = 1W
PVDD = 24V
TA = 25C
RL = 4
90
RL = 6
80
1
PBTL Mode
RL = 4
TA = 25C
60
Efficiency (%)
THD+N (%)
70
0.1
50
40
30
0.01
20
PVDD = 12V
PVDD = 18V
10
PVDD = 24V
0.001
0
20
200
2k
20k
0
20
Frequency (Hz)
40
60
80
Total Output Power (W)
C041
C035
Figure 38. Total Harmonic Distortion vs Frequency (PBTL
Mode)
Figure 39. Efficiency vs Output Power (PBTL Mode)
100
80
PBTL Mode
90
RL = 4
70
TA = 25C
80
50
60
Power (W)
Efficiency (%)
60
PBTL Mode
RL = 6
TA = 25C
70
50
40
40
30
30
20
20
PVDD = 12V
2 Layer Continuous Power
10
PVDD = 18V
10
4 Layer Continuous Power
PVDD = 24V
0
Instantaneous Power
0
0
10
20
30
40
8
50
10
12
14
16
18
20
22
24
Supply Voltage (V)
Total Output Power (W)
C039
C034
Figure 40. Efficiency vs Output Power (PBTL Mode)
Figure 41. Power vs Supply Voltage (PBTL Mode)
80
PBTL Mode
TA = 25C
Idle Channel Noise ( V)
60
40
20
RL = 4
RL = 6
RL = 8
0
8
10
12
14
16
18
20
22
24
Supply Voltage (V)
C036
Figure 42. Idle Channel Noise vs Supply Voltage (PBTL Mode)
20
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
9 Detailed Description
9.1 Overview
The TAS5731M an efficient 30-W stereo I2S input Class-D audio power amplifier. The digital auto processor of
the device uses noise shaping and customized correction algorithms to achieve a great power efficiency and high
audio performance. Also, the device has up to eight Equalizers per channel and two -band configurable Dynamic
Range Control (DRC).
The device needs only a single DVDD supply in addition to the higher-voltage PVDD power supply. An internal
voltage regulator provides suitable voltage levels for the gate drive circuit. The wide PVDD power supply range of
the device enables its use in a multitude of applications.
The TAS5731M is a slave-only device that is controlled by a bidirectional I2C interface that supports both 100kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations. This control interface
is used to program the registers of the device and read the device status.
The PWM of this device operates with a carrier frequency between 384 kHz and 354 kHz, depending the
sampling rate. This device allows the use of the same clock signal for both MCLK and BCLK (64xFs) when using
a sampling frequency of 44.1 kHz or 48 kHz.
This device can be used in three different modes of operation, Stereo BTL mode, Single filter PBTL mono mode,
and 2.1 mode.
9.2 Functional Block Diagrams
OUT_A
2´ HB
FET Out
SDIN
Serial
Audio
Port
Digital Audio Processor
(DAP)
S
R
C
th
4 -Order
Noise Shaper
and PWM
OUT_B
OUT_C
2´ HB
FET Out
OUT_D
Protection
Logic
MCLK
SCLK
LRCLK
SDA
SCL
Sample Rate
Autodetect
and PLL
Serial
Control
Click and Pop
Control
Microcontroller
Based
System
Control
Terminal Control
B0262-14
Figure 43. Functional Block Diagram
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Functional Block Diagrams (continued)
Undervoltage
Protection
FAULT
4
4
Power
On
Reset
Protection
and
I/O Logic
AGND
Temp.
Sense
GND
VALID
Overcurrent
Protection
Isense
BST_D
PVDD_CD
PWM
Rcv
Ctrl
Timing
PWM Controller
PWM_D
Gate
Drive
OUT_D
Pulldown Resistor
PGND_CD
GVDD
Regulator
GVDD_OUT
BST_C
PVDD_CD
PWM_C
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_C
Pulldown Resistor
PGND_CD
BST_B
PVDD_AB
PWM_B
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_B
Pulldown Resistor
GVDD
Regulator
PGND_AB
BST_A
PVDD_AB
PWM_A
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_A
Pulldown Resistor
PGND_AB
B0034-08
Figure 44. Power-Stage Functional Block Diagram
22
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2
I C Subaddress in Red
I2C:53 – V1IM
L
59
1
+
1BQ
+
29
1BQ
1
1BQ
6BQ
+
1
3A
–1
3A
0
Auto-lp
(0x46 Bit 5)
R
1
+
1BQ
+
30
1BQ
ealpha
5D
Log
Math
Attack
Decay
Master ON/OFF
(0x46[0])
1
1BQ
6BQ
+
Vol2
+
32–36, 5C
1
1BQ
52 V2OM
Input Muxing
5E
I2C:56
VDISTA
Vol2
+
I2C:57
VDISTB
31
+
1
ealpha
2B–2F, 58
Energy
MAXMUX
2A
51 V1OM
Vol1
55
I2C:54 – V2IM
3D
ealpha
L
R
+
1
0
3
1
1BQ
1BQ
5A
5B
½
Energy
MAXMUX
½
61
21 (D8, D9)
3D
Log
Math
Attack
Decay
Master ON/OFF
(0x46[1])
ealpha
+
Vol1
60 V6OM
B0321-14
Figure 45. DAP Process Structure
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9.3 Feature Description
9.3.1 Power Supply
To facilitate system design, the TAS5731M needs only a 3.3-V supply in addition to the PVDD power-stage
supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all
circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in
bootstrap circuitry requiring only a few external capacitors.
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical half-bridges with separate bootstrap pins (BST_x). The gate-drive voltage (GVDD_OUT) is
derived from the PVDD voltage. Special attention must be paid to placing all decoupling capacitors as close to
their associated pins as possible. Inductance between the power-supply pins and decoupling capacitors must be
avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive regulator output pin (GVDD_OUT) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 288 kHz to 384 kHz, it is recommended to use 10-nF, X7R ceramic
capacitors, size 0603 or 0805, for the bootstrap supply. These 10-nF capacitors ensure sufficient energy storage,
even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during
the remaining part of the PWM cycle.
Special attention must be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is
decoupled with a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.
The TAS5731M is fully protected against erroneous power-stage turnon due to parasitic gate charging.
9.3.2 I2C Address Selection and Fault Output
ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the
Typical Applications sections in order to set the I2C address. Pulling this pin HIGH through the resistor results in
setting the I2C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in setting the
address to 0011010 (0x34).
During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault
notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to its
default state when register 0x02 is cleared. The behavior of the pin in response to a fault condition is to be pulled
low immediately upon an error. The device then waits for a period of time determined by BKND_ERR Register
(0x1C) before attempting to resume playback. If the error has been cleared when the device attempts to resume
playback, playback will resume, the ADR/FAULT pin will remain high, and normal operation will resume. If the
error has not been removed, then the device will immediately re-enter the protected state and wait again for the
predetermined period of time to pass. The device will pull the fault pin low for over-current, over-temperature, and
under-voltage lock-out.
9.3.3 Single-Filter PBTL Mode
The TAS5731M supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected
before the LC filter. In addition to connecting OUT_A/OUT_B and OUT_C/OUT_D, BST_A/BST_B and
BST_C/BST_D must also be connected before the LC filter, as shown in the Figure 71. In order to put the part in
PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the turnoff of half-bridges A and B (and similarly
C/D) if an overcurrent condition is detected in either half-bridge. There is a pulldown resistor on the PBTL pin that
configures the part in BTL mode if the pin is left floating.
PWM output multiplexers must be updated to set the device in PBTL mode. Output Mux Register (0x25) must be
written with a value of 0x0110 3245.
24
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Feature Description (continued)
9.3.4 Device Protection System
9.3.4.1 Overcurrent (OC) Protection With Current Limiting
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by a protection system. If the high-current condition situation persists, that
is, the power stage is being overloaded, a protection system triggers a latching shutdown, resulting in the power
stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault
condition (that is, a short circuit on the output) is removed. Current-limiting and overcurrent protection are not
independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent
fault, half-bridges A, B, C, and D are shut down.
9.3.4.2 Overtemperature Protection
The TAS5731M has an overtemperature-protection system. If the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the highimpedance (Hi-Z) state. The TAS5731M recovers automatically once the temperature drops approximately 30°C.
9.3.4.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5731M fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD
and AVDD are independently monitored, a supply-voltage drop below the UVP threshold on AVDD or either
PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state.
9.3.5 SSTIMER Functionality
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current
source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is
shut down, the drivers are placed in the high-impedance state and transition slowly down through a 3-kΩ resistor,
similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin
capacitance. Larger capacitors increase the start-up time, while capacitors smaller than 2.2 nF decrease the
start-up time. The SSTIMER pin can be left floating for BD modulation.
9.3.6 Clock, Autodetection, and PLL
The TAS5731M is an I2S slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the Clock Control Register (0x00).
The TAS5731M checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1
× fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section
uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the clock-control register.
The TAS5731M has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect
changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)
and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the
system autodetects the new rate and reverts to normal operation. During this process, the default volume is
restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly
(also called soft unmute) as defined in volume register (0x0E).
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Feature Description (continued)
9.3.7 PWM Section
The TAS5731M DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can
be enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For a detailed description of using audio processing features like DRC and EQ, see the TAS5731 EVM User's
Guide (SLOU331) and TAS570X GDE Software Setup development tool documentation (SLOC124).
9.3.8 2.1-Mode Support
The TAS5731 uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode operation.
To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit D2 must
be set to 1. The SSTIMER pin must be left floating in this mode.
9.3.9 I2C Compatible Serial Control Interface
The TAS5731M DAP has an I2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent. The serial control interface supports
both single-byte and multiple-byte read and write operations for status registers and the general control registers
associated with the PWM.
9.3.10 Audio Serial Interface
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5731M DAP accepts serial data
in 16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.
9.3.10.1 I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
26
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Feature Description (continued)
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 46. I2S 64-FS Format
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Feature Description (continued)
2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
MSB
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
0
LSB
23 22
17 16
9
8
5
4
19 18
13 12
5
4
1
0
15 14
9
1
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
8
8
T0092-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 47. I2S 48-FS Format
2
2-Channel I S (Philips Format) Stereo Input
LRCLK
16 Clks
16 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
MSB
LSB
11 10
9
8
5
4
3
2
1
0
LSB
15 14 13 12
11 10
9
8
5
4
3
2
1
T0266-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 48. I2S 32-FS Format
28
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Feature Description (continued)
9.3.10.2 Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 49. Left-Justified 64-FS Format
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Feature Description (continued)
2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
21
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
1
0
MSB
LSB
21
17 16
9
8
5
4
19 18 17
13 12
5
4
1
0
15 14 13
9
1
0
23 22
1
0
20-Bit Mode
19 18 17
16-Bit Mode
15 14 13
8
8
T0092-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 50. Left-Justified 48-FS Format
2-Channel Left-Justified Stereo Input
16 Clks
16 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
MSB
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
T0266-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 51. Left-Justified 32-FS Format
30
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Feature Description (continued)
9.3.10.3 Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24bit data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK
transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused
leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 52. Right-Justified 64-FS Format
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Feature Description (continued)
2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
LSB
MSB
23 22
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
20-Bit Mode
16-Bit Mode
T0092-03
Figure 53. Right-Justified 48-FS Format
Figure 54. Right-Justified 32-FS Format
32
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Feature Description (continued)
9.3.11 Dynamic Range Control (DRC)
The DRC scheme has two DRC blocks. There is one ganged DRC for the high-band left/right channels and one
DRC for the low-band left/right channels.
Output Level (dB)
The DRC input/output diagram is shown in Figure 55.
1:1 Transfer Function
Implemented Transfer Function
T
Input Level (dB)
M0091-04
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• Each DRC has adjustable threshold levels.
• Programmable attack and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 55. Dynamic Range Control
a, w
T
aa, wa / ad, wd
DRC1
0x3C
0x3B
0x40
DRC2
0x3F
0x3E
0x43
Alpha Filter Structure
S
a
w
–1
Z
B0265-04
T = 9.23 format, all other DRC coefficients are 3.23 format
Figure 56. DRC Structure
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9.4 Device Functional Modes
9.4.1 Stereo BTL Mode
The classic stereo mode of operation uses the TAS5731M device to amplify two independent signals, which
represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented
on differential output pairs shown as OUT_A and OUT_B for a channel and OUT_C and OUT_D for the other
one. The routing of the audio data which is presented on the OUT_x outputs can be changed according to the
PWM Output Mux Register (0x25). By default, the TAS5731M device is configured to output channel 1 to the
OUT_A and OUT_B outputs, and channel 2 to the OUT_C and OUT_D outputs. Stereo Mode operation outputs
are shown in Figure 57.
Figure 57. Stereo BTL Mode
9.4.2 Mono PBTL Mode
When this mode of operation is used, the two stereo outputs of the device are placed in parallel one with another
to increase the power sourcing capabilities of the device. The TAS5731M supports parallel BTL (PBTL) mode
with OUT_A/OUT_B (and OUT_C/OUT_D) connected before the LC filter.
The merging of the two output channels in this device can be done before the inductor portion of the output filter.
This is called Single-Filter PBTL, and this mono operation is shown in Figure 58. More information about this can
be found in Single-Filter PBTL Mode section.
34
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Device Functional Modes (continued)
Figure 58. Post-Filter PBTL
On the input side of the TAS5731M device, the input signal to the mono amplifier can be selected from a mix, left
or right frame from an I2S, LJ, or RJ signal. The routing of the audio data which is presented on the SPK_OUTx
outputs must be configured with the PWM Output Mux Register (0x25).
Refer to the Mono Parallel Bridge Tied Load Application section for more details of the correct PBTL output
connection of the TAS5731M.
9.4.3 2.1 Mode
2.1 Mode is defined as the application of two Single ended channels and one BTL channel used in systems
where a third sub channel is required. Generally, both single-ended inputs drive the Left and Right channels,
while the BTL channel drives a low-frequency content channel called often Subwoofer. More information about
this can be found in the 2.1-Mode Support section.
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Device Functional Modes (continued)
Figure 59. 2.1 Mode
Refer to 2.1 Application section for more details of the correct 2.1 output connection of the TAS5731M.
9.5 Programming
9.5.1 I2C Serial Control Interface
The TAS5731M DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.
This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
9.5.1.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 60. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5731M holds SDA low during the acknowledge
clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the
sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible
devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor
must be used for the SDA and SCL signals to set the high level for the bus.
36
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Programming (continued)
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
2
Figure 60. Typical I C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 60.
The 7-bit address for TAS5731M is 0011 011 (0x36).
9.5.1.2 Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiplebyte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received
when a stop command (or another start command) is received, the received data is discarded.
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5731M also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by
data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place,
and the data for all 16 subaddresses is successfully received by the TAS5731M. For I2C sequential-write
transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted,
before a stop or start is transmitted, determines how many subaddresses are written. As was true for random
addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data
is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is
accepted; only the incomplete data is discarded.
9.5.1.3 Single-Byte Write
As shown in Figure 61, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or
bytes corresponding to the TAS5731M internal memory address being accessed. After receiving the address
byte, the TAS5731M again responds with an acknowledge bit. Next, the master device transmits the data byte to
be written to the memory address being accessed. After receiving the data byte, the TAS5731M again responds
with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte datawrite transfer.
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Programming (continued)
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 61. Single-Byte Write Transfer
9.5.1.4 Multiple-Byte Write
A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 62. After receiving each data byte, the
TAS5731M responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
A5
2
A4
A3
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
Other Data Bytes
First Data Byte
Subaddress
I C Device Address and
Read/Write Bit
Last Data Byte
Stop
Condition
T0036-02
Figure 62. Multiple-Byte Write Transfer
9.5.1.5 Single-Byte Read
As shown in Figure 63, a single-byte data-read transfer begins with the master device transmitting a start
condition, followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5731M address
and the read/write bit, TAS5731M responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the TAS5731M
address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After
receiving the address and the read/write bit, the TAS5731M again responds with an acknowledge bit. Next, the
TAS5731M transmits the data byte from the memory address being read. After receiving the data byte, the
master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read
transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
Acknowledge
A6
A5
A4
Subaddress
A0 ACK
Not
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK D7
2
I C Device Address and
Read/Write Bit
D6
D1
Data Byte
D0 ACK
Stop
Condition
T0036-03
Figure 63. Single-Byte Read Transfer
9.5.1.6 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS5731M to the master device as shown in Figure 64. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
38
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Programming (continued)
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
Acknowledge
A6
A6
A0 ACK
A5
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
2
I C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 64. Multiple-Byte Read Transfer
9.5.2 26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers means that there are 3 bits to the left of the binary point and 23 bits to the right of the binary point. This
is shown in Figure 65.
2
–23
2
2
–5
–1
Bit
Bit
Bit
0
2 Bit
1
2 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0125-01
Figure 65. 3.23 Format
The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 65. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 66 applied to obtain the magnitude
of the negative number.
1
0
2 Bit
2 Bit
1
2
0
–1
Bit
(1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2
2
–1
–4
Bit
+ ....... (1 or 0) ´ 2
2
–4
–23
Bit
+ ....... (1 or 0) ´ 2
–23
M0126-01
Figure 66. Conversion Weighting Factors — 3.23 Format To Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 67.
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Programming (continued)
Fraction
Digit 6
Sign
Bit
Fraction
Digit 1
Integer
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
u u u u
u u S x
x. x x x
x x x x
x x x x
x x x x
x x x x
x x x x 0
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0127-01
2
Figure 67. Alignment of 3.23 Coefficient in 32-Bit I C Word
Table 1. Sample Calculation for 3.23 Format
db
LINEAR
DECIMAL
0
1
8,388,608
80 0000
5
1.77
14,917,288
00E3 9EA8
–5
0.56
4,717,260
0047 FACC
D = 8,388,608 × L
H = dec2hex (D, 8)
(X/20)
X
L = 10
HEX (3.23 Format)
Table 2. Sample Calculation for 9.17 Format
40
db
LINEAR
DECIMAL
HEX (9.17 Format)
0
1
131,072
2 0000
3 8A3D
5
1.77
231,997
–5
0.56
73,400
1 1EB8
X
L = 10(X/20)
D = 131,072 × L
H = dec2hex (D, 8)
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9.6 Register Maps
Table 3. Serial Control Interface Register Summary
SUBADDRESS
REGISTER NAME
CONTENTS (1)
INITIALIZATION VALUE
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x00
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface
register
1
Description shown in subsequent section
0x05
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Channel 3 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0B–0x0D
0x0E
Volume configuration
register
0x0F
(2)
1
Reserved
1
Description shown in subsequent section
1
Reserved (2)
0x91
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0xAC
0x12
IC delay channel 2
1
Description shown in subsequent section
0x54
0x13
IC delay channel 3
1
Description shown in subsequent section
0xAC
0x14
IC delay channel 4
1
Description shown in subsequent section
0x54
1
Reserved (2)
Description shown in subsequent section
0x15-0x18
0x19
PWM channel shutdown
group register
1
0x1A
Start/stop period register
1
0x0F
0x1B
Oscillator trim register
1
0x82
0x1C
BKND_ERR register
1
0x1D–0x1F
0x30
0x02
1
Reserved (2)
0x20
Input MUX register
4
Description shown in subsequent section
0x0001 7772
0x21
Ch 4 source select register
4
Description shown in subsequent section
0x0000 4303
4
Reserved (2)
4
Description shown in subsequent section
0x22 -0x24
0x25
PWM MUX register
0x26-0x28
0x29
0x2A
(1)
(2)
NO. OF
BYTES
ch1_bq[0]
ch1_bq[1]
0x0102 1345
(2)
4
Reserved
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
20
A u indicates unused bits.
Reserved registers must not be accessed.
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Register Maps (continued)
Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
42
REGISTER NAME
ch1_bq[2]
ch1_bq[3]
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
ch2_bq[0]
ch2_bq[1]
ch2_bq[2]
ch2_bq[3]
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
CONTENTS (1)
INITIALIZATION VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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Register Maps (continued)
Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x34
0x35
0x36
REGISTER NAME
ch2_bq[4]
ch2_bq[5]
ch2_bq[6]
0x37 - 0x39
0x3A
DRC1 ae (3)
NO. OF
BYTES
20
20
20
DRC1 aa
DRC1 ad
DRC2 ae
DRC2 aa
DRC2 ad
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
u[31:26], (1 – ad)[25:0]
0x0000 0000
u[31:26], ae[25:0]
0x0080 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
8
8
8
8
8
DRC2 (1 – ad)
u[31:26], (1 – ad)[25:0]
0x0000 0000
0x40
DRC1-T
4
T1[31:0] (9.23 format)
0xFDA2 1490
0x41
DRC1-K
4
u[31:26], K1[25:0]
0x0384 2109
0x42
DRC1-O
4
u[31:26], O1[25:0]
0x0008 4210
0x43
DRC2-T
4
T2[31:0] (9.23 format)
0xFDA2 1490
0x44
DRC2-K
4
u[31:26], K2[25:0]
0x0384 2109
0x45
DRC2-O
4
u[31:26], O2[25:0]
0x0008 4210
0x46
DRC control
4
Description shown in subsequent section
0x0000 0000
4
Reserved (2)
0x47–0x4F
0x50
Bank switch control
4
Description shown in subsequent section
0x0F70 8000
0x51
Ch 1 output mixer
12
Ch 1 output mix1[2]
0x0080 0000
Ch 1 output mix1[1]
0x0000 0000
0x52
(3)
0x0000 0000
u[31:26], b2[25:0]
0x0080 0000
DRC2 (1 – aa)
0x3F
u[31:26], b1[25:0]
u[31:26], ae[25:0]
DRC 2 (1 – ae)
0x3E
0x0080 0000
8
DRC1 (1 – ad)
0x3D
u[31:26], b0[25:0]
Reserved (2)
DRC1 (1 – aa)
0x3C
INITIALIZATION VALUE
4
DRC1 (1 – ae)
0x3B
CONTENTS (1)
Ch 2 output mixer
12
Ch 1 output mix1[0]
0x0000 0000
Ch 2 output mix2[2]
0x0080 0000
Ch 2 output mix2[1]
0x0000 0000
Ch 2 output mix2[0]
0x0000 0000
"ae" stands for ∝ of energy filter, "aa" stands for ∝ of attack filter and "ad" stands for ∝ of decay filter and 1- ∝ = ω.
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Register Maps (continued)
Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x53
0x54
0x55
Ch 1 input mixer
Ch 2 input mixer
Channel 3 input mixer
NO. OF
BYTES
16
16
12
CONTENTS (1)
INITIALIZATION VALUE
Ch 1 input mixer[3]
0x0080 0000
Ch 1 input mixer[2]
0x0000 0000
Ch 1 input mixer[1]
0x0000 0000
Ch 1 input mixer[0]
0x0080 0000
Ch 2 input mixer[3]
0x0080 0000
Ch 2 input mixer[2]
0x0000 0000
Ch 2 input mixer[1]
0x0000 0000
Ch 2 input mixer[0]
0x0080 0000
Channel 3 input mixer [2]
0x0080 0000
Channel 3 input mixer [1]
0x0000 0000
Channel 3 input mixer [0]
0x0000 0000
0x56
Output post-scale
4
u[31:26], post[25:0]
0x0080 0000
0x57
Output pre-scale
4
u[31:26], pre[25:0] (9.17 format)
0x0002 0000
0x58
ch1 BQ[7]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x59
0x5A
0x5B
0x5C
0x5D
44
REGISTER NAME
ch1 BQ[8]
Subchannel BQ[0]
Subchannel BQ[1]
ch2 BQ[7]
ch2 BQ[8]
20
20
20
20
20
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Register Maps (continued)
Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x5E
REGISTER NAME
pseudo_ch2 BQ[0]
0x5F
NO. OF
BYTES
20
INITIALIZATION VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
4
Reserved (2)
Ch 4 output mixer[1]
0x0000 0000
Ch 4 output mixer[0]
0x0080 0000
Ch 4 input mixer[1]
0x0040 0000
Ch 4 input mixer[0]
0x0040 0000
Post-IDF attenuation register
0x0000 0080
0x60
Channel 4 (subchannel)
output mixer
8
0x61
Channel 4 (subchannel)
input mixer
8
IDF post scale
4
0x62
CONTENTS (1)
0x63–0xF7
Reserved
(2)
0x0000 0000
0xF8
Device address enable
register
4
Write F9 A5 A5 A5 in this register to enable write to
device address update (0xF9)
0x0000 0000
0xF9
Device address Update
Register
4
u[31:8], New Dev Id[7:1] , ZERO[0] (New Dev Id
(7:1) defines the new device address
0X0000 0036
4
Reserved (2)
0x0000 0000
0xFA–0xFF
All DAP coefficients are 3.23 format unless specified otherwise.
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TAS5731M
SLOS838C – JULY 2013 – REVISED AUGUST 2015
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9.6.1 Clock Control Register (0x00)
The clocks and data rates are automatically determined by the TAS5731M. The clock control register contains
the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The
device accepts a 64 fS or 32 fS SCLK rate for all MCLK ratios, but accepts a 48 fS SCLK rate for MCLK ratios of
192 fS and 384 fS only.
Table 4. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
fS = 32-kHz sample rate
0
0
1
–
–
–
–
–
Reserved (1)
0
1
0
–
–
–
–
–
Reserved (1)
0
1
1
–
–
–
–
–
fS = 44.1/48-kHz sample rate (2)
1
0
0
–
–
–
–
–
fS = 16-kHz sample rate
1
0
1
–
–
–
–
–
fS = 22.05/24-kHz sample rate
1
1
0
–
–
–
–
–
fS = 8-kHz sample rate
1
1
1
–
–
–
–
–
fS = 11.025/12-kHz sample rate
–
–
–
0
0
0
–
–
MCLK frequency = 64 × fS (3)
–
–
–
0
0
1
–
–
MCLK frequency = 128 × fS (3)
–
–
–
0
1
0
–
–
MCLK frequency = 192 × fS (4)
–
–
–
0
1
1
–
–
MCLK frequency = 256 × fS
–
–
–
1
0
0
–
–
MCLK frequency = 384 × fS
–
–
–
1
0
1
–
–
MCLK frequency = 512 × fS
–
–
–
1
1
0
–
–
Reserved (1)
–
–
–
1
1
1
–
–
Reserved (1)
–
–
–
–
–
–
0
–
Reserved (1)
–
(1)
(2)
(3)
(4)
(5)
–
–
–
–
–
–
0
FUNCTION
Reserved
(2) (5)
(2)
(1) (2)
Reserved registers must not be accessed.
Default values are in bold.
Only available for 44.1-kHz and 48-kHz rates
Rate only available for 32/44.1/48-kHz sample rates
Not available at 8 kHz
9.6.2 Device ID Register (0x01)
The device ID register contains the ID code for the firmware revision.
Table 5. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
46
FUNCTION
Identification code
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Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: TAS5731M
TAS5731M
www.ti.com
SLOS838C – JULY 2013 – REVISED AUGUST 2015
9.6.3 Error Status Register (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error Definitions:
• MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK Error: The number of SCLKs per LRCLK is changing.
• LRCLK Error: LRCLK frequency is changing.
• Frame Slip: LRCLK phase is drifting with respect to internal Frame Sync.
Table 6. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
1
-
–
–
–
–
–
–
MCLK error
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
–
–
–
–
–
1
–
–
Clip indicator
–
–
–
–
–
–
1
–
Overcurrent, overtemperature, or undervoltage errors
–
–
–
–
–
–
–
0
Reserved
0
0
0
0
0
0
0
–
No errors (1)
(1)
FUNCTION
Default values are in bold.
9.6.4 System Control Register 1 (0x03)
The system control register 1 has several functions:
Bit D7:
If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff
