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TAS5754M
SLAS987 – JUNE 2014
Digital Input, Closed-Loop Class-D Amplifier with HybridFlow Processing
1 Features
3 Description
•
The TAS5754M device is a high-performance, stereo
closed-loop amplifier with integrated audio processor
with PurePath™ HybridFlow architecture. To convert
from digital to analog, it uses a high performance
DAC with Burr-Brown® mixed signal heritage. It
requires only two power supplies: one DVDD for lowvoltage circuitry and one PVDD for high-voltage
circuitry. It is controlled via a software control port
using standard I2C communication. In the family, the
TAS5756M uses traditional BD modulation, ensuring
low distortion characteristics. The TAS5754M uses
1SPW modulation, reducing the idle current draw at
the expense of slightly higher distortion.
1
•
•
•
•
Flexible Audio I/O Configuration
– Supports I2S, TDM, LJ, RJ Digital Input
– 8 kHz to 192 kHz Sample Rate Support
– Stereo Bridge Tied Load (BTL) or Mono
Parallel Bridge Tied Load (PBTL) Operation
– BD Modulation with TAS5756M, 1SPW
Modulation with TAS5754M
– Supports 3-Wire Digital Audio Interface (No
MCLK required)
High Performance Closed-Loop Architecture
(PVDD = 12V, RSPK = 8 Ω, SPK_GAIN = 20dBV)
– Idle Channel Noise = 62 µVrms (A-Wtd)
– THD+N = 0.007 % (at 1 W, 1 kHz)
– SNR = 103 A-Wtd (Ref. to THD+N = 1%)
PurePath™ HybridFlow Processing Architecture
– Several Configurable MiniDSP Programs
(called HybridFlows)
– Download Time SPK_MUTE
------00
VDD ≤ SPK_MUTE < 0.7 × VDD
------01
Reserved (do not set)
------10
0.7 × VDD ≤ SPK_MUTE
------11
8.4.2.53 P0-R115
FS Speed Mode Monitor [1:0] (Read Only)
00000000
These bits indicate the actual FS operation mode being used. The actual value is the auto set one when clock auto set is active and register
set one when clock auto set is disabled.
Single speed (fS ≤ 48 kHz)
------00
Double speed (48 kHz ≤ fS ≤ 96 kHz)
------01
Quad speed (96 kHz ≤ fS ≤ 192 kHz)
------10
8.4.2.54 P0-R117
DSP Boot Done Flag [7] (R/W)
00000000
This bit indicates whether the DSP boot is completed.
DSP is booting
0-------
DSP boot completed
1------Power State [3:0] (Read Only)
00000000
These bits indicate the current power state of the DAC
Powerdown
----0000
Wait for CP voltage valid
----0001
Calibration
----0010
Calibration
----0011
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Power State [3:0] (Read Only)
00000000
Volume ramp up
----0100
Run (Playing)
----0101
Line output short or low impedance
----0110
Volume ramp down
----0111
Standby
----1000
8.4.2.55 P0-R119
GPIO2 Input State [5] (Read Only)
00101101
This bit indicates the logic level at GPIO2 pin.
GPIO2 logic level low
---0-----
GPIO2 logic level high
---1----GPIO0 Input State [3] (Read Only)
00101101
This bit indicates the logic level at GPIO0 pin.
GPIO0 logic level low
-----0---
GPIO0 logic level high
-----1--GPIO1 Input State [2] (Read Only)
00101101
This bit indicates the logic level at GPIO1 pin.
GPIO1 logic level low
-----0--
GPIO1 logic level high
-----1--
8.4.2.56 P0-R120
Auto Mute Flag for Channel B [4] (Read Only)
00000000
This bit indicates the auto mute status for Channel B.
Not auto muted
---0----
Auto muted
---1---Auto Mute Flag for Channel A [0] (Read Only)
00000000
This bit indicates the auto mute status for Channel A.
Not auto muted
-------0
Auto muted
-------1
8.4.2.57 P0-R121
DAC Mode [0] (R/W)
00000000
This bit controls the DAC mode.
Mode1
-------0
Mode2
-------1
8.4.2.58 P1-R2
Analog Gain Control for Channel B [4] (R/W)
00000000
This bit controls the Channel B analog gain.
0 dB
---0----
–6 dB
---1---Analog Gain Control for Channel A [0] (R/W)
00000000
This bit controls the Channel A analog gain.
0 dB
-------0
–6 dB
-------1
82
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8.4.2.59 P1-R5
External UVP Control [1] (R/W)
00010001
This bit enables or disables detection of power supply drop via SPK_MUTE pin (external UVLO protection).
Enabled
-------0-
Disabled
-------1Internal UVP Control [0] (R/W)
00010001
This bit enables or disables internal detection of AVDD voltage drop (internal UVLO protection).
Enabled
-------0
Disabled
-------1
8.4.2.60 P1-R6
Analog Mute Control [0] (R/W)
00000000
This bit enables or disables analog mute following digital mute.
Enabled
-------0
Disabled
-------1
8.4.2.61 P1-R7
Analog +10% Gain for Channel B [4] (R/W)
00000000
This bit enables or disables amplitude boost mode for Channel B.
Normal amplitude
---0----
+10% (+0.8 dB) boosted amplitude
---1---Analog +10% Gain for Channel A [0] (R/W)
00000000
This bit enables or disables amplitude boost mode for Channel A.
Normal amplitude
-------0
+10% (+0.8 dB) boosted amplitude
-------1
8.4.2.62 P1-R8
VCOM Reference Ramp-Up [0] (R/W)
00000000
This bit controls the VCOM voltage ramp up speed.
Normal ramp-up time is approximately 600 ms with external capacitance = 1 µF
-------0
Fast ramp-up time is approximately 3 ms with external capacitance = 1 µF
-------1
8.4.2.63 P1-R9
VCOM Power-Down Control [0] (R/W)
00000000
This bit controls VCOM powerdown switch.
VCOM is powered on
-------0
VCOM is powered down
-------1
8.4.2.64 P44-R1
Active CRAM Monitor [3] (Read Only)
00000000
This bit indicates which CRAM is being accessed by the DSP when adaptive mode is disabled. When adaptive mode is enabled, this bit
has no meaning.
CRAM A is being used by the DSP
-----0---
CRAM B is being used by the DSP
-----1---
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Adaptive Mode Control [2] (R/W)
00000000
This bit controls the DSP adaptive mode. When in adaptive mode, only CRAM A is accessible via serial interface when the DSP is disabled
(DAC in standby state), while when the DSP is enabled (DAC is run state) the CRAM A can only be accessed by the DSP and the CRAM B
can only be accessed by the serial interface, or vice versa depending on the value of CRAMSTAT. When not in adaptive mode, both CRAM
A and B can be accessed by the serial interface when the DSP is disabled, but when the DSP is enabled, no CRAM can be accessed by
serial interface. The DSP can access either CRAM, which can be monitored at SWPMON.
Adaptive mode disabled
-----0--
Adaptive mode enabled
-----1-Active CRAM Selection [1] (Read Only)
00000000
This bit indicates which CRAM currently serves as the active one. The other CRAM serves as an update buffer, and can accessed by serial
interface (SPI/I2C)
CRAM A is active and being used by the DSP
-------0-
CRAM B is active and being used by the DSP
-------1-
Switch Active CRAM [0] (R/W)
00000000
This bit is used to request switching roles of the two buffers, (switching the active buffer role between CRAM A and CRAM B). This bit is
cleared automatically when the switching process completed.
No switching requested or switching completed
-------0
Switching is being requested
-------1
8.4.2.65 P253-R63
Clock Flex Register No. 1 [7:0] (R/W)
00000000
Using this register allows the PLL I/O to be set to GPIOs.
Set to 0x11
00000000
00000001
00000010
...
...
00100000
00110000
00110001
...
11111101
11111110
11111111
8.4.2.66 P253-R64
Clock Flex Register No. 2 [7:0] (R/W)
00000000
Using this register allows the PLL I/O to be set to GPIOs.
Set to 0x11
00000000
00000001
00000010
...
...
00100000
00110000
00110001
...
11111101
11111110
11111111
84
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9 Applications and Implementation
9.1 Application Information
One of the most significant benefits of the TAS5754M device is the ability to be used in a variety of applications
and with an assortment of signal processing options. This section details the information needed to configure the
device for several popular configurations and provides guidance on integrating the TAS5754M device into the
larger system.
9.1.1 External Component Selection Criteria
The Supporting Component Requirements table in each application description section lists the details of the
supporting required components in each of the System Application Schematics.
Where possible, the supporting component requirements have been consolidated to minimize the number of
unique components which are used in the design. Component list consolidation is a method to reduce the
number of unique part numbers in a design, to ease inventory management, and reduce the manufacturing steps
during board assembly. For this reason, some capacitors are specified at a higher voltage than what would
normally be required. An example of this is a 50-V capacitor may be used for decoupling of a 3.3-V power supply
net.
In this example, a higher voltage capacitor can be used even on the lower voltage net to consolidate all caps of
that value into a single component type. Similarly, a several unique resistors, having all the same size and value
but with different power ratings can be consolidated by using the highest rated power resistor for each instance
of that resistor value.
While this consolidation may seem excessive, the benefits of having fewer components in the design may far
outweigh the trivial cost of a higher voltage capacitor. If lower voltage capacitors are already available elsewhere
in the design, they can be used instead of the higher voltage capacitors. In all situations, the voltage rating of the
capacitors must be at least 1.45 times the voltage of the voltage which appears across them. The power rating of
the capacitors should be 1.5 times to 1.75 times the power dissipated in it during normal use case.
9.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
Because the layout is important to the overall performance of the circuit, the package size of the components
shown in the component list were intentionally chosen to allow for proper board layout, component placement,
and trace routing. In some cases, traces are passed in between two surface mount pads or ground plane
extends from the TAS5754M device between two pads of a surface mount component and into to the
surrounding copper for increased heat-sinking of the device. While components may be offered in smaller or
larger package sizes, it is highly recommended that the package size remain identical to that used in the
application circuit as shown. This consistency ensures that the layout and routing can be matched very closely,
optimizing thermal, electromagnetic, and audio performance of the TAS5754M device in circuit in the final
system.
9.1.3 Amplifier Output Filtering
The TAS5754M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that do not have other circuits which are sensitive to EMI,
a simple ferrite bead or ferrite bead and capacitor can replace the traditional large inductor and capacitor that are
commonly used. In other high-power applications, large toroid inductors are required for maximum power and
film capacitors may be preferred due to audio characteristics. Refer to the application report SLOA119 for a
detailed description on proper component selection and design of an L-C filter based upon the desired load and
response.
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9.2 Typical Applications
9.2.1 2.0 (Stereo BTL) System
For the stereo (BTL) PCB layout, see Figure 87.
A 2.0 system generally refers to a system in which there are two full range speakers without a separate amplifier
path for the speakers which reproduce the low-frequency content. In this system, two channels are presented to
the amplifier via the digital input signal. These two channels are amplified and then sent to two separate
speakers. In some cases, the amplified signal is further separated based upon frequency by a passive crossover
network after the L-C filter. Even so, the application is considered 2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
It is important to note that the HybridFlows which have been developed for specifically for stereo applications will
frequently apply the same equalizer curves to the left channel and the right channel. This maximizes the
processing capabilities of each HybridFlow by minimizing the cycles required by the BiQuad filters.
When two signals that are not two separate signals, but instead are derived from a single signal which is
separated into low frequency and high frequency by the signal processor, the application is commonly referred to
as 1.1 or Bi-Amped systems. The 2.0 (Stereo BTL) System application is shown in Figure 80.
86
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R100
PVDD
R101
750k
150k
C103
1µF
GND
C100
0.1µF
GND
C101
22µF
GND
C102
22µF
GND
GND
C104
To System Processor
0.22µF
3.3V
2.0-SDA
2.0-SCL
2.0-GPIO0
2.0-GPIO1
2.0-SDOUT
2.0-MCLK
2.0-SCLK
2.0-SDIN
L100
2.0-SPK_OUTA+
C105
1µF
3.3V
C106
2.2µF
2.0-OUTA+
L101
C107
2.2µF
2.0-SPK_OUTA-
2.0-OUTA-
C109
0.68µF
C110
0.68µF
2
1
0.22µF
U100
TAS5754MDCA
TAS5756MDCA
SPK_OUTABSTRPA-
PGND
3
5
4
BSTRAPA+
SPK_OUTA+
PVDD
PVDD
7
6
8
SPK_GAIN/FREQ
GVDO
9
10
AGND
SPK_INA-
11
12
SPK_INA+
13
DAC_OUTA
14
AVDD
AGND
15
17
16
19
18
SCL
SDA
ADR1
GPIO1
GPIO0
20
21
GPIO2
GND
SDIN
SCLK
MCLK
24
23
22
C108
GND
GND
BSTRPB-
GND
48
SPK_OUTB-
PGND
46
47
SPK_OUTB+
45
BSTRPB+
44
SPK_FAULT
PGND
SPK_INB-
SPK_INB+
PVDD
PVDD
PVDD
41
42
43
40
39
38
CPVSS
DAC_OUTB
37
36
35
GND
CN
34
CP
32
33
DVDD
CPVDD
31
30
DVDD_REG
SPK_MUTE
ADR0
DGND
29
28
27
26
25
LRCK/FS
PAD
C111
2.0-LRCK/FS
0.22µF
GND
GND
GND
GND
GND
L102
2.0-SPK_OUTB-
3.3V
C112
1µF
C113
2.2µF
2.0-OUTB-
L103
C114
2.2µF
2.0-SPK_OUTB+
2.0-OUTB+
C115
C118
1µF
2.0-SPK_MUTE
C119
1µF
C120
1µF
C116
0.68µF
GND
PVDD
GND
GND
GND
C117
0.68µF
0.22µF
GND
GND
C121
0.1µF
2.0-SPK_FAULT
GND
C122
22µF
GND
C123
22µF
GND
Figure 80. 2.0 (Stereo BTL) System Application Schematic
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9.2.1.1 Design Requirements
• Power Supplies:
– 3.3-V Supply
– 5-V to 24-V Supply
• Communication: Host Processor serving as I2C Compliant Master
• External Memory (such as EEPROM and Flash) used for coefficients and RAM portions of HybridFlow < 5 kB
The requirements for the supporting components for the TAS5754M device in a Mono (PBTL) System is provided
in Table 22.
Table 22. Supporting Component Requirements for Stereo 2.0 (BTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
U100
TAS5754M
48 Pin TSSOP
R100
See Adjustable
Amplifier Gain and
Switching Frequency
Selection
0402
1%, 0.063 W
R101
See Adjustable
Amplifier Gain and
Switching Frequency
Selection
0402
1%, 0.063 W
L100, L101, L102,
L103
DETAILED DESCRIPTION
Digital-input, closed-loop class-D amplifier with HybridFlow
processing
See Amplifier Output Filtering
C196, C197, C198,
C199
0.01 µF
0603
Ceramic, 0.01 µF, 50V, ±10%, X7R
C100, C121
0.1 µF
0402
Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C104, C108, C111,
C115
0.22 µF
0603
Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C109, C110, C116,
C117
0.68 µF
0805
Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C103
1 µF
0603
Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C105, C118, C119,
C120
1 µF
0402
Ceramic, 1 µF, 6.3V, ±10%, X5R
C106, C107, C113,
C114
2.2 µF
0402
Ceramic, 2.2 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
22 µF
0805
C101, C102, C122,
C123
Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Step One: Hardware Integration
•
•
Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, board layout and routing give in the example layout
above, integrate the device and its supporting components into the system PCB file.
– The most critical section of the circuit is the the power supply inputs, the amplifier output signals, and the
high-frequency signals which go to the serial audio port. It is recommended that these be constructed to
ensure they are given precedent as design trade-offs are made.
– For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the
recommended layout, please visit the E2E forum to request a layout review.
9.2.1.2.2 Step Two: HybridFlow Selection and System Level Tuning
•
•
88
Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to
select the HybridFlow that meets the needs of the target application.
Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the
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appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577 .
9.2.1.2.3 Step Three: Software Integration
•
•
•
Use the Register Dump feature of the PPC software to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
9.2.1.3 Application Specific Performance Plots for Stereo 2.0 (BTL) Systems
Table 23. Relevant Performance Plots
PLOT TITLE
PLOT NUMBER
Figure 25. Output Power vs PVDD
C036
Figure 26. THD+N vs Frequency, VPVDD = 12 V
C034
Figure 27. THD+N vs Frequency, VPVDD = 15 V
C002
Figure 28. THD+N vs Frequency, VPVDD = 18 V
C037
Figure 29. THD+N vs Frequency, VPVDD = 24 V
C003
Figure 30. THD+N vs Power, VPVDD = 12 V
C035
Figure 31. THD+N vs Power, VPVDD = 15 V
C004
Figure 32. THD+N vs Power, VPVDD = 18 V
C038
Figure 33. THD+N vs Power, VPVDD = 24 V
C005
Figure 34. Idle Channel Noise vs PVDD
C006
Figure 35. Efficiency vs Output Power
C007
Figure 36. Idle Current Draw (Filterless) vs PVDD
C013
Figure 37. Idle Current Draw (Traditional LC Filter) vs PVDD
C015
Figure 40. DVDD PSRR vs. Frequency
C028
Figure 41. AVDD PSRR vs. Frequency
C029
Figure 42. CPVDD PSRR vs. Frequency
C030
Figure 43. Powerdown Current Draw vs. PVDD
C032
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9.2.2 Mono (PBTL) Systems
For the mono (PBTL) PCB layout, see Figure 89.
A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge
Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the
loudspeaker simultaneously using an identical audio signal. The primary benefit of operating the TAS5754M
device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the
amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while
the on-resistance is approximately halved.
The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an
audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed
together and sent through a low-pass filter in order to create a single audio signal which contains the low
frequency information of the two channels. Conversely, advanced digital signal processing can create a lowfrequency signal for a multichannel system, with audio processing which is specifically targeted on low-frequency
effects.
Although any of the HybridFlows can be made to work with a mono speaker, it is strongly recommended that
HybridFlows which have been created specifically for mono applications be used. These HybridFlows contain the
mixing and filtering required to generate the mono signal. They also include processing which is targeted at
improving the low-frequency performance of an audio system- a feature that, while targeted at subwoofers, can
also be used to enhance the low-frequency performance of a full-range speaker.
Because low-frequency signals are not perceived as having a direction (at least to the extent of high-frequency
signals) it is common to reproduce the low-frequency content of a stereo signal that is sent to two separate
channels. This configuration pairs one device in Mono PBTL configuration and another device in Stereo BTL
configuration in a single system called a 2.1 system. The Mono PBTL configuration is detailed in the 2.1 (Stereo
BTL + External Mono Amplifier) Systems section.
90
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PVDD
R200
R201
750k
150k
C200
1µF
GND
C201
0.1µF
GND
To System Processor
C202
1µF
GND
GND
C204
390µF
C203
22µF
GND
GND
3.3V
MONO-SDA
MONO-SCL
MONO-GPIO0
MONO-GPIO1
MONO-SDOUT
MONO-MCLK
MONO-SCLK
MONO-SDIN
C208
0.22µF
C205
1µF
C206
2.2µF
C207
2.2µF
L200
MONO-SPK_OUTA
MONO_OUT+
C220
0.68µF
0.22µF
2
1
SPK_OUTABSTRPA-
PGND
3
5
4
BSTRAPA+
SPK_OUTA+
PVDD
PVDD
7
6
8
SPK_GAIN/FREQ
GVDO
9
10
AGND
11
SPK_INA-
12
SPK_INA+
13
DAC_OUTA
14
AVDD
SCL
SDA
AGND
15
17
16
19
18
GPIO1
GPIO0
ADR1
20
21
GPIO2
GND
SDIN
SCLK
MCLK
24
23
22
C209
U200
TAS5754MDCA
TAS5756MDCA
GND
BSTRPB-
GND
48
PGND
SPK_OUTB47
SPK_OUTB+
45
46
BSTRPB+
44
SPK_FAULT
PVDD
PVDD
PVDD
41
42
43
40
SPK_INB-
PGND
39
38
SPK_INB+
CPVSS
DAC_OUTB
37
36
35
GND
CN
34
CP
33
32
CPVDD
DGND
DVDD_REG
SPK_MUTE
ADR0
DVDD
31
30
29
28
27
26
25
LRCK/FS
PAD
C214
MONO-LRCK/FS
0.22µF
GND
GND
GND
GND
L201
GND
MONO-SPK_OUTB
C210
1µF
R202
3.3V
C212
1µF
C213
1µF
MONO-SPK_MUTE
GND
GND
PVDD
GND
C216
0.1µF
MONO-SPK_FAULT
C221
0.68µF
49.9k
0.22µF
C211
1µF
MONO_OUT-
C215
C217
1µF
C219
390µF
C218
22µF
GND
GND
GND
GND
GND
Figure 81. Mono (PBTL) System Application Schematic
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9.2.2.1 Design Requirements
• Power Supplies:
– 3.3-V Supply
– 5-V to 24-V Supply
• Communication: Host Processor serving as I2C Compliant Master
• External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB
The requirements for the supporting components for the TAS5754M device in a Mono (PBTL) System is provided
in Table 24.
Table 24. Supporting Component Requirements for Mono (PBTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
U200
TAS5754M
48 Pin TSSOP
R200
See Adjustable
Amplifier Gain and
Switching Frequency
Selection
0402
1%, 0.063 W
R201
See Adjustable
Amplifier Gain and
Switching Frequency
Selection
0402
1%, 0.063 W
R202
See Adjustable
Amplifier Gain and
Switching Frequency
Selection
0402
1%, 0.063 W
C298, C299
0.01 µF
0603
Ceramic, 0.01 µF, 50 V, ±10%, X7R
C216
0.1 µF
0402
Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C208, C209, C214,
C215
0.22 µF
0603
Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C220, C221
0.68 µF
0805
Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C200
1 µF
0603
Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C205, C211, C213,
C212
1 µF
0402
Ceramic, 1 µF, 6.3 V, ±10%, X5R
C202, C217, C352,
C367
1 µF
0805
Ceramic, 1 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
2.2 µF
0402
Ceramic, 2.2 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
22 µF
0805
Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
390 µF
10 × 10
Aluminum, 390 µF, ±20%, 0.08-Ω
Voltage rating must be > 1.45 × VPVDD
L200, L201
C206, C207
C203, C218
C204, C219
DETAILED DESCRIPTION
Digital-input, closed-loop class-D amplifier with HybridFlow
processing
See Amplifier Output Filtering
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Step One: Hardware Integration
•
•
92
Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, board layout and routing give in the example layout
above, integrate the device and its supporting components into the system PCB file.
– The most critical section of the circuit is the the power supply inputs, the amplifier output signals, and the
high-frequency signals which go to the serial audio port. It is recommended that these be constructed to
ensure they are given precedent as design trade-offs are made.
– For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the
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recommended layout, please visit the E2E forum to request a layout review.
9.2.2.2.2 Step Two: HybridFlow Selection and System Level Tuning
•
•
Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to
select the HybridFlow that meets the needs of the target application.
Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the
appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577 .
9.2.2.2.3 Step Three: Software Integration
•
•
•
Use the Register Dump feature of the PPC software to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
9.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems
Table 25. Relevant Performance Plots
PLOT TITLE
PLOT NUMBER
Figure 44. Output Power vs PVDD
C039
. THD+N vs Frequency, VPVDD = 12 V
C017
. THD+N vs Frequency, VPVDD = 15 V
C018
Figure 47. THD+N vs Frequency, VPVDD = 18 V
C019
Figure 48. THD+N vs Frequency, VPVDD = 24 V
C020
Figure 49. THD+N vs Power, VPVDD = 12 V
C021
Figure 50. THD+N vs Power, VPVDD = 15 V
C022
Figure 51. THD+N vs Power, VPVDD = 18 V
C023
Figure 52. THD+N vs Power, VPVDD = 24 V
C024
Figure 53. Idle Channel Noise vs PVDD
C025
Figure 54. Efficiency vs Output Power
C026
Figure 55. Idle Current Draw (filterless) vs PVDD
C031
Figure 56. Idle Current Draw (traditional LC filter) vs PVDD
C032
Figure 57. PVDD PSRR vs Frequency
C027
Figure 40. DVDD PSRR vs. Frequency
C028
Figure 41. AVDD PSRR vs. Frequency
C029
Figure 42. CPVDD PSRR vs. Frequency
C030
Figure 43. Powerdown Current Draw vs. PVDD
C032
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9.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
Figure 91 shows the PCB Layout for the 2.1 System.
To increase the low-frequency output capabilities of an audio system, a single subwoofer can be added to the
system. Because the spatial clues for audio are predominately higher frequency than that reproduced by the
subwoofer, often a single subwoofer can be used to reproduce the low frequency content of several other
channels in the system. This is frequently referred to as a dot one system. A stereo system with a subwoofer is
referred to as a 2.1 (two-dot-one), a 3 channel system with subwoofer is referred to as a 3.1 (three-dot-one), a
popular surround system with five speakers and one subwoofer is referred to as a 5.1, and so on.
9.2.3.1 Basic 2.1 System (TAS5754M Device + Simple Digital Input Amplifier)
In the most basic 2.1 system, a subwoofer is added to a stereo left and right pair of speakers as discussed
above. The audio amplifiers include one TAS5754M device for the high frequency channels and one simple
digital input device without integrated audio processing for the subwoofer channel. A member of the popular
TAS5760xx family of devices is a popular choice for the subwoofer amplifier. In this system, the subwoofer
content is generated by summing the two channels of audio and sending them through a high-pass filter to filter
out the high frequency content. This is then sent to the SDIN pin of the subwoofer amplifier, which is operating in
PBTL, via the SDOUT line of the TAS5754M device . In the basic 2.1 system, only HybridFlows which included
subwoofer signal generation can be used, because the subwoofer amplifier depends on the TAS5754M device to
create its stereo low-frequency input signal.
9.2.3.2 Advanced 2.1 System ( Two TAS5754M devices)
In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was
done in the high-frequency channels. To accomplish this, two TAS5754M devices are used- one for the high
frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can
be sent from the TAS5754M device through the SDOUT pin. Alternatively, the subwoofer amplifier can accept
the same digital input as the stereo, which might come from a central systems processor. In advanced 2.1
systems, any HybridFlow can be used for the subwoofer, provided the sample rates for the two are the same.
While any of the HybridFlows can be used, it is highly recommended that only mono HybridFlows are used for
the subwoofer. Doing so streamlines development time and effort by minimizing confusion and complexity.
94
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R300
PVDD
R301
750k
150k
C303
1µF
GND
C300
0.1µF
GND
C301
22µF
GND
C302
22µF
GND
GND
C304
To System Processor
0.22µF
3.3V
2.1-SDA
2.1-SCL
2.1-GPIO0_HF
2.1-GPIO1_HF
L300
2.1-SPK_OUT1A+
2.1-MCLK
2.1-SCLK
2.1-SDIN
C305
1µF
3.3V
C306
2.2µF
2.1-HF_OUTA+
L301
C307
2.2µF
2.1-SPK_OUT1A-
2.1-HF_OUTA-
C309
0.68µF
C310
0.68µF
2
1
0.22µF
U300
TAS5754MDCA
TAS5756MDCA
SPK_OUTABSTRPA-
BSTRAPA+
SPK_OUTA+
PGND
3
5
4
7
6
8
GVDO
SPK_GAIN/FREQ
PVDD
PVDD
10
9
AGND
SPK_INA-
SPK_INA+
11
12
13
14
AVDD
DAC_OUTA
15
17
16
SCL
SDA
AGND
20
19
18
GPIO1
GPIO0
ADR1
GPIO2
SDIN
SCLK
MCLK
GND
21
24
23
22
C308
GND
GND
SPK_OUTB-
48
BSTRPB-
GND
47
PGND
SPK_OUTB+
45
46
BSTRPB+
44
41
42
43
PVDD
PVDD
PVDD
SPK_FAULT
PGND
40
39
38
36
37
SPK_INB-
SPK_INB+
DAC_OUTB
CPVSS
35
CN
GND
34
33
CP
CPVDD
32
31
30
29
DVDD
DGND
DVDD_REG
SPK_MUTE
28
27
26
25
ADR0
LRCK/FS
PAD
C311
2.1-LRCK/FS
0.22µF
GND
GND
GND
GND
L302
GND
2.1-SPK_OUT1BC312
1µF
3.3V
C313
2.2µF
2.1-HF_OUTB-
L303
C314
2.2µF
2.1-SPK_OUT1B+
2.1-HF_OUTB+
C315
C318
1µF
C319
1µF
C320
1µF
C316
0.68µF
GND
0.22µF
PVDD
GND
2.1-SPK_MUTE
GND
GND
C317
0.68µF
GND
GND
C321
0.1µF
2.1-SPK_FAULT
GND
C322
22µF
C323
22µF
GND
GND
PVDD
R350
R351
750k
150k
C350
1µF
GND
C351
0.1µF
GND
C352
1µF
GND
GND
C354
390µF
C353
22µF
GND
GND
3.3V
C358
2.1-GPIO0_LF
2.1-GPIO1
2.1-SDOUT_LF
0.22µF
C355
1µF
C356
2.2µF
C357
2.2µF
L350
2.1-SPK_OUT2A
2.1_LF+
C370
0.68µF
2
1
0.22µF
U301
TAS5754MDCA
TAS5756MDCA
SPK_OUTABSTRPA-
PGND
3
5
4
BSTRAPA+
SPK_OUTA+
PVDD
PVDD
7
6
9
8
GVDO
SPK_GAIN/FREQ
11
10
AGND
SPK_INA-
12
SPK_INA+
14
13
DAC_OUTA
AGND
SCL
SDA
GPIO1
GPIO0
AVDD
15
17
16
20
19
18
ADR1
21
GPIO2
GND
SDIN
SCLK
MCLK
24
23
22
C359
GND
BSTRPB-
GND
48
PGND
SPK_OUTB47
SPK_OUTB+
46
45
BSTRPB+
44
SPK_FAULT
PVDD
PVDD
PVDD
41
42
43
40
PGND
SPK_INB38
39
SPK_INB+
DAC_OUTB
37
36
CN
CPVSS
35
34
GND
CP
33
32
CPVDD
31
DGND
DVDD
30
DVDD_REG
28
29
ADR0
SPK_MUTE
27
26
25
LRCK/FS
PAD
C364
0.22µF
GND
GND
GND
GND
L351
GND
2.1-SPK_OUT2B
C360
1µF
R352
3.3V
C371
0.68µF
0.22µF
C361
1µF
C362
1µF
C363
1µF
GND
PVDD
GND
C366
0.1µF
GND
2.1_LF-
C365
49.9k
C367
1µF
C369
390µF
C368
22µF
GND
GND
GND
GND
GND
Figure 82. 2.1 (Stereo BTL + External Mono Amplifier) Application Schematic
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9.2.3.3 Design Requirements
• Power Supplies:
– 3.3-V Supply
– 5-V to 24-V Supply
• Communication: Host Processor serving as I2C Compliant Master
• External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB
The requirements for the supporting components for the TAS5754M device in a 2.1 (Stereo BTL + External Mono
Amplifier) System is provided in Table 26.
Table 26. Supporting Component Requirements for 2.1 (Stereo BTL + External Mono Amplifier) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
TAS5754M
48 Pin TSSOP
R300, R350
See Adjustable
Amplifier Gain and
Switching Frequency
Selection
0402
1%, 0.063 W
R301, R351
See Adjustable
Amplifier Gain and
Switching Frequency
Selection
0402
1%, 0.063 W
R352
See Adjustable
Amplifier Gain and
Switching Frequency
Selection
0402
1%, 0.063 W
U300
DETAILED DESCRIPTION
Digital-input, closed-loop class-D amplifier with HybridFlow
processing
L300, L301, L302,
L303
See Amplifier Output Filtering
L350, L351
See Amplifier Output Filtering
C394, C395, C396,
C397, C398, C399
0.01 µF
0603
Ceramic, 0.01µF, 50V, +/-10%, X7R
C300, C321, C351,
C366
0.1 µF
0402
Ceramic, 0.1µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C304, C308, C311,
C315, C358, C359,
C364, C365
0.22 µF
0603
Ceramic, 0.22µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C309, C310, C316,
C317, C370, C371
0.68 µF
0805
Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C303, C350, C312,
C360
1 µF
0603
Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C305, C318, C319,
C320, C355, C361,
C363, C312, C362
1 µF
0402
Ceramic, 1 µF, 6.3V, ±10%, X5R
C352, C367
1 µF
0805
Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C306, C307, C313,
C314, C356, C357,
2.2 µF
0402
Ceramic, 2.2 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
C301, C302, C322,
C323, C353, C368
22 µF
0805
Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
C354, C369
390 µF
10 × 10
Aluminum, 390 µF, ±20%, 0.08 Ω
Voltage rating must be > 1.45 × VPVDD
9.2.3.4 Detailed Design Procedure
9.2.3.4.1 Step One: Hardware Integration
•
•
96
Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, board layout and routing give in the example layout
above, integrate the device and its supporting components into the system PCB file.
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– The most critical section of the circuit is the the power supply inputs, the amplifier output signals, and the
high-frequency signals which go to the serial audio port. It is recommended that these be constructed to
ensure they are given precedent as design trade-offs are made.
– For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the
recommended layout, please visit the E2E forum to request a layout review.
9.2.3.4.2 Step Two: HybridFlow Selection and System Level Tuning
•
•
Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to
select the HybridFlow that meets the needs of the target application.
Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the
appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577 .
9.2.3.4.3 Step Three: Software Integration
•
•
•
Use the Register Dump feature of the PPC software to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
9.2.3.5 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems
Table 27. Relevant Performance Plots
DEVICE
U300
U301
PLOT TITLE
PLOT NUMBER
Figure 25. Output Power vs PVDD
C036
Figure 26. THD+N vs Frequency, VPVDD = 12 V
C034
Figure 27. THD+N vs Frequency, VPVDD = 15 V
C002
Figure 28. THD+N vs Frequency, VPVDD = 18 V
C037
Figure 29. THD+N vs Frequency, VPVDD = 24 V
C003
Figure 30. THD+N vs Power, VPVDD = 12 V
C035
Figure 31. THD+N vs Power, VPVDD = 15 V
C004
Figure 32. THD+N vs Power, VPVDD = 18 V
C038
Figure 33. THD+N vs Power, VPVDD = 24 V
C005
Figure 34. Idle Channel Noise vs PVDD
C006
Figure 35. Efficiency vs Output Power
C007
Figure 36. Idle Current Draw (Filterless) vs PVDD
C013
Figure 37. Idle Current Draw (Traditional LC Filter) vs PVDD
C015
Figure 44. Output Power vs PVDD
C039
. THD+N vs Frequency, VPVDD = 12 V
C017
. THD+N vs Frequency, VPVDD = 15 V
C018
Figure 47. THD+N vs Frequency, VPVDD = 18 V
C019
Figure 48. THD+N vs Frequency, VPVDD = 24 V
C020
Figure 49. THD+N vs Power, VPVDD = 12 V
C021
Figure 50. THD+N vs Power, VPVDD = 15 V
C022
Figure 51. THD+N vs Power, VPVDD = 18 V
C023
Figure 52. THD+N vs Power, VPVDD = 24 V
C024
Figure 53. Idle Channel Noise vs PVDD
C025
Figure 54. Efficiency vs Output Power
C026
Figure 55. Idle Current Draw (filterless) vs PVDD
C031
Figure 56. Idle Current Draw (traditional LC filter) vs PVDD
C032
Figure 57. PVDD PSRR vs Frequency
C027
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Table 27. Relevant Performance Plots (continued)
DEVICE
U300
and
U301
PLOT TITLE
PLOT NUMBER
Figure 40. DVDD PSRR vs. Frequency
C028
Figure 41. AVDD PSRR vs. Frequency
C029
Figure 42. CPVDD PSRR vs. Frequency
C030
Figure 43. Powerdown Current Draw vs. PVDD
C032
9.2.4 2.2 (Dual Stereo BTL) Systems
For the 2.2 (Dual Stereo BTL) PCB layout, see Figure 93.
A 2.2 system consists of a stereo pair of loudspeakers with a pair of low frequency loudspeakers. In some cases,
this is implemented as two stereo full-range speakers and two subwoofers. In others, it is implemented as two
high frequency speakers and two mid-range speakers.
As in the case of the 2.1 system, the 2.2 system can be created by using the audio processing inside of the
TAS5754M device and creating a subwoofer signal which is sent to a simple digital input amplifier like one of the
TAS5760xx devices (or similar). This requires that a HybridFlow that contains a subwoofer generation processing
block be used in the TAS5754M device. This signal is created by summing the left and right channel, filtering
with a high-pass filter and sending it to the subwoofer amplifier. For this type of system, the TAS5754M device
used for the high-frequency drivers must have a subwoofer generation processing block in order to provide the
appropriate signal to the subwoofer amplifiers.
Alternatively, the low-frequency drivers can be implemented by using two TAS5754M devices; each receiving
their input from a central systems processor. This type of implementation allows for any stereo HybridFlow to be
used for both the low-frequency and high-frequency drivers, increasing the processing options available for the
system. This expands the processing capabilities of the system, introducing digital signal processing to the lowfrequency drivers as well as the high-frequency drivers. This type of 2.2 system is described in Figure 83.
98
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R400
PVDD
R401
750k
150k
C403
1µF
GND
C400
0.1µF
GND
To System Processor
C401
22µF
GND
C402
22µF
GND
GND
C404
0.22µF
3.3V
2.2-SDA
2.2-SCL
2.2-GPIO0_HF
2.2-GPIO1_HF
L400
2.2-SPK_OUT1A+
2.2-MCLK
2.2-SCLK
2.2-SDIN
C405
1µF
3.3V
C406
2.2µF
2.2-HF_OUTA+
L401
C407
2.2µF
2.2-SPK_OUT1A-
2.2-HF_OUTA-
C410
0.68µF
0.22µF
2
1
3
PGND
BSTRAPA+
SPK_OUTA+
C409
0.68µF
U400
TAS5754MDCA
TAS5756MDCA
SPK_OUTABSTRPA-
7
6
5
4
PVDD
PVDD
9
8
SPK_GAIN/FREQ
GVDO
10
AGND
12
11
SPK_INA-
SPK_INA+
14
13
DAC_OUTA
15
AGND
AVDD
17
16
SCL
SDA
20
21
19
18
GPIO1
GPIO0
ADR1
GPIO2
GND
SDIN
SCLK
MCLK
24
23
22
C408
GND
GND
BSTRPB-
SPK_OUTB-
GND
48
47
PGND
SPK_OUTB+
46
BSTRPB+
44
45
41
42
43
PVDD
PVDD
PVDD
SPK_FAULT
PGND
40
39
SPK_INB+
SPK_INB38
DAC_OUTB
36
37
CPVSS
35
GND
CN
34
CP
33
32
CPVDD
31
30
DVDD
DGND
29
SPK_MUTE
DVDD_REG
28
27
ADR0
26
25
LRCK/FS
PAD
C411
2.2-LRCK/FS
0.22µF
GND
GND
GND
GND
GND
L402
2.2-SPK_OUT1BC412
1µF
3.3V
C413
2.2µF
2.2-HF_OUTB-
L403
C414
2.2µF
2.2-SPK_OUT1B+
2.2-HF_OUTB+
C415
C418
1µF
C419
1µF
C420
1µF
C416
0.68µF
GND
0.22µF
PVDD
GND
2.2-SPK_MUTE
GND
GND
C417
0.68µF
GND
GND
C421
0.1µF
2.2-SPK_FAULT
C422
22µF
GND
R450
C423
22µF
GND
GND
PVDD
R451
750k
150k
C453
1µF
GND
C450
0.1µF
GND
C451
22µF
GND
C452
22µF
GND
GND
C454
0.22µF
3.3V
L450
2.2-SPK_OUT2A+
2.2-GPIO0_LF
2.2-GPIO1_LF
2.2-SDOUT_LF
C455
1µF
3.3V
C456
2.2µF
2.2-LF_OUTA+
L451
C457
2.2µF
2.2-SPK_OUT2A-
2.2-LF_OUTA-
C459
0.68µF
C460
0.68µF
2
1
0.22µF
U401
TAS5754MDCA
TAS5756MDCA
SPK_OUTABSTRPA-
BSTRAPA+
SPK_OUTA+
PGND
3
5
4
7
6
PVDD
PVDD
9
8
SPK_GAIN/FREQ
GVDO
10
AGND
11
SPK_INA-
12
SPK_INA+
14
13
DAC_OUTA
AGND
AVDD
15
17
16
SCL
SDA
19
18
GPIO1
GPIO0
21
20
ADR1
GPIO2
GND
SDIN
SCLK
MCLK
24
23
22
C458
GND
GND
BSTRPB-
SPK_OUTB-
GND
48
47
PGND
SPK_OUTB+
46
BSTRPB+
44
45
PVDD
PVDD
PVDD
41
42
43
SPK_FAULT
PGND
40
39
SPK_INB38
SPK_INB+
DAC_OUTB
36
37
CPVSS
35
CN
34
GND
CP
33
32
DVDD
CPVDD
31
30
DGND
29
SPK_MUTE
DVDD_REG
28
27
ADR0
26
25
LRCK/FS
PAD
C461
0.22µF
GND
GND
GND
GND
GND
L452
2.2-SPK_OUT2B3.3V
C462
1µF
C463
2.2µF
2.2-LF_OUTB-
L453
C464
2.2µF
2.2-SPK_OUT2B+
2.2-LF_OUTB+
C465
C468
1µF
C469
1µF
C470
1µF
C466
0.68µF
GND
PVDD
0.22µF
GND
GND
GND
C467
0.68µF
GND
GND
C471
0.1µF
GND
C472
22µF
GND
C473
22µF
GND
Figure 83. 2.2 (Dual Stereo BTL) Application Schematic
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9.2.4.1 Design Requirements
• Power Supplies:
– 3.3-V Supply
– 5-V to 24-V Supply
• Communication: Host Processor serving as I2C Compliant Master
• External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB
The requirements for the supporting components for the TAS5754M device in a 2.1 (Stereo BTL + External Mono
Amplifier) System is provided in Figure 89.
Table 28. Supporting Component Requirements for 2.2 (Dual Stereo BTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
TAS5754M device
48-pin TSSOP
Digital Input, Closed-Loop ClassD Amplifier with HybridFlow
Processing
R400, R450
See Figure 84
0402
1%, 0.063 W
R401, R451
See Figure 84
0402
1%, 0.063 W
U400, U401
L400, L401, L402, L403, L450,
L451, L452, L453
C492, C493, C494, C495, C496,
C497, C498, C499
See Amplifier Output Filtering
0.01 µF
0603
Ceramic, 0.01 µF, 50 V, ±10%,
X7R
0.1 µF
0402
Ceramic, 0.1 µF, ±10%, X7R,
Voltage rating must be > 1.45 ×
VPVDD
C404, C408, C411, C415, C454,
C458, C461, C465
0.22 µF
0603
Ceramic, 0.22 µF, ±10%, X7R,
Voltage rating must be > 1.45 ×
VPVDD
C409, C410, C416, C417, C459,
C460, C466, C467
0.68 µF
0805
Ceramic, 0.68 µF, ±10%, X7R,
Voltage rating must be > 1.8 ×
VPVDD
1 µF
0603
Ceramic, 1 µF, ±10%, X7R,
Voltage rating must be > 1.45 ×
VPVDD
1 µF
0402
C406, C407, C413, C414, C456,
C457, C463, C464
2.2 µF
0402
Ceramic, 2.2 µF, ±10%, X5R,
Voltage rating must be > 1.45 ×
VPVDD
C401, C402, C422, C423, C451,
C452, C472, C473
22 µF
0805
Ceramic, 22 µF, ±20%, X5R,
Voltage rating must be > 1.45 ×
VPVDD
C400, C421, C450, C471
C403, C453, C462
C405, C418, C419, C420, C455,
C468, C469, C470, C412, C462
Ceramic, 1 µF, 6.3V, ±10%, X5R
9.2.4.2 Detailed Design Procedure
9.2.4.2.1 Step One: Hardware Integration
•
•
Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, board layout and routing give in the example layout
above, integrate the device and its supporting components into the system PCB file.
– The most critical section of the circuit is the the power supply inputs, the amplifier output signals, and the
high-frequency signals which go to the serial audio port. It is recommended that these be constructed to
ensure they are given precedent as design trade-offs are made.
– For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the
recommended layout, please visit the E2E forum to request a layout review.
9.2.4.2.2 Step Two: HybridFlow Selection and System Level Tuning
•
100
Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to
select the HybridFlow that meets the needs of the target application.
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Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the
appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577 .
9.2.4.2.3 Step Three: Software Integration
•
•
•
Use the Register Dump feature of the PPC software to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
9.2.4.3 Application Specific Performance Plots for 2.2 (Dual Stereo BTL) Systems
Table 29. Relevant Performance Plots
PLOT TITLE
PLOT NUMBER
Figure 25. Output Power vs PVDD
C036
Figure 26. THD+N vs Frequency, VPVDD = 12 V
C034
Figure 27. THD+N vs Frequency, VPVDD = 15 V
C002
Figure 28. THD+N vs Frequency, VPVDD = 18 V
C037
Figure 29. THD+N vs Frequency, VPVDD = 24 V
C003
Figure 30. THD+N vs Power, VPVDD = 12 V
C035
Figure 31. THD+N vs Power, VPVDD = 15 V
C004
Figure 32. THD+N vs Power, VPVDD = 18 V
C038
Figure 33. THD+N vs Power, VPVDD = 24 V
C005
Figure 34. Idle Channel Noise vs PVDD
C006
Figure 35. Efficiency vs Output Power
C007
Figure 36. Idle Current Draw (Filterless) vs PVDD
C013
Figure 37. Idle Current Draw (Traditional LC Filter) vs PVDD
C015
Figure 40. DVDD PSRR vs. Frequency
C028
Figure 41. AVDD PSRR vs. Frequency
C029
Figure 42. CPVDD PSRR vs. Frequency
C030
Figure 43. Powerdown Current Draw vs. PVDD
C032
9.2.5 1.1 (Dual BTL, Bi-Amped) Systems
The 1.1 use case is a special application of the 2.0 stereo BTL system. In this system, two channels of an
amplifier are used to reproduce a single channel of an audio signal that has been separated based on frequency.
This configuration removes the need for passive cross-over elements inside of a loudspeaker, because the signal
is separated into a low-frequency and a high-frequency component before it is amplified. Systems which operate
in this configuration, in which separate amplifier channels drive the low and high-frequency loudspeakers directly,
are often called “bi-amped” systems.
Popular applications for this configuration include:
• Powered near-field monitors
• Blue-tooth Speakers
• Co-axial Loudspeakers
• Surround/Fill Speakers for multi-channel audio
From a hardware perspective, the TAS5754M device is configured in the same way as the Stereo BTL system.
However, special HybridFlows which support 1.1 operation must be used, because HybridFlows that are
designed for stereo applications frequently apply the same equalizer curves to the left and the right hand
channel. Additionally, many 1.1 HybridFlows include a delay element which can improve time alignment between
two loudspeakers that are mounted on the same baffle some distance apart.
For the 1.1 (Dual BTL, Bi-Amped) PCB layout, see Figure 95.
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R500
PVDD
R501
750k
150k
C503
1µF
GND
C500
0.1µF
GND
C501
22µF
GND
C502
22µF
GND
GND
C504
To System Processor
0.22µF
3.3V
1.1-SDA
1.1-SCL
1.1-GPIO0
1.1-GPIO1
1.1-SDOUT
1.1-MCLK
1.1-SCLK
1.1-SDIN
L500
1.1-SPK_OUTA+
C505
1µF
3.3V
C506
2.2µF
1.1_LF+
L501
C507
2.2µF
1.1-SPK_OUTA-
1.1_LF-
C509
0.68µF
C510
2
1
0.22µF
U500
TAS5754MDCA
TAS5756MDCA
SPK_OUTABSTRPA-
PGND
3
5
4
BSTRAPA+
SPK_OUTA+
PVDD
PVDD
7
6
8
SPK_GAIN/FREQ
GVDO
9
10
AGND
SPK_INA-
11
12
DAC_OUTA
SPK_INA+
13
14
AVDD
SCL
SDA
AGND
15
17
16
19
18
GPIO1
GPIO0
21
20
ADR1
SDIN
SCLK
MCLK
GND
GPIO2
24
23
22
C508
GND
GND
BSTRPB-
GND
48
PGND
SPK_OUTB47
SPK_OUTB+
46
45
BSTRPB+
44
SPK_FAULT
PVDD
PVDD
PVDD
41
42
43
40
SPK_INB-
PGND
39
SPK_INB+
37
38
CPVSS
CN
DAC_OUTB
36
35
34
GND
CP
32
33
DVDD
DGND
DVDD_REG
CPVDD
31
30
29
28
ADR0
SPK_MUTE
27
25
26
LRCK/FS
PAD
C511
1.1-LRCK/FS
0.22µF
GND
GND
GND
GND
GND
L502
1.1-SPK_OUTB-
3.3V
C512
1µF
C513
2.2µF
1.1_HF-
L503
C514
2.2µF
1.1-SPK_OUTB+
1.1_HF+
C515
C518
1µF
1.1-SPK_MUTE
C519
1µF
C520
1µF
C516
0.68µF
GND
PVDD
GND
GND
GND
C517
0.68µF
0.22µF
GND
GND
C521
0.1µF
1.1-SPK_FAULT
GND
C522
22µF
GND
C523
22µF
GND
Figure 84. 1.1 (Dual BTL, Bi-Amped) Application Schematic
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9.2.5.1 Design Requirements
• Power Supplies:
– DVDD Supply, in compliance with the voltage ranges shown in the Recommended Operating Conditions
table.
– PVDD Supply, in compliance with the voltage ranges shown in the Recommended Operating Conditions
table.
• Communication: Host Processor serving as I2C Compliant Master
• External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB
The requirements for the supporting components for the TAS5754M device in a Dual BTL, Bi-Amped System is
provided in Figure 95.
Table 30. Supporting Component Requirements for 1.1 (Dual BTL, Bi-Amped) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
U500
TAS5754M
48 Pin TSSOP
R500
See Adjustable
Amplifier Gain and
Switching Frequency
Selection
0402
1%, 0.063 W
R501
See Adjustable
Amplifier Gain and
Switching Frequency
Selection
0402
1%, 0.063 W
L500, L501, L502,
L503
DETAILED DESCRIPTION
Digital-input, closed-loop class-D amplifier with HybridFlow
processing
See Amplifier Output Filtering
C596, C597, C598,
C599
0.01 µF
0603
Ceramic, 0.01 µF, 50 V, ±10%, X7R
C500, C521
0.1 µF
0402
Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C504, C508, C511,
C515
0.22 µF
0603
Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C509, C510, C516,
C517
0.68 µF
0805
Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C503
1 µF
0603
Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C505, C518, C519,
C520, C512
1 µF
0402
Ceramic, 1 µF, 6.3V, ±10%, X5R
C506, C507, C513,
C514
2.2 µF
0402
Ceramic, 2.2 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
22 µF
805
C501, C502, C522,
C523
Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
9.2.5.2 Detailed Design Procedure
9.2.5.2.1 Step One: Hardware Integration
•
•
Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, board layout and routing give in the example layout
above, integrate the device and its supporting components into the system PCB file.
– The most critical section of the circuit is the the power supply inputs, the amplifier output signals, and the
high-frequency signals which go to the serial audio port. It is recommended that these be constructed to
ensure they are given precedent as design trade-offs are made.
– For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the
recommended layout, please visit the E2E forum to request a layout review.
9.2.5.2.2 Step Two: HybridFlow Selection and System Level Tuning
•
Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to
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•
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select the HybridFlow that meets the needs of the target application.
Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the
appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577 .
9.2.5.2.3 Step Three: Software Integration
•
•
•
Use the Register Dump feature of the PPC software to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
9.2.5.3 Application Specific Performance Plots for 1.1 (Dual BTL, Bi-Amped) Systems
Table 31. Relevant Performance Plots
PLOT TITLE
104
PLOT NUMBER
Figure 25. Output Power vs PVDD
C036
Figure 26. THD+N vs Frequency, VPVDD = 12 V
C034
Figure 27. THD+N vs Frequency, VPVDD = 15 V
C002
Figure 28. THD+N vs Frequency, VPVDD = 18 V
C037
Figure 29. THD+N vs Frequency, VPVDD = 24 V
C003
Figure 30. THD+N vs Power, VPVDD = 12 V
C035
Figure 31. THD+N vs Power, VPVDD = 15 V
C004
Figure 32. THD+N vs Power, VPVDD = 18 V
C038
Figure 33. THD+N vs Power, VPVDD = 24 V
C005
Figure 34. Idle Channel Noise vs PVDD
C006
Figure 35. Efficiency vs Output Power
C007
Figure 36. Idle Current Draw (Filterless) vs PVDD
C013
Figure 37. Idle Current Draw (Traditional LC Filter) vs PVDD
C015
Figure 40. DVDD PSRR vs. Frequency
C028
Figure 41. AVDD PSRR vs. Frequency
C029
Figure 42. CPVDD PSRR vs. Frequency
C030
Figure 43. Powerdown Current Draw vs. PVDD
C032
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10 Power Supply Recommendations
10.1 Power Supplies
The TAS5754M device requires two power supplies for proper operation. A high-voltage supply called PVDD is
required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one lowvoltage power supply called DVDD is required to power the various low-power portions of the device. The
allowable voltage range for both the PVDD and the DVDD supply are listed in the Recommended Operating
Conditions table.
AVDD
Internal Analog Circuitry
Internal Mixed
Signal Circuitry
DVDD
+
±
Internal Digital
Circuitry
DVDD
DVDD_REG
LDO
External Filtering/Decoupling
CPVDD
CPVSS
Charge
Pump
External Filtering/Decoupling
DAC Output Stage
(Positive)
DAC Output Stage
(Negative)
Output Stage
Power Supply
Gate Drive
Voltage
PVDD
GVDD_REG
Linear
Regulator
PVDD
External Filtering/Decoupling
+
±
Figure 85. Power Supply Functional Block Diagram
10.1.1 DVDD Supply
The DVDD supply required from the system is used to power several portions of the device. As shown in the
Figure 85, it provides power to the DVDD pin, the CPVDD pin, and the AVDD pin. Proper connection, routing,
and decoupling techniques are highlighted in the TAS5754M device EVM User's Guide SLAU583 (as well as the
Applications and Implementation section and Layout Examples section) and must be followed as closely as
possible for proper operation and performance. Deviation from the guidance offered in the TAS5754M device
EVM User's Guide, which followed the same techniques as those shown in the Applications and Implementation
section, may result in reduced performance, errant functionality, or even damage to the TAS5754M device.
Some portions of the device also require a separate power supply which is a lower voltage than the DVDD
supply. To simplify the power supply requirements for the system, the TAS5754M device includes an integrated
low-dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD
supply and its output is presented on the DVDD_REG pin, providing a connection point for an external bypass
capacitor. It is important to note that the linear regulator integrated in the device has only been designed to
support the current requirements of the internal circuitry, and should not be used to power any additional external
circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and
operation of the device.
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Power Supplies (continued)
The outputs of the high-performance DACs used in the TAS5754M device are ground centered, requiring both a
positive low-voltage supply and a negative low-voltage supply. The positive power supply for the DAC output
stage is taken from the AVDD pin, which is connected to the DVDD supply provided by the system. A charge
pump is integrated in the TAS5754M device to generate the negative low-voltage supply. The power supply input
for the charge pump is the CPVDD pin. The CPVSS pin is provided to allow the connection of a filter capacitor
on the negative low-voltage supply. As is the case with the other supplies, the component selection, placement,
and routing of the external components for these low voltage supplies are shown in the evmName and should be
followed as closely as possible to ensure proper operation of the device.
10.1.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the evmName and must be followed as closely as possible for proper operation and performance.
Due the high-voltage switching of the output stage, it is particularly important to properly decouple the output
power stages in the manner described in the TAS5754M device EVM User's Guide. Lack of proper decoupling,
like that shown in the EVM User's Guide, results in voltage spikes which can damage the device.
A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker
amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD_REG
pin is provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to
note that the linear regulator integrated in the device has only been designed to support the current requirements
of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on
this pin could cause the voltage to sag, negatively affecting the performance and operation of the device.
106
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11 Layout
11.1 Layout Guidelines
11.1.1 General Guidelines for Audio Amplifiers
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout.
Ideally, the guidance provided in the applications section with regard to device and component selection can be
followed by precise adherence to the layout guidance shown in . These examples represent exemplary baseline
balance of the engineering trade-offs involved with laying out the device. These designs can be modified slightly
as needed to meet the needs of a given application. In some applications, for instance, solution size can be
compromised in order to improve thermal performance through the use of additional contiguous copper near the
device. Conversely, EMI performance can be prioritized over thermal performance by routing on internal traces
and incorporating a via picket-fence and additional filtering components. In all cases, it is recommended to start
from the guidance shown in the Layout Examples section and the TAS5754M-56MEVM, and work with TI field
application engineers or through the E2E community in order to modify it based upon the application specific
goals.
11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
Placing the bypassing and decoupling capacitors close to supply has been long understood in the industry. This
applies to DVDD, AVDD, CPVDD, and PVDD. However, the capacitors on the PVDD net for the TAS5754M
device deserve special attention.
It is imperative that the small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins
as possible. Not only does placing these devices far away from the pins increase the electromagnetic
interference in the system, but doing so can also negatively affect the reliability of the device. Placement of these
components too far from the TAS5754M device may cause ringing on the output pins that can cause the voltage
on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table,
damaging the device. For that reason, the capacitors on the PVDD net must be no further away from their
associated PVDD pins than what is shown in the example layouts in the Layout Examples section
11.1.3 Optimizing Thermal Performance
Follow the layout examples shown in the Layout Examples section of this document to achieve the best balance
of solution size, thermal, audio, and electromagnetic performance. In some cases, deviation from this guidance
may be required due to design constraints which cannot be avoided. In these instances, the system designer
should ensure that the heat can get out of the device and into the ambient air surrounding the device.
Fortunately, the heat created in the device would prefer to travel away from the device and into the lower
temperature structures around the device.
11.1.3.1 Device, Copper, and Component Layout
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips should be followed to achieve that goal:
• Avoid placing other heat producing components or structures near the amplifier (including above or below in
the end equipment).
• If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5754M device
and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top
and bottom layer.
• Place the TAS5754M device away from the edge of the PCB when possible to ensure that heat can travel
away from the device on all four sides.
• Avoid cutting off the flow of heat from the TAS5754M device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
• Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient it so that the narrow end of the passive component is facing the TAS5754M
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Layout Guidelines (continued)
•
device .
Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane
from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.
11.1.3.2 Stencil Pattern
The recommended drawings for the TAS5754M device PCB foot print and associated stencil pattern are shown
at the end of this document in the package addendum. Additionally, baseline recommendations for the via
arrangement under and around the device are given as a starting point for the PCB design. This guidance is
provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all
other performance criteria. In elevated ambient temperatures or under high-power dissipation use-cases, this
guidance may be too conservative and advanced PCB design techniques may be used to improve thermal
performance of the system. It is important to note that the customer must verify that deviation from the guidance
shown in the package addendum, including the deviation explained in this section, meets the customer’s quality,
reliability, and manufacturability goals.
11.1.3.2.1 PCB footprint and Via Arrangement
The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the
shape and position of the copper patterns to which the TAS5754M device will be soldered to. This footprint can
be followed directly from the guidance in the package addendum at the end of this data sheet. It is important to
make sure that the thermal pad, which connects electrically and thermally to the PowerPAD of the TAS5754M
device , be made no smaller than what is specified in the package addendum. This ensures that the TAS5754M
device has the largest interface possible to move heat from the device to the board.
The via pattern shown in the package addendum provides an improved interface to carry the heat from the
device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)
present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away
from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the
Layout Examples section, this interface can benefit from improved thermal performance.
NOTE
Vias can obstruct heat flow if they are not constructed properly.
•
•
•
•
•
•
Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the
additional cost of filled vias.
The drill diameter should be no more than 8mils in diameter. Also, the distance between the via barrel and
the surrounding planes should be minimized to help heat flow from the via into the surrounding copper
material. In all cases, minimum spacing should be determined by the voltages present on the planes
surrounding the via and minimized wherever possible.
Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding
area. This arrangement is shown in the Layout Examples section.
Ensure that vias do not cut-off power current flow from the power supply through the planes on internal
layers. If needed, remove some vias which are farthest from the TAS5754M device to open up the current
path to and from the device.
11.1.3.2.1.1 Solder Stencil
During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste
on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity
and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most
cases, the aperture for each of the component pads is almost the same size as the pad itself.
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Layout Guidelines (continued)
However, the thermal pad on the PCB is quite large and depositing a large, single deposition of solder paste
would lead to manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the
solder paste to outgas during the assembly process and reduce the risk of solder bridging under the device. This
structure is called an aperture array, and is shown in the Layout Examples section. It is important that the total
area of the aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the
area of the thermal pad itself.
11.2 Layout Examples
11.2.1 2.0 (Stereo BTL) System
Figure 86. 2.0 (Stereo BTL) 3-D View
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Layout Examples (continued)
Figure 87. 2.0 (Stereo BTL) Top Copper View
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Layout Examples (continued)
11.2.2 Mono (PBTL) System
Figure 88. Mono (PBTL) 3-D View
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Layout Examples (continued)
Figure 89. Mono (PBTL) Top Copper View
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Layout Examples (continued)
11.2.3 2.1 (Stereo BTL + Mono PBTL) Systems
Figure 90. 2.1 (Stereo BTL + Mono PBTL) 3-D View
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Layout Examples (continued)
Figure 91. 2.1 (Stereo BTL + Mono PBTL) Top Copper View
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Layout Examples (continued)
11.2.4 2.2 (Dual Stereo BTL) Systems
Figure 92. 2.2 (Dual Stereo BTL) 3-D View
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Layout Examples (continued)
Figure 93. 2.2.2 (Dual Stereo BTL) Top Copper View
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Layout Examples (continued)
11.2.5 1.1 (Bi-Amped BTL) Systems
Figure 94. 1.1 (Bi-Amped BTL) 3-D View
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Layout Examples (continued)
Figure 95. 2. 1.1 (Bi-Amped BTL) Top Copper View
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Specification Definitions
The glossary listed in the Glossary section is a general glossary with commonly used acronyms and words which
are defined in accordance with a broad TI initiative to comply with industry standards such as JEDEC, IPC, IEEE,
and others. The glossary provided in this section defines words, phrases, and acronyms that are unique to this
product and documentation, collateral, or support tools and software used with this product. For any additional
questions regarding definitions and terminology, please see the e2e Audio Amplfier Forum.
Bridge tied load (BTL) is an output configuration in which one terminal of the speaker is connected to one halfbridge and the other terminal is connected to another half-bridge.
DUT refers to a device under test to differentiate one device from another.
Closed-loop architecture describes a topology in which the amplifier monitors the output terminals, comparing
the output signal to the input signal and attempts to correct for non-linearities in the output.
Dynamic controls are those which are changed during normal use by either the system or the end-user.
GPIO is a general purpose input/output pin. It is a highly configurable, bi-directional digital pin which can perform
many functions as required by the system.
Host processor refers to device which serves as a central system controller, providing control information to
devices connected to it as well as gathering audio source data from devices upstream from it and distributing it to
other devices. Configuring the controls of a device to optimize the audio output of a loudspeaker based on
frequency response, time alignment, target sound pressure level, safe operating area of the system, and user
preference.
HybridFlow uses components which are built in RAM and components which are built in ROM to make a
configurable device that is easier to use than a fully-programmable device while remaining flexible enough to be
used in several applications
Maximum continuous output power refers to the maximum output power that the amplifier can continuously
deliver without shutting down when operated in a 25°C ambient temperature. Testing is performed for the period
of time required that their temperatures reach thermal equilibrium and are no longer increasing
Parallel bridge tied load (PBTL) is an output configuration in which one terminal of the speaker is connected to
two half-bridges which have been placed in parallel and the other terminal is connected to another pair of half
bridges placed in parallel
rDS(on) is a measure of the on-resistance of the MOSFETs used in the output stage of the amplifier.
Static configuration information are controls which do not change while the system is in normal use.
Vias are copper-plated through-hole in a PCB.
12.2 Trademarks
PurePath is a trademark of Texas Instruments.
Burr-Brown is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TAS5754MDCA
ACTIVE
HTSSOP
DCA
48
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-25 to 85
TAS5754M
TAS5754MDCAR
ACTIVE
HTSSOP
DCA
48
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-25 to 85
TAS5754M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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