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TAS5756M
Burr-Brown Audio
SLAS988B – JUNE 2014 – REVISED AUGUST 2015
TAS5756M Digital Input, Closed-Loop Class-D Amplifier With Processing
1 Features
3 Description
•
The TAS5756M device is a high-performance, stereo
closed-loop amplifier with integrated audio processor
with architecture. To convert from digital to analog,
the device uses a high performance DAC with BurrBrown® mixed signal heritage. It requires only two
power supplies; one DVDD for low-voltage circuitry
and one PVDD for high-voltage circuitry. It is
controlled by a software control port using standard
I2C communication. In the family, the TAS5756M
uses traditional BD modulation, ensuring low
distortion characteristics. The TAS5754M uses 1SPW
modulation to reduce output ripple current, the
expense of slightly higher distortion.
1
•
•
•
•
Flexible Audio I/O Configuration
– Supports I2S, TDM, LJ, RJ Digital Input
– 8 kHz to 192 kHz Sample Rate Support
– Stereo Bridge Tied Load (BTL) or Mono
Parallel Bridge Tied Load (PBTL) Operation
– BD Amplifier Modulation
– Supports 3-Wire Digital Audio Interface (No
MCLK required)
High-Performance Closed-Loop Architecture
(PVDD = 12V, RSPK = 8 Ω, SPK_GAIN = 20 dBV)
– Idle Channel Noise = 56 µVrms (A-Wtd)
– THD+N = 0.006 % (at 1 W, 1 kHz)
– SNR = 104 A-Wtd (Ref. to THD+N = 1%)
PurePath™ HybridFlow Processing Architecture
– Several Configurable MiniDSP Programs
(called HybridFlows)
– Download Time 0, P = 1
6.7
20
1
20
Clock divider uses integer divide
D = 0, P = 1
fS (2)
MHz
A unit of fS indicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the
TAS5756M device.
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Product Folder Links: TAS5756M
TAS5756M
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SLAS988B – JUNE 2014 – REVISED AUGUST 2015
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL AUDIO PORT
tDLY
Required LRCK/FS to
SCLK rising edge delay
DSCLK
Allowable SCLK duty
cycle
fS
Supported input sample
rates
fSCLK
Supported SCLK
frequencies
fSCLK
SCLK frequency
5
ns
40%
60%
8
192
kHz
32
64
fS (2)
24.576
MHz
Either master mode or slave mode
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)
AV(SPK_AMP)
Speaker amplifier gain
SPK_GAIN/FREQ voltage < 3 V,
see Adjustable Amplifier Gain and Switching
Frequency Selection
20
dBV
SPK_GAIN/FREQ voltage > 3.3 V,
see Adjustable Amplifier Gain and Switching
Frequency Selection
26
dBV
±1
dBV
ΔAV(SPK_AMP)
Typical variation of
speaker amplifier gain
fSPK_AMP
Switching frequency of
the speaker amplifier
Switching frequency depends on voltage
presented at SPK_GAIN/FREQ pin and the
clocking arrangement, including the incoming
sample rate, see Adjustable Amplifier Gain
and Switching Frequency Selection
KSVR
Power supply rejection
ratio
Injected Noise = 50 Hz to 60 Hz, 200 mVP-P,
Gain = 26 dBV, input audio signal = digital
zero
60
dB
rDS(on)
Drain-to-source on
resistance of the
individual output
MOSFETs
VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C,
includes PVDD/PGND pins, leadframe,
bondwires and metallization layers.
90
mΩ
VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C
90
mΩ
OCETHRES
SPK_OUTxx Overcurrent
Error Threshold
7.5
A
OTETHRES
Overtemperature Error
Threshold
150
°C
OCECLRTIME
Time required to clear
Overcurrent Error after
error condition is
removed.
1.3
s
OTECLRTIME
Time required to clear
Overtemperature Error
after error condition is
removed.
1.3
s
OVETHRES(PVDD)
PVDD Overvoltage Error
Threshold
27
V
UVETHRES(PVDD)
PVDD Undervoltage Error
Threshold
4.5
V
176.4
768
kHz
SPEAKER AMPLIFIER (STEREO BTL)
|VOS|
Amplifier offset voltage
Measured differentially with zero input data,
SPK_GAIN/FREQ pin configured for 20 dBV
gain, VPVDD = 12 V
2
Measured differentially with zero input data,
SPK_GAIN/FREQ pin configured for 26 dBV
gain, VPVDD = 24 V
6
10
mV
15
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TAS5756M
SLAS988B – JUNE 2014 – REVISED AUGUST 2015
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ICN(SPK)
Idle channel noise
Output Power (Per
Channel)
PO(SPK)
Signal-to-noise ratio
(referenced to 0 dBFS
input signal)
SNR
THD+NSPK
12
Total harmonic distortion
and noise
TEST CONDITIONS
MIN
TYP
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, A-Weighted
56
VPVDD = 15 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, A-Weighted
58
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted
86
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted
88
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
15
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
20
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
28
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, THD+N = 0.1%
20
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
18
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
18
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
18
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
12
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
104
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
104
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
106
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
105
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4
Ω, PO = 1 W
0.011%
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, PO = 1 W
0.007%
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
0.02%
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
0.015%
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
0.01%
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
0.017%
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
0.015%
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
0.017%
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MAX
UNIT
µVRMS
W
dB
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TAS5756M
TAS5756M
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SLAS988B – JUNE 2014 – REVISED AUGUST 2015
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
X-talkSPK
Cross-talk (worst case
between left-to-right and
right-to-left coupling)
TEST CONDITIONS
MIN
TYP
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)
–88
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)
–97
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)
–88
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)
–88
Measured differentially with zero input data,
SPK_GAIN/FREQ pin configured for 20 dBV
gain, VPVDD = 12 V
0.5
Measured differentially with zero input data,
SPK_GAIN/FREQ pin configured for 26 dBV
gain, VPVDD = 24 V
1
VPVDD = 15 V, SPK_GAIN = 20 dBV, RSPK =
8 Ω, A-Weighted
58
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, A-Weighted
57
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK =
8 Ω, A-Weighted
85
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted
85
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, THD+N = 0.1%, Unless otherwise noted
40
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
56
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
34
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, THD+N = 0.1%, Unless otherwise noted
40
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, THD+N = 0.1%
8
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
36
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
21.3
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, THD+N = 0.1%, Unless otherwise noted
36
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
24
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
13.5
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 2
Ω, THD+N = 0.1%, Unless otherwise noted
30
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
15
MAX
UNIT
dB
SPEAKER AMPLIFIER (MONO PBTL)
|VOS|
ICN
PO
Amplifier offset voltage
Idle channel noise
Output Power (Per
Channel)
8
mV
14
µVRMS
W
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SLAS988B – JUNE 2014 – REVISED AUGUST 2015
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Signal-to-noise ratio
(referenced to 0 dBFS
input signal)
SNR
Total harmonic distortion
and noise
THD+N
TEST CONDITIONS
MIN
TYP
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
104
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
104
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
107
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
105
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4
Ω, PO = 1 W
0.013%
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, PO = 1 W
0.007%
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
0.02%
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, PO = 1 W
0.028%
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
0.018%
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
0.017%
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, PO = 1 W
0.027%
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
0.016%
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, PO = 1 W
0.03%
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
0.01%
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 2
Ω, PO = 1 W
0.03%
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
0.012%
MAX
UNIT
dB
7.6 MCLK Timing
See Figure 18.
MIN
NOM
20
MAX
UNIT
1000
ns
tMCLK
MCLK period
tMCLKH
MCLK pulse width, high
9
ns
tMCLKL
MCLK pulse width, low
9
ns
7.7 Serial Audio Port Timing – Slave Mode
See Figure 19.
MIN
MAX
UNIT
SCLK frequency
tSCLK
SCLK period
40
ns
tSCLKL
SCLK pulse width, low
16
ns
tSCLKH
SCLK pulse width, high
16
ns
tSL
SCLK rising to LRCK/FS edge
8
ns
tLS
LRCK/FS Edge to SCLK rising edge
8
ns
tSU
Data setup time, before SCLK rising edge
8
ns
tDH
Data hold time, after SCLK rising edge
8
ns
14
1.024
NOM
fSCLK
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MHz
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TAS5756M
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SLAS988B – JUNE 2014 – REVISED AUGUST 2015
Serial Audio Port Timing – Slave Mode (continued)
See Figure 19.
MIN
tDFS
NOM
Data delay time from SCLK falling edge
MAX
UNIT
15
ns
7.8 Serial Audio Port Timing – Master Mode
See Figure 20.
MIN
NOM
MAX
UNIT
tSCLK
SCLK period
40
ns
tSCLKL
SCLK pulse width, low
16
ns
tSCLKH
SCLK pulse width, high
16
tLRD
LRCK/FS delay time from to SCLK falling edge
tSU
Data setup time, before SCLK rising edge
8
tDH
Data hold time, after SCLK rising edge
8
tDFS
Data delay time from SCLK falling edge
ns
–10
20
ns
ns
ns
15
ns
7.9 I2C Bus Timing – Standard
MIN
MAX
UNIT
100
kHz
fSCL
SCL clock frequency
tBUF
Bus free time between a STOP and START condition
4.7
µs
tLOW
Low period of the SCL clock
4.7
µs
tHI
High period of the SCL clock
4
µs
tRS-SU
Setup time for (repeated) START condition
4.7
µs
tS-HD
Hold time for (repeated) START condition
4
µs
tD-SU
Data setup time
250
ns
tD-HD
Data hold time
0
900
ns
tSCL-R
Rise time of SCL signal
20 + 0.1CB
1000
ns
tSCL-R1
Rise time of SCL signal after a repeated START condition and after an acknowledge bit
20 + 0.1CB
1000
ns
tSCL-F
Fall time of SCL signal
20 + 0.1CB
1000
ns
tSDA-R
Rise time of SDA signal
20 + 0.1CB
1000
ns
tSDA-F
Fall time of SDA signal
20 + 0.1CB
1000
tP-SU
Setup time for STOP condition
4
ns
µs
7.10 I2C Bus Timing – Fast
See Figure 21.
MIN
MAX
UNIT
400
kHz
fSCL
SCL clock frequency
tBUF
Bus free time between a STOP and START condition
1.3
µs
tLOW
Low period of the SCL clock
1.3
µs
tHI
High period of the SCL clock
600
ns
tRS-SU
Setup time for (repeated)START condition
600
ns
tRS-HD
Hold time for (repeated)START condition
600
ns
tD-SU
Data setup time
100
tD-HD
Data hold time
tSCL-R
tSCL-R1
ns
0
900
ns
Rise time of SCL signal
20 + 0.1CB
300
ns
Rise time of SCL signal after a repeated START condition and after an acknowledge bit
20 + 0.1CB
300
ns
tSCL-F
Fall time of SCL signal
20 + 0.1CB
300
ns
tSDA-R
Rise time of SDA signal
20 + 0.1CB
300
ns
tSDA-F
Fall time of SDA signal
20 + 0.1CB
300
ns
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I2C Bus Timing – Fast (continued)
See Figure 21.
MIN
tP-SU
Setup time for STOP condition
tSP
Pulse width of spike suppressed
MAX
600
UNIT
ns
50
ns
7.11 SPK_MUTE Timing
See Figure 22.
MIN
MAX
UNIT
tr
Rise time
20
ns
tf
Fall time
20
ns
tMCLKH
"H"
0.7 × VDVDD
0.3 × VDVDD
"L"
tMCLKL
tMCLK
Figure 18. Timing Requirements for MCLK Input
LRCK/FS
(Input)
0.5 × DVDD
tSCLKH
tSCLKL
tLS
SCLK
(Input)
0.5 × DVDD
tSCLK
tSL
DATA
(Input)
0.5 × DVDD
tSU
tDH
tDFS
DATA
(Output)
0.5 × DVDD
Figure 19. MCLK Timing Diagram in Slave Mode
16
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SLAS988B – JUNE 2014 – REVISED AUGUST 2015
BCL
ttBCL
tSCLK.
SCLK
(Input)
0.5 × DVDD
tSCLK
tLRD
LRCK/FS
(Input)
0.5 × DVDD
tDFS
DATA
(Input)
0.5 × DVDD
tSU
tDH
DATA
(Output)
0.5 × DVDD
Figure 20. MCLK Timing Diagram in Master Mode
Repeated
START
START
tD-SU
SDA
STOP
tD-HD
tSDA-F
tSDA-R
tP-SU
tBUF.
tSCL-R.
tRS-HD
tSP
tLOW.
SCL
tHI.
tRS-SU
tS-HD.
tSCL-F.
Figure 21. I2C Communication Port Timing Diagram
0.9 × DVDD
0.1 × DVDD
SPK_MUTE
tr
< 20 ns
tff