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TAS5805M
SLASEH5C – MAY 2018 – REVISED DECEMBER 2018
TAS5805M 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio
Amplifier with Enhanced Processing and Low Power Dissipation
1 Features
2 Applications
•
•
•
PART NUMBER
PACKAGE
TAS5805M
BODY SIZE (NOM)
TSSOP (28) PWP
9.7 mm × 4.4 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
BST_B-
OUT_BLRCLK
SDIN
SCLK (BCLK)
BST_A-
BST_B+
Speaker
R Channel
OUT_B+
Speaker
L Channel
OUT_A-
•
Device Information(1)
SCL
•
Featuring TI's proprietary Hybrid Modulation scheme,
the TAS5805M consumes very-low quiescent current
(16.5 mA at 13.5 V PVDD), extending battery life in
portable audio applications. With advanced EMI
suppression technology, designers can leverage
inexpensive ferrite bead filters to reduce board space
and system cost.
SDOUT
•
The TAS5805M is a high-efficiency, stereo, closedloop Class-D amplifier offering a cost-effective digitalinput solution with low power dissipation and sound
enrichment. The device’s integrated audio processor
and 96 kHz architecture support advanced audio
process flow, including SRC, 15 BQs per channel,
volume control, audio mixing, 3-band 4th order DRC,
full-band AGL, THD manager and level meter.
SDA
•
3 Description
PDN
•
•
•
BST_A+
•
•
LCD TV, OLED TV
Wireless Speaker, Smart Speaker with Voice
Assistant
Soundbar, Wired Speaker , Bookshelf Stereo
System
Desktop PC, Notebook PC
AV Receiver, Smart Home and IoT Appliance
OUT_A+
•
Supports Multiple Output Configurations
– 2 × 23 W in 2.0 Mode (8-Ω, 21 V, THD+N=1%)
– 45 W in Mono Mode (4-Ω, 21 V, THD+N=1%)
Excellent Audio Performance
– THD+N ≤ 0.03% at 1 W, 1 kHz, PVDD = 12 V
– SNR ≥ 107 dB (A-weighted), Noise Level < 40
µVRMS
Low Quiescent Current with Hybrid Modulation
– 16.5 mA at PVDD = 13.5 V , 22 µH + 0.68 µF
Filter
Flexible Power Supply Configurations
– PVDD: 4.5 V to 26.4 V
– DVDD and I/O: 1.8 V or 3.3 V
Flexible Audio I/O
– I2S, LJ, RJ, TDM, 3-Wire Digital Audio
Interface (No MCLK Required)
– Supports 32, 44.1, 48, 88.2, 96 kHz Sample
Rates
– SDOUT for Audio Monitoring, Sub-Channel or
Echo Cancellation
Enhanced Audio Processing
– Multi-Band Advanced DRC and AGL
– 2×15 BQs, Thermal Foldback, DC Blocking
– Input Mixer, Output Crossbar, Level Meter
– 5 BQs + 1 Band DRC +THD Manager for the
Subwoofer Channel
– Sound Field Spatializer option
Integrated Self-Protection
– Adjacent Pin to Pin Short Without Damage
– Over-Current Error (OCE)
– Over-Temperature Warning (OTW)
– Over-Temperature Error (OTE)
– Under/Over-Voltage Lock-out (UVLO/OVLO)
Easy System Integration
– I2C Software Control
– Reduced Solution Size
– Fewer Passives Required Compared to
Open-Loop Devices
– Inductor-less Operation (Ferrite Bead) for
most cases where PVDD ≤ 14V
ADR/FAULT
1
DVDD
System
Processor
Digital
Audio
Source
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5805M
SLASEH5C – MAY 2018 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements ............................................... 9
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 25
Detailed Description ............................................ 27
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
27
27
28
34
9.5 Programming and Control ....................................... 39
9.6 Register Maps ......................................................... 45
10 Application and Implementation........................ 76
10.1 Application Information.......................................... 76
10.2 Typical Applications ............................................. 78
11 Power Supply Recommendations ..................... 86
11.1 DVDD Supply ........................................................ 86
11.2 PVDD Supply ........................................................ 86
12 Layout................................................................... 88
12.1 Layout Guidelines ................................................. 88
12.2 Layout Example .................................................... 90
13 Device and Documentation Support ................. 91
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
91
91
92
92
92
92
14 Mechanical, Packaging, and Orderable
Information ........................................................... 92
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2018) to Revision C
Page
•
Added Figure 97 .................................................................................................................................................................. 43
•
Added Figure 98 .................................................................................................................................................................. 43
Changes from Revision A (July 2018) to Revision B
Page
•
Changed From: (5A OCP), not
recommended
24
4.7
0.68
768
3.25A
24
10
0.68
384
3A
24
10
0.68
768
1.55A
12
4.7
0.68
384
3.32A
12
10
0.68
384
1.55A
2. During music playing, some audio burst signal (high frequency) with very hard PVDD clipping will cause
PWM duty cycle increase dramatically. This is the worst case and it rarely happens.
I peak _ clipping | PVDD u (1 T ) /( Fsw u L)
(2)
3. Peak current due to Max output power. Ignore the ripple current flow through capacitor here.
I peak _ output _ power | 2 u Max _ Output _ Power / Rspea ker_ Load
(3)
Same PVDD and switching frequency, larger inductance means smaller idle current for lower power dissipation.
It's suggested that inductor's saturation current Isat, is larger than the amplifier's peak current during power-up
and play audio.
76
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SLASEH5C – MAY 2018 – REVISED DECEMBER 2018
I SAT t max(I peak _ power _ up , I peak _ clipping, I peak _ output_ power )
(4)
In addition, the effective inductance at the peak current is required to be at least 80% of the inductance value in
Table 51, to meet datasheet specifications.
The minimum inductance is given in Table 51
Table 51. LC filter recommendation
PVDD (V)
Switching Frequency (kHz)
Modulation Scheme
384
BD
384
1SPW/Hybrid
≤12
>12
≤12
>12
Recommended Minimum
Inductance (uH) for LC filter design
4.7uH + 0.68uF
10uH + 0.68uF
10uH + 0.68uF
15uH + 0.68uF
For higher switching frequency (Fsw), select inductors with minimum inductance to be 384kHz/Fsw×L.
10.1.3 Power Supply Decoupling
To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise
transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency
components that extend into the hundreds of megahertz. The power supply input must be decoupled with some
good quality, low ESL, Low ESR capacitors larger than 22 µF. These capacitors bypasses low frequency noise to
the ground plane. For high frequency decoupling, place 1-µF or 0.1-µF capacitors as close as possible to the
PVDD pins of the device.
10.1.4 Output EMI Filtering
The TAS5805M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a
simple ferrite bead or a ferrite bead plus a capacitor can replace the tradition large inductor and capacitor that
are commonly used. In other high-power applications, large toroid inductors are required for maximum power and
film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter Design
(SLOA119) for a detailed description on the proper component selection and design of an L-C filter based upon
the desired load and response.
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TAS5805M
SLASEH5C – MAY 2018 – REVISED DECEMBER 2018
www.ti.com
10.2 Typical Applications
10.2.1 2.0 (Stereo BTL) System
In the 2.0 system, two channels are presented to the amplifier via the digital input signal. These two channels are
amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated based
upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered 2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
Figure 142 shows the 2.0 (Stereo BTL) system application.
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Figure 142. 2.0 (Stereo BTL) System Application Schematic with Ferrite Bead as the output filter
78
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SLASEH5C – MAY 2018 – REVISED DECEMBER 2018
Typical Applications (continued)
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Figure 143. 2.0 (Stereo BTL) System Application Schematic with Inductor as the output filter
10.2.1.1 Design Requirements
• Power supplies:
– 3.3-V or 1.8-V supply
– 4.5-V to 24-V supply
• Communication: host processor serving as I2C compliant master
• External memory (Such as EEPROM and FLASH) used for coefficients
The requirement for the supporting components for the TAS5805M device in a Stereo 2.0 (BTL) system is
provide in Table 52 and Table 53
Table 52. Supporting Component Requirements for Stereo 2.0 (BTL) system (With Ferrite bead as
output filter)
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C1,C2,C5,C6
22uF
0805
CAP, CERM, 22 µF, 35 V, +/- 20%, JB, 0805
C3,C4
0.1uF
0402
CAP, CERM, 0.1 µF, 50 V, +/- 10%, X7R, 0402
C7
4.7uF
0603
CAP, CERM, 4.7 µF, 10 V, +/- 10%, X5R, 0603
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Typical Applications (continued)
Table 52. Supporting Component Requirements for Stereo 2.0 (BTL) system (With Ferrite bead as output
filter) (continued)
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C8
0.1uF
0603
CAP, CERM, 0.1 µF, 16 V, +/- 10%, X7R, 0603
C9,C10
1uF
0603
CAP, CERM, 1 µF, 16 V, +/- 10%, X5R, 0603
R1
4.70k
0402
RES, 4.70 k, 1%, 0.0625 W, 0402
R2
10.0k
0404
RES, 10.0 k, 1%, 0.063 W, 0402
C11,C12,C13,C14
0.22uF
0603
CAP, CERM, 0.22 µF, 50 V, +/- 10%, X7R, 0603
C15,C16,C17,C18,C19,
C20,C21,C22,C23
2200pF
0603
CAP, CERM, 2200 pF, 100 V,+/- 10%, X7R, 0603
R3,R4,R5,R6
68 ohm
0603
ES, 68, 5%, 0.1 W, 0603
L1,L2,L3,L4
300 ohm
0806
Ferrite Bead, 300 ohm @ 100 MHz, 3.1 A, 0806
L5
100 ohm
0806
Ferrite Bead, 100 ohm @ 100 MHz, 4 A, 0806
With Low EMI technology, TAS5805M keeps enough EMI margin for most of application cases where PVDD <
14V with ferrite bead (Low BOM cost). With Ferrite Bead and capacitor as the output filter, Figure 142 and
Table 52 includes a good configuration (Proper value of Ferrite bead, Capacitor, Resistor) to achieve enough
EMI margin for the typical case which PVDD = 12V, Speaker Load = 8Ω/6Ω, each speaker wire with 1m length,
Output Power = 1W/4W/8W for each channel.
• Select Ferrite bead (L1~L5). The trade-off is impedance and rated current. If the rated current meet the
system's requirement, larger impedance means larger EMI margin for the EMI, especially for the frequency
band 5MHz~50MHz. The typical ferrite bead recommend for TAS5805M is NFZ2MSM series (Murata) and
UPZ2012E series (Sunlord). 300 ohm @ 100MHz ferrite bead is a typical value which can pass EMI for most
of application cases.
• Select capacitor (C15~C23). The trade-off is capacitor value and idle current. Larger capacitor means larger
idle current, increase the capacitor value from 1nF to 2.2nF makes much help for frequency band
5MHz~100MHz.
• Using Ferrite bead as the output filter, recommend designer to use Fsw=384kHz with Spread spectrum
enable, BD Modulation, refer to Spread Spectrum
• With Ferrite bead as the output power. In order to pass EMI (AC Conducted Emission) standard, an AC to DC
adapter with EMI filter in it is needed. For most of applications (TV/Voice Control Speaker/Wireless
speaker/Soundbar) which need a 110V~220V power supply usually has a EMI filter in the AC to DC adapter.
Some cases use DC power supply and also need to test the DC Conducted Emission , this applications
(Automotive/Industry) need a simple EMI filter on PVDD for TAS5805M. Refer to application note: AN-2162
Simple Success With Conducted EMI From DC to DC Converters.
Table 53. Supporting Component Requirements for Stereo 2.0 (BTL) system (With Inductor as output
filter)
80
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C1,C6
390uF
10mmx10mm
CAP, AL, 390 µF, 35 V, +/- 20%, 0.08 ohm, SMD
C2,C5
22uF
0603
CAP, CERM, 22 µF, 35 V, +/- 20%, JB, 0805
C3,C4
0.1uF
0402
CAP, CERM, 0.1 µF, 50 V, +/- 10%, X7R, 0402
C7
4.7uF
0603
CAP, CERM, 4.7 µF, 10 V, +/- 10%, X5R, 0603
C8
0.1uF
0603
CAP, CERM, 0.1 µF, 16 V, +/- 10%, X7R, 0603
C9,C10
1uF
0603
CAP, CERM, 1 µF, 16 V, +/- 10%, X5R, 0603
R1
4.70k
0402
RES, 4.70 k, 1%, 0.0625 W, 0402
R2
10.0k
0404
RES, 10.0 k, 1%, 0.063 W, 0402
C11,C12,C13,C14
0.22uF
0603
CAP, CERM, 0.22 µF, 50 V, +/- 10%, X7R, 0603
C15,C16,C17,C18
0.68uF
0805
CAP, CERM, 0.68 µF, 50 V, +/- 10%, X7R, 0805
L1,L2,L3,L4
10uH
Inductor, Shielded, 10 µH, 4.4 A, 0.023 ohm, SMD
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With Inductor as the output filter, designers can achieve ultra low idle current (with Hybrid Modulation or 1SPW
Modulation) and keep large EMI margin. As the switching frequency of TAS5805M can be adjustable from
384kHz to 768kHz. Higher switching frequency means smaller Inductor value needed.
• With 768kHz switching frequency. Designers can select 10uH + 0.68uF or 4.7uH +0.68uF as the output filter,
this will help customer to save the Inductor size with the same rated current during the inductor selection.
With 4.7uH + 0.68uF, make sure PVDD ≤ 12V to avoid the large ripple current to trigger the OC threshold
(5A).
• With 384kHZ switching frequency. Designers can select 22uH + 0.68uF or 15uH + 0.68uF or 10uH + 0.68uF
as the output filter, this will help customer to save power dissipation for some battery power supply
application. With 10uH + 0.68uF, make sure PVDD ≤ 12V to avoid the large ripple current to trigger the OC
threshold (5A).
10.2.1.2 Detailed Design Procedures
The design procedure can be used for Stereo 2.0, Mono, 2.1 system.
10.2.1.2.1 Step 1: Hardware Integration
•
•
Use the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Follow the recommended component placement, board layout, and routing given in the example layout
above, integrate the device and its supporting components into the system PCB file.
– The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the
high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they
are given precedent as design trade-offs are made is recommended.
– For questions and support, go to the E2E forums (E2E.ti.com). If deviating from the recommended layout
is necessary, go to the E2E forum to request a layout review.
10.2.1.2.2 Step 2: Speaker Tuning
Use the TAS5805MEVM evaluation module and the PPC3 app to configure the desired device settings.
10.2.1.2.3 Step 3: Software Integration
•
•
•
Use the End System Integration feature of the PPC3 app to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
10.2.1.3 Application Curves
10.2.1.3.1 Audio Performance
10
10
5 PV CC =12V
TA=25qC
2 R L=6:
1
5 PV CC =18V
TA=25qC
2 R L=8:
1
0.5
THD+N (%)
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.002
0.001
0.01
0.1
0.05
0.02
0.01
0.005
0.2
0.01
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.002
0.1
1
Output Power (W)
0.001
0.01
10
D007
D139
Figure 144. THD+N vs Frequency (Ferrite bead as Output
Filter, BD Modulation, BTL Mode)
f= 20Hz
f= 1kHz
f= 10KHz
0.1
1
Output Power (W)
10
20
D004
D118
D010
D007
Figure 145. THD+N vs Frequency (Inductor as Output
Filter, Hybrid Modulation, BTL Mode)
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10.2.1.3.2 EN55022 Conducted Emissions Results with Ferrite Bead as output filter
With (Ferrite Bead as the output filter), 220V to 12V adapter from a major TV customer, 8-Ω speaker, Spread
Spectrum Enabled, Stereo Output Power = 8W/CH, 1 meter speaker cable for each channel.
Figure 146. Conducted Emission with Ferrite Bead Filter Line
Figure 147. Conducted Emission with Ferrite Bead Filter Neutral
10.2.1.3.3 EN55022 Radiated Emissions Results with Ferrite Bead as output filter
With (Ferrite Bead as the output filter), 220V to 12V adapter from a major TV customer, 8-Ω speaker, Spread
Spectrum Enabled, Stereo Output Power = 8W/CH, 1 meter speaker cable for each channel.
Figure 148. Radiated Emission with Ferrite Bead Filter Horizontal
Figure 149. Radiated Emission with Ferrite Bead Filter Vertical
With Inductor as the output filter, the EMI margin reserve ≥ 15dB Margin for both Conducted Emission and
Radiated Emission. More data are included in the application note -TAS5805M Design Considerations for EMC.
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10.2.2 MONO (PBTL) Systems
In MONO mode, TAS5805M can be used as PBTL mode to drive sub-woofer with more output power.
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10.2.2.1 Design Requirements
• Power supplies:
– 3.3-V or 1.8-V supply
– 4.5-V to 24-V supply
• Communication: host processor serving as I2C compliant master
• External memory (Such as EEPROM and FLASH) used for coefficients
The requirement for the supporting components for the TAS5805M device in a MONO (PBTL) system is provide
in Table 54
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Table 54. Supporting Component Requirements for MONO (PBTL) system (With Inductor as output
filter)
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C24,C25
390uF
10mmx10mm
CAP, AL, 390 µF, 35 V, +/- 20%, 0.08 ohm, SMD
C27,C30
22uF
0603
CAP, CERM, 22 µF, 35 V, +/- 20%, JB, 0805
C28,C29
0.1uF
0402
CAP, CERM, 0.1 µF, 50 V, +/- 10%, X7R, 0402
C33
4.7uF
0603
CAP, CERM, 4.7 µF, 10 V, +/- 10%, X5R, 0603
C34
0.1uF
0603
CAP, CERM, 0.1 µF, 16 V, +/- 10%, X7R, 0603
C37,C39
1uF
0603
CAP, CERM, 1 µF, 16 V, +/- 10%, X5R, 0603
R7
4.70k
0402
RES, 4.70 k, 1%, 0.0625 W, 0402
R8
10.0k
0404
RES, 10.0 k, 1%, 0.063 W, 0402
C35,C38,C40,C41
0.22uF
0603
CAP, CERM, 0.22 µF, 50 V, +/- 10%, X7R, 0603
C32,C36
0.68uF
0805
CAP, CERM, 0.68 µF, 50 V, +/- 10%, X7R, 0805
L1,L2
10uH
Inductor, Shielded, 10 µH, 7A, 0.023 ohm, SMD
10.2.2.2 Detailed Design Procedure
For information about the Detailed Design Procedure, see the Detailed Design Procedures section.
10.2.2.3 Application Curves
10
100
5 PV CC =18V
TA=25qC
2 R L=4:
1
90
70
0.5
THD+N (%)
Power Efficiency (%)
80
60
50
40
30
20 TA=25qC
10 R L=4:
PBTL Mode
0
0
10
PV CC
PV CC
PV CC
PV CC
PV CC
20
30
40
Output Power (W)
50
0.1
0.05
0.02
= 5V
= 7.4 V
= 12 V
= 18 V
= 24 V
0.01
0.005
0.002
0.001
0.01
60
D024
D156
Figure 151. Efficiency vs Output Power (Inductor as
Output Filter, Hybrid modulation, PBTL mode)
84
0.2
f= 20Hz
f= 10kHz
f= 1KHz
0.1
1
Output Power (W)
10
20
D007
D152
Figure 152. THD+N vs Output Power (Inductor as Output
Filter, Hybrid Modulation, PBTL mode)
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10.2.3 Advanced 2.1 System (Two TAS5805M Devices)
In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was
done in the high-frequency channels. To accomplish this, two TAS5805M devices are used - one for the high
frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can
be sent from the TAS5805M device through the SDOUT pin. Alternatively, the subwoofer amplifier can accept
the same digital input as the stereo, which might come from a central systems processor. Figure 153 shows the
2.1 (Stereo BTL with Two TAS5805M devices) system application.
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Figure 153. 2.1 (2.1 CH with Two TAS5805M Devices) Application Schematic
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11 Power Supply Recommendations
The TAS5805M device requires two power supplies for proper operation. A high-voltage supply calls PVDD is
required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one lowvoltage power supply which is calls DVDD is required to power the various low-power portions of the device. The
allowable voltage range for both PVDD and DVDD supply are listed in the Recommended Operating Conditions
table. Once the device has been initialized, PVDD must keep within the normal operation voltage. Once PVDD
lower than 3.5V, all registers need re-initialize again.
DVDD
Internal Digital
Circuitry
Digital IO
VR_DIG
1.8V/3.3VÅ
1.5V
LDO
External Filtering/Decoupling
DVDD
PVDD
4.5V~26.4V
Gate Drive/Internal
Analog Circuitry
Output Stage
Power Supply
AVDD
5V
LDO
External Filtering/Decoupling
PVDD
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Figure 154. Power Supply Function Block Diagram
11.1 DVDD Supply
The DVDD supply that is required from the system is used to power several portions of the device. As shown in
Figure 154, it provides power to the DVDD pin. Proper connection, routing and decoupling techniques are
highlighted in the Application and Implementation section and the Layout Example section and must be followed
as closely as possible for proper operation and performance.
Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.
To simplify the power supply requirements for the system, the TAS5805M device includes an integrated low
dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD
supply and its output is presented on the DVDD_REG pin, providing a connection point for an external bypass
capacitor. It is important to note that the linear regulator integrated in the device has only been designed to
support the current requirements of the internal circuitry, and should not be used to power any additional external
circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and
operation of the device.
11.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the TAS5805MMEVM and must be followed as closely as possible for proper operation and
performance. Due to the high-voltage switching of the output stage, it is particularly important to properly
decouple the output power stages in the manner described in the TAS5805M device Application and
Implementation. Lack of proper decoupling, like that shown in the Application and Implementation, results in
voltage spikes which can damage the device.
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PVDD Supply (continued)
A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker
amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD pin is
provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note
that the linear regulator integrated in the device has only been designed to support the current requirements of
the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this
pin could cause the voltage to sag, negatively affecting the performance and operation of the device.
Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD.
AVDD pin is provided for the attachment of decoupling capacitor for the TAS5805M internal circuitry. It is
important to note that the linear regulator integrated in the device has only been designed to support the current
requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional
loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the
device.
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12 Layout
12.1 Layout Guidelines
12.1.1 General Guidelines for Audio Amplifiers
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout.
Ideally, the guidance provided in the applications section with regard to device and component selection can be
followed by precise adherence to the layout guidance shown in the Layout Example section. These examples
represent exemplary baseline balance of the engineering trade-offs involved with lying out the device. These
designs can be modified slightly as needed to meet the needs of a given application. In some applications, for
instance, solution size can be compromised to improve thermal performance through the use of additional
contiguous copper neat the device. Conversely, EMI performance can be prioritized over thermal performance by
routing on internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it
is recommended to start from the guidance shown in the Layout Example section and work with TI field
application engineers or through the E2E community to modify it based upon the application specific goals.
12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This
applies to DVDD, AVDD, GVDD and PVDD. However, the capacitors on the PVDD net for the TAS5805M device
deserve special attention.
The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as
possible. Not only dose placing these device far away from the pins increase the electromagnetic interference in
the system, but doing so can also negatively affect the reliability of the device. Placement of these components
too far from the TAS5805M device can cause ringing on the output pins that can cause the voltage on the output
pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the
deice . For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD
pins than what is shown in the example layouts in the Layout Example section.
12.1.3 Optimizing Thermal Performance
Follow the layout example shown in the Figure 155 to achieve the best balance of solution size, thermal, audio,
and electromagnetic performance. In some cases, deviation from this guidance can be required due to design
constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can
get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device
naturally travels away from the device and into the lower temperature structures around the device.
12.1.3.1 Device, Copper, and Component Layout
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips should be followed to achieve that goal:
• Avoid placing other heat producing components or structures near the amplifier (including above or below in
the end equipment).
• If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5805M device
and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top
and bottom layer.
• Place the TAS5805M device away from the edge of the PCB when possible to ensure that the heat can travel
away from the device on all four sides.
• Avoid cutting off the flow of heat from the TAS5805M device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
• Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient it so that the narrow end of the passive component is facing the TAS5805M
device.
• Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane
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Layout Guidelines (continued)
from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.
12.1.3.2 Stencil Pattern
The recommended drawings for the TAS5805M device PCB foot print and associated stencil pattern are shown
at the end of this document in the package addendum. Additionally, baseline recommendations for the via
arrangement under and around the device are given as a starting point for the PCB design. This guidance is
provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all
other performance criteria. In elevated ambient temperature or under high-power dissipation use-cases, this
guidance may be too conservative and advanced PCB design techniques may be used to improve thermal
performance of the system.
NOTE
The customer must verify that deviation from the guidance shown in the package
addendum, including the deviation explained in this section, meets the customer’s quality,
reliability, and manufacturability goals.
12.1.3.2.1 PCB footprint and Via Arrangement
The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the
shape and position of the copper patterns to which the TAS5805M device will be soldered. This footprint can be
followed directly from the guidance in the package addendum at the end of this data sheet. It is important to
make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the TAS5805M
device, be made no smaller than what is specified in the package addendum. This ensures that the TAS5805M
device has the largest interface possible to move heat from the device to the board.
The via pattern shown in the package addendum provides an improved interface to carry the heat from the
device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)
present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away
from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the
Layout Example section, this interface can benefit from improved thermal performance.
NOTE
Vias can obstruct heat flow if they are not constructed properly.
More notes on the construction and placement of vias are as follows:
• Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
• Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the
additional cost of filled vias.
• The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding
planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases,
minimum spacing should be determined by the voltages present on the planes surrounding the via and
minimized wherever possible.
• Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding
area. This arrangement is shown in the Layout Example section.
• Ensure that vias do not cut off power current flow from the power supply through the planes on internal
layers. If needed, remove some vias that are farthest from the TAS5805M device to open up the current path
to and from the device.
12.1.3.2.2 Solder Stencil
During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste
on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity
and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most
cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the
thermal pad on the PCB is large and depositing a large, single deposition of solder paste would lead to
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Layout Guidelines (continued)
manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste
to outgas during the assembly process and reduce the risk of solder bridging under the device. This structure is
called an aperture array, and is shown in the Layout Example section. It is important that the total area of the
aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the
thermal pad itself.
12.2 Layout Example
Top Layer 3D view
Top Layer Layout
Bot Layer Layout
Figure 155. 2.0 (Stereo BTL with Ferrite Bead as Output Filter) Layout View
Top Layer 3D view
Top Layer Layout
Bot Layer 3D view
Bot Layer Layout
Figure 156. 2.0 (Stereo BTL with Inductor as Output Filter) Layout View
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Device Nomenclature
The glossary listed in the Glossary section is a general glossary with commonly used acronyms and words which
are defined in accordance with a broad TI initiative to comply with industry standards such as JEDEC, IPC, IEEE,
and others. The glossary provided in this section defines words, phrases, and acronyms that are unique to this
product and documentation, collateral, or support tools and software used with this product. For any additional
questions regarding definitions and terminology, please see the e2e Audio Amplfier Forum.
Bridge tied load (BTL) is an output configuration in which one terminal of the speaker is connected to one halfbridge and the other terminal is connected to another half-bridge.
DUT refers to a device under test to differentiate one device from another.
Closed-loop architecture describes a topology in which the amplifier monitors the output terminals, comparing
the output signal to the input signal and attempts to correct for non-linearities in the output.
Dynamic controls are those which are changed during normal use by either the system or the end-user.
GPIO is a general purpose input/output pin. It is a highly configurable, bi-directional digital pin which can perform
many functions as required by the system.
Host processor (also known as System Processor, Scalar, Host, or System Controller) refers to device
which serves as a central system controller, providing control information to devices connected to it as well as
gathering audio source data from devices upstream from it and distributing it to other devices. This device often
configures the controls of the audio processing devices (like the TAS5805M) in the audio path in order to
optimize the audio output of a loudspeaker based on frequency response, time alignment, target sound pressure
level, safe operating area of the system, and user preference.
Maximum continuous output power refers to the maximum output power that the amplifier can continuously
deliver without shutting down when operated in a 25°C ambient temperature. Testing is performed for the period
of time required that their temperatures reach thermal equilibrium and are no longer increasing
Parallel bridge tied load (PBTL) is an output configuration in which one terminal of the speaker is connected to
two half-bridges which have been placed in parallel and the other terminal is connected to another pair of half
bridges placed in parallel
rDS(on) is a measure of the on-resistance of the MOSFETs used in the output stage of the amplifier.
Static controls/Static configurations are controls which do not change while the system is in normal use.
Vias are copper-plated through-hole in a PCB.
13.1.2 Development Support
For TAS5805M Evaluation Module, TAS5805MEVM
Request PurePathTM Console Graphical
Development,PUREPATHCONSOLE
Development
Suite
for
Audio
System
Design
and
Request TAS5805M PPC3 app access by click 'Request Now' in TAS5805M product folder,TAS5805M
Or contact TI field support team to get the PPC3 platform access and TAS5805M app access.
Application notes: Minimize Idle Current in Portable Audio With TAS5805M Hybrid Mode
Application notes: TAS5805M Process Flows
Class-D LC Filter Design,Class-D LC Filter Design
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
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13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TAS5805MPWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
NIPDAU
Level-3-260C-168 HR
-25 to 85
5805
TAS5805MPWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-3-260C-168 HR
-25 to 85
5805
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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