TB5R2LD

TB5R1, TB5R2 www.ti.com SLLS588B – NOVEMBER 2003 – REVISED MAY 2004 QUAD DIFFERENTIAL PECL RECEIVERS FEATURES • • • • • • • • • • • • • DESCRIPTION Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B Pin Equivalent to General Trade 26LS32 High Input Impedance Approximately 8 kΩ 4-ns Maximum Propagation Delay TB5R1 Provides 50-mV Hysteresis TB5R2 With -125-mV Threshold Offset for Preferred State Output -1.1-V to 7.1-V Common Mode Range Single 5-V ±10% Supply Slew Rate Limited (1 ns min 80% to 20%) TB5R2 Output Defaults to Logic 1 When Inputs Left Open or Shorted to VCC or GND ESD Protection HBM > 3 kV, CDM > 2 kV Operating Temperature Range: -40°C to 85°C Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package APPLICATIONS • Digital Data or Clock Transmission Over Balanced Lines These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels. The TB5R1 is a pin- and function-compatible replacement for the Agere systems BRF1A and BRF2A; it includes 3-kV HBM and 2-kV CDM ESD protection. The TB5R2 is a pin- and function-compatible replacement for the Agere systems BRS2A and BRS2B and incorporates a 125-mV receiver input offset, preferred state output, 3-kV HBM and 2-kV CDM ESD protection. The TB5R2 preferred state feature places the high state when the inputs are open, shorted to ground, or shorted to the power supply. The power-down loading characteristics of the receiver input circuit are approximately 8 kΩ relative to the power supplies; hence they do not load the transmission line when the circuit is powered down. The packaging for these differential line receivers include a 16-pin gull wing SOIC (DW) and SOIC (D). The enable inputs of this device include internal pullup resistors of approximately 40 kΩ that are connected to VCC to ensure a logical high level input if the inputs are open circuited. FUNCTIONAL BLOCK DIAGRAM PIN ASSIGNMENTS AI D PACKAGE (TOP VIEW) AO AI BI AI AI AO E1 BO BI BI GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC DI DI DO E2 CO CI CI BO BI C1 CO C1 D1 DO D1 E1 E2 Enable Truth Table E1 E2 CONDITION 0 0 Active 1 0 Active 0 1 Disabled 1 1 Active Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2004, Texas Instruments Incorporated TB5R1, TB5R2 www.ti.com SLLS588B – NOVEMBER 2003 – REVISED MAY 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER PART MARKING Package LEAD FINISH STATUS TB5R1DW TB5R1 Gull-Wing SOIC NiPdAu Production TB5R1D TB5R1 SOIC NiPdAu Production TB5R2DW TB5R2 Gull-Wing SOIC NiPdAu Production TB5R2D TB5R2 SOIC NiPdAu Production TB5R1LDW TB5R1 Gull-Wing SOIC SnPb Production TB5R1LD TB5R1 SOIC SnPb Production TB5R2LDW TB5R2 Gull-Wing SOIC SnPb Production TB5R2LD TB5R2 SOIC SnPb Production POWER RATINGTA≤ 25°C THERMAL RESISTANCE,JUNCTION-TOAMBIENTWITH NO AIR FLOW DERATINGFACT OR (1)TA≥ 25°C POWER RATINGTA = 85°C Low-K (2) 763 mW 131.1°C/W 7.6 mW/°C 305 mW High-K (3) 1190 mW 84.1°C/W 11.9 mW/°C 475 mW Low-K (2) 831 mW 120.3°C/W 8.3 mW/°C 332 mW High-K (3) 1240 mW 80.8°C/W 12.4 mW/°C 494 mW POWER DISSIPATION RATINGS PACKAGE CIRCUIT BOARD MODEL D DW (1) (2) (3) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow. In accordance with the low-K thermal metric definitions of EIA/JESD51-3. In accordance with the high-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICs PARAMETER PACKAGE VALUE UNIT D 47.5 °C/W θJB Junction-to-Board Thermal Resistance DW 53.7 °C/W θJC Junction-to-Case Thermal Resistance D 44.2 °C/W DW 47.1 °C/W ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT Supply voltage, VCC 0 V to 6 V Magnitude of differential bus (input) voltage, |VAI - V|, |VBI - V|, |VCI - V|, |VDI - V| ESD Human Body Model (2) All pins Charged-Device Model (3) All pins Continuous power dissipation Storage temperature, Tstg (1) (2) (3) 2 8.4 V ±3 kV ±2 kV See Dissipation Rating Table -65°C to 150°C Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. TB5R1, TB5R2 www.ti.com SLLS588B – NOVEMBER 2003 – REVISED MAY 2004 RECOMMENDED OPERATING CONDITIONS Supply voltage, VCC MIN Nom 4.5 5 MAX UNIT 5.5 V -1.2 (1) 7.2 V Magnitude of differential input voltage, |VAI - V|, |VBI - V|, |VCI - V|, |VDI - V| 0.1 6 V Operating free-air temperature, TA -40 85 °C Bus pin input voltage, VAI, V, VBI, V, VCI, V, VDI, V (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless otherwise noted. DEVICE ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER Supply current (1) ICC (1) TEST CONDITIONS MIN TYP MAX UNIT Outputs disabled 40 mA Outputs enabled 38 mA Current is dc power draw as measured through GND pin and does not include power delivered to load. RECEIVER ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted parameter test conditions VOL Output low voltage VCC = 4.5 V, IOL = 8 mA VOH Output high voltage VCC = 4.5 V, IOH = -400 µA VIL Low level enable input voltage (1) VCC = 5.5 V VIH High level enable input voltage (1) VCC = 5.5 V VIK Enable input clamp voltage VCC = 4.5 V, VTH+ Positive-going differential input threshold voltage (1), (Vxl - V) x = A, B, C, or D VTH- Negative-going differential input threshold voltage (1), (Vxl - V) x = A, B, C, or D VHYST Differential input threshold voltage hysteresis, (VTH+ - VTH_) TB5R1 IOZL IOZH Output off-state current, (High-Z) current (4) IOS Output short circuit IIL Enable input low current IIH Enable input high current 0.4 2.4 VCC = 5.5 V unit V V 0.8 2 V V II = -5 mA -1 (2) V TB5R1 100 mV TB5R2 (3) -50 mV TB5R1 -100 (2) mV TB5R2 (3) -200 (2) mV 50 mV VO = 0.4 V -20 (2) µA VO = 2.4 V 20 µA -100 (2) mA VIN = 0.4 V -400 (2) µA VIN = 2.7 V 20 µA VCC = 5.5 V VCC = 5.5 V, max VIN = 5.5 V 100 µA IIL Differential input low current VCC = 5.5V, VIN = -1.2 V -2 (2) mA IIH Differential input high current VCC= 5.5V, VIN = 7.2 V 1 mA RO Output resistance (1) (2) (3) (4) Enable input reverse current VCC = 5.5 V min typ 20 Ω The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment. This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data sheet. Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recomended that all unused positive inputs be tied to the positive power supply. No external series resistor is required.) Test must be performed one lead at a time to prevent damage to the device. 3 TB5R1, TB5R2 www.ti.com SLLS588B – NOVEMBER 2003 – REVISED MAY 2004 SWITCHING CHARACTERISTICS over operating free-air temperature range unless otherwise noted parameter test conditions tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tPHZ Output disable time, high-level-to-high-impedance output (2) tPLZ Output disable time, low-level-to-high-impedance output (2) tskew1 CL = 0 pF (1), See Figure 2 and Figure 4 CL = 15 pF, See Figure 2 and Figure 4 Part-to-part output waveform CL = 5 pF, See Figure 3 and Figure 5 max 2.5 4 2.5 4 3 5 3 5 4.1 12 ns 2.8 ns ns ns 4 ns 1.4 ns CL = 10 pF, TA = -40°C to 85°C, See Figure 2 and Figure 4 1.5 ns 0.3 ns 12 ns ∆tskew Same part output waveform skew (3) CL = 10 pF, See Figure 2 and Figure 4 tPZH Output enable time, high-impedance-to-high-level output (2) CL = 10 pF, See Figure 3 and Figure 4 tPZL Output enable time, high-impedance-to-low-level output (2) tTLH Rise time (20%-80%) tTHL Fall time (80%-20%) 0.8 5 4 CL = 10 pF, See Figure 2 and Figure 4 12 ns 1 3.5 ns 1 3.5 ns The propagation delay values with a 0 pF load are based on design and simulation. See Table 1. Output waveform skews are when devices operate with the same supply voltage at the same temperature and have the same packages and the same test circuits. TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE t pd - Propagation Delay Time - ns 10 8 tPLH 6 tPHL 4 2 0 0 A. 4 ns 12 CL = 10 pF, TA = 75°C, See Figure 2 and Figure 4 skew (3) unit 0.7 CL = 150 pF, See Figure 2 and Figure 4 p (1) (2) (3) typ CL = 10 pF, See Figure 2 and Figure 4 Pulse width distortion, |tPHL - tPLH| ∆tskew1p- min 50 100 150 CL - Load Capacitance - pF 200 NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed in the table above as the 0 pF load condition. The incremental increase in delay between the 0 pF load condition and the actual total load capacitance represents the extrinsic, or external delay contributed by the load. TB5R1, TB5R2 www.ti.com SLLS588B – NOVEMBER 2003 – REVISED MAY 2004 TYPICAL CHARACTERISTICS (continued) Figure 1. Typical Propagation Delay vs Load Capacitance at 25°C 3.7 V INPUT 3.2 V 2.7 V INPUT t PHL OUTPUT t PLH 80% V OH 80% 1.5 V 20% 20% t THL V OL t TLH Figure 2. Receiver Propagation Delay Times E1(A) 2.4 V 1.5 V 0.4 V 2.4 V E1(B) 1.5 V 0.4 V t PHZ t PZH t PLZ t PZL VOH OUTPUT 0.2 V VOL 0.2 V 0.2 V 0.2 V A. E2 = 1 while E1 changes states. B. E1 = 0 while E2 changes states. Figure 3. Receiver Enable and Disable Timing Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data transmission driver devices are measured with the following output load circuits. 5V TO OUTPUT OF DEVICE UNDER TEST 2k CL 5k DIODES TYPE 458E, 1N4148, OR EQUIVALENT CL includes test-fixture and probe capacitance. Figure 4. Receiver Propagation Delay Time and Enable Time (tPZH, tPZL) Test Circuit 5 TB5R1, TB5R2 www.ti.com SLLS588B – NOVEMBER 2003 – REVISED MAY 2004 TYPICAL CHARACTERISTICS (continued) TO OUTPUT OF DEVICE UNDER TEST 500
1.5 V CL CL includes test-fixture and probe capacitance. Figure 5. Receiver Disable Time (tPHZ, tPLZ) Test Circuit LOW-TO-HIGH PROPAGATION DELAY vs FREE-AIR TEMPERATURE HIGH-TO-LOW PROPAGATION DELAY vs FREE-AIR TEMPERATURE 6 VCC = 5 V 5 Max 4 Nom 3 Min 2 -50 0 50 100 TA - Free-Air Temperature -
C Figure 6. 6 t PHL- High-to-Low Propagation Delay - ns tPLH - Low-to-High Propagation Delay - ns 6 150 VCC = 5 V 5 Max 4 Nom 3 Min 2 -50 0 50 100 TA - Free-Air Temperature -
C Figure 7. 150 TB5R1, TB5R2 www.ti.com SLLS588B – NOVEMBER 2003 – REVISED MAY 2004 TYPICAL CHARACTERISTICS (continued) MINIMUM VOH AND MAXIMUM VOL vs FREE-AIR TEMPERATURE TYPICAL AND MAXIMUM ICC vs FREE-AIR TEMPERATURE 4 45 VCC = 4.5 V 3.5 VOH min 40 ICC - Supply Current - mA VO - Output Voltage - V 3 2.5 2 1.5 1 ICC max at VCC = 5.5 V 35 30 ICC Typical at VCC = 5 V 25 20 0.5 0 -50 VOL min 0 50 100 TA - Free-Air Temperature - °C Figure 8. 150 15 -50 0 50 100 TA - Free-Air Temperature -
C 150 Figure 9. 7 TB5R1, TB5R2 www.ti.com SLLS588B – NOVEMBER 2003 – REVISED MAY 2004 APPLICATION INFORMATION Power Dissipation The power dissipation rating, often listed as the package dissipation rating, is a function of the ambient temperature, TA, and the airflow around the device. This rating correlates with the device's maximum junction temperature, sometimes listed in the absolute maximum ratings tables. The maximum junction temperature accounts for the processes and materials used to fabricate and package the device, in addition to the desired life expectancy. There are two common approaches to estimating the internal die junction temperature, TJ. In both of these methods, the device internal power dissipation PD needs to be calculated This is done by totaling the supply power(s) to arrive at the system power dissispation: V Sn
I Sn  (1) and then subtracting the total power dissipation of the external load(s): (V Ln
I Ln) (2) The first TJ calculation uses the power dissipation and ambient temperature, along with one parameter: θJA, the junction-to-ambient thermal resistance, in degrees Celsius per watt. The product of PD and θJA is the junction temperature rise above the ambient temperature. Therefore: T J  T A  PD

JA (3) 140 Thermal Impedance − C/W 120 In this analysis, there are two parallel paths, one through the case (package) to the ambient, and another through the device to the PCB to the ambient. The system-level junction-to-ambient thermal impedance, θJA(S), is the equivalent parallel impedance of the two parallel paths:
JA(S)  80 DW, High−K D, High−K 100 200 300 (4) where 100 60 400 500 Figure 10. Thermal Impedance vs Air Flow 8 The standardized θJA values may not accurately represent the conditions under which the device is used. This can be due to adjacent devices acting as heat sources or heat sinks, to nonuniform airflow, or to the system PCB having significantly different thermal characteristics than the standardized test PCBs. The second method of system thermal analysis is more accurate. This calculation uses the power dissipation and ambient temperature, along with two device and two system-level parameters: • θJC, the junction-to-case thermal resistance, in degrees Celsius per watt • θJB, the junction-to-board thermal resistance, in degrees Celsius per watt • θCA, the case-to-ambient thermal resistance, in degrees Celsius per watt • θBA, the board-to-ambient thermal resistance, in degrees Celsius per watt. T J  T A  PD

JA(S) D, Low−K DW, Low−K 40 0 Note that θJA is highly dependent on the PCB on which the device is mounted and on the airflow over the device and PCB. JEDEC/EIA has defined standardized test conditions for measuring θJA. Two commonly used conditions are the low-K and the high-K boards, covered by EIA/JESD51-3 and EIA/JESD51-7 respectively. Figure 10 shows the low-K and high-K values of θJA versus air flow for this device and its package options. 
JC
CA

JB
BA 
JC
CA
JB
BA (5) The device parameters θJC and θJB account for the internal structure of the device. The system-level parameters θCA and θBA take into account details of the PCB construction, adjacent electrical and mechanical components, and the environmental conditions including airflow. Finite element (FE), finite difference (FD), or computational fluid dynamics (CFD) programs can determine θCA and θBA. Details on using these programs are beyond the scope of this data sheet, but are available from the software manufacturers. PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TB5R1D ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R1DE4 ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R1DR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R1DRE4 ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R1DW ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R1DWE4 ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R1DWR ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R1DWRE4 ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R2D ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R2DE4 ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R2DR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R2DRE4 ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R2DW ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R2DWE4 ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R2DWR ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5R2DWRE4 ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TB5R1DR D 16 SITE 60 330 16 6.5 10.3 2.1 8 16 Q1 TB5R1DWR DW 16 SITE 60 330 16 10.75 10.7 2.7 12 16 Q1 TB5R2DR D 16 SITE 60 330 16 6.5 10.3 2.1 8 16 Q1 TB5R2DWR DW 16 SITE 60 330 16 10.75 10.7 2.7 12 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 4-Oct-2007 Package Pins Site Length (mm) Width (mm) Height (mm) TB5R1DR D 16 SITE 60 346.0 346.0 33.0 TB5R1DWR DW 16 SITE 60 346.0 346.0 33.0 TB5R2DR D 16 SITE 60 346.0 346.0 33.0 TB5R2DWR DW 16 SITE 60 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony Low Power Wireless www.ti.com/lpw Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated