TCA39306-Q1
SCPS239A – JUNE 2021 – REVISED DECEMBER 2021
TCA39306-Q1 Dual Bidirectional I2C Bus and SMBus Voltage-Level Translator
1 Features
2 Applications
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•
•
•
•
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Qualified for automotive applications
Functional Safety-Capable
– Documentation available to aid in functional
safety system design
2-Bit bidirectional translator for SDA and SCL lines
in mixed-mode I2C applications
Standard-mode, fast-mode, and fast-mode plus
I2C and SMBus compatible
I3C compatible (12.5 MHz supported)
Allows voltage-level translation between
– 0.9-V VREF1 and 1.8-V, 2.5-V, 3.3-V,
or 5-V VREF2
– 1.2-V VREF1 and 1.8-V, 2.5-V, 3.3-V,
or 5-V VREF2
– 1.8-V VREF1 and 2.5-V, 3.3-V, or 5-V VREF2
– 2.5-V VREF1 and 3.3-V or 5-V VREF2
– 3.3-V VREF1 and 5-V VREF2
Provides bidirectional voltage translation with no
direction Pin
Low ON-state resistance between input and output
ports provides less signal distortion
Open-drain I2C I/O ports (SCL1, SDA1, SCL2, and
SDA2)
5-V Tolerant I2C I/O ports to support mixed-mode
signal operation
High-impedance SCL1, SDA1, SCL2, and SDA2
pins for EN = Low
Lockup-free operation for isolation when EN = Low
Flow-through pinout for ease of printed-circuitboard trace routing
ESD Protection Exceeds JESD 22
– 2000-V human-body model (A114-A)
– 1000-V charged-device model (C101)
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•
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I2C, SMBus, PMBus, MDIO, UART, low-speed
SDIO, GPIO, and other two-signal interfaces
Servers
Routers (telecom switching equipment)
Personal computers
Industrial automation
3 Description
The TCA39306-Q1 is a dual bidirectional voltage-level
translator compatible with I2C, SMBus, and I3C with
an enable (EN) input, and is operational from 0.9-V to
3.3-V VREF1 and 1.8-V to 5.5-V VREF2.
The device allows bidirectional voltage translations
between 0.85 V and 5 V, without the use of a
direction pin. The low ON-state resistance (RON)
of the switch allows connections to be made with
minimal propagation delay. When EN is high, the
translator switch is ON, and the SCL1 and SDA1
I/O are connected to the SCL2 and SDA2 I/O,
respectively, allowing bidirectional data flow between
ports. When EN is low, the translator switch is off, and
a high-impedance state exists between ports.
In addition to voltage translation, the TCA39306Q1 can be used to isolate a higher speed bus
from a lower speed bus by controlling the EN
pin to disconnect the slower bus during fast-mode
communication.
Device Information
PART NUMBER
TCA39306-Q1
(1)
PACKAGE(1)
BODY SIZE (NOM)
VSSOP (8)
2.30 mm x 2.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
200 k
VREF1
I2C, SMBus, or
I3C controller
VREF2
EN
TCA39306-Q1
SCL1
SCL2
SDA1 GND SDA2
Responder
devices
Simplified Application Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA39306-Q1
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SCPS239A – JUNE 2021 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics (Translating Down).............6
6.7 Switching Characteristics (Translating Up)................. 7
6.8 Switching Characteristics............................................8
6.9 Typical Characteristics................................................ 9
7 Parameter Measurement Information.......................... 10
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 18
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................18
9 Application and Implementation.................................. 19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 19
9.3 Systems Examples: I3C Usage Considerations....... 22
10 Power Supply Recommendations..............................24
11 Layout........................................................................... 25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Receiving Notification of Documentation Updates..26
12.2 Support Resources................................................. 26
12.3 Trademarks............................................................. 26
12.4 Electrostatic Discharge Caution..............................26
12.5 Glossary..................................................................26
13 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2021) to Revision A (December 2021)
Page
• Changed the document from Advanced Information to Production data............................................................ 1
2
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5 Pin Configuration and Functions
GND
1
8
EN
2
7
V
SCL1
3
6
SCL2
SDA1
4
5
SDA2
V
REF1
REF2
Figure 5-1. DCU Package, 8-Pin VSSOP, Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
DCU
EN
8
I
Switch enable input
GND
1
—
Ground, 0 V
SCL1
3
I/O
Serial clock, low-voltage side
SCL2
6
I/O
Serial clock, high-voltage side
SDA1
4
I/O
Serial data, low-voltage side
SDA2
5
I/O
Serial data, high-voltage side
VREF1
2
I
Low-voltage-side reference supply voltage for SCL1 and SDA1
VREF2
7
I
High-voltage-side reference supply voltage for SCL2 and SDA2
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VREF1
DC reference voltage range
–0.5
7
V
VREF2
DC reference bias voltage range
–0.5
7
V
–0.5
7
V
–0.5
7
V
(2)
VI
Input voltage range
VI/O
Input-output voltage range (2)
Continuous channel current
128
mA
IIK
Input Clamp Current (VI < 0 )
–50
mA
TJ(Max)
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
The input and input-output negative voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±2000
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VI/O
Input-output voltage
MIN
MAX
UNIT
0
5.5
V
VREF1 (1)
Reference Voltage
0
5.5
V
(1)
Reference Voltage
0
5.5
V
1.5
5.5
V
0
5.5
V
64
mA
125
°C
VREF2
ENSwitch(2)
Switch mode enable voltage (Switch mode enable voltage)
EN
Enable input voltage
IPASS
Pass switch current
TA
Ambient temperature
(1)
(2)
4
SCL1, SDA1, SCL2,
SDA2
–40
To support translation, VREF1 supports 0.85 V to VREF2 - 0.6 V. VREF2 must be between VREF1 + 0.6 V to 5.5 V. See Typical
Application for more information.
To support switching, VREF1 and VREF2 Do not need to be connected. EN pin should use a voltage not less than 1.5V when the switch
mode is to be enabled. Enabled voltage on this pin should be equal to 1.5V or I/O supply voltage, whichever is higher.
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6.4 Thermal Information
TCA39306Q1
THERMAL METRIC(1)
UNIT
DCU
8 PINS
RθJA
Junction-to-ambient thermal resistance
275.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
127.1
°C/W
RθJB
Junction-to-board thermal resistance
186.9
°C/W
ΨJT
Junction-to-top characterization parameter
65.7
°C/W
ΨJB
Junction-to-board characterization parameter
185.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
(1)
VIK
Input clamp voltage
II = -18 mA
EN = 0 V
IIH
Input leakage current
VI = 5 V, VO
= 0V
EN = 0 V
VT
Threshold voltage
IO = 500 µA
VI = 0.1 V, VO = 0 V, Find
VEN where IO = 500 µA
CI(EN)
Input capacitance
VI = 3 V or 0
V
CIO(off)
Off capacitance
SCLn, SDAn
VO = 3 V or 0
EN = 0 V
V
4
6
pF
CIO(on)
On capacitance
SCLn, SDAn
VO = 3 V or 0
EN = 3 V
V
10.5
12.5
pF
5.5
Ω
RON
On-state resistance
SCLn, SDAn (-40 to
125C)
0.7
0
V
5
µA
1.0
V
11
pF
VI = 0 V(3)
IO = 64 mA
EN = 4.5 V
3.5
V(3)
IO = 64 mA
EN = 3 V
4.7
7
Ω
VI = 0 V(3)
IO = 64 mA
EN = 2.3 V
6.3
9.5
Ω
V(3)
VI = 0
(2)
-1.2
MAX UNIT
VI = 0
IO = 15 mA
EN = 1.5 V
VI = 2.4 V(4)
IO = 15 mA
EN = 4.5 V
V(4)
IO = 15 mA
VI = 1.7 V(4)
IO = 15 mA
VI = 2.4
25.5
32
Ω
1
6
15
Ω
EN = 3 V
20
50
75
Ω
EN = 2.3 V
20
55
75
Ω
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6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IO = 64 mA
VI = 0 V,
VCC2 = 5
V(5)
IO = 32 mA
RON
(1)
(2)
(3)
(4)
(5)
On-state resistance
SCLn, SDAn
MIN
TYP
(1)
MAX UNIT
VCC1 = 1 V
5
25
VCC1 = 1.8
V
4
10
VCC1 = 2.5
V
3
8
VCC1 = 3.3
V
3
7
VCC1 = 1 V
5
10
VCC1 = 1.8
V
4
9
VCC1 = 2.5
V
3
8
VCC1 = 3.3
V
3
7
Ω
Ω
VI = 1.8 V,
VCC2 = 5
V(5)
IO = 15 mA
VCC1 = 3.3
V
4
13
Ω
VI = 1 V,
VCC2 = 3.3
V(5)
IO = 10 mA
VCC1 = 1.8
V
7
24
Ω
VI = 0 V,
VCC2 = 3.3
V(5)
IO = 10 mA
VCC1 = 1 V
5
18
Ω
VI = 0 V,
VCC2 = 1.8
V(5)
IO = 10 mA
VCC1 = 1 V
6
19
Ω
All typical values are at TA = 25°C.
Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals, at the indicated current through the switch.
Minimum ON-state resistance is determined by the lowest voltage of the two terminals.
Measured in current source configuration only. See Figure 7-1
Measured in current sink configuration only. See Figure 7-1
Measured in application connected current source configuration only. See Figure 7-3
6.6 Switching Characteristics (Translating Down)
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TPLH
TEST CONDITIONS
Low-to-high propagation delay
EN = 3.3 V, VIH = 3.3 V, VIL = 0, VM
= 1.15 V(2)
TPHL
TPLH
High to low propagation delay
Low-to-high propagation delay
EN = 2.5 V, VIH = 3.3 V, VIL = 0, VM
= 0.75 V(2)
TPHL
6
High to low propagation delay
MIN
TYP
MAX
CL = 15 pF
0
0.3
CL = 30 pF
0
0.6
CL = 50 pF
0
0.8
CL = 15 pF
0
0.75
CL = 30 pF
0
1
CL = 50 pF
0
1.2
CL = 15 pF
0
0.4
CL = 30 pF
0
0.6
CL = 50 pF
0
1
CL = 15 pF
0
0.8
CL = 30 pF
0
1.3
CL = 50 pF
0
1.3
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UNIT
ns
ns
ns
ns
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6.6 Switching Characteristics (Translating Down) (continued)
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TPLH
TEST CONDITIONS
Low-to-high propagation delay
EN = 2.5 V, VIH = 2.5 V, VIL = 0, VM
= 0.75 V(2)
TPHL
(1)
(2)
High to low propagation delay
MIN
TYP
MAX
CL = 15 pF
0
0.4
CL = 30 pF
0
0.7
CL = 50 pF
0
1
CL = 15 pF
0
0.75
CL = 30 pF
0
1
CL = 50 pF
0
1.3
UNIT
ns
ns
Guaranteed by simulation, not tested in production
Translating Down: the high-voltage side driving toward the low-voltage side. See Fig 7.2 Direct Propagation Measurement
6.7 Switching Characteristics (Translating Up)
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TPLH
TEST CONDITIONS
Low-to-high propagation delay
EN = 3.3 V, VIH = 2.3 V, VT = 3.3 V,
VM = 1.15 V(2)
TPHL
TPLH
High to low propagation delay
Low-to-high propagation delay
EN = 2.5 V, VIH = 2.3 V, VT = 3.3 V,
VM = 0.75 V(2)
TPHL
TPLH
High to low propagation delay
Low-to-high propagation delay
EN = 2.5 V, VIH = 1.5 V, VT = 2.5 V,
VM = 0.75 V(2)
TPHL
(1)
(2)
High to low propagation delay
MIN
TYP
MAX
CL = 15 pF
0
0.4
CL = 30 pF
0
0.6
CL = 50 pF
0
0.9
CL = 15 pF
0
1.0
CL = 30 pF
0
1.4
CL = 50 pF
0
1.7
CL = 15 pF
0
0.4
CL = 30 pF
0
0.6
CL = 50 pF
0
1
CL = 15 pF
0
1.6
CL = 30 pF
0
2.0
CL = 50 pF
0
2.7
CL = 15 pF
0
0.4
CL = 30 pF
0
0.6
CL = 50 pF
0
1
CL = 15 pF
0
1.3
CL = 30 pF
0
1.7
CL = 50 pF
0
2.1
UNIT
ns
ns
ns
ns
ns
ns
Guaranteed by simulation, not tested in production
Translating up: the low-voltage side driving toward the high-voltage side. See Fig 7.2 Direct Propagation Measurement
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6.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPLH
TPHL
Low-to-high propagation
High-to-low propagation delay(1)
8
MAX
CL = 50 pF
32
VCC1 = 0.85 V, VCC2 = 3.6 V, RL_Input CL = 15 pF
= 1.35 kΩ
CL = 50 pF
15
VCC1 = 0.85 V, VCC2 = 5.5 V, RL_Input CL = 15 pF
= 1.35 kΩ
CL = 50 pF
20
VCC1 = 1.65 V, VCC2 = 3.6 V, RL_Input CL = 15 pF
= 1.35 kΩ
CL = 50 pF
8
45
46
20
VCC1 = 1.65 V, VCC2 = 5.5 V, RL_Input CL = 15 pF
= 1.35 kΩ
CL = 50 pF
15
VCC1 = 3 V, VCC2 = 5.5 V, RL_Input =
1.35 kΩ
CL = 15 pF
2
CL = 50 pF
5
VCC1 = 0.85 V, VCC2 = 1.98 V,
RL_Input = 1.35 kΩ
CL = 15 pF
3
CL = 50 pF
4
VCC1 = 0.85 V, VCC2 = 3.6 V, RL_Input CL = 15 pF
= 1.35 kΩ
CL = 50 pF
3
VCC1 = 0.85 V, VCC2 = 5.5 V, RL_Input CL = 15 pF
= 1.35 kΩ
CL = 50 pF
3
VCC1 = 1.65 V, VCC2 = 3.6 V, RL_Input CL = 15 pF
= 1.35 kΩ
CL = 50 pF
2
VCC1 = 1.65 V, VCC2 = 5.5 V, RL_Input CL = 15 pF
= 1.35 kΩ
CL = 50 pF
3
CL = 15 pF
1.5
CL = 50 pF
2
VCC1 = 3 V, VCC2 = 5.5 V, RL_Input =
1.35 kΩ
(1)
TYP
13
VCC1 = 0.85 V, VCC2 = 1.98 V,
RL_Input = 1.35 kΩ
delay(1)
MIN
CL = 15 pF
35
5
5
3
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measured with an application propagation delay setup. See Figure 7-4
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6.9 Typical Characteristics
300
110
125C
85C
25C
-40C
270
240
90
80
210
70
180
RON ()
RON ()
125C
85C
25C
-40C
100
150
120
60
50
40
90
30
60
20
30
10
0
0
0
0.5
1
VEN = 1.5 V
1.5
2
2.5
3
VSDA1 or VSCL1 (V)
3.5
4
4.5
0
II = 15 mA
0.5
1
1.5
2
2.5
3
VSDA1 or VSCL1 (V)
VEN = 4.5 V
Figure 6-1. On-Resistance (RON) vs Input Voltage
(VSDA1 or VSCL1)
3.5
4
4.5
II = 15 mA
Figure 6-2. On-Resistance (RON) vs Input Voltage
(VSDA1 or VSCL1)
0
Bandwidth (dB)
-2
-4
-6
-8
-10
-12
10M
100M
Frequency (Hz)
VEN = 2.5 V
1G
VBIAS = GND
Figure 6-3. Typical Bandwidth
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7 Parameter Measurement Information
VEN
+
–
VEN
IO
+
–
Source Current
VI - RON*IO
VI + RON*IO
VI
Sink Current
+
–
VI
+
–
IO
B) Current Sink Configuration
A) Current Source Configuration
Figure 7-1. Current Source and Current Sink Configurations for Direct RON Measurements
VEN
+
–
EN
VCC2
VREF1
VREF2
RL
VO
SCL1/SDA1
VI
SCL2/SDA2
+
–
Figure 7-2. Direct Propagation Measurement
10
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VCC1
VCC2
200 k
EN
VREF1
VREF2
IO
VI + RON*IO
SCL1/SDA1
VI
SCL2/SDA2
+
–
Figure 7-3. Application Setup for RON Delay
VCC1
VCC2
200 k
EN
VCC2
VREF1
VREF2
RL
VO
SCL1/SDA1
VI
SCL2/SDA2
+
–
Figure 7-4. Application Setup for Propagation Delays Delay
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SWITCH
USAGE
S1
Translating up
S2
Translating down
VT
RL
S1
VIH
Open
From Output
under Test
VM
S2
VM
Input
CL
(see Note A)
VIL
tPLH
VOH
VM
Load Circuit
tPHL
Output
VM
VOL
NOTES: A. CL includes probe and jig capacitance
B. All input pulses are supplied by generators having the following characteristics: WZZ G 10 MHz, ZO = 50 Q , tr G 2 ns, tf G 2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 7-5. Load Circuit for Outputs
12
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8 Detailed Description
8.1 Overview
The TCA39306-Q1 is a dual bidirectional voltage-level translator compatible with I2C, SMBus, and I3C with an
enable (EN) input, and is operational from 0.9-V to 3.3-V VREF1 and 1.8-V to 5.5-V VREF2.
The device allows bidirectional voltage translations between 0.85 V and 5 V, without the use of a direction pin.
The low ON-state resistance (RON) of the switch allows connections to be made with minimal propagation delay.
When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2
I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and
a high-impedance state exists between ports.
In addition to voltage translation, the TCA39306-Q1 can be used to isolate a higher speed bus from a lower
speed bus by controlling the EN pin to disconnect the slower bus during fast-mode communication.
In I2C applications, the bus capacitance limit of 400 pF for Standard and Fast Modes, 550 pF for Fast Mode Plus
restricts the number of devices and bus length. The capacitive load on both sides of the device must be taken
into account when approximating the total load of the system, specifying the sum of both sides is under 400/550
pF.
Both the SDA and SCL channels of the device have the same electrical characteristics, and there is minimal
deviation from one output to another in voltage or propagation delay. This is a benefit over discrete-transistor
voltage-translation solutions, because the fabrication of the switch is symmetrical.
8.1.1 Definition of threshold voltage
This document references a threshold voltage denoted as Vth, which appears multiple times throughout this
document when discussing the NFET between VREF1 and VREF2. The value of Vth is approximately 0.6 V at room
temperature.
8.1.2 Correct Device Set Up
In a normal set up shown in Figure 8-1, the enable pin and VREF2 are shorted together and tied to a 200-kΩ
resistor, and a reference voltage equal to VREF1 plus the FET threshold voltage is established. This reference
voltage is used to help pass lows from one side to another more effectively while still separating the different pull
up voltages on both sides.
VCC2 = +3.3 V
Normal Setup
VCC1 < VCC2
200 kŸ
VCC1 = +1.8 V
EN
+1.8 V + VTH
RPU
RPU
RPU
RPU
+
Vgs
VREF1
-
VREF2
IREF2 = 4 µA
SDA1
SDA2
SCL1
SCL2
Figure 8-1. Normal Setup
Care should be taken to make sure VREF2 has an external resistor tied between it and VCC2. If VREF2 is tied
directly to the VCC2 rail without a resistor, then there is no external resistance from the VCC2 to VCC1 to limit the
current such as in Figure 8-2. This effectively looks like a low impedance path for current to travel through and
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potentially break the pass FET if the current flowing through the pass FET is larger than the absolute maximum
continuous channel current specified in the Absolute Maximum Ratings. The continuous channel current is larger
with a higher voltage difference between VCC1 and VCC2.
Figure 8-2 shows an improper set up. If VCC2 is larger than VCC1 but less than Vth, the impedance between VCC1
and VCC2 is high resulting in a low drain to source current, which does not cause damage to the device. Concern
arises when VCC2 becomes larger than VCC1 by Vth. During this event, the NFET turns on and begin to conduct
current. This current is dependent on the gate to source voltage and drain to source voltage.
VCC2 = +3.3 V
Abnormal Setup
VCC1 < VCC2
200k Ÿ
VCC1 = +1.8 V
EN
RPU
RPU
RPU
RPU
+
Vgs
VREF1
-
VREF2
SDA1
SDA2
SCL1
SCL2
Figure 8-2. Abnormal Setup
8.1.3 Disconnecting a Responder from the Main Bus Using the EN Pin
TCA39306-Q1 can be used as a switch to disconnect one side of the device from the main bus, whether
isolating I3C and I2C devices or different speed groups. This can be advantageous in multiple situations. One
instance of this situation is if there are devices on the I2C bus which only supports fast mode (400 kHz) while
other devices on the bus support fast mode plus (1 MHz). An example of this is displayed in Figure 8-3.
3.3 V I2C bus
(1 MHz)
TCA39306-Q1
EN
3.3 V I2C bus
(400 kHz)
GPIO
Note: GPIO logic high must not
exceed 3.3 V +Vth in this example
Figure 8-3. Example of an I2C bus with multiple supported frequencies
In this situation, if the controller is on the 1 MHz side then communicating at 1 MHz should not be attempted if
TCA39306-Q1 were enabled. It needs to be disabled for the device to avoid possibly glitching state machines
in devices which were designed to operate correctly at 400 kHz or slower. When the device is disabled, the
controller can communicate with the 1 MHz devices without disturbing the 400 kHz bus. When the device is
enabled, communication across both sides at 400 kHz is acceptable.
8.1.4 Supporting Remote Board Insertion to Backplane with TCA39306-Q1
Another situation where TCA39306-Q1 is advantageous when using its enable feature is when a remote board
with I2C lines needs to be attached to a main board (backplane) with an I2C bus such as in Figure 8-4. If
connecting a remote board to a backplane is not done properly, the connection could result in data corruption
during a transaction or the insertion could generate an unintended pulse on the SCL line. Which could glitch an
I2C device state machine causing the I2C bus to get stuck.
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Main Board
3.3 V I2C bus
Remote Board
3.3 V I2C bus
TCA39306-Q1
EN
GPIO
Note: GPIO logic high must not
exceed 3.3 V +Vth in this example
Figure 8-4. An example of connecting a remote board to a main board (backplane)
TCA39306-Q1 can be used to support this application because it can be disabled while making the connection.
Then it is enabled once the remote board is powered on and the buses on both sides are IDLE.
8.1.5 Switch Configuration
TCA39306-Q1 has the capability of being used with its VREF1 voltage equal to VREF2. This essentially turns the
device from a translator to a device which can be used as a switch, and in some situations this can be useful.
The switch configuration is shown in Figure 8-5 and translation mode is shown in Figure 8-6.
VCC2
GPIO: high logic does not
exceed Vref2 + Vth
VCC1
200 k
Where Vcc2 = Vcc1
VCC1
VCC1
R
R
Vref1
Vref2
VCC2 VCC2
EN
R
TCA39306-Q1
SCL1
SCL2
SDA1
SDA2
R
Switch Configuration: Vref1=Vref2 and
Enable is controlled by a GPIO
Figure 8-5. Switch Configuration
VCC2
VCC1
200 k
VCC1
VCC1
R
R
Vref1
Vref2
VCC2 VCC2
EN
R
TCA39306-Q1
SCL1
SCL2
SDA1
SDA2
R
Translation Configuration
where Vcc2 >= Vref1 + 0.7 V
Figure 8-6. Translation Configuration
When TCA39306-Q1 is in the switch configuration (VREF1 = VREF2), the propagation delays are different
compared to the translator configuration. Taking a look at the propagation delays, if the pull up resistance and
capacitance on both sides of the bus are equal, then in switch mode the device has the same propagation delay
from side one to two and side two to one. The propagation delays become lower when VCC1/VCC2 is larger. For
example, the propagation delay at 1.8 V is longer than at 5 V in the switching configuration. When the device is
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in translation mode, side one propagate lows to side two faster than side two can propagate lows to side 1. This
time difference becomes larger the larger the difference between VCC2 and VCC1 becomes.
8.1.6 Controller on Side 1 or Side 2 of Device
I2C and SMBus are bidirectional protocol meaning devices on the bus can both transmit and receive data.
TCA39306-Q1 was designed to allow for signals to be able to be transmitted from either side, thus allowing for
the controller to be able to place on either side of the device. Figure 8-7 shows the controller on side two as
opposed to the diagram on page 1 of this data sheet.
VCC2
VCC1
200 k
Vref1
Vref2
EN
TCA39306-Q1
I2C responder
devices
SCL1
SCL2
SDA1
SDA2
I2C or SMBus
Controller (processor)
Figure 8-7. Controller on side 2
8.1.7 LDO and TCA39306-Q1 Concerns
The VREF1 pin can be supplied by a low-dropout regulator (LDO), but in some cases the LDO may lose its
regulation because of the bias current from VREF2 to VREF1. If the LDO cannot sink the bias current, then the
current has no other paths to ground and instead charges up the capacitance on the VREF1 node (both external
and parasitic). This results in an increase in voltage on the VREF1 node. If no other paths for current to flow
are established (such as back biasing of body diodes or clamping diodes through other devices on the VREF1
node), then the VREF1 voltage ends up stabilizing when Vgs of the pass FET is equal to Vth. This means VREF1
node voltage is VCC2 - Vth. Note that any secondary or primaries running off of the LDO now see the VCC2 - Vth
voltage which may cause damage to those secondary or primaries if they are not rated to handle the increased
voltage.
Translator Setup with Vref1
provided by LDO and no path
for bias current
VCC2 = +3.3 V
200 k
VCC1 < VCC2
Ven = Vref1 + VTH
EN
LDO
Vout
+
Vgs
-
+
VREF1 = Vcc2 - Vth
-
VREF1
pin
VREF2
pin
Ibias = (Vcc2 – Ven) / 200 k
CREF1
Figure 8-8. Example of no leakage current path when using LDO
To make sure the LDO does not lose regulation due to the bias current of TCA39306-Q1, a weak pull down
resistor can be placed on VREF1 to ground to provide a path for the bias current to travel. The recommended
pull down resistor is calculated by Equation 4 where 0.75 gives about 25% margin for error incase bias current
increases during operation.
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VCC2 = +3.3 V
Translator Setup
200 k
VCC1 < VCC2
Ven = Vref1 + VTH
EN
LDO
+
Vgs
-
Vout = +1.8 V
VREF1
VREF2
Rpulldown
CREF1
Ibias = (Vcc2 – Ven) / 200 k
Figure 8-9. Example with Leakage current path when using an LDO
Ven = VREF1 + Vth
(1)
where
• Vth is approximately 0.6 V
Ibias = (VCC2 - Ven)/200 k
(2)
Rpulldown = VOUT/Ibias
(3)
Recommended Rpulldown = Rpulldown x 0.75
(4)
8.1.8 Current Limiting Resistance on VREF2
The resistor is used to limit the current between VREF2 and VREF1 (denoted as RCC) and helps to establish the
reference voltage on the enable pin. The 200k resistor can be changed to a lower value; however, the bias
current proportionally increases as the resistor decreases.
Ibias = (VCC2 - Ven)/RCC : Ven = VREF1 + Vth
(5)
where
• Vth is approximately 0.6 V
Keep in mind RCC should not be sized low enough that ICC exceeds the absolute maximum continuous channel
current specified in the Absolute Maximum Ratings which is described in Equation 6.
RCC(min) ≥ (VCC2 - Ven)/0.128 : Ven = VREF1 + Vth
(6)
where
• Vth is approximately 0.6 V
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8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Enable (EN) Pin
The device is a double-pole, single-throw switch in which the gate of the transistors is controlled by the voltage
on the EN pin. In Figure 9-1, the device is always enabled when power is applied to VREF2. In Figure 9-2, the
device is enabled when a control signal from a processor is in a logic-high state.
8.3.2 Voltage Translation
The primary feature of the device is translating voltage from an I2C bus referenced to VREF1 up to an I2C bus
referenced to VDPU, to which VREF2 is connected through a 200-kΩ pullup resistor. Translation on a standard,
open-drain I2C bus is achieved by simply connecting pullup resistors from SCL1 and SDA1 to VREF1 and
connecting pullup resistors from SCL2 and SDA2 to VDPU. Information on sizing the pullup resistors can be
found in the Sizing Pullup Resistors section.
8.4 Device Functional Modes
(1)
18
INPUT
EN(1)
TRANSLATOR FUNCTION
H
Logic Lows are propagated from one side to the other, Logic Highs blocked (independent
pull up resistors passively drive the line high)
L
Disconnect
The SCL switch conducts if EN is ≥ 0.6 V higher than SCL1 or SCL2. The same is true of SDA.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 General Applications of I2C
As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the translator
bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup
resistor. The device is designed to work with standard-mode and fast-mode I2C devices in addition to SMBus
devices. Standard-mode I2C devices only specify 3 mA in a generic I2C system where standard-mode devices
and multiple controllers are possible. Under certain conditions, high termination currents can be used. When
the SDA1 or SDA2 port is low, the clamp is in the ON state, and a low-resistance connection exists between
the SDA1 and SDA2 ports. Assuming the higher voltage is on the SDA2 port when the SDA2 port is high,
the voltage on the SDA1 port is limited to the voltage set by VREF1. When the SDA1 port is high, the SDA2
port is pulled to the pullup supply voltage of the drain (VDPU) by the pullup resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user, without the need for directional
control. The SCL1-SCL2 channel also functions in the same way as the SDA1-SDA2 channel.
9.2 Typical Application
Figure 9-1 and Figure 9-2 show how these pullup resistors are connected in a typical application, as well as two
options for connecting the EN pin.
VPU_1 = 1.8 V
VPU_2 = 3.3 V
200 kΩ
TCA39306-Q1
RPU
VCC
RPU
VREF1
VREF2
RPU
RPU
EN
I2C
Controller
SCL1
SCL
SDA1
SDA
SW
SW
VCC
I2C
Responder
SCL
SCL2
SDA2
SDA
GND
GND
GND
Figure 9-1. Typical Application Circuit (Switch Always Enabled)
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On
3.3 V EN Signal
Off
VPU_1 = 1.8 V
VPU_2 = 3.3 V
200 k
TCA39306-Q1
RPU
VCC
RPU
VREF1
VREF2
RPU
RPU
VCC
EN
I2C
Controller
SCL1
SCL
SDA1
SDA
SW
SW
I2C
Responder
SCL
SCL2
SDA2
SDA
GND
GND
GND
Figure 9-2. Typical Application Circuit (Switch Enable Control)
9.2.1 Design Requirements
MIN TYP(1)
MAX
UNIT
VREF2
Reference voltage
VREF1 + 0.6
2.1
5
V
EN
Enable input voltage
VREF1 + 0.6
2.1
5
V
VREF1
Reference voltage
0.9
1.5
4.4
IPASS
Pass switch current
6
mA
IREF
Reference-transistor current
5
μA
(1)
V
All typical values are at TA = 25°C.
9.2.2 Detailed Design Procedure
9.2.2.1 Bidirectional Voltage Translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the EN input must be connected to VREF2 and both pins pulled to high-side VDPU through a pullup resistor
(typically 200 kΩ). This allows VREF2 to regulate the EN input. A 100-pF filter capacitor connected to VREF2 is
recommended. The I2C bus controller output can be push-pull or open-drain (pullup resistors may be required)
and the I2C bus device output can be open-drain (pullup resistors are required to pull the SCL2 and SDA2
outputs to VDPU). However, if either output is push-pull, data must be unidirectional or the outputs must be
3-state capable and be controlled by some direction-control mechanism to prevent high-to-low contentions in
either direction. If both outputs are open-drain, no direction control is needed.
9.2.2.2 Sizing Pullup Resistors
To get an estimate for the range of values that can be used for the pullup resistor, please refer to the application
note SLVA689. Figure 9-3 and Figure 9-4 respectively show the maximum and minimum pullup resistance
allowable by the I2C specification for standard-mode (100 kHz) and fast-mode (400 kHz) operation.
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9.2.2.3 Bandwidth
The maximum frequency of the device depends on the application. The device can operate at speeds of > 100
MHz given the correct conditions. The maximum frequency is dependent upon the loading of the application.
However, this is an analog type of measurement. For digital applications, the signal should not degrade up to the
fifth harmonic of the digital signal. The frequency bandwidth should be at least five times the maximum digital
clock rate. This component of the signal is important in determining the overall shape of the digital signal. In the
case of the device, digital clock frequency of >100 MHz can be achieved.
The device does not provide any drive capability like the TCA9517 or other buffered translators. Therefore,
higher-frequency applications require higher drive strength from the host side. No pullup resistor is needed on
the host side (3.3 V) if the device is being driven by standard CMOS push-pull output driver. Ideally, it is best to
minimize the trace length from device on the sink side (1.8 V) to minimize signal degradation.
You can then use a simple formula to compute the maximum practical frequency component or the knee
frequency (fknee). All fast edges have an infinite spectrum of frequency components. However, there is an
inflection (or knee) in the frequency spectrum of fast edges where frequency components higher than fknee are
insignificant in determining the shape of the signal.
To calculate fknee:
fknee = 0.5 / RT (10%–90%)
(7)
fknee = 0.4 / RT (20%–80%)
(8)
For signals with rise-time characteristics based on 10- to 90-percent thresholds, fknee is equal to 0.5 divided by
the rise time of the signal. For signals with rise-time characteristics based on 20- to 80-percent thresholds, which
is very common in many current device specifications, fknee is equal to 0.4 divided by the rise time of the signal.
Some guidelines to follow that help maximize the performance of the device:
• Keep trace length to a minimum by placing the device close to the I2C output of the processor.
• The trace length should be less than half the time of flight to reduce ringing and line reflections or nonmonotonic behavior in the switching region.
• To reduce overshoots, a pullup resistor can be added on the 1.8 V side; be aware that a slower fall time is to
be expected.
9.2.3 Application Curve
VDPUX < 2 V
VDPUX > 2 V
Standard mode
(fSCL = 100 kHz,
tr = 1 μs)
Fast mode
(fSCL = 400 kHz,
tr = 300 ns)
Fast mode plus
(fSCL = 1000 kHz,
tr = 120 ns)
Figure 9-3. Maximum Pullup Resistance (Rp(max))
vs Bus Capacitance (Cb)
VOL = 0.2 x VDPUX , IOL = 2 mA when VDPUX ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V
Figure 9-4. Minimum Pullup Resistance (Rp(min)) vs
Pullup Reference Voltage (VDPUX)
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9.3 Systems Examples: I3C Usage Considerations
The TCA39306-Q1 has bandwidth to support the high speeds needed for I3C, but there are special
considerations which are required. Since I3C uses both push-pull and open-drain, it may not be possible to
support all I3C applications with a FET-based translator.
9.3.1 I3C Bus Switching
Bus switching is when the bus path is enabled or disabled, but does not translate the bus voltage. External
pull-up resistors are not needed for I3C, because the controller enables or disables the pull-up resistor on the
SDA line. This presents a unique challenge for FET-based translators, like the TCA39306-Q1, because they rely
on a pull-up resistor to pull the output side of the switch all the way to supply. For the switching use case, there is
no translation, but the enable voltage must be high enough for the switch to stay on for the entire voltage range
of the bus (0 V to bus voltage).
RON must be low enough for the full push-pull voltage range. The EN voltage must be at least 1 Vt (~0.6 V)
above the maximum desired pass-voltage. This comes out to VEN ≥ VBUS + 0.6 V. Since the switch enable
voltage is being directly controlled, the VREF1 and VREF2 pins are not needed, and can be shorted to ground to
improve power consumption.
It is possible to control the EN pin with a voltage equal to VBUS, but external pull-up resistors on the downstream
side are a requirement to ensure the bus is pulled entirely to VBUS.
On
VEN VBUS + 0.6 V
Off
TCA39306-Q1
VCC
VREF1
EN
I3C
Controller
SCL1
SCL
SDA
SDA1
VCC
VREF2
SW
SW
SCL2
SDA2
I3C
Responder
SCL
SDA
GND
GND
GND
Figure 9-5. I3C Bus Switching Application (Without Pull-up Resistors)
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On
VEN = VBUS
Off
VBUS = 3.3 V
TCA39306-Q1
RPU
VCC
RPU
VREF1
VREF2
RPU
RPU
VCC
EN
I3C
Controller
SCL1
SCL
SDA1
SDA
SW
SW
I3C
Responder
SCL
SCL2
SDA2
SDA
GND
GND
GND
Figure 9-6. I3C Bus Switching Application (With Pull-up Resistors)
9.3.2 I3C Bus Voltage Translation
Bus voltage translation is when the bus voltage is translated up or down. This presents a unique challenge
with I3C for FET-based translators, like the TCA39306-Q1, because they rely on a pull-up resistor to translate
the voltage up from the low-voltage side. The pull-up resistor selected must be strong enough to meet the
timing requirements (based on bus capacitance and translation voltages), but not so strong to violate the VIL
requirements of the I3C devices.
The pull-up resistors are needed on both sides. The reason for this is that with the normal translation setup,
the switch is "on" when either side's bus voltage drops to roughly VPU_1. This means that the pull-up resistors
are required to pull the bus voltage on the high-voltage side from VPU_1 to VPU_2. When the device on the
high-voltage side is controlling the bus, the switch will turn off at VPU_1. The pull-up resistors on the low-voltage
side are used to bleed off any additional current that might "leak" through the switch.
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VPU_1 = 1.8 V
VPU_2 = 3.3 V
200 kΩ
TCA39306-Q1
RPU
VCC
RPU
VREF1
VREF2
EN
I3C
Controller
SCL
SDA
SCL1
SDA1
SW
SW
SCL2
SDA2
GND
RPU
RPU
VCC
I3C
Responder
SCL
SDA
GND
GND
Figure 9-7. I3C Bus Translation
10 Power Supply Recommendations
For supplying power to the device, the VREF1 pin can be connected directly to a power supply. The VREF2 pin
must be connected to the VDPU power supply through a 200-kΩ resistor. Failure to have a high-impedance
resistor between VREF2 and VDPU results in excessive current draw and unreliable device operation. It is also
worth noting, that in order to support voltage translation, the device must have the EN and VREF2 pins shorted
and then pulled up to VDPU through a high-impedance resistor.
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11 Layout
11.1 Layout Guidelines
For printed-circuit board (PCB) layout of the device, common PCB layout practices should be followed, but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other on leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. The 100-pF filter capacitor should be
placed as close to VREF2 as possible. A larger decoupling capacitor can also be used, but a longer time constant
of two capacitors and the 200-kΩ resistor results in longer turnon and turnoff times for the TCA39306-Q1 device.
These best practices are shown in Figure 11-1.
For the layout example provided in Figure 11-1, it would be possible to fabricate a PCB with only two layers by
using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND).
However, a four-layer board is preferable for boards with higher-density signal routing. On a four-layer PCB,
it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and
dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and
ground, vias are placed directly next to the surface-mount component pad, which must attach to VCC or GND,
and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when
a signal trace must be routed to the opposite side of the board, but this technique is not demonstrated in Figure
11-1.
11.2 Layout Example
Figure 11-1. Layout Example
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
26
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TCA39306-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TCA39306DCURQ1
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2GST
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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