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TCA6408A-Q1
SCPS234 – SEPTEMBER 2016
TCA6408A-Q1 Low-Voltage 8-Bit I2C and SMBus I/O Expander With Interrupt Output
1 Features
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2 Applications
2
I C to Parallel Port Expander
Operating Power-Supply Voltage Range of 1.65 V
to 3.6 V
Allows Bidirectional Voltage-Level Translation and
GPIO Expansion Between 1.8-, 2.5-, and 3.3-V
I2C Bus and P-Ports
Low Standby Current Consumption
400-kHz Fast I2C Bus
Hardware Address Pin Allows Two TCA6408A-Q1
Devices on the Same I2C/SMBus Bus
Active-Low Reset (RESET) Input
Open-Drain Active-Low Interrupt (INT) Output
Input and Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Power Up With All Channels Configured as Inputs
No Glitch On Power Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance meets 100 mA Per AEC
Q100-004
Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise Immunity at
the SCL and SDA Inputs
ESD Protection
– 2000-V Human Body Model (Q100-002)
– 1000-V Charged-Device Model (Q100-011)
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Automotive Infotainment
Advanced Drive Assistance Systems (ADAS)
Automotive Body Electronics
HEV, EV, and Power train
Industrial, Factory, and Building Automation
Test & Measurement
EPOS
3 Description
The TCA6408A-Q1 is a 16-pin device that provides 8bits of general purpose parallel input and output (I/O)
expansion for the two-line bidirectional I2C bus (or
SMBus) protocol. This device can operate with a
power supply voltage ranging from 1.65 V to 3.6 V on
both the I2C bus side (VCCI) and on the P-port side
(VCCP). This allows the TCA6408A-Q1 to interface
with
next-generation
microprocessors
and
microcontrollers on the SDA/SCL side, where supply
levels are dropping down to conserve power. In
contrast to the dropping power supplies of
microprocessors and microcontrollers, some PCB
components such as LEDs remain at a higher power
supply.
The device supports both 100-kHz (Standard-mode)
and 400-kHz (Fast-mode) clock frequencies. I/O
expanders such as the TCA6408A-Q1 provide a
simple solution when additional I/Os are needed for
switches, sensors, push-buttons, LEDs, fans, and so
forth.
Device Information(1)
PART NUMBER
TCA6408A-Q1
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCCI
I2C or SMBus Master
(e.g. Processor)
VCCP
SDA
P0
SCL
P1
INT
P2
RESET
P3
TCA6408A-Q1
P4
Peripheral
Devices
x
x
x
x
RESET, EN or
Control Inputs
INT or status
outputs
LEDs
Keypad
P5
P6
P7
ADDR
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA6408A-Q1
SCPS234 – SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
6
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Reset Timing Requirements .....................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Map...........................................................
18
19
19
23
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application .................................................. 26
10 Power Supply Recommendations ..................... 29
10.1 Power-On Reset Requirements ........................... 29
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
Parameter Measurement Information ................ 11
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagrams ..................................... 16
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
2
DATE
REVISION
NOTES
September 2016
*
Initial release.
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
VCCI
ADDR
RESET
P0
P1
P2
P3
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCCP
SDA
SCL
INT
P7
P6
P5
P4
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
ADDR
2
I
GND
8
—
Address input. Connect directly to VCCP or ground
Ground
INT
13
O
Interrupt output. Connect to VCCI through a pull-up resistor
P0
4
I/O
P-port input-output (push-pull design structure).
At power on, P0 is configured as an input
P1
5
I/O
P-port input-output (push-pull design structure).
At power on, P1 is configured as an input
P2
6
I/O
P-port input-output (push-pull design structure).
At power on, P2 is configured as an input
P3
7
I/O
P-port input-output (push-pull design structure).
At power on, P3 is configured as an input
P4
9
I/O
P-port input-output (push-pull design structure).
At power on, P4 is configured as an input
P5
10
I/O
P-port input-output (push-pull design structure).
At power on, P5 is configured as an input
P6
11
I/O
P-port input-output (push-pull design structure).
At power on, P6 is configured as an input
P7
12
I/O
P-port input-output (push-pull design structure).
At power on, P7 is configured as an input
RESET
3
I
Active-low reset input. Connect to VCCI through a pull-up resistor, if no active
connection is used
SCL
14
I
Serial clock bus. Connect to VCCI through a pull-up resistor
SDA
15
I/O
Serial data bus. Connect to VCCI through a pull-up resistor
VCCI
1
—
Supply voltage of I2C bus. Connect directly to the VCC of the external I2C
master. Provides voltage level translation
VCCP
16
—
Supply voltage of TCA6408A-Q1 for P-ports
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (see
(1)
)
MIN
MAX
UNIT
VCCI
Supply voltage for I2C pins
–0.5
3.6
V
VCCP
Supply voltage for P-ports
–0.5
3.6
V
VI
Input voltage (2)
–0.5
3.6
V
VO
Output voltage (2)
–0.5
3.6
V
IIK
Input clamp current
ADDR, RESET, SCL
VI < 0
±20
mA
IOK
Output clamp current
INT
VO < 0
±20
mA
P-port
VO < 0 or VO > VCCP
±20
SDA
VO < 0 or VO > VCCI
±20
Continuous output low current
P-port
VO = 0 to VCCP
50
Continuous output low current
SDA, INT
VO = 0 to VCCI
25
Continuous output high current
P-port
VO = 0 to VCCP
50
IIOK
Input/output clamp current
IOL
IOH
ICC
200
160
Continuous current through VCCI
10
Maximum junction temperature
Storage temperature
(2)
mA
Continuous current through VCCP
Tstg
(1)
mA
Continuous current through GND
Tj(MAX)
–65
mA
mA
135
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCCI
(1)
VCCP
2
SCL, SDA, INT
1.65
3.6
V
P-ports, ADDR, RESET
1.65
3.6
V
0.7 × VCCI
VCCI
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
4
UNIT
Supply voltage for P-ports
RESET
0.7 × VCCI
3.6
0.7 × VCCP
3.6
SCL, SDA, RESET
–0.5
0.3 × VCCI
ADDR, P7–P0
–0.5 0.3 × VCCP
ADDR, P7–P0
(1)
MAX
Supply voltage for I C pins
SCL, SDA
VIH
MIN
P00-P07
10
V
V
mA
For voltages applied above VCCI, and increase in ICC will result.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
P00-P07
IOL (2)
Low-level output current
INT, SDA
MAX
Tj = 65°C
25
Tj = 85°C
18
Tj = 105°C
9
Tj = 125°C
4.5
Tj = 135°C
3.5
Tj = 85°C
6
Tj = 105°C
3
Tj = 125°C
1.8
Tj = 135°C
TA
(2)
UNIT
mA
1.5
Operating free-air temperature
–40
125
°C
The values shown apply to specific junction temperature. See the Calculating Junction Temperature and Power Dissipation section on
how to calculate the junction temperature.
6.4 Thermal Information
TCA6408A-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
122
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.4
°C/W
RθJB
Junction-to-board thermal resistance
67.1
°C/W
ψJT
Junction-to-top characterization parameter
10.8
°C/W
ψJB
Junction-to-board characterization parameter
66.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range, VCCI = 1.65 V to 3.6 V (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input diode clamp voltage
MIN TYP (1)
VCCP
II = –18 mA
1.65 V to 3.6 V
VPORR
Power-on reset voltage, VCCP rising
(2)
VI = VCCP or GND, IO = 0
1.65 V to 3.6 V
VPORF
Power-on reset voltage, VCCP falling (2)
VI = VCCP or GND, IO = 0
1.65 V to 3.6 V
0.6
1.65 V
1.2
2.3 V
1.8
IOH = –8 mA
VOH
P-port high-level output voltage
IOH = –10 mA
(1)
(2)
MAX
–1.2
V
1.2
3V
2.6
3.6 V
3.3
1.65 V
1.0
2.3 V
1.7
3V
2.5
3.6 V
3.2
UNIT
1.5
1
V
V
V
All typical values are at nominal supply voltage (1.8-V, 2.5-V, or 3.3-V VCC) and TA = 25°C.
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6408A-Q1 in a reset condition until VCCP has
reached VPORR. At that time, the reset condition is released, and the TCA6408A-Q1 registers and I2C/SMBus state machine initialize to
their default states. After that, VCCP must be lowered to below VPORF and back up to the operating voltage for a power-reset cycle.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range, VCCI = 1.65 V to 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOL = 8 mA
VOL
P-port low-level output voltage
IOL = 10 mA
MIN TYP (1)
VCCP
MAX
1.65 V
0.45
2.3 V
0.25
3V
0.25
3.6 V
0.23
1.65 V
0.6
2.3 V
0.3
3V
0.25
3.6 V
SDA
IOL
VOL = 0.4 V
INT
VI = VCCI or GND
VI = VCCP or GND
IIH
P-port
VI = VCCP
1.65 V to 3.6 V
IIL
P-port
VI = GND
1.65 V to 3.6 V
Operating mode
VI = VCC or GND, I/O =
inputs,
fSCL = 400 kHz, No load
Standby mode
SCL, SDA,
P-port,
ADDR,
RESET
VI = VCC or GND, I/O =
inputs,
fSCL = 0 kHz, No load
SCL, SDA
One input at VCCI – 0.6 V,
Other inputs at VCCI or GND
ICC
(ICCI + ICCP)
ΔICCI
Additional current
in standby mode
Cio
3
mA
15
±0.1
1.65 V to 3.6 V
μA
±0.1
1
μA
1
μA
2.3 V to 3.6 V
9
36
1.65 V to 2.3 V
5
33
2.3 V to 3.6 V
1.2
10
1.65 V to 2.3 V
0.6
7
6
10
6
55
80
μA
pF
μA
1.65 V to 3.6 V
μA
RESET
RESET at VCCI – 0.6 V,
Other inputs at VCCI or GND
P-port, ADDR
One input at VCCP – 0.6 V,
Other inputs at VCCP or GND
1.65 V to 3.6 V
6
SCL
VI = VCCI or GND
1.65 V to 3.6 V
7
9
SDA
VIO = VCCI or GND
8
10.5
P-port
VIO = VCCP or GND
7
8
ΔICCP
Ci
3
1.65 V to 3.6 V
ADDR
SDA,
P-port,
ADDR,
RESET
V
0.23
SCL, SDA, RESET
II
UNIT
1.65 V to 3.6 V
pF
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 17)
MIN
MAX
UNIT
I2C BUS—STANDARD MODE
fscl
I2C clock frequency
0
2
100
4
kHz
tsch
I C clock high time
tscl
I2C clock low time
tsp
I2C spike time
tsds
I2C serial data setup time
tsdh
I2C serial data hold time
ticr
I2C input rise time
1000
ns
ticf
I2C input fall time
300
ns
300
ns
μs
4.7
0
μs
50
250
ns
0
2
ns
ns
tocf
I C output fall time, 10-pF to 400-pF bus
tbuf
I2C bus free time between Stop and Start
4.7
μs
tsts
I2C Start or repeater Start condition setup time
4.7
μs
2
tsth
I C Start or repeater Start condition hold time
4
μs
tsps
I2C Stop condition setup time
4
μs
6
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I2C Interface Timing Requirements (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 17)
MIN
MAX
UNIT
tvd(data)
Valid data time, SCL low to SDA output valid
1
μs
tvd(ack)
Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low
1
μs
I2C BUS—FAST MODE
fscl
I2C clock frequency
tsch
I2C clock high time
0.6
tscl
I2C clock low time
1.3
tsp
I2C spike time
tsds
I2C serial data setup time
tsdh
I2C serial data hold time
ticr
I2C input rise time
ticf
0
400
kHz
μs
μs
0
50
ns
100
ns
0
ns
20
300
ns
I2C input fall time
20 x (Vcc/
5.5 V)
300
ns
tocf
I2C output fall time, 10-pF to 400-pF bus
20 x (Vcc/
5.5 V)
300
ns
tbuf
I2C bus free time between Stop and Start
1.3
μs
tsts
I2C Start or repeater Start condition setup time
0.6
μs
tsth
I2C Start or repeater Start condition hold time
0.6
μs
2
tsps
I C Stop condition setup time
tvd(data)
Valid data time, SCL low to SDA output valid
0.6
1
μs
tvd(ack)
Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low
1
μs
μs
6.7 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 20)
MIN
MAX
UNIT
I2C BUS—STANDARD and FAST MODE
tW
Reset pulse duration
tREC
Reset recovery time
tRESET
Time to reset
40
ns
0
ns
600
ns
6.8 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 17)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
P-Port
INT
MIN
MAX
UNIT
2
I C BUS—STANDARD and FAST MODE
tiv
Interrupt valid time
4
tir
Interrupt reset delay time
SCL
INT
tpv
Output data valid
SCL
P7–P0
tps
Input data setup time
P-Port
SCL
0
ns
tph
Input data hold time
P-Port
SCL
300
ns
4
μs
400
ns
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6.9 Typical Characteristics
TA = 25°C (unless otherwise noted)
12
2
2.5 V
3.3 V
3.6 V
ICC - Standby Supply Current (µA)
ICC - Supply Current (µA)
1.65 V
1.8 V
10
8
6
4
2
-40
-25
-10
5
20 35 50 65
Temperature, TA (°C)
80
95
110 125
2.5 V
3.3 V
3.6 V
1.6
1.4
1.2
1
0.8
0.6
0.4
-40
-25
-10
5
D001
Figure 1. Supply Current vs Temperature
20 35 50 65
Temperature, TA (°C)
80
95
110 125
D002
Figure 2. Standby Supply Current vs Temperature
16
10
2.5 V (125qC)
3.3 V (-40qC)
3.3 V (125qC)
tr = 3 ns
tr = 150 ns
tr = 300 ns
14
ICC - Supply Current (µA)
1.8 V (-40qC)
1.8 V (125qC)
2.5 V (-40qC)
ICC - Supply Current (PA)
1.65 V
1.8 V
1.8
8
6
4
12
10
8
6
4
2
1.6
2
0
30
60
90 120 150 180 210
tr - Rise and fall time (ns)
240
270
300
Figure 3. Supply Current vs Rise and Fall Times (tr)
2.2 2.4 2.6 2.8
3
VCCP - Supply Voltage(V)
3.2
3.4
3.6
D004
25
-40qC
25qC
85qC
125qC
15
-40qC
25qC
85qC
125qC
20
IOL - Sink Current (mA)
20
IOL - Sink Current (mA)
2
Figure 4. Supply Current vs Supply Voltage
25
VCCP = 1.65 V
10
5
15
VCCP = 1.8 V
10
5
0
0
0
0.1
0.2
0.3
0.4
VOL - Output Low Voltage (V)
0.5
0.6
0
D005
Figure 5. I/O Sink Current vs Output Low Voltage
(VCCP = 1.65 V)
8
1.8
D003
0.1
0.2
0.3
0.4
VOL - Output Low Voltage (V)
0.5
0.6
D006
Figure 6. I/O Sink Current vs Output Low Voltage
(VCCP = 1.8 V)
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
25
25
-40qC
25qC
85qC
125qC
15
20
IOL - Sink Current (mA)
IOL - Sink Current (mA)
20
VCCP = 2.5 V
10
5
15
VCCP = 3.3 V
10
5
0
0
0
0.05
0.1
0.15 0.2 0.25 0.3 0.35
VOL - Output Low Voltage (V)
0.4
0.45
0.5
0
0.1
0.15
0.2
0.25
0.3
VOL - Output Low Voltage (V)
0.35
0.4
D008
Figure 8. I/O Sink Current vs Output Low Voltage
(VCCP = 3.3 V)
0.3
25
15
VOL - Output Low Voltage (V)
-40qC
25qC
85qC
125qC
20
VCCP = 3.6 V
10
5
0
0.05
0.1
0.15
0.2
0.25
0.3
VOL - Output Low Voltage (V)
0.35
VCC = 1.8 V, IOL = 1 mA
VCC = 5 V, IOL = 1 mA
0.25
0.4
VCC = 1.8 V, IOL = 10 mA
VCC = 5 V, IOL = 10 mA
0.2
0.15
0.1
0.05
0
-40
0
-25
-10
D009
Figure 9. I/O Sink Current vs Temperature
(VCCP = 3.6 V)
5
20 35 50 65 80
TA - Temperature (qC)
95
110 125
D010
Figure 10. I/O Low Voltage vs Temperature
21
18
-40qC
25qC
85qC
125qC
14
12
VCCP = 1.65 V
10
-40qC
25qC
85qC
125qC
18
IOH - Source Current (mA)
16
IOH - Source Current (mA)
0.05
D007
Figure 7. I/O Sink Current vs Output Low Voltage
(VCCP = 2.5 V)
IOL - Sink Current (mA)
-40qC
25qC
85qC
125qC
8
6
4
15
VCCP = 1.8 V
12
9
6
3
2
0
0
0
0.1
0.2
0.3
0.4
0.5
Output High Voltage VCCP - VOH (V)
0.6
0
D011
Figure 11. I/O Source Current vs Output High Voltage
(VCCP = 1.65 V)
0.1
0.2
0.3
0.4
0.5
Output High Voltage VCCP - VOH (V)
0.6
D012
Figure 12. I/O Source Current vs Output High Voltage
(VCCP = 1.8 V)
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
35
50
-40qC
25qC
85qC
125qC
25
VCCP = 2.5 V
20
15
10
5
40
35
30
VCCP = 3.3 V
25
20
15
10
5
0
0
0
0.1
0.2
0.3
0.4
0.5
Output High Voltage VCCP - VOH (V)
0.6
0
0.1
D013
0.2
0.3
0.4
0.5
Output High Voltage VCCP - VOH (V)
0.6
D014
Figure 13. I/O Source Current vs Output High Voltage
(VCCP = 2.5 V)
Figure 14. I/O Source Current vs Output High Voltage
(VCCP = 3.3 V)
50
40
-40qC
25qC
85qC
125qC
45
40
ISOURCE = -10 mA
35
30
VCCP = 1.8 V
VCCP = 5 V
35
VCCP - VOH (mV)
IOH - Source Current (mA)
-40qC
25qC
85qC
125qC
45
IOH - Source Current (mA)
IOH - Source Current (mA)
30
VCCP = 3.6 V
25
20
15
10
30
25
20
15
5
0
0
0.1
0.2
0.3
0.4
0.5
Output High Voltage VCCP - VOH (V)
0.6
-25
D015
Figure 15. I/O Source Current vs Output High Voltage
(VCCP = 3.6 V)
10
10
-40
-10
5
20 35 50 65 80
TA - Temperature (°C)
95
110 125
D015
Figure 16. I/O High Voltage vs Temperature
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7 Parameter Measurement Information
VCCI
RL = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Two Bytes for READ Input Port Register
Address
Bit 7
(MSB)
Start
Stop
Condition Condition
(S)
(P)
tscl
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Stop
Condition
(P)
tsch
0.7 ´ VCCI
SCL
0.3 ´ VCCI
ticr
tsp
ticf
tbuf
tvd
tocf
tvd
tsts
tsps
SDA
0.7 ´ VCCI
0.3 ´ VCCI
ticr
ticf
tsth
tsdh
tsds
tvd(ack)
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2
Input register port data
A.
CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
Figure 17. I2C Interface Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCCI
RL = 4.7 kW
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
0
1
0
0
0
0
AD
DR
1
A
1
2
3
4
5
6
7
8
A
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
tiv
A
tsps
A
Data
Into
Port
Address
Data 1
0.5 ´ VCCI
INT
SCL
Data 2
0.7 ´ VCCI
R/W
tiv
A
0.3 ´ VCCI
tir
0.5 ´ VCCP
Pn
0.5 ´ VCCI
INT
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
Figure 18. Interrupt Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
500 W
Pn
DUT
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
SCL
P0
A
P3
0.7 ´ VCCP
0.3 ´ VCCI
Slave
ACK
SDA
tpv
(see Note B)
Pn
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
SCL
0.7 ´ VCCI
P0
A
tps
P3
0.3 ´ VCCI
tph
Pn
0.5 ´ VCCP
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
Figure 19. P-Port Load Circuit and Timing Waveforms
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Parameter Measurement Information (continued)
VCCI
RL = 1 kW
500 W
Pn
SDA
DUT
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 ´ VCCI
tRESET
VCCP/2
RESET
tREC
tREC
tW
VCCP/2
Pn
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
I/Os are configured as inputs.
Figure 20. Reset Load Circuits and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The bidirectional voltage-level translation in the TCA6408A-Q1 is provided through VCCI. VCCI must be connected
to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6408A-Q1. The
voltage level on the P-port of the TCA6408A-Q1 is determined by VCCP.
The TCA6408A-Q1 consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity
Inversion (active high) Register. At power on, the I/Os are configured as inputs. However, the system master can
enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or
output is kept in the corresponding Input or Output Register. The polarity of the Input Port Register can be
inverted with the Polarity Inversion Register. All registers can be read by the system master.
The system master can reset the TCA6408A-Q1 in the event of a timeout or other improper operation by
asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the
I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the
part.
The TCA6408A-Q1 open-drain interrupt (INT) output is activated when any input state differs from its
corresponding Input Port Register state and is used to indicate to the system master that an input state has
changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the TCA6408A-Q1 can remain a simple slave device.
The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low
device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to
share the same I2C bus or SMBus.
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8.2 Functional Block Diagrams
INT
ADDR
13
Interrupt
Logic
LP Filter
2
14
SCL
15
SDA
V CCI
V CCP
RESET
GND
I 2C Bus
Control
Input
Filter
1
8 Bits
I/O Port
P7±P0
Write Pulse
Read Pulse
16
3
Shift
Register
Power-On
Reset
8
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All pin numbers shown are for the PW package.
All I/Os are set to inputs at reset.
Figure 21. Logic Diagram (Positive Logic)
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Functional Block Diagrams (continued)
Data From
Shift Register
Output Port
Register Data
Configuration
Register
Data From
Shift Register
V CCP
Q
D
Q1
FF
Write Configuration
Pulse
Q
D
CK Q
FF
Write Pulse
P0 to P7
CK Q
Output
Port
Register
Q2
ESD Protection Diode
Input
Port
Register
GND
Input Port
Register Data
Q
D
FF
Read Pulse
CK Q
To INT
Data From
Shift Register
Polarity
Register Data
Q
D
FF
Write Polarity Pulse
CK Q
Polarity
Inversion
Register
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On power up or reset, all registers return to default values.
Figure 22. Simplified Schematic of P0 to P7
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8.3 Feature Description
8.3.1 Voltage Translation
Table 1 shows some common supply voltage options for voltage translation between the I2C bus and the P-ports
of the TCA6408A-Q1.
Table 1. Voltage Translation
VCCI
(SCL AND SDA OF I2C MASTER)
(V)
VCCP
(P-PORT)
(V)
1.8
1.8
1.8
2.5
1.8
3.3
2.5
1.8
2.5
2.5
2.5
3.3
3.3
1.8
3.3
2.5
3.3
3.3
8.3.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 3.6 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin must not exceed the recommended levels for proper operation.
8.3.3 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur
during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to VCCP or VCCI, depending on the
application. INT must be connected to the voltage source of the device that requires the interrupt information.
8.3.4 Reset Input (RESET)
The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset
can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6408A-Q1 registers and
I2C/SMBus state machine are changed to their default state when RESET is low (0). When RESET is high (1),
the I/O levels at the P-port can be changed externally or through the master. This input requires a pull-up resistor
to VCCI, if no active connection is used. It is not recommended to assert the RESET pin during communication
with the TCA6408A-Q1. Assertion of RESET during communication can result in data corruption.
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8.4 Device Functional Modes
8.4.1 Power-On Reset (POR)
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6408A-Q1 in a reset
condition until VCCP has reached VPORR. At that time, the reset condition is released, and the TCA6408A-Q1
registers and I2C/SMBus state machine initialize to their default states. After that, VCCP must be lowered to below
VPORF and back up to the operating voltage for a power-reset cycle.
8.4.2 Powered-Up
When power has been applied to both VCCP and VCCI and a POR has taken place, the device is in a functioning
mode. The device is always ready to receive new requests via the I2C bus.
8.5 Programming
8.5.1 I2C Interface
The TCA6408A-Q1 has a standard bidirectional I2C interface that is controlled by a master device in order to be
configured or read the status of this device. Each slave on the I2C bus has a specific device address to
differentiate between other slave devices that are on the same I2C bus. Many slave devices require configuration
upon startup to set the behavior of the device. This is typically done when the master accesses internal register
maps of the slave, which have unique register addresses. A device can have one or multiple registers where
data is stored, written, or read.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I2C lines. (For further details, see the application report, I2C Pull-up Resistor Calculation
(SLVA689)). Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and
SCL lines are high after a STOP condition. See Figure 23 and Figure 24.
The following is the general procedure for a master to access a slave device:
1. If a master wants to send data to a slave:
– Master-transmitter sends a START condition and addresses the slave-receiver.
– Master-transmitter sends data to slave-receiver.
– Master-transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive or read data from a slave:
– Master-receiver sends a START condition and addresses the slave-transmitter.
– Master-receiver sends the requested register to read to slave-transmitter.
– Master-receiver receives data from the slave-transmitter.
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Programming (continued)
– Master-receiver terminates the transfer with a STOP condition.
SCL
SDA
Data Transfer
START
Condition
STOP
Condition
Figure 23. Definition of Start and Stop Conditions
SDA line stable while SCL line is high
SCL
1
0
1
0
1
0
1
0
ACK
MSB
Bit
Bit
Bit
Bit
Bit
Bit
LSB
ACK
SDA
Byte: 1010 1010 ( 0xAAh )
Figure 24. Bit Transfer
Table 2 shows the interface definition for the TCA6408A-Q1 device.
Table 2. Interface Definition
BYTE
BIT
7 (MSB)
2
6
5
4
3
2
1
0 (LSB)
I C slave address
L
H
L
L
L
L
ADDR
R/W
I/O data bus
P7
P6
P5
P4
P3
P2
P1
P0
8.5.2 Bus Transactions
Data must be sent to and received from the slave devices, and this is accomplished by reading from or writing to
registers in the slave device.
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Programming (continued)
Registers are locations in the memory of the slave which contain information, whether it be the configuration
information or some sampled data to send back to the master. The master must write information to these
registers in order to instruct the slave device to perform a task.
While it is common to have registers in I2C slaves, note that not all slave devices will have registers. Some
devices are simple and contain only 1 register, which may be written to directly by sending the register data
immediately after the slave address, instead of addressing a register. An example of a single-register device is
an 8-bit I2C switch, which is controlled via I2C commands. Since it has 1 bit to enable or disable a channel, there
is only 1 register needed, and the master merely writes the register data after the slave address, skipping the
register number.
8.5.2.1 Writes
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well
as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master
then sends the register address of the register to which it wishes to write. The slave will acknowledge again,
letting the master know it is ready. After this, the master starts sending the register data to the slave until the
master has sent all the data necessary (which is sometimes only a single byte), and the master terminates the
transmission with a STOP condition.
Figure 25 and Figure 26 show an example of writing a single byte to a slave register.
Master controls SDA line
Slave controls SDA line
Write to one register in a device
Register Address N (8 bits)
Device (Slave) Address (7 bits)
S
0
1
0
0
0
0
START
AD
DR
0
R/W=0
A
Data Byte to Register N (8 bits)
B7 B6 B5 B4 B3 B2 B1 B0
ACK
D7 D6 D5 D4 D3 D2 D1 D0
A
ACK
A
ACK
P
STOP
Figure 25. Write to Register
Master controls SDA line
Slave controls SDA line
Register Address 0x02 (8 bits)
Device (Slave) Address (7 bits)
S
0
START
1
0
0
0
0
AD
DR
0
R/W=0
A
ACK
0
0
0
0
0
0
1
0
Data Byte to Register 0x02 (8 bits)
A
D7 D6 D5 D4 D3 D2 D1 D0
ACK
A
ACK
P
STOP
Figure 26. Write to the Polarity Inversion Register
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Programming (continued)
8.5.2.2 Reads
Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave,
the master must first instruct the slave which register it wishes to read from. This is done by the master starting
off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0
(signifying a write), followed by the register address it wishes to read from. When the slave acknowledges this
register address, the master sends a START condition again, followed by the slave address with the R/W bit set
to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA
bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the
master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data.
At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for
more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the
slave to halt communications and release the bus. The master follows this up with a STOP condition.
Read transactions that are performed without writing to the address of the device and simply supply the
command byte will result in a NACK.
Figure 27 and Figure 28 show an example of reading a single byte from a slave register.
Master controls SDA line
Slave controls SDA line
Read from one register in a device
Register Address N (8 bits)
Device (Slave) Address (7 bits)
S
0
1
0
0
0
0
START
AD
DR
0
R/W=0
A
Data Byte from Register N (8 bits)
Device (Slave) Address (7 bits)
B7 B6 B5 B4 B3 B2 B1 B0
ACK
A
Sr
ACK
0
1
0
0
0
0
AD
DR
1
A
R/W=1
Repeated START
D7 D6 D5 D4 D3 D2 D1 D0 NA
ACK
NACK
P
STOP
Figure 27. Read from Register
1
SCL
2
3
4
5
6
7
R
9
Data From Port
Slave Address
S 0
SDA
1
0
0
0
AD
0 DR 1
Start
Condition
R/W
Data From Port
Data 1
A
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT is cleared
by Read from Port
INT
tiv
Stop not needed
to clear INT
tir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port Register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P-port (see Figure 27).
Figure 28. Read from Input Port Register
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8.6 Register Map
8.6.1 Device Address
The address of the TCA6408A-Q1 is shown in Figure 29.
Slave Address
0
0
1
0
Fixed
0
0 AD
DR R/W
Programmable
Figure 29. TCA6408A-Q1 Address
Table 3 shows the TCA6408A-Q1 address reference.
Table 3. Address Reference
ADDR
I2C BUS SLAVE ADDRESS
L
32 (decimal), 20 (hexadecimal)
H
33 (decimal), 21 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.6.2 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte (see
Table 4), which is stored in the Control Register in the TCA6408A-Q1. Two bits of this data byte state both the
operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that is
affected. This register can be written or read through the I2C bus. The command byte is sent only during a write
transmission. See Figure 30.
B7
B6
B5
B4
B3
B2
B0
B1
Figure 30. Control Register Bits
Table 4. Command Byte
CONTROL REGISTER BITS
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND
BYTE
(HEX)
0
0
0
0
0
0
0
0
00
Input Port
Read byte
xxxx xxxx
0
0
0
0
0
0
0
1
01
Output Port
Read/write byte
1111 1111
0
0
0
0
0
0
1
0
02
Polarity Inversion
Read/write byte
0000 0000
0
0
0
0
0
0
1
1
03
Configuration
Read/write byte
1111 1111
REGISTER
PROTOCOL
POWER-UP
DEFAULT
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8.6.3 Register Descriptions
The Input Port Register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration Register. They act only on read operation. Writes to this
register have no effect. The default value (X) is determined by the externally applied logic level. Before a read
operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port
Register will be accessed next. See Table 5.
Table 5. Register 0 (Input Port Register)
BIT
I-7
I-6
I-5
I-4
I-3
I-2
I-1
I-0
DEFAULT
X
X
X
X
X
X
X
X
The Output Port Register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration Register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See
Table 6.
Table 6. Register 1 (Output Port Register)
BIT
O-7
O-6
O-5
O-4
O-3
O-2
O-1
O-0
DEFAULT
1
1
1
1
1
1
1
1
The Polarity Inversion Register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
Register. If a bit in this register is set (written with 1), the polarity of the corresponding port pin is inverted. If a bit
in this register is cleared (written with a 0), the original polarity of the corresponding port pin is retained. See
Table 7.
Table 7. Register 2 (Polarity Inversion Register)
BIT
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N-0
DEFAULT
0
0
0
0
0
0
0
0
The Configuration Register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output. See Table 8.
Table 8. Register 3 (Configuration Register)
24
BIT
C-7
C-6
C-5
C-4
C-3
C-2
C-1
C-0
DEFAULT
1
1
1
1
1
1
1
1
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA6408A-Q1 has this device connected as a slave to an I2C master (processor), and the I2C
bus may contain any number of other slave devices. The TCA6408A-Q1 is in a remote location from the master,
placed close to the GPIOs to which the master needs to monitor or control.
A typical application of the TCA6408A-Q1 operates with a lower voltage on the master side (VCCI), and a higher
voltage on the P-port side (VCCP). The P-ports can be configured as outputs connected to inputs of devices such
as enable, reset, power select, the gate of a switch, and LEDs. The P-ports can also be configured as inputs to
receive data from interrupts, alarms, status outputs, or push buttons.
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9.2 Typical Application
Figure 31 shows an application in which the TCA6408A-Q1 can be used.
10 k
(x 4)
VCC
Master SCL
Controller
SDA
VCCP
(3.3 V)
VCCI
VCCP
SCL
100 k
(x 3)
Subsystem 1
(e.g., Alarm)
ALARM
(see Note D)
P0
SDA
INT
INT
GND
VCCI
(1.8 V)
RESET
RESET
P1
ENABLE
TCA6408A-Q1
P2
P3
P4
Keypad
P5
P6
ADDR
P7
GND
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A.
Device address configured as 0100000 for this example.
B.
P0 and P2–P4 are configured as inputs.
C.
P1 and P5–P7 are configured as outputs.
D.
Resistors are required for inputs (on P-port) that may float. If a driver to an input will never let the input float, a resistor
is not needed. Outputs (in the P-port) do not need pull-up resistors.
Figure 31. Typical Application Schematic
9.2.1 Design Requirements
9.2.1.1 Calculating Junction Temperature and Power Dissipation
When designing with the TCA6408A-Q1, it is important that the Recommended Operating Conditions not be
violated. Many of the parameters of this device are rated based on junction temperature. So junction temperature
must be calculated in order to verify that safe operation of the device is met. The basic equation for junction
temperature is shown in Equation 1.
Tj = TA + (qJA ´ Pd )
(1)
26
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Typical Application (continued)
θJA is the standard junction to ambient thermal resistance measurement of the package, as seen in Thermal
Information table. Pd is the total power dissipation of the device, and the approximation is shown in Equation 2.
(
Pd » ICC _ STATIC ´ VCC
) + å Pd _ PORT _ L + å Pd _ PORT _ H
(2)
Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the
summation of power dissipated by each port (with a different equation based on if the port is outputting high, or
outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by
the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these
transients to be small. They can easily be included in the power dissipation calculation by using Equation 3 to
calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power
dissipation.
Pd _ PORT _ L = (IOL ´ VOL )
(3)
Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the
port is the VOL of the port multiplied by the current it is sinking.
(
)
Pd _ PORT _H = IOH ´ (VCC - VOH )
(4)
Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the
port is the current sourced by the port multiplied by the voltage drop across the device (difference between VCC
and the output voltage).
9.2.1.2 Minimizing ICC When I/O is Used to Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 31. The LED acts as a diode, so when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in the Electrical Characteristics table shows how ICC increases as VIN becomes lower than VCC.
Designs that must minimize current consumption, such as battery power applications, must consider maintaining
the I/O pins greater than or equal to VCC when the LED is off.
Figure 32 shows a high-value resistor in parallel with the LED. Figure 33 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply current consumption when the LED is off.
VCC
LED
100 kΩ
VCC
Px
Figure 32. High-Value Resistor in Parallel With LED
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Typical Application (continued)
3.3 V
5V
LED
VCC
Px
Figure 33. Device Supplied by a Low Voltage
9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL as shown in Equation 5.
Rp(min) =
VCC - VOL(max)
IOL
(5)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation,
fSCL = 400 kHz) and bus capacitance, Cb as shown in Equation 6.
Rp(max) =
tr
0.8473 ´ Cb
(6)
2
The maximum bus capacitance for an I C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA6408A-Q1, Ci for
SCL or Cio for SDA, the capacitance of wires, connections, traces, and the capacitance of additional slaves on
the bus.
9.2.3 Application Curves
25
1.8
Standard-mode
Fast-mode
1.6
1.4
Rp(min) (kOhm)
Rp(max) (kOhm)
20
15
10
1.2
1
0.8
0.6
0.4
5
VCC > 2V
VCC 2 V
Standard-mode: fSCL= 100 kHz, tr = 1 µs
Fast-mode: fSCL= 400 kHz, tr= 300 nsb
Figure 34. Maximum Pull-Up Resistance (Rp(max)) vs Bus
Capacitance (C)
28
0
D008
Figure 35. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up
Reference Voltage (VCCI)
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA6408A-Q1 can be reset to its default conditions by using the
power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset.
This reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 36 and Figure 37.
VCCP
Ramp-Up
Re-Ramp-Up
Ramp-Down
tRR_GND
Time
Time to Re-Ramp
t RT
t RT
t FT
Figure 36. VCCP is Lowered Below 0.2 V and then Ramped Up to VCCP
VCCP
Ramp-Up
Ramp-Down
t RR_POR50
V IN drops below POR levels
Time
Time to Re-Ramp
t FT
t RT
Figure 37. VCCP is Lowered Below the POR Threshold, then Ramped Back Up to VCCP
Table 9 specifies the performance of the power-on reset feature for TCA6408A-Q1 for both types of power-on
reset.
Table 9. Recommended Supply Sequencing and Ramp Rates at TA = 25°C (1)
MAX
UNIT
tFT
Fall rate
PARAMETER
See Figure 36
0.1
2000
ms
tRT
Rise rate
See Figure 36
0.1
2000
ms
tRR_GND
Time to re-ramp (when VCCP drops to GND)
See Figure 36
1
μs
tRR_POR50
Time to re-ramp (when VCCP drops to VPOR_MIN – 50 mV)
See Figure 37
1
μs
VCCP_GH
Level that VCCP can glitch down from VCCP, but not cause a
functional disruption when tVCCP_GW = 1 μs
See Figure 38
VCCP_MV
The minimum voltage that VCC can glitch down to without
causing a reset (VCC_GH must not be violated)
See Figure 38
tVCCP_GW
Glitch width that does not cause a functional disruption when
tVCCP_GH = 0.5 × VCCx
See Figure 38
VPORF
Voltage trip point of POR on falling VCCP
VPORR
Voltage trip point of POR on rising VCCP
(1)
MIN
TYP
1.2
1.5
V
10
0.6
V
1
1.2
μs
V
1.5
V
Not tested. Specified by design.
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(tVCCP_GW) and height (VCCP_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 38 and Table 9 provide more
information on how to measure these specifications.
V CCP
VCCP_GH
VCCP_MV
Time
t VCCP_GW
Figure 38. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPORR / VPORF is the voltage level at which the reset condition is
released/asserted and all the registers and the I2C/SMBus state machine are initialized to their default states
(upon a release of a reset condition). The voltage that the device has a reset condition asserted or released
differs based on whether VCCP is being lowered to or from 0. Figure 39 and Table 9 provide more details on this
specification.
V CCP
V PORR
V PORF
Time
POR
Time
Figure 39. Power On Reset
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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA6408A-Q1, common PCB layout practices must be followed, but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCCI and VCCP pins, using a larger capacitor to provide
additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency
ripple. These capacitors must be placed as close to the TCA6408A-Q1 as possible. These best practices are
shown in Layout Example.
For the layout example provided in Layout Example, it is possible to fabricate a PCB with only 2 layers by using
the top layer for signal routing and the bottom layer as a split plane for power (VCCI and VCCP) and ground (GND).
However, a 4-layer board is preferable for boards with higher density signal routing. On a 4-layer PCB, it is
common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate
the other internal layer to a power plane. In a board layout using planes or split planes for power and ground,
vias are placed directly next to the surface mount component pad which needs to attach to VCCI, VCCP, or GND
and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a
signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in
Layout Example.
11.2 Layout Example
= Via to GND Plane
0402
C ap
0402
C ap
To CPU/MCU
V CCP
V CCI
AD D R
SD A
R ST
SC L
P0
IN T
TCA6408A-Q1
P1
P7
P2
P6
P3
P5
GN D
P4
Figure 40. Example Layout (PW Package)
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
32
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TCA6408AQPWRQ1
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
6408AQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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