TCA6418E
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SCPS243 – SEPTEMBER 2012
I2C CONTROLLED 18 CHANNEL GPIO EXPANDER
Check for Samples: TCA6418E
FEATURES
APPLICATIONS
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
Operating Power-Supply Voltage Range of
1.65 V to 3.6 V
18 GPIOs Configurable as Inputs or Outputs
ESD Protection Exceeds JESD 22 on NonGPIO Pins
– 2000-V Human Body Model (A114-A)
– 1000-V Charged Device Model (C101)
Low Standby (Idle) Current Consumption: 3 μA
Supports 1-MHz Fast Mode Plus I2C Bus
Open-Drain Active-Low Interrupt Output,
Asserted When Key is Pressed or Key is
Released
Selectable Debounce Time of 50 μs
Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise
Immunity at the SCL and SDA Inputs: Typical
Vhys at 1.8 V is 0.18 V
Latch-Up Performance Exceeds 200 mA Per
JESD 78, Class II
Very Small Package
– WCSP (YFP): 2 mm × 2 mm; 0.4 mm pitch
Smart Phones
PDAs
GPS Devices
MP3 Players
Digital Cameras
DESCRIPTION/ORDERING INFORMATION
The TCA6418E is a 18 channel GPIO expansion device with integrated ESD protection. It can operate from 1.65
V to 3.6 V and has 18 general purpose inputs/outputs (GPIO) that can be used via the I2C interface [serial clock
(SCL), serial data (SDA)].
The major benefit of this device is it frees up the processor from having to individually monitor changes in
multiple inputs and also frees up the GPIOs on the processor to drive other outputs.. This provides power and
bandwidth savings. The TCA6418E is also ideal for usage with processors that have limited GPIOs.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 85°C
(1)
(2)
WCSP – YFP
Tape and reel
ORDERABLE PART NUMBER
TCA6418EYFPR
TOP-SIDE MARKING
AZ2
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TCA6418E
SCPS243 – SEPTEMBER 2012
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
YFP PACKAGE
E
E
D
D
C
C
B
B
A
A
4
5
3
2
1
1
3
2
5
4
(Bump View)
(Laser Marking View)
Table 1. YFP Package Terminal Assignments
2
E
INT
GND
GPIO13
GPIO8
GPIO4
D
SCL
GPIO17
GPIO12
GPIO7
GPIO3
C
SDA
GPIO16
GPIO11
GPIO6
GPIO2
B
VCC
GPIO15
GPIO10
GND
GPIO1
A
RESET
GPIO14
GPIO9
GPIO5
GPIO0
5
4
3
2
1
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TERMINAL FUNCTIONS
TERMINAL
NO.
TYPE
DESCRIPTION
WCSP
(YFP)
NAME
A1
GPIO0
I/O
GPIO port
B1
GPIO1
I/O
GPIO port
C1
GPIO2
I/O
GPIO port
D1
GPIO3
I/O
GPIO port
E1
GPIO4
I/O
GPIO port
A2
GPIO5
I/O
GPIO port
B2
GND
-
C2
GPIO6
I/O
GPIO port
D2
GPIO7
I/O
GPIO port
E2
GPIO8
I/O
GPIO port
A3
GPIO9
I/O
GPIO port
Ground
B3
GPIO10
I/O
GPIO port
C3
GPIO11
I/O
GPIO port
D3
GPIO12
I/O
GPIO port
E3
GPIO13
I/O
GPIO port
A4
GPIO14
I/O
GPIO port
B4
GPIO15
I/O
GPIO port
C4
GPIO16
I/O
GPIO port
D4
GPIO17
I/O
GPIO port
E4
GND
–
Ground
A5
RESET
I
Active-low reset input. Connect to VCC through a pullup resistor, if no active connection is
used.
B5
VCC
Pwr
Supply voltage of 1.65 V to 3.6 V
C5
SDA
I/O
Serial data bus. Connect to VCC through a pullup resistor.
D5
SCL
I
Serial clock bus. Connect to VCC through a pullup resistor.
E5
INT
O
Active-low interrupt output. Open drain structure. Connect to VCC through a pullup resistor.
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
Output voltage range in the high or low state (2)
–0.5
4.6
VO
V
IIK
Input clamp current
VI < 0
±20
mA
IOK
Output clamp current
VO < 0
±20
mA
IOL
Continuous output Low current
IOH
Continuous output High current
Tstg
Storage temperature range
(1)
(2)
P port, SDA
INT
P port
50
VO = 0 to VCC
25
VO = 0 to VCC
mA
50
–65
150
°C
Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under RECOMMENDED
OPERATING CONDITIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
θJA
(1)
Package thermal impedance (1)
YFP package
VALUE
UNIT
98.8
°C/W
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
1.65
3.6
V
SCL, SDA, GPIO0-17, RESET
0.7 × VCC
3.6
V
Low-level input voltage
SCL, SDA, GPIO0-17, RESET
–0.5
0.3 × VCC
V
IOH
High-level output current
GPIO0-17
10
mA
IOL
Low-level output current
GPIO0-17
25
mA
TA
Operating free-air temperature
85
°C
VCC
Supply voltage
VIH
High-level input voltage
VIL
4
–40
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UNIT
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 1.65 V to 3.6 V (unless otherwise noted)
PARAMETER
VIK
Input diode clamp voltage
VPOR Power-on reset voltage
TEST CONDITIONS
VCCP
MIN
II = –18 mA
1.65 V to 3.6 V
–1.2
VI = VCCP or GND, IO = 0
1.65 V to 3.6 V
IOH = –1 mA
IOH = –8 mA
VOH
GPIO0-17 high-level output
voltage
IOH = –10 mA
IOL = 1 mA
IOL = 8 mA
VOL
GPIO0-17 low-level output
voltage
IOL = 10 mA
1.65 V
1.25
1.65 V
1.2
2.3 V
1.8
3V
2.6
1.65 V
1.1
2.3 V
1.7
3V
2.5
1.65 V
0.45
2.3 V
0.25
3V
0.25
1.65 V
0.6
2.3 V
0.3
3V
0.25
3
INT
VOL = 0.4 V
1.65 V to 3.6 V
3
II
SCL, SDA, GPIO0-17, RESET
VI = VCCI or GND; Pull-downs disabled for GPIO017
1.65 V to 3.6 V
rINT
GPIO0-17
1
fSCL = 0 kHz
CI
Cio
SCL
SDA
GPIO0-17
fSCL = 400
kHz
VIO = VCC or GND
kΩ
25
1.65 V to 3.6 V
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μA
35
1.65 V to 3.6 V
1.65 V to 3.6 V
6
8
10
12.5
5
6
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μA
13
fSCL = 1
MHz
VI = VCCI or GND
V
mA
55
VI on SDA,
GPIO0–17,
= VCC or GND,
IO = 0, I/O = inputs,
V
V
0.4
1.65 V to 3.6 V
ICC
1.4
1.65 V
VOL = 0.4 V
UNIT
V
1
SDA
IOL
TYP MAX
pF
pF
5
TCA6418E
SCPS243 – SEPTEMBER 2012
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I2C INTERFACE TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12)
STANDARD MODE
I2C BUS
MIN
MAX
100
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial data setup time
2
FAST MODE
I2C BUS
FAST MODE PLUS (FM+)
I2C BUS
MIN
MAX
0
400
0.6
4.7
250
MAX
0
1000
0
50
50
0
kHz
μs
0.5
50
100
UNIT
μs
0.26
1.3
50
MIN
ns
ns
tsdh
I C serial data hold time
ticr
I2C input rise time
1000 20 + 0.1Cb
(1)
300
0
120
ns
ns
ticf
I2C input fall time
300 20 + 0.1Cb
(1)
300
120
ns
tocf
I2C output fall time; 10 pF to 400 pF bus
300 20 + 0.1Cb
(1)
300
120
μs
2
tbuf
I C bus free time between Stop and
Start
4.7
1.3
0.5
μs
tsts
I2C Start or repeater Start condition
setup time
4.7
0.6
0.26
μs
tsth
I2C Start or repeater Start condition hold
time
4
0.6
0.26
μs
tsps
I2C Stop condition setup time
4
0.6
0.26
μs
tvd(data)
Valid data time; SCL low to SDA output
valid
1
0.9
0.45
μs
tvd(ack)
Valid data time of ACK condition; ACK
signal from SCL low to SDA (out) low
1
0.9
0.45
μs
(1)
Cb = total capacitance of one bus line in pF
RESET TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 15)
STANDARD MODE, FAST
MODE, FAST MODE PLUS
(FM+)
I2C BUS
MIN
UNIT
MAX
(1)
μs
tW
Reset pulse duration
120
tREC
Reset recovery time
120 (1)
μs
tRESET
Time to reset
120 (1)
μs
(1)
6
The GPIO debounce circuit uses each GPIO input which passes through a two-stage register circuit. Both registers are clocked by the
same clock signal, presumably free-running, with a nominal period of 50uS. When an input changes state, the new state is clocked into
the first stage on one clock transition. On the next same-direction transition, if the input state is still the same as the previously clocked
state, the signal is clocked into the second stage, and then on to the remaining circuits. Since the inputs are asynchronous to the clock,
it will take anywhere from zero to 50 μsec after the input transition to clock the signal into the first stage. Therefore, the total debounce
time may be as long as 100 μsec. Finally, to account for a slow clock, the spec further guard-banded at 120 μsec.
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SWITCHING CHARACTERISTICS
PARAMETER
tIV
FROM
GPI_INT with
Debounce Enabled
Interrupt valid time
GPI_INT with
Debounce Disabled
TO
GPIO0-17
STANDARD MODE,
FAST MODE, FAST
MODE PLUS (FM+)
I2C BUS
MIN
MAX
40
120
0
1
UNIT
μs
INT
1
μs
400
ns
tIR
Interrupt reset delay time
SCL
INT
tPV
Output data valid
SCL
GPIO0-17
tPS
Input data setup time
GPIO
SCL
0
ns
tPH
Input data hold time
GPIO
SCL
300
ns
Debounce Disabled
LOGIC DIAGRAM (POSITIVE LOGIC)
Interrupt
Control
INT
SCL
SDA
I2C Bus
Control
VCC
Power-On
Reset
Control
Registers
and FIFO
Keypad
Control
ROW0–COL9
Oscillator
(32 kHz)
RESET
At power on, the GPIOs are configured as inputs with internal 50-kΩ pulldown resistors enabled; however, the
system master can enable the GPIOs to function as inputs or outputs.
The system master can reset the TCA6418E in the event of a timeout or other improper operation by asserting a
low in the RESET input, while keeping the VCC at its operating level.
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6418E registers and
I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1),
the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor
to VCC, if no active connection is used.
The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The
RESET pin causes the same reset/initialization to occur without de-powering the part.
The open-drain interrupt (INT) output is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote input can inform the microcontroller if there is incoming data on its ports without having to communicate
via the I2C bus. Thus, the TCA6418E can remain a simple slave device.
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Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA6418E in a reset condition
until VCC reaches VPOR. At that time, the reset condition is released, and the TCA6418E registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered below 0.2 V and back up to the
operating voltage for a power-reset cycle.
Power-On Reset Requirements
In the event of a glitch or data corruption, TCA6418E can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 1 and Figure 2.
VCC
Ramp-Up
Ramp-Down
Re-Ramp-Up
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 1. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
VCC
Ramp-Down
Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 2. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 2 specifies the performance of the power-on reset feature for TCA6418E for both types of power-on reset.
Table 2. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES (1)
PARAMETER
MIN
TYP
MAX
UNIT
VCC_FT
Fall rate
See Figure 1
1
100
ms
VCC_RT
Rise rate
See Figure 1
0.01
100
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 1
0.001
ms
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 2
0.001
ms
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 3
VCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 3
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on rising VCC
1.033
1.428
V
(1)
8
1.2
V
μs
TA = –40°C to 85°C (unless otherwise noted)
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 3 and Table 2 provide more
information on how to measure these specifications.
VCC
VCC_GH
Time
VCC_GW
Figure 3. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 4 and Table 2 provide more details on this specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 4. VPOR
For proper operation of the power-on reset feature, use as directed in the figures and table above.
Interrupt Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge
(ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the
ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse.
Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the input port register.
The INT output has an open-drain structure and requires a pullup resistor to VCC depending on the application.
For more information on the interrupt output feature, see Control Register and Command Byte and Typical
Applications.
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I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high (see Figure 5). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must
not be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 6).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 5).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 7). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 5. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
Figure 6. Bit Transfer
10
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Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 7. Acknowledgment on the I2C Bus
Device Address
The address of the TCA6418E is shown in Table 3.
Table 3.
BYTE
I2C slave address
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
0
1
1
0
1
0
0
R/W
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
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Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is
stored in the control register in the TCA6418E. The command byte indicates the register that will be updated with
information. All registers can be read and written to by the system master.
Table 4 shows all the registers within this device and their descriptions. The default value in all registers is 0.
Table 4. Register Descriptions
ADDRESS
REGISTER NAME
REGISTER
DESCRIPTION
0×00
Reserved
Reserved
0×01
Reserved
Reserved
0×02
INT_STAT
Interrupt status register
0×03
Reserved
Reserved
0×04
Reserved
Reserved
0×05
Reserved
Reserved
0×06
Reserved
Reserved
0×07
Reserved
Reserved
0×08
Reserved
Reserved
0×09
Reserved
Reserved
0×0A
Reserved
Reserved
12
7
6
5
4
3
2
1
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
GPI_IN
T
N/A
0
0×0B
Reserved
Reserved
0×0C
Reserved
Reserved
0×0D
Reserved
Reserved
0×0E
Reserved
Reserved
0×0F
Reserved
Reserved
0×10
Reserved
Reserved
0×11
GPIO_INT_STAT1
GPIO interrupt status
GPIO0
0
GPIO1
0
GPIO2
0
GPIO3
0
GPIO4
0
GPIO
5
0
GPIO6
0
GPIO7
0
0×12
GPIO_INT_STAT2
GPIO interrupt status
GPIO15 GPIO14
0
0
GPIO13
0
GPIO12 GPIO11
0
0
GPIO
10
0
GPIO9
0
GPIO8
0
0×13
GPIO_INT_STAT3
GPIO interrupt status
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
0×14
GPIO_DAT_STAT1
(read twice to clear)
GPIO data status
GPIO0
0
GPIO1
0
GPIO2
0
GPIO3
0
GPIO4
0
GPIO
5
0
GPIO6
0
GPIO7
0
0×15
GPIO_DAT_STAT2
(read twice to clear)
GPIO data status
GPIO15 GPIO14
0
0
GPIO13
0
GPIO12 GPIO11
0
0
GPIO
10
0
GPIO9
0
GPIO8
0
0×16
GPIO_DAT_STAT3
(read twice to clear)
GPIO data status
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
0×17
GPIO_DAT_OUT1
GPIO data out
GPIO0
0
GPIO1
0
GPIO2
0
GPIO3
0
GPIO4
0
GPIO
5
0
GPIO6
0
GPIO7
0
0×18
GPIO_DAT_OUT2
GPIO data out
GPIO15 GPIO14
0
0
GPIO13
0
GPIO12 GPIO11
0
0
GPIO
10
0
GPIO9
0
GPIO8
0
0×19
GPIO_DAT_OUT3
GPIO data out
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
0×1A
GPIO_INT_EN1
GPIO interrupt enable
GPIO0
0
GPIO1
0
GPIO2
0
GPIO3
0
GPIO4
0
GPIO
5
0
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GPIO17 GPIO16
0
0
GPIO17 GPIO16
0
0
GPIO17 GPIO16
0
0
GPIO6
0
GPIO7
0
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Table 4. Register Descriptions (continued)
ADDRESS
REGISTER NAME
REGISTER
DESCRIPTION
0×1B
GPIO_INT_EN2
GPIO interrupt enable
0×1C
GPIO_INT_EN3
GPIO interrupt enable
0×1D
Reserved
Reserved
0×1E
Reserved
Reserved
0×1F
Reserved
Reserved
0×20
Reserved
Reserved
0×21
Reserved
Reserved
0×22
Reserved
7
6
GPIO15 GPIO14
0
0
5
GPIO13
0
4
3
GPIO12 GPIO11
0
0
2
1
0
GPIO
10
0
GPIO9
0
GPIO8
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
GPIO17 GPIO16
0
0
GPIO0
0
GPIO1
0
GPIO2
0
GPIO3
0
GPIO4
0
GPIO
5
0
GPIO6
0
GPIO7
0
GPIO15 GPIO14
0
0
GPIO13
0
GPIO12 GPIO11
0
0
GPIO
10
0
GPIO9
0
GPIO8
0
Reserved
0×23
GPIO_DIR1
GPIO data direction
0: input
1: output
0×24
GPIO_DIR2
GPIO data direction
0: input
1: output
0×25
GPIO_DIR3
GPIO data direction
0: input
1: output
0×26
GPIO_INT_LVL 1
GPIO edge/level detect
0: low
1: high
0×27
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
GPIO17 GPIO16
0
0
GPIO0
0
GPIO1
0
GPIO2
0
GPIO3
0
GPIO4
0
GPIO
5
0
GPIO6
0
GPIO7
0
GPIO_INT_LVL 2
GPIO edge/level detect
GPIO15 GPIO14
0: low
0
0
1: high
GPIO13
0
GPIO12 GPIO11
0
0
GPIO
10
0
GPIO9
0
GPIO8
0
0×28
GPIO_INT_LVL 3
GPIO edge/level detect
0: low
1: high
0×29
DEBOUNCE_DIS 1
0×2A
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
Debounce disable
0: enabled
1: disabled
GPIO0
0
GPIO1
0
GPIO2
0
GPIO3
0
GPIO4
0
GPIO
5
0
GPIO6
0
GPIO7
0
DEBOUNCE_DIS 2
Debounce disable
0: enabled
1: disabled
GPIO15 GPIO14
0
0
GPIO13
0
GPIO12 GPIO11
0
0
GPIO
10
0
GPIO9
0
GPIO8
0
0×2B
DEBOUNCE_DIS 3
Debounce disable
0: enabled
1: disabled
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
0×2C
GPIO_PULL1
GPIO pulldown
0: pulldown enabled
1: pulldown disabled
GPIO0
0
GPIO1
0
GPIO2
0
GPIO3
0
GPIO4
0
GPIO
5
0
GPIO6
0
GPIO7
0
0×2D
GPIO_PULL2
GPIO pulldown
0: pulldown enabled
1: pulldown disabled
GPIO15 GPIO14
0
0
GPIO13
0
GPIO12 GPIO11
0
0
GPIO
10
0
GPIO9
0
GPIO8
0
0×2E
GPIO_PULL3
GPIO pulldown
0: pulldown enabled
1: pulldown disabled
0×2F
Reserved
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
GPIO17 GPIO16
0
0
GPIO17 GPIO16
0
0
GPIO17 GPIO16
0
0
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Interrupt Status Register, INT_STAT (Address 0×02)
GPI_INT (BIT1) reflects the status of the INT pin. If GPI_INT is 1, INT is asserted. Write 0x02 to INT_STAT
register to clear interrupt.
GPIO Interrupt Status Registers, GPIO_INT_STAT1–3 (Address 0×11–0×13)
These registers are used to check GPIO interrupt status and are cleared on read.
GPIO Data Status Registers, GPIO_DAT_STAT1–3 (Address 0×14–0×16)
These registers show GPIO state when read for inputs and outputs.
GPIO Data Out Registers, GPIO_DAT_OUT1–3 (Address 0×17–0×19)
These registers contain GPIO data to be written to GPIO out driver; inputs are not affected. This is needed so
that the value can be written prior to being set as an output.
GPIO Interrupt Enable Registers, GPIO_INT_EN1–3 (Address 0×1A–0×1C)
These registers enable interrupts for GP inputs only.
GPIO Data Direction Registers, GPIO_DIR1–3 (Address 0×23–0×25)
A bit value of '0' in any of the unreserved bits sets the corresponding pin as an input. A '1' in any of these bits
sets the pin as an output.
GPIO Edge/Level Detect Registers, GPIO_INT_LVL1–3 (Address 0×26–0×28)
A bit value of '0' indicates that interrupt will be triggered on a high-to-low transition for the inputs in GPIO mode.
A bit value of '1' indicates that interrupt will be triggered on a low-to-high value for the inputs in GPIO mode.
Debounce Disable Registers, DEBOUNCE_DIS1–3 (Address 0×29–0×2B)
This is for pins configured as inputs. A bit value of ‘0’ in any of the unreserved bits enables the debounce while a
bit value of ‘1’ disables the debounce.
DEBOUNCE ENABLED
50 ms
GPI with INTE
50 ms
INT
VALID HIGH TRIGGER INTERRUPT
VALID LOW TRIGGER INTERRUPT
DEBOUNCE ENABLED
GPI with INTE
INT
VALID HIGH TRIGGER INTERRUPT
VALID LOW TRIGGER INTERRUPT
The reset line always has a 50-μs debounce time.
The 50 μs debounce time for inputs is the time required for the input to be stable to be noticed.
GPIO Pull Disable Register, GPIO_PULL1–3 (Address 0×2C–0×2E)
This register enables or disables pulldown registers from inputs.
14
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Bus Transactions
Data is exchanged between the master and TCA6418E through write and read commands.
Writes
Data is transmitted to the TCA6418E by sending the device address and setting the least significant bit (LSB) to
a logic 0. The command byte is sent after the address and determines which register receives the data that
follows the command byte. There is no limitation on the number of data bytes sent in one write transmission.
SCL
1
2
3
4
5
6
7
8
9
Command Byte
Slave Address
S
SDA
0
1
0
0 0
AD 0
DR
0
A 0
0
0
0
0
0
Data to Port
0
1
R/W Acknowledge
From Slave
Start Condition
0.0 A
Data 1
A
Acknowledge
From Slave
P
Acknowledge
From Slave
Write to Port
Data Out
from Port
Data Valid
tpv
Figure 8. Write to Output Port Register
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
1
0
0
0
Data to Register
Command Byte
0 AD
DR 0
A
0
0
0
0
0
0
1
1
R/W Acknowledge
From Slave
Start Condition
Data
A
A
Acknowledge
From Slave
P
Acknowledge
From Slave
Figure 9. Write to Configuration or Polarity Inversion Register
Reads
The bus master first must send the TCA6418E address with the LSB set to a logic 0. The command byte is sent
after the address and determines which register is accessed. After a restart, the device address is sent again
but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the
TCA6418E (see Figure 10 and Figure 11). Data is clocked into the register on the rising edge of the ACK clock
pulse.
Slave Address
S
0
1
0
0
0
Acknowledge
From Slave
Acknowledge
From Slave
0 AD
DR 0
A
R/W
Command Byte
A
S
Slave Address
0
1
0
0
0
0
At this moment, master transmitter
becomes master receiver, and
slave receiver becomes slave transmitter.
Acknowledge
From Slave
AD 1
DR
Data From Lower
or Upper Byte Acknowledge
of Register
From Master
Data
A
R/W
A
First Byte
Data From Upper
or Lower Byte No Acknowledge
of Register
From Master
MS
Data
LS
NA P
Last Byte
Figure 10. Read From Register
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SCL
1
2
3
4
5
6
7
8
9
Data from Port
SDA
S 0 1 0 0 0 0
AD
DR
Data 1
1 A
R/W Acknowledge
From Slave
1
Data from Port
A
Data 4
A P
Acknowledge
From Master
Acknowledge
From Master
Read From
Port
Data Into
Port
INT
tiv
tir
Figure 11. Read From Input Port Register
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TYPICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
SUPPLY CURRENT
vs
TEMPERATURE
STANDBY SUPPLY CURRENT
vs
TEMPERATURE
12
1600
11
1400
10
V CC = 3.6 V
8
1200
Supply Current, I CC (nA)
Supply Current, I CC (µA)
9
V CC = 3.3 V
7
6
V CC = 2.5 V
5
4
V CC = 1.8 V
3
2
1000
800
V CC = 3.6 V
V CC = 3.3 V
V CC = 2.5 V
600
V CC = 1.8 V
400
V CC = 1.65 V
V CC = 1.65 V
200
1
0
-40
-15
10
35
60
0
-40
85
-15
Tem perature, TA (°C)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
11
35
60
85
60
V CC = 1.65 V
10
50
9
TA = -40°C
(mA)
8
40
TA = 25°C
SINK
7
6
Sink Current, I
Supply Current, I CC (uA)
10
Tem perature, TA (°C)
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
5
4
3
2
TA = 85°C
30
20
10
1
0
0
1.6
2.0
2.4
2.8
3.2
3.6
0.0
Supply Voltage, V CC (V)
0.1
0.2
0.3
0.4
0.5
0.6
Output Low Voltage, V OL (V)
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
70
100
V CC = 1.8 V
V CC = 2.5 V
60
TA = -40°C
TA = -40°C
TA = 25°C
(mA)
50
SINK
TA = 85°C
40
Sink Current, I
Sink Current, I
SINK
(mA)
80
TA = 25°C
30
20
TA = 85°C
60
40
20
10
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.1
Output Low Voltage, V OL (V)
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
0.5
0.6
0.5
0.6
120
100
TA = -40°C
TA = -40°C
(mA)
TA = 25°C
80
Sink Current, I
SINK
TA = 85°C
SINK
(mA)
0.4
V CC = 3.6 V
V CC = 3.3 V
Sink Current, I
0.3
140
120
60
40
20
100
TA = 25°C
TA = 85°C
80
60
40
20
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
Output Low Voltage, V OL (V)
18
0.2
Output Low Voltage, V OL (V)
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
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0.1
0.2
0.3
0.4
Output Low Voltage, V OL (V)
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
I/O LOW VOLTAGE
vs
TEMPERATURE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
120
20
V CC = 1.65 V
(-mA)
15
TA = 25°C
SOURCE
V CC = 1.8 V, IOL = 10 m A
60
Source Current, I
Output Low Voltage, V OL (mV)
TA = -40°C
90
V CC = 3.3 V, IOL = 10 m A
30
V CC = 1.8 V, IOL = 1 m A
0
-40
TA = 85°C
10
5
V CC = 3.3 V, IOL = 1 m A
0
-15
10
35
60
85
0.0
0.1
Tem perature, TA (°C)
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
0.4
0.5
0.6
0.5
0.6
36
V CC = 1.8 V
V CC = 2.5 V
TA = -40°C
(-mA)
TA = -40°C
18
27
TA = 25°C
SOURCE
TA = 25°C
SOURCE
(-mA)
0.3
V CCP - V OH (V)
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
24
TA = 85°C
Source Current, I
Source Current, I
0.2
12
6
TA = 85°C
18
9
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.1
0.2
0.3
0.4
V CCP - V OH (V)
V CCP - V OH (V)
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
44
44
V CC = 3.6 V
V CC = 3.3 V
(-mA)
33
TA = 25°C
SOURCE
TA = 85°C
Source Current, I
Source Current, I
TA = -40°C
TA = 25°C
SOURCE
(-mA)
TA = -40°C
33
22
11
TA = 85°C
22
11
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.1
V CCP - V OH (V)
0.2
0.3
0.4
0.5
0.6
V CCP - V OH (V)
I/O HIGH VOLTAGE
vs
TEMPERATURE
350
300
V CC = 1.8 V, IOH = -10 m A
V CC - V OH (mV)
250
200
V CC = 3.3 V, IOH = -10 m A
150
100
50
0
-40
-15
10
35
60
85
Tem perature, TA (°C)
20
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PARAMETER MEASUREMENT INFORMATION
VCCI
RL = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Two Bytes for READ Input Port Register
(see Figure 9)
Address
Bit 7
(MSB)
Stop
Start
Condition Condition
(P)
(S)
tscl
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 ´ VCCI
SCL
0.3 ´ VCCI
ticr
tsp
ticf
tbuf
tvd
tocf
tvd
tsts
tsps
SDA
0.7 ´ VCCI
0.3 ´ VCCI
ticr
ticf
tsth
tsdh
tsds
tvd(ack)
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
2
1
I C address
2
Input register port data
A.
CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 12. I2C Interface Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
VCCI
RL = 4.7 kW
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
0
1
0
0
0
0
AD
DR
1
A
1
2
3
4
5
6
7
8
A
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
tiv
A
tsps
A
Data
Into
Port
Address
Data 1
0.5 ´ VCCI
INT
SCL
Data 2
0.7 ´ VCCI
R/W
tiv
A
0.3 ´ VCCI
tir
0.5 ´ VCCP
Pn
0.5 ´ VCCI
INT
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 13. Interrupt Load Circuit and Voltage Waveforms
22
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PARAMETER MEASUREMENT INFORMATION (continued)
500 W
Pn
DUT
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
SCL
P0
A
P3
0.7 ´ VCCP
0.3 ´ VCCI
Slave
ACK
SDA
tpv
(see Note B)
Pn
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
SCL
0.7 ´ VCCI
P0
A
tps
P3
0.3 ´ VCCI
tph
Pn
0.5 ´ VCCP
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 14. P Port Load Circuit and Timing Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
VCCI
RL = 1 kW
500 W
Pn
SDA
DUT
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 ´ VCCI
tRESET
VCCP/2
RESET
tREC
tREC
tW
VCCP/2
Pn
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
I/Os are configured as inputs.
E.
All parameters and waveforms are not applicable to all devices.
Figure 15. Reset Load Circuits and Voltage Waveforms
24
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TCA6418EYFPR
ACTIVE
DSBGA
YFP
25
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(AZ2, AZN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
