TCA9535
SCPS201E – AUGUST 2009 – REVISED MAY 2022
TCA9535 Low-Voltage 16-Bit I2C and SMBus Low-Power I/O Expander
with Interrupt Output and Configuration Registers
1 Features
•
•
•
•
•
•
•
•
•
•
•
3 Description
I2C
to Parallel port expander
Wide power supply voltage range of 1.65 V to
5V
Low standby-current consumption
Open-drain active-low interrupt output
5-V tolerant I/O ports
400-kHz Fast I2C bus
Polarity inversion register
Address by three hardware address pins for use of
up to eight devices
Latched outputs with high-current drive capability
for directly driving LEDs
Latch-up performance exceeds 100 mA per
JESD 78, class II
ESD protection exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
The TCA9535 is a 24-pin device that provides 16
bits of general purpose parallel input and output (I/O)
expansion for the two-line bidirectional I2C bus or
(SMBus) protocol. The device can operate with a
power supply voltage ranging from 1.65 V to 5.5 V.
The TCA9535 consists of two 8-bit Configuration
(input or output selection), Input Port, Output Port,
and Polarity Inversion (active-high or active-low
operation) registers. At power on, the I/Os are
configured as inputs. The system controller can
enable the I/Os as either inputs or outputs by writing
to the I/O configuration bits.
The TCA9535 is identical to the TCA9555, except that
the TCA9535 does not include the internal I/O pull-up
resistor, which requires pull-ups and pull-downs on
unused I/O pins when configured as an input and
undriven.
2 Applications
•
•
•
•
•
•
Device Information
Servers
Routers (telecom switching equipment)
Personal computers
Personal electronics (for example, gaming
consoles)
Industrial automation
Products with GPIO-limited processors
PART NUMBER
TCA9535
(1)
BODY SIZE (NOM)
TSSOP (24)
7.80 mm x 4.40 mm
SSOP (24)
6.20 mm x 5.30 mm
WQFN (24)
4.00 mm x 4.00 mm
VQFN (24)
4.00 mm x 4.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VCC
I2C or SMBus Controller
PACKAGE(1)
P00
Peripheral
Devices
SDA
P01
SCL
P02
INT
P03
x
P04
x
(e.g. Processor)
P05
P06
x
x
RESET, EN or
Control Inputs
INT or status
outputs
LEDs
Keypad
P07
TCA9535
P10
P11
P12
P13
A2
P14
A1
P15
A0
P16
GND
P17
Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9535
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SCPS201E – AUGUST 2009 – REVISED MAY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 I2C Interface Timing Requirements.............................6
6.7 Switching Characteristics............................................7
6.8 Typical Characteristics................................................ 8
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................16
7.5 Programming............................................................ 16
7.6 Register Maps...........................................................22
8 Application and Implementation.................................. 23
8.1 Application Information............................................. 23
8.2 Typical Application.................................................... 23
9 Power Supply Recommendations................................27
10 Layout...........................................................................29
10.1 Layout Guidelines................................................... 29
10.2 Layout Example...................................................... 29
11 Device and Documentation Support..........................30
11.1 Documentation Support.......................................... 30
11.2 Receiving Notification of Documentation Updates.. 30
11.3 Support Resources................................................. 30
11.4 Trademarks............................................................. 30
11.5 Electrostatic Discharge Caution.............................. 30
11.6 Glossary.................................................................. 30
12 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2016) to Revision E (May 2022)
Page
• Globally changed instances of legacy terminology to controller and target where I2C is mentioned..................1
• Changed VCC to GND on the Controlled Switch in Figure 8-1 .........................................................................23
Changes from Revision C (May 2016) to Revision D (June 2016)
Page
• Added DB package ............................................................................................................................................1
Changes from Revision B (August 2015) to Revision C (May 2016)
Page
• Added RGE package.......................................................................................................................................... 1
• Added IOL for different Tj ....................................................................................................................................4
• Deleted ΔICC spec from the Electrical Characteristics table, added ΔICC typical characteristics graph............. 5
• Changed ICC standby into different input states, with increased maximums ..................................................... 5
• Changed Cio maximum ...................................................................................................................................... 5
Changes from Revision A (September 2009) to Revision B (August 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section................................................................................................................................................................ 1
2
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1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
P10
24
P00
P01
P02
P03
P04
P05
23
22
21
20
19
1
18
2
17
Exposed
Center
Pad
3
4
16
15
5
14
6
13
7
8
9
10
11
A0
P17
P16
P15
P14
P13
12
P06
P07
GND
P10
P11
P12
INT
A1
A2
P00
P01
P02
P03
P04
P05
P06
P07
GND
A2
A1
INT
VCC
SDA
SCL
5 Pin Configuration and Functions
Figure 5-1. DB, PW (TSSOP) Package
24-Pin (Top View)
The exposed center pad, if used, must be connected as a
secondary ground or left electrically open.
Figure 5-2. RTW (WQFN), RGE (VQFN) Package
24-Pin (Top View)
Table 5-1. Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
DB, PW
RTW,
RGE
A0
21
18
Input
Address input 0. Connect directly to VCC or ground
A1
2
23
Input
Address input 1. Connect directly to VCC or ground
A2
3
24
Input
Address input 2. Connect directly to VCC or ground
GND
12
9
—
INT
1
22
Output
P00(1)
4
1
I/O
P-port I/O. Push-pull design structure. At power on, P00 is configured as an input
P01(1)
5
2
I/O
P-port I/O. Push-pull design structure. At power on, P01 is configured as an input
P02(1)
6
3
I/O
P-port I/O. Push-pull design structure. At power on, P02 is configured as an input
P03(1)
7
4
I/O
P-port I/O. Push-pull design structure. At power on, P03 is configured as an input
P04(1)
8
5
I/O
P-port I/O. Push-pull design structure. At power on, P04 is configured as an input
P05(1)
9
6
I/O
P-port I/O. Push-pull design structure. At power on, P05 is configured as an input
P06(1)
10
7
I/O
P-port I/O. Push-pull design structure. At power on, P06 is configured as an input
Ground
Interrupt output. Connect to VCC through an external pull-up resistor
P07(1)
11
8
I/O
P-port I/O. Push-pull design structure. At power on, P07 is configured as an input
P10(1)
13
10
I/O
P-port I/O. Push-pull design structure. At power on, P10 is configured as an input
P11(1)
14
11
I/O
P-port I/O. Push-pull design structure. At power on, P11 is configured as an input
P12(1)
15
12
I/O
P-port I/O. Push-pull design structure. At power on, P12 is configured as an input
P13(1)
16
13
I/O
P-port I/O. Push-pull design structure. At power on, P13 is configured as an input
P14(1)
17
14
I/O
P-port I/O. Push-pull design structure. At power on, P14 is configured as an input
P15(1)
18
15
I/O
P-port I/O. Push-pull design structure. At power on, P15 is configured as an input
P16(1)
19
16
I/O
P-port I/O. Push-pull design structure. At power on, P16 is configured as an input
P17(1)
20
17
I/O
P-port I/O. Push-pull design structure. At power on, P17 is configured as an input
SCL
22
19
Input
Serial clock bus. Connect to VCC through a pull-up resistor
SDA
23
20
Input
Serial data bus. Connect to VCC through a pull-up resistor
VCC
24
21
—
(1)
Supply voltage
If port is unused, it must be tied to either VCC or GND through a resistor of moderate value (about 10 kΩ)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6
V
voltage(2)
–0.5
6
V
–0.5
6
V
VI
Input
VO
Output voltage(2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input-output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
ICC
–50
mA
Continuous current through GND
–250
mA
Continuous current through VCC
160
mA
100
°C
150
°C
Tj(MAX) Maximum junction temperature
Tstg
(1)
(2)
Storage temperature
–65
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
MAX
5.5
V
SCL, SDA
0.7 × VCC
VCC (1)
V
A2–A0, P07–P00, P17–P10
0.7 × VCC
5.5
V
–0.5 0.3 × VCC
V
VIH
High-level input voltage
VIL
Low-level input voltage
SCL, SDA, A2–A0, P07–P00, P17–P10
IOH
High-level output current
P07–P00, P17–P10
IOL
Low-level output current(2)
IOL
Low-level output current(2)
TA
Operating free-air temperature
(1)
(2)
4
MIN
1.65
Supply voltage
P07–P00, P17–P10
INT, SDA
–10
Tj ≤ 65°C
25
Tj ≤ 85°C
18
Tj ≤ 100°C
11
Tj ≤ 85°C
6
Tj ≤ 100°C
3.5
–40
85
UNIT
mA
mA
mA
°C
For voltages applied above VCC, an increase in ICC results.
The values shown apply to specific junction temperatures, which depend on the RθJA of the package used. See the Calculating
Junction Temperature and Power Dissipation section on how to calculate the junction temperature.
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6.4 Thermal Information
TCA9535
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
ψJB
RθJC(bot)
(1)
PW
(TSSOP)
DB
(SSOP)
RTW
(WQFN)
RGE
(VQFN)
24 PINS
24 PINS
24 PINS
24 PINS
108.8
92.9
43.6
48.4
°C/W
UNIT
54
53.5
46.2
58.1
°C/W
62.8
50.4
22.1
27.1
°C/W
Junction-to-top characterization parameter
11.1
21.9
1.5
3.3
°C/W
Junction-to-board characterization parameter
62.3
50.1
22.2
27.2
°C/W
Junction-to-case (bottom) thermal resistance
N/A
N/A
10.7
15.3
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPORR
Power-on reset voltage, VCC rising
VI = VCC or GND, IO = 0
VPORF
Power-on reset voltage, VCC falling
VI = VCC or GND, IO = 0
IOH = –8 mA
VOH
P-port high-level output voltage(2)
IOH = –10 mA
II
Low-level output
current
Input leakage current
1.65 V to 5.5 V
MIN TYP(1)
MAX
–1.2
0.75
1.65 V
1.2
2.3 V
1.8
3V
2.6
4.75 V
4.1
1.65 V
1
2.3 V
1.7
3V
2.5
1.5
1
V
V
V
4.75 V
4
1.65 V to 5.5 V
3
VOL = 0.5 V
1.65 V to 5.5 V
8
VOL = 0.7 V
1.65 V to 5.5 V
10
INT
VOL = 0.4 V
1.65 V to 5.5 V
3
SCL, SDA Input
leakage
VI = VCC or GND
1.65 V to 5.5 V
±1
A2–A0 Input
leakage
VI = VCC or GND
1.65 V to 5.5 V
±1
P port(3)
UNIT
V
1.2
VOL = 0.4 V
SDA
IOL
VCC
mA
μA
IIH
Input high leakage
current
P port
VI = VCC
1.65 V to 5.5 V
1
μA
IIL
Input low leakage
current
P port
VI = GND
1.65 V to 5.5 V
–1
μA
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Operating mode
ICC
TEST CONDITIONS
VCC
MIN TYP(1)
5.5 V
22
40
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 400 kHz,
No load
3.6 V
11
30
VI = VCC, IO = 0, I/O = inputs,
fSCL = 0 kHz, No load
Quiescent current
Standby mode
VI = GND, IO = 0, I/O =
inputs,
fSCL = 0 kHz, No load
CI
Cio
(1)
(2)
(3)
MAX
2.7 V
8
19
1.95 V
5
11
5.5 V
1.5
3.9
3.6 V
0.9
2.2
2.7 V
0.6
1.8
1.95 V
0.6
1.5
5.5 V
1.5
8.7
3.6 V
0.9
4
2.7 V
0.6
3
1.95 V
0.4
2.2
Input capacitance
SCL
VI = VCC or GND
1.65 V to 5.5 V
3
8
Input-output pin
capacitance
SDA
VIO = VCC or GND
1.65 V to 5.5 V
3
9.5
P port
VIO = VCC or GND
1.65 V to 5.5 V
3.7
9.5
UNIT
μA
pF
pF
All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA = 25°C.
Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum
current of 100 mA, for a device total of 200 mA.
The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-2)
MIN
MAX
UNIT
0
100
kHz
I2C
BUS—STANDARD MODE
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
tsp
I2C
tsds
I2C serial-data setup time
tsdh
I2C
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time
tbuf
I2C
tsts
I2C start or repeated start condition setup
tsth
I2C
tsps
I2C stop condition setup
tvd(data)
Valid data time
SCL low to SDA output valid
3.45
µs
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
3.45
µs
Cb
I2C bus capacitive load
400
pF
400
kHz
clock high time
4
µs
4.7
µs
spike time
50
250
serial-data hold time
ns
0
input fall time
10-pF to 400-pF bus
bus free time between stop and start
start or repeated start condition hold
ns
ns
1000
ns
300
ns
300
ns
4.7
µs
4.7
µs
4
µs
4
µs
I2C BUS—FAST MODE
6
fscl
I2C clock frequency
tsch
I2C clock high time
0.6
µs
tscl
I2C
1.3
µs
0
clock low time
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6.6 I2C Interface Timing Requirements (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-2)
MIN
tsp
I2C spike time
tsds
I2C
tsdh
I2C serial-data hold time
ticr
I2C
MAX
50
serial-data setup time
input rise time
UNIT
ns
100
ns
0
ns
20
300
ns
20 × (VCC /
5.5 V)
300
ns
20 × (VCC /
5.5 V)
300
ns
ticf
I2C input fall time
tocf
I2C output fall time
tbuf
I2C bus free time between stop and start
1.3
µs
tsts
I2C
0.6
µs
tsth
I2C start or repeated start condition hold
0.6
µs
tsps
I2C
tvd(data)
Valid data time
SCL low to SDA output valid
0.9
µs
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
0.9
µs
Cb
I2C bus capacitive load
400
pF
10-pF to 400-pF bus
start or repeated start condition setup
stop condition setup
0.6
µs
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7-2 and Figure
7-3)
PARAMETER
tiv
Interrupt valid time
tir
Interrupt reset delay time
tpv
Output data valid; For VCC = 2.3 V–5.5 V
Output data valid; For VCC = 1.65 V–2.3 V
FROM
(INPUT)
TO
(OUTPUT)
P port
INT
SCL
INT
SCL
P port
MIN
MAX
UNIT
4
μs
4
μs
200
ns
300
ns
tps
Input data setup time
P port
SCL
150
ns
tph
Input data hold time
P port
SCL
1
μs
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6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
40
2.2
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
32
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
Vcc = 5.5V
1.8
28
24
20
16
12
8
-15
10
35
TA - Temperature (°C)
60
1.4
1.2
1
0.8
0.6
0.2
-40
85
-15
D001
Figure 6-1. Supply Current vs Temperature for Different Supply
Voltage (VCC)
10
35
TA - Temperature (°C)
60
85
D002
Figure 6-2. Standby Supply Current vs Temperature for
Different Supply Voltage (VCC)
30
30
-40qC
25qC
85qC
-40qC
25qC
85qC
25
IOL - Sink Current (mA)
25
ICC - Supply Current (µA)
Vcc = 5.5V
0.4
0
-40
20
15
10
5
20 VCC = 1.65 V
15
10
5
0
1.5
0
2
2.5
3
3.5
4
4.5
VCC - Supply Voltage (V)
5
5.5
0
0.1
D003
Figure 6-3. Supply Current vs Supply Voltage for Different
Temperature (TA)
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
D004
Figure 6-4. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 1.65 V
60
35
25
IOL - Sink Current (mA)
-40qC
25qC
85qC
30
IOL - Sink Current (mA)
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
1.6
4
VCC = 1.8 V
20
15
10
50
-40qC
25qC
85qC
40
VCC = 2.5 V
30
20
10
5
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
0
D005
Figure 6-5. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 1.8 V
8
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
2
ICC - Supply Current (µA)
ICC - Supply Current (µA)
36
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
D006
Figure 6-6. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 2.5 V
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6.8 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
70
80
-40qC
25qC
85qC
50
VCC = 3.3 V
40
30
20
10
60
VCC = 5 V
50
40
30
20
10
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
D007
Figure 6-7. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 3.3 V
0.6
0.7
D009
Figure 6-8. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 5 V
300
90
70
VOL - Output Low Voltage (V)
-40qC
25qC
85qC
80
IOL - Sink Current (mA)
-40qC
25qC
85qC
70
IOL - Sink Current (mA)
IOL - Sink Current (mA)
60
VCC = 5.5 V
60
50
40
30
20
1.8 V, 1 mA
1.8 V, 10 mA
3.3 V, 1mA
250
3.3 V, 10 mA
5 V, 1 mA
5 V, 10 mA
200
150
100
50
10
0
-40
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
Figure 6-9. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 5.5 V
10
35
TA - Temperature (°C)
60
85
D011
Figure 6-10. I/O Low Voltage vs Temperature for Different VCC
and IOL
20
25
-40qC
25qC
85qC
IOH - Source Current (mA)
IOH - Source Current (mA)
-15
D010
15
VCC = 1.65 V
10
5
0
-40qC
25qC
85qC
20
VCC = 1.8 V
15
10
5
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
D012
Figure 6-11. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.65 V
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
D013
Figure 6-12. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.8 V
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6.8 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
60
40
IOH - Source Current (mA)
35
IOH - Source Current (mA)
-40qC
25qC
85qC
30
VCC = 2.5 V
25
20
15
10
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
VCC = 3.3 V
30
20
0.7
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
D014
Figure 6-13. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 2.5 V
0.6
0.7
D015
Figure 6-14. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 3.3 V
70
80
-40qC
25qC
85qC
50
-40qC
25qC
85qC
70
IOH - Source Current (mA)
60
IOH - Source Current (mA)
40
0
0
VCC = 5 V
40
30
20
10
60
VCC = 5.5 V
50
40
30
20
10
0
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
D016
Figure 6-15. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5 V
350
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
D017
Figure 6-16. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5.5 V
400
18
1.65 V, 10 mA
2.5 V, 10 mA
3.6 V, 10 mA
5 V, 10 mA
5.5 V, 10 mA
15
1.65 V
1.8 V
2.5 V
3.3 V
5V
5.5 V
300
Delta ICC (µA)
VCC-VOH - I/O High Voltage (mV)
-40qC
25qC
85qC
10
5
250
200
150
12
9
6
3
100
50
-40
-15
10
35
TA - Temperature (°C)
60
85
0
-40
D018
Figure 6-17. VCC – VOH Voltage vs Temperature for Different VCC
10
50
-15
10
35
TA - Temperature (°C)
60
85
D019
Figure 6-18. Δ ICC vs Temperature for Different VCC (VI = VCC –
0.6 V)
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Parameter Measurement Information
A.
B.
C.
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
Figure 7-1. I2C Interface Load Circuit and Voltage Waveforms
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VCC
RL = 4.7 kΩ
DUT
INT
CL = 100 pF
(see Note A)
Interrupt Load Configuration
1
SCL
2
3
4
5
6
7
8
Data From Port
Target Address
SDA
S
1
1
1
Start
Condition
0
1 A1 A0 1
R/W
Data 1
A
Data From Port
Data 4
A
NACK From
Stop
Controller Condition
ACK From
Controller
ACK From
Target
NA P
Read From
Port
Data Into
Port
Data 2
Data 3
tph
Data 4
Data 5
tps
INT
tiv
tir
0.7 × VCC
INT
SCL
0.3 × VCC
0.7 × VCC
R/W
tiv
0.3 × VCC
tir
Data Into
0.7 × VCC
Port (Pn)
0.3 × VCC
A.
B.
C.
A
0.7 × VCC
INT
0.3 × VCC
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
Figure 7-2. Interrupt Load Circuit and Voltage Waveforms
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A.
B.
C.
D.
E.
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CL includes probe and jig capacitance.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Figure 7-3. P-Port Load Circuit and Voltage Waveforms
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7 Detailed Description
7.1 Overview
The TCA9535 device is a 16-bit I/O expander for the I2C bus and is designed for 1.65-V to 5.5-V VCC operation.
It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface.
The TCA9535 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The
system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration register
bits. The data for each input or output is kept in the corresponding Input or output register. The polarity of the
Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system
controller.
The TCA9535 open-drain interrupt ( INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system controller that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the TCA9535 can remain a simple target device.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low
current consumption.
The TCA9535 device is similar to the PCA9555, except for the removal of the internal I/O pull-up resistor, which
greatly reduces power consumption when the I/Os are held low. The TCA9535 is equivalent to the PCA9535 with
lower voltage support (down to VCC = 1.65 V), and also improved power-on-reset circuitry for different application
scenarios.
Three hardware pins (A0, A1 and A2) are used to program and vary the fixed I2C address and allow up to 8
devices to share the same I2C bus or SMBus.
7.2 Functional Block Diagram
TCA9535
INT
A0
A1
A2
SCL
SDA
1
Interrupt
Logic
LP Filter
21
2
P07-P00
3
22
23
Input
Filter
I2C Bus
Control
Shift
Register
16 Bits
I/O
Port
P17-P10
Write Pulse
VCC
GND
24
12
Read Pulse
Power-On
Reset
Pin numbers shown are for the PW package.
14
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All I/Os are set to inputs at reset.
Figure 7-1. Logic Diagram (Positive Logic)
Data From
Shift Register
Output Port
Register Data
Configuration
Register
Data From
Shift Register
D
Q
FF
Write Configuration
Pulse
VCC
Q1
D
CLK Q
Q
FF
I/O Pin
CLK Q
Write Pulse
Output Port
Register
Q2
Input Port
Register
D
Q
FF
Read Pulse
GND
Input Port
Register Data
CLK Q
To INT
Data From
Shift Register
D
Q
Polarity
Register Data
FF
Write Polarity
Pulse
CLK Q
Polarity Inversion
Register
At power-on reset, all registers return to default values.
Figure 7-2. Simplified Schematic of P-Port I/Os
7.3 Feature Description
7.3.1 5-V Tolerant I/O Ports
The TCA9535 features I/O ports, which are tolerant up to 5 V. This allows the TCA9535 to be connected to a
large array of devices. To minimize ICC, any input signals must be designed so the input voltage stays within VIH
and VIL of the device as described in the Electrical Characteristics section.
7.3.2 Hardware Address Pins
The TCA9535 features 3 hardware address pins (A0, A1, and A2). The user selects the device I2C address
by pulling each pin to either VCC or GND to signify the bit value in the address. This allows up to 8 TCA9535
devices to be on the same bus without address conflicts. See the Functional Block Diagram for the 3 address
pins. The voltage on the pins must not change while the device is powered up in order to prevent possible I2C
glitches as a result of the device address changing during a transmission. All of the pins must be tied either to
VCC or GND and cannot be left floating.
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7.3.3 Interrupt ( INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge
(ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of
changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because
of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is
transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read
independently, the interrupt caused by port 0 is not cleared by a read of port 1, or the interrupt caused by port 1
is not cleared by a read of port 0.
INT has an open-drain structure. INT requires a pull-up resistor to VCC of moderate value (typically about 10 kΩ).
7.4 Device Functional Modes
7.4.1 Power-On Reset (POR)
When power (from 0 V) is applied to VCC, an internal power-on reset circuit holds the TCA9535 in a reset
condition until VCC has reached VPORR. At that time, the reset condition is released. The TCA9535 registers and
I2C-SMBus state machine initialize to their default states. Then, VCC must be lowered to below VPORF and back
up to the operating voltage for a power-reset cycle.
7.4.2 Powered-Up
When power has been applied to VCC above VPORR, and the POR has taken place, the device is in a functioning
mode. In this state, the device is ready to accept any incoming I2C requests and is monitoring for changes on the
input ports.
7.5 Programming
7.5.1 I2C Interface
The TCA9535 has a standard bidirectional I2C interface that is controlled by a controller device in order to
be configured or read the status of this device. Each target on the I2C bus has a specific device address
to differentiate between other target devices that are on the same I2C bus. Many target devices require
configuration upon startup to set the behavior of the device. This is typically done when the controller accesses
internal register maps of the target, which have unique register addresses. A device can have one or multiple
registers where data is stored, written, or read. For more information see Understanding the I2C Bus application
report, SLVA704.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL
lines must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by
the amount of capacitance on the I2C lines. For further details, see I2C Pull-up Resistor Calculation application
report, SLVA689. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA
and SCL lines are high after a STOP condition. See Table 7-1.
Figure 7-3 and Figure 7-4 show the general procedure for a controller to access a target device:
1. If a controller wants to send data to a target:
• Controller-transmitter sends a START condition and addresses the target-receiver.
• Controller-transmitter sends data to target-receiver.
• Controller-transmitter terminates the transfer with a STOP condition.
2. If a controller wants to receive or read data from a target:
• Controller-receiver sends a START condition and addresses the target-transmitter.
• Controller-receiver sends the requested register to read to target-transmitter.
• Controller-receiver receives data from the target-transmitter.
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Controller-receiver terminates the transfer with a STOP condition.
SCL
SDA
Data Transfer
START
Condition
STOP
Condition
Figure 7-3. Definition of Start and Stop Conditions
SDA line stable while SCL line is high
SCL
1
0
1
0
1
0
1
0
ACK
MSB
Bit
Bit
Bit
Bit
Bit
Bit
LSB
ACK
SDA
Byte: 1010 1010 ( 0xAAh )
Figure 7-4. Bit Transfer
Table 7-1 shows the interface definition.
Table 7-1. Interface Definition
BYTE
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I2C target address
L
H
L
L
A2
A1
A0
R/ W
P0x I/O data bus
P07
P06
P05
P04
P03
P02
P01
P00
P1x I/O data bus
P17
P16
P15
P14
P13
P12
P11
P10
7.5.1.1 Bus Transactions
Data is exchanged between the controller and the TCA9535 through write and read commands, and this is
accomplished by reading from or writing to registers in the target device.
Registers are locations in the memory of the target which contain information, whether it be the configuration
information or some sampled data to send back to the controller. The controller must write information to these
registers in order to instruct the target device to perform a task.
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7.5.1.1.1 Writes
To write on the I2C bus, the controller sends a START condition on the bus with the address of the target, as
well as the last bit (the R/ W bit) set to 0, which signifies a write. After the target sends the acknowledge bit, the
controller then sends the register address of the register to which it wishes to write. The target acknowledges
again, letting the controller know it is ready. After this, the controller starts sending the register data to the target
until the controller has sent all the data necessary (which is sometimes only a single byte), and the controller
terminates the transmission with a STOP condition.
See the Control Register and Command Byte section to see list of the TCA9535 internal registers and a
description of each one.
Figure 7-5 shows an example of writing a single byte to a target register.
Controller controls SDA line
Target controls SDA line
Write to one register in a device
Device (Target) Address (7 bits)
S
0
1
0
0
START
A2 A1 A0
Register Address N (8 bits)
0
R/W=0
A
Data Byte to Register N (8 bits)
B7 B6 B5 B4 B3 B2 B1 B0
ACK
A
D7 D6 D5 D4 D3 D2 D1 D0
ACK
A
P
ACK STOP
Figure 7-5. Write to Register
Figure 7-6 shows the Write to the Polarity Inversion Register.
Controller controls SDA line
Target controls SDA line
Register Address 0x02 (8 bits)
Device (Target) Address (7 bits)
S
0
START
1
0
0
A2 A1 A0
0
R/W=0
A
0
0
0
0
ACK
0
1
0
Data Byte to Register 0x02 (8 bits)
0
A
D7 D6 D5 D4 D3 D2 D1 D0
ACK
A
ACK
P
STOP
Figure 7-6. Write to the Polarity Inversion Register
Figure 7-7 shows the Write to Output Port Registers.
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1
SCL
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2
3
4
5
6
7
8
9
Command Byte
Target Address
SDA
S
0
1
0
0
A2 A1 A0
0
A
0
0
0
0
0
0
Data to Port 0
1
0
A
R/W Acknowledge
From Target
Start Condition
0.7
Data to Port 1
0.0
Data 0
A 1.7
Acknowledge
From Target
Data 1
1.0
A
P
Acknowledge
From Target
Write to Port
Data Out from Port 0
tpv
Data Valid
Data Out from Port 1
tpv
Figure 7-7. Write to Output Port Registers
7.5.1.1.2 Reads
Reading from a target is very similar to writing, but requires some additional steps. In order to read from a target,
the controller must first instruct the target which register it wishes to read from. This is done by the controller
starting off the transmission in a similar fashion as the write, by sending the address with the R/ W bit equal to
0 (signifying a write), followed by the register address it wishes to read from. When the target acknowledges this
register address, the controller sends a START condition again, followed by the target address with the R/ W
bit set to 1 (signifying a read). This time, the target acknowledges the read request, and the controller releases
the SDA bus but continues supplying the clock to the target. During this part of the transaction, the controller
becomes the controller-receiver, and the target becomes the target-transmitter.
The controller continues to send out the clock pulses, but releases the SDA line so that the target can transmit
data. At the end of every byte of data, the controller sends an ACK to the target, letting the target know that it
is ready for more data. When the controller has received the number of bytes it is expecting, it sends a NACK,
signaling to the target to halt communications and release the bus. The controller follows this up with a STOP
condition.
See the Control Register and Command Byte section to see list of the TCA9535's internal registers and a
description of each one.
Figure 7-8 shows an example of reading a single byte from a target register.
Controller controls SDA line
Target controls SDA line
Read from one register in a device
Device (Target) Address (7 bits)
S
0
START
1
0
0
A2 A1 A0
Register Address N (8 bits)
0
R/W=0
A
B7 B6 B5 B4 B3 B2 B1 B0
ACK
Data Byte from Register N (8 bits)
Device (Target) Address (7 bits)
A
ACK
Sr
0
1
0
0
A2 A1 A0
Repeated START
1
R/W=1
A
D7 D6 D5 D4 D3 D2 D1 D0 NA
ACK
P
NACK
STOP
Figure 7-8. Read from Register
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
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Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus controller must not
acknowledge the data. Figure 7-9 and Figure 7-10 show two different scenarios of Read Input Port Register.
SCL
1
2
3
4
5
6
7
8
9
I0.x
SDA
S
0
0
1
0
A2 A1 A0
7
A
1
R/W
6
5
4
3
I1.x
2
1
0
A
7
6
5
4
3
Acknowledge
From Controller
Acknowledge
From Target
I0.x
2
1
0
A
7
6
5
4
3
I1.x
2
1
0
A
7
6
5
4
3
2
Acknowledge
From Controller
Acknowledge
From Controller
1
0
1
P
No Acknowledge
From Controller
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
tiv
tir
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is
valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register).
This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual
data transfer from the P port.
Figure 7-9. Read Input Port Register, Scenario 1
1
SCL
2
3
4
5
6
7
8
9
10.x
SDA
S
0
1
0
0
00
1 0A
A2 A1 A0
R/W
Acknowledge
From Target
11.x
A
10
10.x
A
11.x
03
A
Acknowledge
From Controller
Acknowledge
From Controller
tps
tph
11
1
P
Acknowledge
From Controller
No Acknowledge
From Controller
t ph
Read From Port 0
Data Into Port 0
Data 00
Data 01
t iv
Data 02
Data 03
tph
Read From Port 1
Data 11
Data 10
Data Into Port 1
Data 12
tir
INT
tiv
t iv
t ir
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is
valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register).
This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual
data transfer from the P port.
Figure 7-10. Read Input Port Register, Scenario 2
7.5.2 Device Address
Figure 7-11 shows the address byte of the TCA9535.
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R/W
Target Address
0
1
0
0 A2 A1 A0
Fixed
Programmable
Figure 7-11. TCA9535 Address
Table 7-2 shows the address reference of the TCA9535.
Table 7-2. Address Reference
INPUTS
I2C BUS TARGET ADDRESS
A2
A1
A0
L
L
L
32 (decimal), 0×20 (hexadecimal)
L
L
H
33 (decimal), 0x21 (hexadecimal)
L
H
L
34 (decimal), 0x22 (hexadecimal)
L
H
H
35 (decimal), 0x23 (hexadecimal)
H
L
L
36 (decimal), 0x24 (hexadecimal)
H
L
H
37 (decimal), 0x25 (hexadecimal)
H
H
L
38 (decimal), 0x26 (hexadecimal)
H
H
H
39 (decimal), 0x27 (hexadecimal)
The last bit of the target address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
7.5.3 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus controller sends a command byte shown
in Table 7-3 that is stored in the control register in the TCA9535. Three bits of this data byte state the operation
(read or write) and the internal register (input, output, polarity inversion, or configuration) that is affected. This
register can be written or read through the I2C bus. The command byte is sent only during a write transmission.
When a command byte has been sent, the register that was addressed continues to be accessed by reads until
a new command byte has been sent. Figure 7-12 shows the control register bits.
0
0
0
0
0
B2
B1
B0
Figure 7-12. Control Register Bits
Table 7-3. Command Byte
CONTROL REGISTER BITS
B2
B1
B0
COMMAND
BYTE (HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0
0x00
Input Port 0
Read byte
xxxx xxxx
0
0
1
0x01
Input Port 1
Read byte
xxxx xxxx
0
1
0
0x02
Output Port 0
Read-write byte
1111 1111
0
1
1
0x03
Output Port 1
Read-write byte
1111 1111
1
0
0
0x04
Polarity Inversion Port 0
Read-write byte
0000 0000
1
0
1
0x05
Polarity Inversion Port 1
Read-write byte
0000 0000
1
1
0
0x06
Configuration Port 0
Read-write byte
1111 1111
1
1
1
0x07
Configuration Port 1
Read-write byte
1111 1111
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7.6 Register Maps
7.6.1 Register Descriptions
The Input Port registers (registers 0 and 1) shown in Table 7-4 reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration Register. It only acts on
read operation. Writes to these registers have no effect. The default value, X, is determined by the externally
applied logic level.
Before a read operation, a write transmission is sent with the command byte to let the I2C device know that the
Input Port registers are accessed next.
Table 7-4. Registers 0 and 1 (Input Port Registers)
Bit
I0.7
Default
Bit
Default
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
X
X
X
X
X
X
X
X
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
X
X
X
X
X
X
X
X
The Output Port registers (registers 2 and 3) shown in Table 7-5 show the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as
inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not
the actual pin value.
Table 7-5. Registers 2 and 3 (Output Port Registers)
Bit
O0.7
Default
Bit
Default
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
1
1
1
1
1
1
1
1
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
1
1
1
1
1
1
1
1
The Polarity Inversion registers (registers 4 and 5) shown in Table 7-6 allow polarity inversion of pins defined as
inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding pin's polarity
is inverted. If a bit in this register is cleared (written with a 0), the corresponding pin's original polarity is retained.
Table 7-6. Registers 4 and 5 (Polarity Inversion Registers)
Bit
Default
Bit
Default
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
0
0
0
0
0
0
0
0
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
0
0
0
0
0
0
0
0
The Configuration registers (registers 6 and 7) shown in Table 7-7 configure the directions of the I/O pins. If a bit
in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver.
If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
Table 7-7. Registers 6 and 7 (Configuration Registers)
Bit
Default
Bit
Default
22
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
1
1
1
1
1
1
1
1
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
1
1
1
1
1
1
1
1
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
Applications of the TCA9535 has the device connected as a target to an I2C controller (processor), and the I2C
bus may contain any number of other target devices. The TCA9535 is typically in a remote location from the
controller, placed close to the GPIOs to which the controller needs to monitor or control.
IO Expanders such as the TCA9535 are typically used for controlling LEDs (for feedback or status lights),
controlling enable or reset signals of other devices, and even reading the outputs of other devices or buttons.
8.2 Typical Application
Figure 8-1 shows an application in which the TCA9535 can be used.
Subsystem 1
(e.g., Temper ature
Sensor)
INT
V CC
(5 V)
10 k
( X 4)
VCC
SCL
Controller
SDA
INT
GND
2k
24
22
23
1
V DD
SCL
SDA
P00
P01
P02
INT
P03
4
Subsystem 2
(e.g., Counter)
100 k
(X 3)
RESET
5
A
6
7
8
ENABLE
P04
P05
9
TCA9535
10 k
( X 5)
B
GND
P06
P07
3
P10
A2
P11
2
A1
P12
P13
21
A0
P14
P15
P16
GND P17
12
10
11
13
14
15
16
17
18
19
20
Controlled Switch
(e.g., CBT Device)
ALARM
Keypad
Subsystem 3
(e.g., Alarm)
Device address is configured as 0100100 for this example.
P00, P02, and P03 are configured as outputs.
P01, P04–P07, and P10–P17 are configured as inputs.
Pin numbers shown are for the PW package.
Figure 8-1. Application Schematic
8.2.1 Design Requirements
The designer must take into consideration the system, to be sure not to violate any of the parameters. Table 8-1
shows some key parameters which must not be violated.
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Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
I2C and Subsystem Voltage (VCC)
5V
Output current rating, P-port
sinking (IOL)
25 mA
I2C bus clock (SCL) speed
400 kHz
8.2.1.1 Calculating Junction Temperature and Power Dissipation
When designing with this device, it is important that the Recommended Operating Conditions not be violated.
Many of the parameters of this device are rated based on junction temperature. So junction temperature must be
calculated in order to verify that safe operation of the device is met. The basic equation for junction temperature
is shown in Equation 1.
Tj = TA + (qJA ´ Pd )
(1)
θJA is the standard junction to ambient thermal resistance measurement of the package, as seen in Thermal
Information table. Pd is the total power dissipation of the device, and the approximation is shown in Equation 2.
(
Pd » ICC _ STATIC ´ VCC
) + å Pd _ PORT _ L + å Pd _ PORT _ H
(2)
Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the
summation of power dissipated by each port (with a different equation based on if the port is outputting high,
or outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied
by the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these
transients to be small. They can easily be included in the power dissipation calculation by using Equation 3
to calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power
dissipation.
Pd _ PORT _ L = (IOL ´ VOL )
(3)
Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the
port is the VOL of the port multiplied by the current it is sinking.
(
)
Pd _ PORT _H = IOH ´ (VCC - VOH )
(4)
Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the
port is the current sourced by the port multiplied by the voltage drop across the device (difference between VCC
and the output voltage).
8.2.1.2 Minimizing ICC When I/O is Used to Control LED
When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure
8-1. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in the Electrical Characteristics table shows how ICC increases as VIN becomes lower than VCC. For
battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when the
LED is off to minimize current consumption.
Figure 8-2 shows a high-value resistor in parallel with the LED. Figure 8-3 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply current consumption when the LED is off.
24
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VCC
LED
100 kΩ
VCC
Pn
Figure 8-2. High-Value Resistor in Parallel With LED
3.3 V
VCC
5V
LED
Pn
Figure 8-3. Device Supplied by Lower Voltage
8.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all targets on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL as shown in Equation 5.
Rp(min) =
VCC - VOL(max)
IOL
(5)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL
= 400 kHz) and bus capacitance, Cb as shown in Equation 6.
Rp(max) =
tr
0.8473 ´ Cb
(6)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA9535, Ci for SCL or
CIO for SDA, the capacitance of wires/connections/traces, and the capacitance of additional targets on the bus.
For further details, refer to I2C Pull-up Resistor Calculation application report, SLVA689.
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8.2.3 Application Curves
1.8
Standard-Mode
Fast-Mode
Minimum Pull-Up Resistance (k:)
Maximum Pull-Up Resistance (k:)
25
20
15
10
5
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
0
50
100
150 200 250 300
Bus Capacitance (pF)
350
400
450
0
0.5
D008
1
1.5 2 2.5 3 3.5 4
Pull-Up Reference Voltage (V)
4.5
5
5.5
D009
VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VCC > 2 V
Standard-mode: fSCL = 100 kHz, tr = 1 µs
Fast-mode: fSCL = 400 kHz, tr = 300 ns
Figure 8-4. Maximum Pull-Up Resistance (Rp(max))
vs Bus Capacitance (Cb)
26
VDPUX > 2 V
VDUPX