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TCA9554A
SCPS196E – DECEMBER 2010 – REVISED FEBRUARY 2017
TCA9554A Low Voltage 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt
Output and Configuration Registers
1 Features
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
3 Description
The TCA9554A is a 16-pin device that provides 8 bits
of general purpose parallel input-output (I/O)
expansion for the two-line bidirectional I2C bus (or
SMBus) protocol. The device can operate with a
power supply voltage ranging from 1.65 V to 5.5 V.
The device supports both 100-kHz (Standard-mode)
and 400-kHz (Fast-mode) clock frequencies. I/O
expanders such as the TCA9554A provide a simple
solution when additional I/Os are needed for
switches, sensors, push-buttons, LEDs, fans, and
other similar devices.
2
I C to Parallel Port Expander
Open-Drain Active-Low Interrupt Output
Operating Power-Supply Voltage Range of 1.65 V
to 5.5 V
5-V Tolerant I/O Ports
400-kHz Fast I2C Bus
Three Hardware Address Pins Allow up to Eight
Devices on the I2C/SMBus
Input and Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Low Standby Current Consumption
Power-Up With All Channels Configured as Inputs
No Glitch on Power Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
The features of the TCA9554A include an interrupt
that is generated on the INT pin whenever an input
port changes state. The A0, A1, and A2 hardware
selectable address pins allow up to eight TCA9554A
devices on the same I2C bus. The device can also be
reset to its default sate by cycling the power supply
and causing a power-on reset.
Device Information(1)
PART NUMBER
TCA9554A
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
SSOP (16)
4.90 mm × 3.90 mm
SSOP (16)
6.20 mm × 5.30 mm
SOIC (16)
7.50 mm × 10.30 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
•
•
Servers
Routers (Telecom Switching Equipment)
Personal Computers
Personal Electronics (for example: Gaming
Consoles)
Industrial Automation
Products With GPIO-Limited Processors
Simplified Block Diagram
VCC
I2C or SMBus
Master
SDA
SCL
INT
(e.g. Processor)
TCA9554A
A0
A1
A2
GND
P0
P1
P2
P3
P4
P5
P6
P7
Peripheral
Devices
• RESET,
ENABLE, or
control
inputs
• INT or
status
outputs
• LEDs
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9554A
SCPS196E – DECEMBER 2010 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
6
6
8
8
9
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 17
8.5 Programming........................................................... 17
8.6 Register Maps ......................................................... 19
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 27
10.1 Power-On Reset Requirements ........................... 27
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 30
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
13 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2015) to Revision E
Page
•
Added DW package. .............................................................................................................................................................. 1
•
Added Maximum junction temperature to the Absolute Maximum Ratings (1) table .............................................................. 5
•
Added IOL for different Tj to the Recommended Operating Conditions table.......................................................................... 5
•
Changed ICC standby into different input states, with increased maximums ......................................................................... 7
•
Removed ΔICC spec from the Electrical Characteristics table, added ΔICC typical characteristics graph .............................. 7
•
Changed Cio, Ci values ........................................................................................................................................................... 7
•
Clarified interrupt reset time (tir) with respect to falling edge of ACK related SCL pulse. ................................................... 12
•
Made changes to the Interrupt Output (INT) section............................................................................................................ 16
•
Made changes to the Reads section ................................................................................................................................... 22
•
Added the Calculating Junction Temperature and Power Dissipation section..................................................................... 25
•
Power on reset requirements relaxed ................................................................................................................................. 27
Changes from Revision C (May 2015) to Revision D
•
Page
Added DB package. ............................................................................................................................................................... 1
Changes from Revision B (October 2014) to Revision C
Page
•
Added standby mode current for VI = VCC test condition........................................................................................................ 7
•
Added clarification in datasheet that raising voltage above VCC on P-port I/O will result in current flow from P-port to
VCC. ...................................................................................................................................................................................... 16
2
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SCPS196E – DECEMBER 2010 – REVISED FEBRUARY 2017
Changes from Revision A (March 2012) to Revision B
Page
•
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1
•
Updated IOL PARAMETER in the Electrical Characteristics table. ........................................................................................ 6
Changes from Original (December 2010) to Revision A
Page
•
Initial release of full version .................................................................................................................................................... 1
•
Updated part number in the DESCRIPTION/ORDERING INFORMATION section. ............................................................ 14
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TCA9554A
SCPS196E – DECEMBER 2010 – REVISED FEBRUARY 2017
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5 Pin Configuration and Functions
PW, DB, DBQ, or DW Package
16-Pin TSSOP, SSOP, SOIC
Top View
VCC
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A0
1
I
Address input. Connect directly to VCC or ground
A1
2
I
Address input. Connect directly to VCC or ground
A2
3
I
Address input. Connect directly to VCC or ground
GND
8
—
Ground
INT
13
O
Interrupt output. Connect to VCC through a pull-up resistor
P0
4
I/O
P-port input-output. Push-pull design structure. At power on, P0 is configured
as an input
P1
5
I/O
P-port input-output. Push-pull design structure. At power on, P1 is configured
as an input
P2
6
I/O
P-port input-output. Push-pull design structure. At power on, P2 is configured
as an input
P3
7
I/O
P-port input-output. Push-pull design structure. At power on, P3 is configured
as an input
P4
9
I/O
P-port input-output. Push-pull design structure. At power on, P4 is configured
as an input
P5
10
I/O
P-port input-output. Push-pull design structure. At power on, P5 is configured
as an input
P6
11
I/O
P-port input-output. Push-pull design structure. At power on, P6 is configured
as an input
P7
12
I/O
P-port input-output. Push-pull design structure. At power on, P7 is configured
as an input
SCL
14
I
Serial clock bus. Connect to VCC through a pull-up resistor
SDA
15
I/O
Serial data bus. Connect to VCC through a pull-up resistor
VCC
16
—
Supply voltage
4
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SCPS196E – DECEMBER 2010 – REVISED FEBRUARY 2017
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6
V
(2)
–0.5
6
V
–0.5
6
V
VI
Input voltage
VO
Output voltage (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input-output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current through a single P-port
VO = 0 to VCC
50
mA
IOH
Continuous output high current through a single P-port
VO = 0 to VCC
–50
mA
Continuous current through GND by all P-ports, INT, and SDA
250
Continuous current through VCC by all P-ports
–160
Tj(MAX)
Maximum junction temperature
100
°C
Tstg
Storage temperature
150
°C
ICC
(1)
(2)
–65
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
VCC
SCL, SDA
VIH
High-level input voltage
A2–A0, P7–P0
SCL, SDA
VIL
IOH
Low-level input voltage
High-level output current
A2–A0, P7–P0
Low-level output current (2)
INT, SDA
ICC
TA
(1)
(2)
MAX
5.5
VCC = 1.65 V to 5.5 V
0.7 × VCC
VCC (1)
VCC = 1.65 V to 2.7 V
0.7 × VCC
5.5
VCC = 3 V to 5.5 V
0.8 × VCC
5.5
VCC = 1.65 V to 5.5 V
–0.5
0.3 × VCC
VCC = 1.65 V to 2.7 V
–0.5
0.3 × VCC
VCC = 3 V to 5.5 V
–0.5
0.2 × VCC
Any P-port, P7–P0
P00–P07, P10–P17
IOL
MIN
1.65
Supply voltage
UNIT
–10
Tj ≤ 65°C
25
Tj ≤ 85°C
18
Tj ≤ 100°C
9
Tj ≤ 85°C
6
Tj ≤ 100°C
V
V
mA
mA
3
Continuous current through GND
All P-ports P7-P0, INT, and SDA
200
Continuous current through VCC
All P-ports P7-P0
–80
Operating free-air temperature
V
–40
85
mA
°C
The SCL and SDA pins shall not be at a higher potential than the supply voltage VCC in the application, or an increase in leakage
current, II, will result.
For voltages applied above VCC, an increase in ICC will result.
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SCPS196E – DECEMBER 2010 – REVISED FEBRUARY 2017
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6.4 Thermal Information
TCA9554A
THERMAL METRIC (1)
PW (TSSOP) DBQ (SSOP)
DB (SSOP)
DW (SOIC)
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
84.7
°C/W
RθJA
Junction-to-ambient thermal resistance
122
121.7
113.2
RθJC(top)
Junction-to-case (top) thermal resistance
56.4
72.9
63.6
48
°C/W
RθJB
Junction-to-board thermal resistance
67.1
64.2
64
49.1
°C/W
ψJT
Junction-to-top characterization parameter
10.8
24.4
21.2
22.7
°C/W
ψJB
Junction-to-board characterization parameter
66.5
63.8
63.4
48.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPORR
Power-on reset voltage, VCC rising
VI = VCC or GND, IO = 0
VPORF
Power-on reset voltage, VCC falling
VI = VCC or GND, IO = 0
IOH = –8 mA
VOH
P-port high-level output voltage (2)
IOH = –10 mA
SDA (3)
II
SCL, SDA
A2–A0
–1.2
0.75
1.65 V
1.2
2.3 V
1.8
3V
2.6
4.5 V
4.1
1.65 V
1.1
2.3 V
1.7
3V
2.5
MAX
1.2
1.5
UNIT
V
1
V
V
V
4
3
11
1.65 V
8
10
2.3 V
8
13
3V
8
15
4.5 V
8
17
1.65 V
10
14
2.3 V
10
17
3V
10
20
4.5 V
10
24
VOL = 0.4 V
1.65 V to 5.5 V
3
7
VI = VCC or GND
1.65 V to 5.5 V
VOL = 0.7 V
INT
1.65 V to 5.5 V
TYP (1)
1.65 V to 5.5 V
VOL = 0.4 V
P port (4)
(5)
MIN
4.5 V
VOL = 0.5 V
IOL
VCC
mA
±1
±1
μA
IIH
P port
VI = VCC
1.65 V to 5.5 V
1
μA
IIL
P port
VI = GND
1.65 V to 5.5 V
–100
μA
(1)
(2)
(3)
(4)
(5)
6
All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA = 25°C.
Each P-port I/O configured as a high output must be externally limited to a maximum of 10 mA, and the total current sourced by all I/Os
(P-ports P7-P0) through VCC must be limited to a maximum current of 80 mA.
The SDA pin must be externally limited to a maximum of 12 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA)
through GND must be limited to a maximum current of 200 mA.
Each P-port I/O configured as a low output must be externally limited to a maximum of 25 mA, and the total current sunk by all I/Os (Pports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.
The INT pin must be externally limited to a maximum of 7 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA)
through GND must be limited to a maximum current of 200 mA.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Operating mode
TEST CONDITIONS
VI = VCC or GND, IO = 0, I/O = inputs,
fSCL = 400 kHz, no load
ICC
VI = VCC
Standby mode
I/O = inputs,
fSCL = 0 kHz
VI = GND
Ci
Cio
SCL
SDA
P port
VI = VCC or GND
VIO = VCC or GND
VCC
MIN
TYP (1)
5.5 V
34
3.6 V
15
2.7 V
9
MAX
1.95 V
5
5.5 V
1.9
3.5
3.6 V
1.1
1.8
2.7 V
1
1.6
1.95 V
0.4
1
5.5 V
0.45
0.7
3.6 V
0.3
0.6
2.7 V
0.23
0.5
1.95 V
0.23
0.5
1.65 V to 5.5 V
1.65 V to 5.5 V
3
8
5.5
9.5
8
9.5
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UNIT
μA
mA
pF
pF
7
TCA9554A
SCPS196E – DECEMBER 2010 – REVISED FEBRUARY 2017
www.ti.com
6.6 I2C Interface Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see Figure 11)
MIN
MAX
UNIT
0
100
kHz
STANDARD MODE
I2C clock frequency
fscl
tsch
2
4
2
4.7
I C clock high time
tscl
I C clock low time
tsp
I2C spike time
tsds
µs
µs
50
2
250
2
0
I C serial-data setup time
ns
ns
tsdh
I C serial-data hold time
ticr
I2C input rise time
1000
ns
ticf
I2C input fall time
300
ns
2
ns
tocf
I C output fall time
tbuf
I2C bus free time between Stop and Start
10-pF to 400-pF bus
4.7
300
µs
tsts
I2C Start or repeated Start condition setup
4.7
µs
4
µs
2
tsth
I C Start or repeated Start condition hold
2
ns
tsps
I C Stop condition setup
tvd(data)
Valid data time
SCL low to SDA output valid
4
3.45
µs
ns
tvd(ack)
Valid data time of ACK
condition
ACK signal from SCL low to
SDA (out) low
3.45
µs
Cb
I2C bus capacitive load
400
pF
400
kHz
FAST MODE
fscl
I2C clock frequency
tsch
I2C clock high time
0.6
tscl
I2C clock low time
1.3
tsp
0
µs
µs
2
50
I C spike time
2
tsds
I C serial-data setup time
tsdh
I2C serial-data hold time
ticr
I2C input rise time
ticf
I2C input fall time
tocf
I2C output fall time
ns
100
ns
0
10-pF to 400-pF bus
2
ns
20
300
ns
20 × (VDD / 5.5
V)
300
ns
20 × (VDD / 5.5
V)
300
ns
tbuf
I C bus free time between Stop and Start
1.3
µs
tsts
I2C Start or repeated Start condition setup
0.6
µs
tsth
I2C Start or repeated Start condition hold
0.6
µs
2
tsps
I C Stop condition setup
tvd(data)
Valid data time
SCL low to SDA output valid
0.9
ns
tvd(ack)
Valid data time of ACK
condition
ACK signal from SCL low to
SDA (out) low
0.9
µs
400
pF
Cb
0.6
µs
2
I C bus capacitive load
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 12 and Figure 13)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
STANDARD MODE and FAST MODE
tiv
Interrupt valid time
P port
INT
4
µs
tir
Interrupt reset delay time
SCL
INT
4
µs
tpv
Output data valid
SCL
P7–P0
350
ns
tps
Input data setup time
P port
SCL
100
ns
tph
Input data hold time
P port
SCL
1
μs
8
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6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
22
1.8
1.8 V
2.5 V
3.3 V
5V
ICC - Supply Current (µA)
18
16
1.6
ICC - Supply Current (µA)
20
14
12
10
8
6
4
1.4
1.2
1
0.8
1.8 V
2.5 V
3.3 V
5V
0.6
0.4
0.2
2
0
-40
-15
10
35
TA - Free-Air Temperature (°C)
fSCL = 400 kHz
60
0
-40
85
I/Os = High or Low Inputs
fSCL = 0 kHz
Figure 1. Supply Current (ICC, Operating Mode) vs
Temperature (TA) at Four Supply Voltages
60
85
D002
I/Os = High Inputs
250
VOL - Output Low Voltage (mV)
ICC - Supply Current (µA)
10
35
TA - Free-Air Temperature (°C)
Figure 2. Supply Current (ICC, Standby Mode) vs
Temperature (TA) at Four Supply Voltages
25
20
15
10
5
0
0
0.5
1
1.5
fSCL = 400 kHz
2
2.5
3
3.5
4
VCC - Supply Voltage (V)
I/Os = High or Low
Inputs
4.5
5
200
150
100
VCC
VCC
VCC
VCC
50
0
-40
5.5
-15
D003
TA = 25°C
=
=
=
=
1.8 V, IOL = 8 mA
5 V, IOL = 8 mA
1.8 V, IOL = 10 mA
5 V, IOL = 10 mA
10
35
TA - Free-Air Temperature (°C)
60
85
D004
I/Os = High or Low
Inputs
Figure 3. Supply Current (ICC, Operating Mode) vs Supply
Voltage (VCC)
Figure 4. Output Low Voltage (VOL) vs Temperature (TA) for
P-Port I/Os
80
500
1.8 V
2.5 V
3.3 V
5V
70
60
(VCC - VOH) - Output High Voltage (mV)
IOL - Output Sink Current (mA)
-15
D001
50
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
VOL - Output Low Voltage - (V)
0.7
0.8
450
400
VCC
VCC
VCC
VCC
=
=
=
=
1.8 V, IOH = 8 mA
5 V, IOH = 8 mA
1.65 V, IOH = 10 mA
5 V, IOH = 10 mA
350
300
250
200
150
100
50
0
-40
D005
-15
10
35
TA - Free-Air Temperature (°C)
60
85
D006
TA = 25°C
Figure 5. Sink Current (IOL) vs Output Low Voltage (VOL) for
P-Ports at Four Supply Voltages
Figure 6. Output High Voltage (VCC – VOH) vs Temperature
(TA) for P-Ports
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
6
1.8 V
2.5 V
3.3 V
5V
60
50
VOH - Output High Voltage (V)
IOH - Output Source Current (mA)
70
40
30
20
10
5
4
3
2
1
IOH = -8 mA
IOH = -10 mA
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
(VCC - VOH) - Output High Voltage (V)
0.7
0.8
0
1
TA = 25°C
6
D008
Figure 8. Output High Voltage (VOH) vs Supply Voltage (VCC)
for P-Ports
600
18
1.65 V
1.8 V
2.5 V
550
500
15
3.3 V
5V
5.5 V
450
400
Delta ICC (µA)
ICC Supply Current (PA)
5
TA = 25°C
Figure 7. Source Current (IOH) vs Output High Voltage (VOH)
for P-Ports at Four Supply Voltages
350
300
250
200
12
9
6
150
25qC
85qC
-40qC
100
50
3
0
0
1
2
3
4
5
6
Number of I/Os Held Low (#)
7
8
0
-40
D001
VCC = 5 V
Figure 9. Supply Current (ICC) vs Number of I/Os Held Low
(#)
10
2
3
4
VCC - Supply Voltage (V)
D007
-15
10
35
TA - Temperature (°C)
60
85
D019
Figure 10. Δ ICC vs Temperature for Different VCC
(VI = VCC – 0.6 V)
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7 Parameter Measurement Information
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 11. I2C Interface Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCC
RL = 4.7 kΩ
DUT
INT
CL = 100 pF
(see Note A)
Interupt Load Configuration
1
SCL
2
3
4
5
6
7
8
Data From Port
Slave Address
S
SDA
0
1
1
1 A2 A1 A0 1
Start
Condition
R/W
Data 1
A
Data From Port
Data 4
A
NACK From
Master
ACK From
Master
ACK From
Slave
NA P
Stop
Condition
Read From
Port
Data Into
Port
Data 1
Data 2
Data 3
tph
Data 4
Data 5
tps
INT
tiv
tir
0.7 × VCC
INT
SCL
0.3 × VCC
0.7 × VCC
R/W
tiv
A
0.3 × VCC
tir
0.7 × VCC
Data Into
Port (Pn)
0.7 × VCC
INT
0.3 × VCC
0.3 × VCC
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 12. Interrupt Load Circuit and Voltage Waveforms
12
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Parameter Measurement Information (continued)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 13. P-Port Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TCA9554A is an 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 1.65-V to 5.5-V VCC
operation. It provides general-purpose remote I/O expansion for most micro-controller families via the I2C
interface (serial clock, SCL, and serial data, SDA, pins).
The TCA9554A open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed. The INT
pin can be connected to the interrupt input of a micro-controller. By sending an interrupt signal on this line, the
remote I/O can inform the micro-controller if there is incoming data on its ports without having to communicate
via the I2C bus. Thus, the TCA9554A can remain a simple slave device. The device outputs (latched) have highcurrent drive capability for directly driving LEDs.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C slave address and allow up to
eight devices to share the same I2C bus or SMBus.
The system master can reset the TCA9554A in the event of a timeout or other improper operation by cycling the
power supply and causing a power-on reset (POR). A reset puts the registers in their default state and initializes
the I2C /SMBus state machine.
The TCA9554A consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and
Polarity Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs. However,
the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The
data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the
Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system
master.
The TCA9554A and TCA9554 are identical except for their fixed I2C address. This allows for up to 16 of these
devices (8 of each) on the same I2C/SMBus.
The TCA9554A is identical to the TCA9534A except for the addition of the internal I/O pull-up resistors, which
keeps P-ports from floating when configured as inputs.
14
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8.2 Functional Block Diagram
INT
A0
A1
A2
SCL
SDA
13
Interrupt
Logic
LP Filter
1
2
P7−P0
3
14
15
I2C Bus
Control
Input
Filter
Shift
Register
8 Bits
I/O
Port
Write Pulse
VCC
GND
16
8
Power-On
Reset
Read Pulse
Pin numbers shown are for the PW package.
Figure 14. Functional Block Diagram
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Functional Block Diagram (continued)
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
Configuration
Register
VCC
Q1
Q
D
FF
Write Configuration
Pulse
100 k
CK Q
D
Q
FF
Write Pulse
P0 to P7
CK Q
Q2
Output Port
Register
Input Port
Register
D
GND
Input Port
Register Data
Q
FF
Read Pulse
ESD Protection
Diode
CK Q
INT
Data From
Shift Register
D
Write Polarity
Pulse
CK Q
Polarity
Register Data
Q
FF
Polarity
Inversion
Register
At power-on reset, all registers return to default values.
Figure 15. Simplified Schematic Of P0 To P7
8.3 Feature Description
8.3.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak
pull-up (100 kΩ typical) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V, however it
must be noted that because of the integrated 100 kΩ pull-up resistor it may result in current flow from I/O to VCC
pin (Figure 15).
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In
this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin must not exceed the recommended levels for proper operation.
8.3.2 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of any P-port I/O configured as an input. After time tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the ports is changed back to the
original state or when data is read from the Input Port register. Resetting occurs in the read mode at the
acknowledge (ACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK clock pulse
can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after
resetting is detected and is transmitted as an interrupt on the INT pin.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register.
16
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Feature Description (continued)
The INT output has an open-drain structure and requires pull-up resistor to VCC.
8.4 Device Functional Modes
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9554A in a reset condition
until VCC has reached VPORR. At that point, the reset condition is released and the TCA9554A registers and
SMBus/I2C state machine initializes to their default states. After that, VCC must be lowered to below VPORF and
then back up to the operating voltage for a power-on reset cycle.
8.5 Programming
8.5.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 16). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA inputoutput during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must not
be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 17).
A Stop condition, a low-to-high transition on the SDA input-output while the SCL input is high, is sent by the
master (see Figure 16).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 18). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 16. Definition of Start and Stop Conditions
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Programming (continued)
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 17. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 18. Acknowledgment on I2C Bus
Table 1 shows the TCA9554A interface definition.
Table 1. Interface Definition Table
BYTE
I2C slave address
Px I/O data bus
18
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
H
H
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
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8.6 Register Maps
8.6.1 Device Address
Figure 19 shows the address byte of the TCA9554A.
Slave Address
0
1
1
1
A2
A1
A0
R/W
Hardware Selectable
Fixed
Figure 19. TCA9554A Address
Table 2 shows the address reference of the TCA9554A.
Table 2. Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
A1
A0
L
L
L
56 (decimal), 38 (hexadecimal)
L
L
H
57 (decimal), 39 (hexadecimal)
L
H
L
58 (decimal), 3A (hexadecimal)
L
H
H
59 (decimal), 3B (hexadecimal)
H
L
L
60 (decimal), 3C (hexadecimal)
H
L
H
61 (decimal), 3D (hexadecimal)
H
H
L
62 (decimal), 3E (hexadecimal)
H
H
H
63 (decimal), 3F (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
8.6.2 Control Register and Command Byte
Following the successful Acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the TCA9554A (see Figure 20). Two bits of this command byte state the operation
(read or write) and the internal register (input, output, polarity inversion or configuration) that are affected. This
register can be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent. Figure 20 shows the TCA9554A control register bits and Table 3 shows the
command byte.
0
0
0
0
0
B2
B1
B0
Figure 20. Control Register Bits
Table 3. Command Byte Table
CONTROL REGISTER BITS
B1
B0
COMMAND BYTE
(HEX)
0
0
0x00
0
1
0x01
1
0
0x02
1
1
0x03
REGISTER
PROTOCOL
POWER-UP DEFAULT
Input Port
Read byte
XXXX XXXX
Output Port
Read/write byte
1111 1111
Polarity Inversion
Read/write byte
0000 0000
Configuration
Read/write byte
1111 1111
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8.6.3 Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register is accessed next. See Table 4.
Table 4. Register 0 (Input Port Register) Table
BIT
I7
I6
I5
I4
I3
I2
I1
I0
DEFAULT
X
X
X
X
X
X
X
X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See
Table 5.
Table 5. Register 1 (Output Port Register) Table
BIT
O7
O6
O5
O4
O3
O2
O1
O0
DEFAULT
1
1
1
1
1
1
1
1
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained. See Table 6.
Table 6. Register 2 (Polarity Inversion Register) Table
BIT
N7
N6
N5
N4
N3
N2
N1
N0
DEFAULT
0
0
0
0
0
0
0
0
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output. See Table 7.
Table 7. Register 3 (Configuration Register) Table
20
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
1
1
1
1
1
1
1
1
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8.6.3.1 Bus Transactions
Data is exchanged between the master and the TCA9554A through write and read commands.
8.6.3.1.1 Writes
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well
as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master
then sends the register address of the register to which it wishes to write. The slave acknowledges again, letting
the master know it is ready. After this, the master starts sending the register data to the slave until the master
has sent all the data necessary (which is sometimes only a single byte), and the master terminates the
transmission with a STOP condition. Note that the command byte/register address does NOT automatically
increment. Writing multiple bytes during a write results in the last byte sent being stored in the register.
See the Register Descriptions section to see list of the TCA9554A's internal registers and a description of each
one.
Figure 21 shows an example of writing a single byte to a slave register.
Master controls SDA line
Slave controls SDA line
Write to one register in a device
Register Address N (8 bits)
Device (Slave) Address (7 bits)
S
0
1
1
1
START
A2 A1 A0
0
R/W=0
A
Data Byte to Register N (8 bits)
B7 B6 B5 B4 B3 B2 B1 B0
ACK
D7 D6 D5 D4 D3 D2 D1 D0
A
ACK
A
ACK
P
STOP
Figure 21. Write to Register
Figure 22 shows an example of writing to the ploarity inversion register.
Master controls SDA line
Slave controls SDA line
Register Address 0x02 (8 bits)
Device (Slave) Address (7 bits)
S
0
START
1
1
1
A2 A1 A0
0
R/W=0
A
0
ACK
0
0
0
0
0
1
Data Byte to Register 0x02 (8 bits)
0
A
D7 D6 D5 D4 D3 D2 D1 D0
ACK
A
ACK
P
STOP
Figure 22. Write to the Polarity Inversion Register
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Figure 23 shows an example of writingto output port register.
SCL
1
2
3
4
5
7
8
9
Slave Address
SDA
S
0
1
1
1
Command Byte
A2
A0
Start Condition
0
R/W
A
0
0
0
0
0
Data to Port
0
0
1
Data 1
A
ACK From Slave
A
ACK From Slave
P
ACK From Slave
Write to Port
Data Out
From Port
Data 1 Valid
tpv
Figure 23. Write to Output Port Register
8.6.3.1.2 Reads
The bus master first must send the TCA9554A address with the LSB set to a logic 0 (see Figure 19 for device
address). The command byte is sent after the address and determines which register is accessed. After a restart,
the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the
command byte then is sent by the TCA9554A (see Figure 25). The command byte does not increment
automatically. If multiple bytes are read, data from the specified command byte/register is going to be
continuously read.
See the Register Descriptions section for the list of the TCA9554A's internal registers and a description of each
one.
Figure 24 shows an example of reading a single byte from a slave register.
Master controls SDA line
Slave controls SDA line
Read from one register in a device
Device (Slave) Address (7 bits)
S
0
START
1
1
1
A2 A1 A0
Register Address N (8 bits)
0
R/W=0
A
B7 B6 B5 B4 B3 B2 B1 B0
ACK
Data Byte from Register N (8 bits)
Device (Slave) Address (7 bits)
A
ACK
Sr
0
1
1
1
A2 A1 A0
Repeated START
1
R/W=1
A
D7 D6 D5 D4 D3 D2 D1 D0 NA
ACK
NACK
P
STOP
Figure 24. Read from Register
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first
byte, additional bytes may be read, but the same register specified by the command byte is read.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
22
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1
SCL
2
3
4
5
6
7
8
9
Data From Port
Slave Address
S 0
SDA
1
Start
Condition
1
1 A2 A1 A0 1
R/W
Data 1
A
Data From Port
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT
tiv
tir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 24 for these details).
Figure 25. Read Input Port Register
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA9554A has this device connected as a slave to an I2C master (processor), and the I2C
bus may contain any number of other slave devices. The TCA9554A is typically in a remote location from the
master, placed close to the GPIOs to which the master must monitor or control. IO Expanders such as the
TCA9554A are typically used for controlling LEDs (for feedback or status lights), controlling enable or reset
signals of other devices, and even reading the outputs of other devices or buttons.
9.2 Typical Application
Figure 26 shows an application in which the TCA9554A can be used.
VCC
(1)
VCC
10 kΩ
(1)
10 kΩ
VCC
15
Subsystem 1
(e.g., temperature sensor)
4
SDA
SDA
Master
Controller
2 kΩ
16
10 kΩ
P0
14
SCL
SCL
13
INT
5
INT
P2
P3
GND
INT
P1
TCA9554A
6
7
RESET
9
Subsystem 2
(e.g., counter)
P4
10
A
P5
3
A2
P6
11
P7
12
2
ENABLE
A1
1
Controlled Device
(e.g., CBT device)
B
A0
GND
ALARM
8
Subsystem 3
(e.g., alarm system)
VCC
(1)
The SCL and SDA pins must be tied directly to VCC because if SCL and SDA are tied to an auxiliary power supply
that can be powered on while VCC is powered off, then the supply current, ICC, increases as a result.
(2)
Device address is configured as 0111000 for this example.
(3)
P0, P2, and P3 are configured as outputs.
(4)
P1, P4, and P5 are configured as inputs.
(5)
P6 and P7 are not used and have internal 100-kΩ pullup resistors to protect them from floating.
Figure 26. Application Schematic
24
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Calculating Junction Temperature and Power Dissipation
When designing with this device, it is important that the Recommended Operating Conditions not be violated.
Many of the parameters of this device are rated based on junction temperature. So junction temperature must be
calculated in order to verify that safe operation of the device is met. The basic equation for junction temperature
is shown in Equation 1.
Tj = TA + (qJA ´ Pd )
(1)
θJA is the standard junction to ambient thermal resistance measurement of the package, as seen in Thermal
Information table. Pd is the total power dissipation of the device, and the approximation is shown in Equation 2.
(
Pd » ICC _ STATIC ´ VCC
) + å Pd _ PORT _ L + å Pd _ PORT _ H
(2)
Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the
summation of power dissipated by each port (with a different equation based on if the port is outputting high, or
outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by
the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these
transients to be small. They can easily be included in the power dissipation calculation by using Equation 3 to
calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power
dissipation.
Pd _ PORT _ L = (IOL ´ VOL )
(3)
Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the
port is the VOL of the port multiplied by the current it is sinking.
(
)
Pd _ PORT _H = IOH ´ (VCC - VOH )
(4)
Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the
port is the current sourced by the port multiplied by the voltage drop across the device (difference between VCC
and the output voltage).
9.2.1.2 Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 26. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a diode,
with threshold voltage VT, and when a P-port is configured as an input the LED is off but VI is a VT drop below
VCC.
For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or
equal to VCC when the P-ports are configured as input to minimize current consumption. Figure 27 shows a highvalue resistor in parallel with the LED. Figure 28 shows VCC less than the LED supply voltage by at least VT.
Both of these methods maintain the I/O VI at or above VCC and prevents additional supply current consumption
when the P-port is configured as an input and the LED is off.
The TCA9554A has an integrated 100-kΩ pull-up resistor, so there is no need for an external pull-up.
VCC
LED
100 k
VCC
LEDx
Figure 27. High-Value Resistor in Parallel With LED
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Typical Application (continued)
5V
3.3 V
VCC
LED
LEDx
Figure 28. Device Supplied by a Lower Voltage
9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL as shown in Equation 5.
VCC - VOL(max)
Rp(min) =
IOL
(5)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation,
fSCL = 400 kHz) and bus capacitance, Cb as shown in Equation 6.
tr
Rp(max) =
0.8473 ´ Cb
(6)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA9554A, Ci for SCL or
Cio for SDA, the capacitance of wires, connections, traces, and the capacitance of additional slaves on the bus.
9.2.3 Application Curves
25
1.8
Standard-mode
Fast-mode
1.6
1.4
Rp(min) (kOhm)
Rp(max) (kOhm)
20
15
10
1.2
1
0.8
0.6
0.4
5
VCC > 2V
VCC 2 V
Figure 30. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up
Reference Voltage (VCC)
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, the TCA9554A can be reset to its default conditions by using the
power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset.
This reset also happens when the device is powered on for the first time in an application.
The power-on reset is shown in Figure 31.
VCC
Ramp-Up
Ramp-Down
VCC_TRR
VCC drops below VPORF – 50 mV
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 31. VCC is Lowered Below the POR Threshold, then Ramped Back Up to VCC
Table 8 specifies the performance of the power-on reset feature for the TCA9554A.
Table 8. Recommended Supply Sequencing and Ramp Rates (1)
MIN
MAX
UNIT
VCC_FT
Fall rate
PARAMETER
See Figure 31
1
2000
ms
VCC_RT
Rise rate
See Figure 31
0.1
2000
ms
VCC_TRR
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or
when VCC drops to GND)
See Figure 31
2
VCC_GH
Level that VCCP can glitch down to, but not cause a
functional disruption when VCC_GW = 1 μs
See Figure 32
VCC_MV
The minimum voltage that VCC can glitch down to without
causing a reset (VCC_GH must not be violated)
See Figure 32
VCC_GW
Glitch width that does not cause a functional disruption when
See Figure 32
VCC_GH = 0.5 × VCC
(1)
μs
1.2
1.5
V
V
10
μs
All supply sequencing and ramp rate values are measured at TA = 25°C
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 32 and Table 8 provide more
information on how to measure these specifications.
VCC
VCC_GH
VCC_MV
Time
VCC_GW
Figure 32. Glitch Width and Glitch Height
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VPORR is critical to the power-on reset. VPORR is the voltage level at which the reset condition is released and all
the registers and the I2C/SMBus state machine are initialized to their default states. The value of power-on-reset
voltage differs based on the VCC being lowered to or from 0 (VPORR or VPORF). Figure 33 and Table 8 provide
more details on this specification.
VPORR
Figure 33. Waveform Describing VCC Voltage Level at Which Power-On-Reset Occurs
28
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SCPS196E – DECEMBER 2010 – REVISED FEBRUARY 2017
11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA9554A, common PCB layout practices must be followed but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in
the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors must be placed as close to the TCA9554A as possible. These best practices are shown in Figure 34.
For the layout example provided in Figure 34, it is possible to fabricate a PCB with only 2 layers by using the top
layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However, a 4
layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route
signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal
layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed
directly next to the surface mount component pad which needs to attach to VCC or GND and the via is connected
electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be
routed to the opposite side of the board, but this technique is not demonstrated in Figure 34.
11.2 Layout Example
LEGEND
Power or GND Plane
To I2C Master
VIA to Power Plane
VCC
VIA to GND Plane
A0
VCC
16
2
A1
SDA
15
3
A2
SCL
14
4
P0
INT
13
5
P1
P7
12
6
P2
P6
11
7
P3
P5
10
8
GND
P4
9
TCA9554A
1
To I/Os
To I/Os
By-pass/De-coupling
capacitors
GND
Figure 34. TCA9554A Layout
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TCA9554A
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• I2C Pull-up Resistor Calculation
• Maximum Clock Frequency of I2C Bus Using Repeaters
• Introduction to Logic
• Understanding the I2C Bus
• Choosing the Correct I2C Device for New Designs
• I/O Expander EVM User's Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TCA9554ADBQR
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
9554A
TCA9554ADBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TD554A
TCA9554ADWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TCA9554A
TCA9554ADWT
ACTIVE
SOIC
DW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TCA9554A
TCA9554APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PW554A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Feb-2017
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TCA9554ADBQR
SSOP
DBQ
16
2500
330.0
12.5
6.4
5.2
2.1
8.0
12.0
Q1
TCA9554ADWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
TCA9554ADWT
SOIC
DW
16
250
180.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
TCA9554APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TCA9554ADBQR
SSOP
DBQ
16
2500
340.5
338.1
20.6
TCA9554ADWR
SOIC
DW
16
2000
350.0
350.0
43.0
TCA9554ADWT
SOIC
DW
16
250
213.0
191.0
55.0
TCA9554APWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
16
1
14X .0250
[0.635]
2X
.175
[4.45]
.189-.197
[4.81-5.00]
NOTE 3
8
9
B
.150-.157
[3.81-3.98]
NOTE 4
16X .008-.012
[0.21-0.30]
.007 [0.17]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 -8
.016-.035
[0.41-0.88]
(.041 )
[1.04]
DETAIL A
TYPICAL
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
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EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
.002 MAX
[0.05]
ALL AROUND
METAL
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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