TCAN1043-Q1, TCAN1043H-Q1
TCAN1043-Q1, TCAN1043G-Q1
TCAN1043H-Q1
TCAN1043HG-Q1,
TCAN1043G-Q1
SLLSEV0E –TCAN1043HG-Q1,
NOVEMBER 2017 – REVISED
MARCH 2021
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TCAN1043xx-Q1 Low-Power Fault Protected CAN Transceiver with CAN FD and Wake
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
12-V or 24-V System applications
Automotive and transportation
– Advanced driver assistance system (ADAS)
– Infotainment
– Cluster
– Body electronics & lighting
3 Description
The TCAN1043xx-Q1 meets the physical layer
requirements of the ISO 11898–2 (2016) High Speed
Controller Area Network (CAN) specification providing
an interface between the CAN bus and the CAN
protocol controller. These devices support both
classical CAN and CAN FD up to 2 megabits per
second (Mbps). Devices with part numbers that
include the suffix “G” are designed for CAN FD data
rates up to 5 Mbps. The TCAN1043xx-Q1 allows for
system-level
reductions
in
battery
current
consumption by selectively enabling (via the INH
output pin) the various power supplies that may be
present on a node. This allows an ultra-low-current
sleep state in which power is gated to all system
components except for the TCAN1043xx-Q1, which
remains in a low-power state monitoring the CAN bus.
Device Information
PACKAGE(1)
PART NUMBER
TCAN1043xx-Q1
(1)
BODY SIZE (NOM)
SOIC (14)
8.95 mm x 3.91 mm
VSON (14)
4.50 mm x 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VCC
VIO
3
5
VSUP
NC
11
10
VCC
VIO
TXD
1
VSUP
INH
7
WAKE
9
nFAULT
13
VSUP
WAKE
LDO
12
8
14
nSTB
EN
VCC
TRANSMIT
DOMINANT
TIME OUT
BIAS UNIT
•
AEC Q100: Qualified for automotive applications
– Temperature Grade 1: –55°C to 125°C, TA
– Device HBM classification level: ±16 kV
– Device CDM classification level: ±1500 V
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Meets the requirements of the ISO 11898-2 (2016)
All devices support classic CAN and 2 Mbps CAN
FD (flexible data rate) and "G" options support 5
Mbps
– Short and symmetrical propagation delays and
fast loop times for enhanced timing margin
– Higher data rates in loaded CAN networks
VIO Level shifting supports 2.8 V to 5.5 V
Operating modes
– Normal mode
– Standby Mode with INH output and local and
remote wake up request
– Low power sleep mode with INH output and
local and remote wake up request
Ideal passive behavior when unpowered
– Bus and logic terminals are high impedance (no
load to operating bus or application)
– Hot plug capable: power up/down glitch free
operation on bus and RXD output
Meets or exceeds EMC standard requirements
– IEC 62228-3 – 2007 compliant
– SAE J2962-2 compliant
Protection features
– IEC ESD protection of bus terminals: ±8 kV
– Bus fault protection: ±58 V (non-H variants) and
±70 V (H variants)
– Undervoltage protection on supply terminals
– Driver dominant time Out (TXD DTO): data
rates down to 9.2 kbps
– Thermal shutdown protection (TSD)
Receiver common mode input voltage: ±30 V
Typical loop delay: 110 ns
Junction temperatures from –55°C to 150°C
Available in SOIC (14) package and leadless
VSON (14) package (4.5 mm x 3.0 mm) with
improved automated optical inspection (AOI)
capability
6
CONTROL and MODE
LOGIC
Sleep Receiver
UNDER
VOLTAGE
RXD
4
WUP
Detect
OVER
TEMP
MUX
RECEIVE
DOMINANT
TIME OUT
Normal Receiver
2
GND
Copyright © 2016, Texas Instruments Incorporated
Functional Block Diagram
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 ESD Ratings IEC Specification................................... 6
7.4 Recommended Operating Conditions.........................6
7.5 Thermal Information....................................................6
7.6 Dissipation Ratings..................................................... 7
7.7 Electrical Characteristics.............................................7
7.8 Switching Characteristics..........................................10
7.9 Typical Characteristics.............................................. 12
8 Parameter Measurement Information.......................... 13
9 Detailed Description......................................................18
9.1 Overview................................................................... 18
9.2 Functional Block Diagram......................................... 18
9.3 Feature Description...................................................19
9.4 Device Functional Modes..........................................24
10 Application Information Disclaimer........................... 33
10.1 Application Information........................................... 33
10.2 Typical Application.................................................. 33
11 Power Supply Recommendations..............................36
12 Layout...........................................................................37
12.1 Layout..................................................................... 37
12.2 Layout Example...................................................... 38
13 Device and Documentation Support..........................39
13.1 Related Links.......................................................... 39
13.2 Receiving Notification of Documentation Updates..39
13.3 Community Resources............................................39
13.4 Trademarks............................................................. 39
14 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
Changes from Revision D (July 2019) to Revision E (January 2021)
Page
• Added Functional Safety to the Features list...................................................................................................... 1
Changes from Revision C (October 2018) to Revision D (July 2019)
Page
• Changed the second sentence in the CAN Bus Dominant Fault section..........................................................21
• Changed the D0014A mechanical pages ........................................................................................................ 39
Changes from Revision B (May 2018) to Revision C (October 2018)
Page
• Updated ICC dominant with bus fault ..................................................................................................................7
• Added footnote for IIH and IIL ............................................................................................................................. 7
• Changed the Under-Voltage callout in Figure 9-4 ............................................................................................24
• Added sentence: "This minimizes the current flowing into the WAKE pin..." to the last paragraph in Local
Wake Up (LWU) via WAKE Input Terminal ...................................................................................................... 29
Changes from Revision A (December 2017) to Revision B (May 2018)
Page
• Updated note 1 to: AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/
JEDEC JS-01 specification.................................................................................................................................5
• Added Note 2 To ESD Specification Table..........................................................................................................6
• Updated IEC 61000-4-2 Unpowered Contact Dicharge to ±15kV ..................................................................... 6
• Changed Max tWK_FILTER to 1.8µs.....................................................................................................................10
Changes from Revision * (November 2017) to Revision A (December 2017)
Page
• Changed status from Advance Information to Production Data .........................................................................1
2
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5 Description (continued)
When a wake-up pattern is detected on the bus or when a local wake-up is requested via the WAKE input, the
TCAN1043xx-Q1 will initiate node start-up by driving INH high. The TCAN1043xx-Q1 includes internal logic level
translation via the VIO terminal to allow for interfacing directly to 3.3 V or 5 V controllers. The device includes
many protection and diagnostic features including CAN bus line short-circuit detection and battery connection
detection. The TCAN1043xx-Q1 meets the ESD and EMC requirements of IEC 62228-3 and J2962-2 without the
need for additional protection components.
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Device Comparison Table
DEVICE NUMBER
BUS FAULT PROTECTION
MAXIMUM DATA RATE
TCAN1043-Q1
±58 V
2 Mbps
TCAN1043H-Q1
±70 V
2 Mbps
TCAN1043G-Q1
±58 V
5 Mbps
TCAN1043HG-Q1
±70 V
5 Mbps
6 Pin Configuration and Functions
TXD
1
14
nSTB
TXD
1
14
nSTB
GND
2
13
CANH
GND
2
13
CANH
12
CANL
3
12
CANL
11
NC
V
CC
RXD
4
11
VCC
3
RXD
4
VIO
5
10
VSUP
EN
6
9
WAKE
INH
7
8
nFAULT
NC
IO
5
10
EN
6
9
WAKE
INH
7
8
nFAULT
V
V
SUP
Thermal
Pad
Not to scale
Figure 6-2. DMT Package, 14 Pin (VSON), Top View
Figure 6-1. D Package, 14 Pin (SOIC), Top View
Table 6-1. Pin Functions
PINS
NAME
4
TYPE
NO
Digital Input
DESCRIPTION
TXD
1
GND
2
GND
VCC
3
Supply
RXD
4
Digital Output
VIO
5
Supply
EN
6
Digital Input
INH
7
High Voltage Output
nFAULT
8
Digital Output
WAKE
9
High Voltage Input
VSUP
10
Supply
Reverse-blocked battery supply input
NC
11
—
No connect (not internally connected)
CANL
12
Bus I/O
Low-level CAN bus input/output line
CANH
13
Bus I/O
High-level CAN bus input/output line
nSTB
14
Digital Input
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CAN transmit data input (low for dominant and high for recessive bus states)
Ground connection
5-V CAN bus supply voltage
CAN receive data output (low for dominant and high for recessive bus states), tri-state
I/O supply voltage
Enable input for mode control, integrated pull down
Can be used to control system voltage regulators
Fault output, inverted logic
Wake input terminal, high voltage input
Standby input for mode control, integrated pull down
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7 Specifications
7.1 Absolute Maximum Ratings
See (1) (2)
MIN
MAX
Battery supply (reverse-blocked) voltage range – standard versions
–0.3
58
V
Battery supply (reverse blocked) voltage range – H versions
–0.3
70
V
VCC
5-V bus supply voltage
–0.3
7
V
VIO
I/O level shifting voltage
–0.3
7
V
VSUP
UNIT
CAN bus I/O voltage range (CANH, CANL)
Devices without the "H" suffix
–58
58
V
CAN bus I/O voltage range (CANH, CANL)
Devices with the "H" suffix
–70
70
V
V(DIFF)
Max differential voltage between CANH and
CANL
Devices without the "H" suffix
–58
58
V
Devices with the "H" suffix
–70
70
V
V(Logic_Input)
Logic input terminal voltage range
–0.3
7
V
V(Logic_Output)
Logic output terminal voltage range
–0.3
7
V
VBUS
INH output pin voltage range
Devices without the "H" suffix
–0.3
58 and VO ≤ VSUP + 0.3
V
INH output pin voltage range
H versions
–0.3
70 and VO ≤ VSUP + 0.3
V
WAKE input pin voltage range
Devices without the "H" suffix
–0.3
58 and VI ≤ VSUP + 0.3
V
WAKE input pin voltage range
H versions
–0.3
70 and VI ≤ VSUP + 0.3
IO(LOGIC)
Logic output current
RXD, and nFAULT
IO(INH)
VINH
V(WAKE)
V
8
mA
INH output current
4
mA
IO(WAKE)
Wake current if due to ground shifts V(WAKE) ≤ V(GND) – 0.3 V, thus the current into WAKE
must be limited via an external serial resistor
3
mA
TJ
Operating virtual junction temperature range
150
°C
(1)
(2)
–55
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
7.2 ESD Ratings
Human body model (HBM), per AEC Q100-002
V(ESD)
Electrostatic discharge
Charged device model (CDM) - SOIC
Charged device model (CDM) - DMT
Machine model (MM)
(1)
(2)
(3)
(4)
VALUE
UNIT
VSUP, INH(1)
±4000
V
All pins, except VSUP, INH(1)
±6000
V
CAN bus terminals (CANH, CANL)(2)
±16000
V
All terminals(3)
±1500
V
All terminals(3)
±500
V
Corner terminals(3)
±750
V
All terminals(4)
±200
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Test method based upon AEC-Q100-002, CAN bus terminals stressed with respect to each other and to GND.
Tested in accordance to AEC-Q100-011.
Tested in accordance to JEDEC Standard 22, Test Method A115A.
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7.3 ESD Ratings IEC Specification
CAN bus terminals (CANH, CANL)
System level electrostatic discharge to GND
(ESD)
VSUP and WAKE
V(ESD)
ISO 7637-2
Transients according to GIFT - ICT
CAN EMC test specification(1)
CAN bus terminals (CANH, CANL)
to GND, VSUP, WAKE
ISO 7637-3 Transients
(1)
(2)
CAN bus terminals (CANH, CANL)
to GND, VSUP, WAKE
VALUE
UNIT
ISO 10605 per SAE J2962-2:
Powered Air Discharge(2)
±15000
V
ISO 10605 per SAE J2962-2:
Powered Contact Discharge(2)
±8000
V
IEC 61000-4-2 (150 pF, 330 Ω):
Unpowered contact discharge
±15000
V
IEC 61000-4-2 (150 pF, 330 Ω)
Unpowered contact discharge
±6000
V
Pulse 1
–100
V
Pulse 2
+75
V
Pulse 3a
–150
V
Pulse 3b
+100
V
Direct coupling capacitor "slow
transient pulse" with 100-nF
coupling capacitor - powered
±85
V
ISO 7637 is a system level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system level configurations will lead to different results.
Verified by external test facility on SOIC package
7.4 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Battery supply (reverse-blocked) voltage range - standard version
4.5
45
V
Battery supply (reverse-blocked) voltage range - H version
4.5
60
V
VCC
5V Supply Voltage
4.5
5.5
V
VIO
I/O supply voltage
2.8
5.5
V
IOH(LOGIC)
Logic terminal high level output current – RXD and nFAULT
–2
IOL(LOGIC)
Logic terminal low level output current – RXD and nFAULT
IO(INH)
INH output current
TA
Operational free-air temperature
VSUP
–55
mA
2
mA
1
mA
125
°C
7.5 Thermal Information
TCAN1043x-Q1
THERMAL
D (SOIC)
DMT (VSON)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
78
33.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
33.6
30.5
°C/W
RθJB
Junction-to-board thermal resistance
34.7
10.8
°C/W
ΨJT
Junction-to-top characterization parameter
5.7
0.4
°C/W
ΨJB
Junction-to-board characterization parameter
34.3
10.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
1.3
°C/W
(1)
6
METRIC(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.6 Dissipation Ratings
PARAMETER
PD
TEST CONDITIONS
Average power dissipation
VSUP = 14 V, VCC = 5 V, VIO = 5 V, TJ = 27°C, RL = 60 Ω,
nSTB = 5 V, EN = 5 V, CL_RXD = 15 pF. Typical CAN
operating conditions at 500 kbps with 25% transmission
(dominant) rate.
POWER
DISSIPATION
58
UNIT
mW
VSUP = 14 V, VCC = 5.5 V, VIO = 5.5 V, TJ = 150°C, RL = 50
Ω, nSTB = 5.5 V, EN = 5.5 V, CL_RXD = 15 pF. Typical high
126
load CAN operating conditions at 1 Mbps with 50%
transmission (dominant) rate and loaded network.
mW
TTSD
Thermal shutdown temperature
170
°C
TTSD_HYS
Thermal shutdown hysteresis
10
°C
7.7 Electrical Characteristics
Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
SUPPLY CHARACTERISTICS
Normal, Silent, Go-to-Sleep
ISUP
40
70
µA
Standby mode
Standby mode, VCC > 4.5 V, VIO > 2.8 V,
VINH = V(WAKE) = VSUP
15
45
µA
Sleep mode
Sleep mode, VCC = VIO = VINH = 0 V
V(WAKE) = VSUP
15
30
µA
See Figure 8-2. TXD = 0 V, RL = 60 Ω, CL =
open. Typical bus load.
70
mA
See Figure 8-2. TXD = 0 V, RL = 50 Ω, CL =
open. High bus load.
80
mA
Dominant with bus fault
See Figure 8-2. TXD = 0 V, CANH = -25 V,
RL = open, CL = open
110
mA
Recessive
See Figure 8-2. TXD = VIO, RL = 50 Ω, CL =
open, RCM = open
5
mA
Supply current Silent and Go-to-Sleep mode
See Figure 8-2. TXD = VIO, RL = 50 Ω, CL =
open
2.5
mA
Supply current Standby mode
See Figure 8-2. EN = L, NSTB = L
5
Sleep mode
See Figure 8-2. EN = H or L, NSTB = L
5
Supply current
VSUP
Dominant
Supply current
Normal mode
VCC
ICC
Normal mode
IIO
I/O supply current
RXD floating, TXD = 0 V (dominant) nSTB =
VIO, EN = VIO
Normal, Silent or Go-toRXD floating, TXD = VIO recessive
Sleep mode
5
Sleep mode
5
NSTB = L
UVSUP
Undervoltage detection on VSUP for protected mode
VHYS(UVSUP)
Hysteresis voltage on UVSUP
UVVCC
450
3.0
4.2
50
Rising undervoltage detection on VCC for protected mode
Falling undervoltage detection on VCC for protected mode
VHYS(UVVCC)
Hysteresis voltage on UVVCC
UVVIO
Undervoltage detection on VIO for protected mode
VHYS(UVIO)
Hysteresis voltage on UVIO
4.1
3.5
µA
µA
µA
µA
µA
V
mV
4.4
V
3.9
V
200
mV
1.3
2.75
80
V
mV
Driver Electrical Characteristics
VO(D)
Bus output voltage
dominant - normal
mode
VO(R)
Bus output voltage
recessive
CANH
CANL
CANH and CANL
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See Figure 8-2 and Figure 9-3, TXD = 0 V,
Normal mode, 50 ≤ RL ≤ 65 Ω, CL = open,
RCM = open
See Figure 8-2 and Figure 9-3, TXD = VCC,
VIO = VCC, Normal or Silent(2), RL = open,
RCM = open
2.75
4.5
V
0.5
2.25
V
3
V
2
0.5 × VCC
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7.7 Electrical Characteristics (continued)
Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
Differential output
voltage dominant
VOD(D)
Differential output
voltage recessive
VOD(R)
CANH - CANL
CANH - CANL
MIN
See Figure 8-2 and Figure 9-3, TXD = 0 V,
Normal mode, 50 Ω ≤ RL ≤ 65 Ω, CL = open,
RCM = open
1.5
3
V
See Figure 8-2 and Figure 9-3, TXD = 0 V,
Normal mode, 45 Ω ≤ RL ≤ 50 Ω, CL = open,
RCM = open
1.4
3
V
See Figure 8-2 and Figure 9-3, TXD = 0 V,
Normal mode, RL = 2240 Ω, CL = open, RCM
= open
1.5
5
V
See Figure 8-2 and Figure 9-3, TXD = 0 V,
Normal mode, 45 Ω ≤ RL ≤ 70 Ω, CL = open,
RCM = open
1.4
3.3
V
See Figure 8-2 and Figure 9-3, TXD = VCC,
Normal or Silent mode(2), RL = 60 Ω, CL =
open, RCM = open
–120
12
mV
See Figure 8-2 and Figure 9-3, TXD = VCC,
Normal or Silent mode(2), RL = open, CL =
open, RCM = open
–50
50
mV
0.9
1.1
V/V
400
mV
VSYM
Driver symmetry, dominant or recessive
VSYM = (VO(CANH) + VO(CANL))/VCC
See Figure 8-2 and Figure 10-4, Normal
mode, CL = open, RCM = open, TXD =
1MHz(3)
VSYM_DC
Driver symmetry, dominant
VSYM(DC) = VCC - VO(CANH) - VO(CANL)
See Figure 8-2 and Figure 9-3, Normal or
Silent mode, RL = 60 Ω, CL = open, RCM =
open
–400
See Figure 8-10 and Figure 9-3, VCANH = -5
V, CANL = open, TXD = 0 V
–100
IOS(DOM)
Short circuit steady-state output current
dominant
IOS(REC)
Short circuit steady-state output current
recessive
VO(STB)
Bus output voltage
Standby mode
See Figure 8-10 and Figure 9-3
–27 V ≤ VBUS ≤ 32 V, VBUS = CANH = CANL,
TXD = VIO
CANH - CANL
MAX
UNIT
mA
See Figure 8-10 and Figure 9-3, VCANL = 40
V, CANH = open, TXD = 0 V
CANH
CANL
TYP(1)
TEST CONDITIONS
–5
100
mA
5
mA
–0.1
0
0.1
V
STB = VCC or VIO, RL = open,
RCM = open
–0.1
0
0.1
V
–0.2
0
0.2
V
See Figure 8-3 and Table 9-5
-30
30
V
Receiver Electrical Characteristics
8
VCM
Common mode range
Normal and Silent modes
VIT
Input threshold voltage
Normal and Silent modes
See Figure 8-3 and Table 9-5, VCM ≤ ±20 V
500
900
mV
See Figure 8-3 and Table 9-5, VCM ≤ ±30 V
400
1000
mV
See Figure 8-3 and Table 9-5
Normal or Silent mode, VCM = ±20V
-3
0.5
V
0.9
8
V
VREC
Receiver recessive voltage
VDOM
Receiver dominant voltage
VHYS
Hysteresis voltage for input threshold
Normal and Silent modes
VIT(Sleep)
Input threshold
Sleep mode
VREC(Sleep)
Receiver recessive voltage
Sleep mode
VDOM(Sleep)
Receiver dominant voltage
Sleep mode
VCM
Common mode range
Standby, Go-to-Sleep and Sleep modes
See Figure 8-3 and Table 9-5
IIOFF(LKG)
Power-off (unpowered) bus input leakage current
CANH = CANL = 5 V, VCC = GND, VIO =
GND, VSUP = 0 V
CI
Input capacitance to ground (CANH or CANL)
CID
Differential input capacitance (CANH or CANL)
RID
Differential input resistance
RIN
Input resistance (CANH or CANL)
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See Figure 8-3 and Table 9-5
See Figure 8-3 and Table 9-5; VCM = ±12
120
400
1150
-3
0.4
V
1.15
8
V
-12
12
V
4.8
µA
24
30
pF
12
TXD = VCC, VIO = VCC (4)
TXD = VCC = VIO = 5 V, Normal mode; -30 ≤
VCM ≤ +30V
mV
mV
15
pF
30
80
kΩ
15
40
kΩ
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7.7 Electrical Characteristics (continued)
Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
RIN(M)
Input resistance matching:
[1 – RIN(CANH) / RIN(CANL)] × 100%
V(CANH) = V(CANL) = 5V
RCBF
Valid differential load impedance range for bus
fault circuitry
RCM = RL, CL = open
MIN
TYP(1)
MAX
–2%
2%
45
70
UNIT
Ω
TXD TERMINAL (CAN TRANSMIT DATA INPUT)
VIH
High level input voltage
VIL
Low level input voltage
IIH
High level input leakage current
0.7 VIO
TXD = VCC = VIO = 5.5 V
–2.5
IIL
Low level input leakage current
TXD = 0 V, VCC = VIO = 5.5 V
–100
ILKG(OFF)
Unpowered leakage current
TXD = 5.5 V, VCC = VIO = 0 V
–1
CI
Input capacitance
VIN = 0.4 x sin(2 x π x 2 x
106
x t) + 2.5 V
V
0
0
0.3 VIO
V
1
µA
–2.5
µA
1
µA
5
pF
RXD TERMINAL (CAN RECEIVE DATA OUTPUT)
VOH
High level output voltage
See Figure 8-3, IO = –2 mA.
VOL
Low level output voltage
See Figure 8-3, IO = –2 mA.
0.8 VIO
V
0.2 VIO
V
nFAULT TERMINAL (FAULT AND STATUS OUTPUT)
VOH
High level output voltage
See Figure 8-1, IO = –2 mA.
VOL
Low level output voltage
See Figure 8-1 IO = 2 mA.
0.8 VIO
V
0.2 VIO
V
0.3 VIO
V
10
µA
nSTB TERMINAL (STANDBY MODE INPUT)
VIH
High level input voltage
VIL
Low level input voltage
IIH
High level input leakage current
0.7 VIO
nSTB = VCC = VIO = 5.5 V
V
0.5
IIL
Low level input leakage current
nSTB = 0 V, VCC = VIO = 5.5 V
–1
ILKG(OFF)
Unpowered leakage current
nSTB = 5.5 V, VCC = 0V, VIO = 0 V
–1
0
1
µA
1
µA
0.3 VIO
V
EN TERMINAL (ENABLE MODE INPUT)
VIH
High level input voltage
VIL
Low level input voltage
0.7 VIO
V
IIH
High level input leakage current
EN = VCC = VIO = 5.5 V
0.5
10
µA
IIL
Low level input leakage current
EN = 0 V, VCC = VIO = 5.5 V
–1
1
µA
ILKG(OFF)
Unpowered leakage current
EN = 5.5 V, VCC = 0V, VIO = 0 V
–1
0
1
µA
0.5
1
V
5
µA
INH TERMINAL (INHIBIT OUTPUT)
ΔVH
High level voltage drop INH with respect to VSUP
IINH = –0.5 mA
ILKG(INH)
Leakage current
INH = 0 V, Sleep Mode
-5
Wake TERMINAL (WAKE INPUT)
VIH
High level input voltage
Standby and Sleep Mode
VIL
Low level input voltage
Standby and Sleep Mode
IIH
High level input current(5)
WAKE = VSUP – 1 V
IIL
current(5)
(1)
(2)
(3)
(4)
(5)
Low level input
VSUP - 1.9
V
VSUP 3.5
–25
WAKE = 1 V
–15
15
V
µA
25
µA
All typical values are at 25°C and supply voltages of VCC = 5 V, VIO = 3.3 V, and RL = 60 Ω. Unless otherwise noted.
The recessive bus voltage will be the same if the device is in Normal mode with the nSTB and EN terminals high or if the device is in
Silent mode with the nSTB terminal high and EN terminal low.
The bus output voltage symmetry, VSYM, is measured using RTERM / 2 = 30 Ω and CSPLIT = 4.7 nF as shown in Figure 10-4
Specified by design and verified during product validation using the ISO 11898-2 method.
To minimize system level current consumption, the WAKE pin will automatically configure itself based on the applied voltage to have
either an internal pull-up or pull-down current source. A high level input results in an internal pull-up and a low level input results in an
internal pull-down. For more information, refer to Section 10.4.6.2
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7.8 Switching Characteristics
Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX
UNI
T
DRIVER SWITCHING CHARACTERISTICS
tpHR
Propagation delay time, high TXD to driver recessive
tpLD
Propagation delay time, low TXD to driver dominant
tsk(p)
Pulse skew (|tpHR - tpLD|)
tR
Differential output signal rise time
tF
Differential output signal fall time
tTXD_DTO
Dominant time out
50
See Figure 8-2, Normal mode.
RL = 60 Ω, CL = 100 pF, RCM
= open
See Figure 8-9, RL = 60 Ω, CL
= open
ns
40
ns
10
ns
45
ns
45
ns
1.2
3.8
ms
RECEIVER SWITCHING CHARACTERISTICS
tpRH
Propagation delay time, bus recessive input to high RXD
tpDL
Propagation delay time, bus dominant input to RXD low
output
tR
Output signal rise time (RXD)
tF
Output signal fall time (RXD)
tBUS_DOM
Dominant time out
See Figure 17, RL = 60 Ω, CL
= open
1.3
tCBF
Bus fault detection time
45 Ω ≤ RCM ≤ 70 Ω, CL = open
1.9
See Figure 8-3
CL(RXD) = 15 pF
50
ns
50
ns
8
ns
8
ns
3.8
ms
µs
Wake Terminal (Wake input)
tWAKE_HT
WAKE hold time
See Figure 8-12 and Figure
8-13
Time required for LWU from a
high to low or low to high on
WAKE
5
50
µs
100
160
ns
110
175
ns
Mode change time
See Figure 8-4 and Figure
8-5, Mode change time for
leaving Sleep mode to
entering normal and silent
mode after VCC and VIO have
crossed UV thresholds
20
µs
tMODE2
Mode change time
Mode changes between
Normal, Silent and Standby
modes, and Sleep to Standby
mode transition
10
µs
tUV_RE-ENABLE
Re-enable time after under voltage event
Time for device to return to
normal operation from UVVCC
or UVVIO under voltage event
200
µs
tPower_Up
Power up time on VSUP
See Figure 8-11
tWK_FILTER
Bus time to meet filtered bus requirements for wake up
request
See Figure 9-5
Device Switching Characteristics
tPROP(LOOP1)
tPROP(LOOP2)
tMODE1
Total loop delay, driver input (TXD) to receiver output (RXD),
See Figure 8-5, Normal mode,
recessive to dominant
RL = 60 Ω, CL = 100 pF,
Total loop delay, driver input (TXD) to receiver output (RXD), C
L(RXD) = 15 pF
dominant to recessive
250
0.5
µs
1.8
µs
tWK_TIMEOUT
Bus Wake-up timeout value
See Figure 9-5
0.5
2
ms
tUV
Undervoltage filter time for VIO and VCC
VIO ≤ UVVIO or VCC < UVVCC
159
340
ms
tGo_To_Sleep
Minimum hold time for transition to sleep mode
EN = H and nSTB = L
5
50
µs
FD Timing Parameters
10
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7.8 Switching Characteristics (continued)
Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted)
PARAMETER
tBIT(BUS)
tBIT(RXD)
ΔtREC
TEST CONDITIONS
MIN TYP(1) MAX
UNI
T
Bit time on CAN bus output pins with tBIT(TXD) = 500 ns, all
devices
435
530
ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns, G
device variants only
155
210
ns
400
550
ns
120
220
ns
Receiver timing symmetry with tBIT(TXD) = 500 ns, all devices
-65
40
ns
Receiver timing symmetry with tBIT(TXD) = 200 ns, G device
variants only
-45
15
ns
Normal mode, RL = 60 Ω, CL
= 100 pF,
CL(RXD) = 15 pF,
Bit time on RXD output pins with tBIT(TXD) = 200 ns, G device Δt
REC = tBIT(RXD) - tBIT(BUS)
variants only
Bit time on RXD output pins with tBIT(TXD) = 500 ns, all
devices
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3
3
2.5
2.5
2
2
VOD(D) (V)
VOD(D) (V)
7.9 Typical Characteristics
1.5
1.5
1
1
0.5
0.5
0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
0
4.5
125
4.6
4.9
5
5.1
VCC (V)
5.2
5.3
5.4
5.5
D002
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
VIO = 5 V
STB = 0 V
RL = 60 Ω
RCM = Open
STB = 0 V
CL = Open
RCM = Open
Temp = 25°C
Figure 7-2. VOD(D) over VCC
1.48
150
1.47
125
Total Loop Delay (ns)
ICC Recessive (mA)
4.8
CL = Open
Figure 7-1. VOD(D) over Temperature
1.46
1.45
1.44
1.43
100
75
50
25
1.42
1.41
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
125
0
-55
-35
-15
D003
5
25
45
65
Temperature (°C)
85
105
125
D004
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
CL = Open
RCM = Open
STB = 0 V
CL = 100 pF
CL_RXD = 15 pF
STB = 0 V
Figure 7-3. ICC Recessive over Temperature
12
4.7
D001
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Figure 7-4. Total Loop Delay over Temperature
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8 Parameter Measurement Information
CANH
TXD
CL
RL
CANL
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Supply Test Circuit
RCM
CANH
TXD
VCC
50%
TXD
RL
CL
VOD
0V
VCM
VO(CANH)
CANL
50%
tpHR
tpLD
90%
RCM
VO(CANL)
0.9V
VOD
0.5V
10%
tR
tF
Copyright © 2016, Texas Instruments Incorporated
Figure 8-2. Driver Test Circuit and Measurement
CANH
RXD
VID
IO
1.5V
0.9V
0.5V
0V
VID
CANL
CL_RXD
VO
tpDL
tpRH
VOH
90%
VO(RXD)
50%
10%
VOL
tF
tR
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Figure 8-3. Receiver Test Circuit and Measurement
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CANH
VIH
TXD
0V
CL
RL
EN
50%
CANL
EN
VI
0V
tMODE1
RXD
VO
VOH
CL_RXD
RXD
50%
VOL
Copyright © 2017, Texas Instruments Incorporated
Figure 8-4. tMODE1 Test Circuit and Measurement, Silent Mode to Normal Mode
CANH
VIH
TXD
TXD
CL
RL
VI
0V
CANL
VI
EN
200 ns
EN
50%
RXD
0V
VO
tMODE2
CL_RXD
RXD
VOH
50%
VOL
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Figure 8-5. tMODE2 Test Circuit and Measurement, Normal Mode to Silent Mode
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CANH
VCC
TXD
VI
CL
RL
TXD
50%
CANL
0V
VO
tPROP(LOOP2)
tPROP(LOOP1)
RXD
VOH
CL_RXD
50%
RXD
VOL
Copyright © 2016, Texas Instruments Incorporated
Figure 8-6. tPROP(LOOP) Test Circuit and Measurement
CANH
RCM
VCC
TXD
VI
CL
RL
VCM
TXD
CANL
50%
RCM
0V
VO
tPROP(LOOP2)
tPROP(LOOP1)
RXD
VOH
CL_RXD
RXD
50%
VOL
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Figure 8-7. tPROP(LOOP) Test Circuit and Measurement with CM Range
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CANH
VI
TXD
VI
70%
CL
RL
TXD
30%
CANL
30%
0V
tBIT
5 x tBIT
RXD
VOH
70%
VO
RXD
CL_RXD
30%
VOL
tREC_SYM
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Figure 8-8. Loop Delay Symmetry Test Circuit and Measurement
CANH
VIH
TXD
TXD
RL
CL
0V
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
tTXD_DTO
0V
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Figure 8-9. TXD Dominant Timeout Test Circuit and Measurement
CANH
200 s
IOS
TXD
VBUS
IOS
CANL
VBUS
VBUS
0V
or
0V
VBUS
VBUS
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Figure 8-10. Driver Short-Circuit Current Test and Measurement
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VSUP
4.5V
VSUP
VO
INH
VSUP
0V
CVSUP
tPower_Up
TCAN1043
INH = H
VSUP -1V
INH
Copyright © 2016, Texas Instruments Incorporated
Figure 8-11. tPower_Up Timing Measurement
VSUP
VSUP
INH
VWAKE
VSUP
VSUP - 2
VWAKE
VSUP - 3
0V
CVSUP
OR
tWAKE_HT
TCAN1043
tWAKE_HT
VWAKE_IN
INH = H
INH = H
INH
INH
VSUP -1V
VSUP -1V
Copyright © 2016, Texas Instruments Incorporated
Figure 8-12. tWAKE_HT While Monitoring INH Output
VSUP
VSUP
RXD
VWAKE
VSUP
VWAKE
VSUP - 2
VSUP - 3
0V
CVSUP
OR
tWAKE_HT
TCAN1043
tWAKE_HT
VWAKE_IN
INH = H
RXD
50%
INH = H
RXD
50%
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Figure 8-13. tWAKE_HT While Monitoring RXD Output
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9 Detailed Description
9.1 Overview
The TCAN1043xx-Q1 meets or exceeds the specifications of the ISO 11898-2 (2016) High Speed CAN
(Controller Area Network) physical layer standard. The device has been certified to the requirements of
ISO11898-2/5 according to the GIFT/ICT High Speed CAN test specification.
This device provides CAN transceiver differential transmit capability to the bus and differential receive capability
from the bus. The device includes many protection features providing device and CAN bus robustness. All of the
devices are available to support CAN and CAN FD (Flexible Data Rate) up to 2 Mbps while the G version of the
device support CAN and CAN FD data rates up to 5 Mbps.
9.2 Functional Block Diagram
VCC
VIO
3
5
VSUP
NC
11
10
VCC
VIO
VSUP
INH
7
WAKE
9
nFAULT
8
13
VSUP
14
nSTB
EN
VCC
TRANSMIT
DOMINANT
TIME OUT
BIAS UNIT
TXD
1
6
WAKE
LDO
12
CONTROL and MODE
LOGIC
Sleep Receiver
UNDER
VOLTAGE
RXD
4
WUP
Detect
OVER
TEMP
MUX
RECEIVE
DOMINANT
TIME OUT
Normal Receiver
2
GND
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9.3 Feature Description
9.3.1 Internal and External Indicator Flags (nFAULT and RXD)
The following device status indicator flags are implemented to allow for the MCU to determine the status of the
device and the system. In addition to faults, the nFAULT terminal also signals wake up requests and a “cold”
power-up sequence on the VSUP battery terminal so the system can do any diagnostics or cold booting sequence
necessary. The RXD terminal indicates wake up request and the faults are multiplexed (ORed) to the nFAULT
output.
Table 9-1. Device Status Indicator Flags
EVENT
FLAG NAME
CAUSE
INDICATORS(1)
FLAG IS CLEARED
Power-up
PWRON
Power up on VSUP and
any return of VSUP after
it has been below
UVVSUP
nFAULT = L upon
entering Silent mode
from Standby, Go-toSleep, or Sleep mode
After transition to normal
mode
WAKERQ(2)
Wake up event on CAN
bus, state transition on
WAKE pin, or initial
power up
Wake up request may
nFAULT = RXD = L after
After transition to normal only be set from standby,
wake up in standby
mode, or either a UVVCC
Go-to-sleep, or sleep
mode, go-to-sleep mode,
or UVVIO event
mode. Resets timers for
and sleep mode
UVVCC or UVVIO
WAKESR
Wake up event on CAN
bus, state transition on
WAKE pin, initial power
up
Available upon entering
After four recessive to
normal mode(4) , nFAULT
dominant edges on TXD
= L indicates wake from
A LWU source flag is set
in normal mode,leaving
WAKE terminal, nFAULT
on intial power up
normal mode, or either a
= H indicates wake from
UVVCC or UVVIO event
CAN bus
UVVCC
Under voltage VCC
Not externally indicated
VCC returns, or Wake-up
request occurs
UVVIO
Under voltage VIO
Not externally indicated
VIO returns, or Wake-up
request occurs
UVVSUP
Under voltage VSUP
Not externally indicated
VSUP returns
VSUP undervoltage event
triggers the PWRON and
WAKERQ flags upon
return of VSUP
CBF
CANH shorted to GND,
VCC, VSUP or CANL
shorted to GND, VCC,
VSUP
nFAULT = L in Normal
mode only(5)
Upon leaving Normal
mode
Failure must persist for
four consecutive
dominant to recessive
transistions
TXDDTO
TXD Dominant Time Out,
dominant (low) signal for
t ≥ tTXD_DTO
TXDRXD
TXD and RXD pins are
shorted together for t ≥
tTXD_DTO
CANDOM
CAN bus dominant fault,
when dominant bus
signal received for t ≥
tBUS_DOM
TSD
Thermal Shutdown,
junction temperature ≥
TTSD
Wake-up Request
Wake-up Source
Recognition(3)
Under voltage
CAN Bus Failures
Local Faults
(1)
(2)
(3)
(4)
(5)
RXD = L and TXD = H,
or upon transitioning into
Normal, Standby, Go-toSleep, or Sleep modes
nFAULT = L upon
entering Silent mode
from Normal mode
RXD = H, or upon
transitioning into Normal,
Standby, Go-to-Sleep, or
Sleep modes
COMMENT
CAN driver remains
disabled until the
TXDDTO is cleared
CAN driver remains
disabled until the
TXDRXD is cleared
Driver remains enabled
TJ drops below tTSD and
either RXD = L and TXD
CAN driver remains
= H, or upon transitioning
disabled until the TSD is
into Normal, Standby,
cleared
Go-to-Sleep, or Sleep
modes
VIO and VSUP are present
Transitions to Go-to-sleep mode is blocked until WAKERQ flag is cleared
Wake-up source recognition reflects the first wake up source. If additional wake-up events occur the source still indicates the original
wake up source
Indicator is only available in normal mode until the flag is cleared
CAN Bus failure flag is indicated after four recessive to dominant edges on TXD
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9.3.2 Power-Up Flag (PWRON)
This is an internal and external flag that is set and controls the power up state of the device. The device powers
on to standby mode with the PWRON flag set after VSUP has cleared the under voltage lock out for VSUP,
UVVSUP
9.3.3 Wake-Up Request Flag (WAKERQ)
This is an internal and external flag that can be set in standby, go-to-sleep, or sleep mode. This flag is set when
either a valid local wake up (LWU) request occurs, or a valid remote wake request occurs, or on power up on
VSUP. The setting of this flag clears tUV timer for the UVVCC or UVVIO. This flag is cleared upon entering normal
mode or during a under voltage event on VCC or VIO.
9.3.4 Wake-Up Source Recognition Flag (WAKESR)
This flag is an internal and external flag that is set high or low after a valid local wake up (LWU) request occurs,
or a valid remote wake request occurs. This flag is only available in Normal mode before four recessive to
dominant transitions occur on TXD. If the nFAULT pin is high after entering normal mode, this indicates that a
remote wake request was received. If the nFAULT output is low after entering Normal mode, this indicates that a
local wake up event occurred. Upon power up on VSUP, or after and under voltage event on VSUP, the local wake
up request is indicated on nFAULT.
9.3.5 Undervoltage Fault Flags
The TCAN1043xx-Q1 device comes with undervoltage detection circuits on all three supply terminals: VSUP,
VCC, and VIO. These flags are internal flags and are not indicated on the nFAULT terminal.
9.3.5.1 Undervoltage on VCC Fault
This internal flag is set when the voltage on VCC drops below the undervoltage detection voltage threshold,
UVVCC, for longer than the undervoltage filter time, tUV.
9.3.5.2 Undervoltage on VIO Fault
This internal flag is set when the voltage on VIO drops below the undervoltage detection voltage threshold,
UVVIO, for longer than the undervoltage filter time, tUV.
9.3.5.3 Undervoltage on VSUP Fault
This internal flag is set when the voltage on VSUP drops below the undervoltage detection voltage threshold,
UVVSUP. While this flag is not externally indicated, the PWRON and WAKERQ flags are set once the VSUP
supply returns
9.3.6 CAN Bus Failure Fault Flag
The TCAN1043xx-Q1 devices are able to detect the following six faults that can occur on the CANH and CANL
bus terminals. These faults are only detected in Normal mode and are only indicated via the nFAULT terminal
while in Normal mode.
1.
2.
3.
4.
5.
6.
CANH bus pin shorted VSUP
CANH bus pin shorted VCC
CANH bus pin shorted GND
CANL bus pin shorted VSUP
CANL bus pin shorted VCC
CANL bus pin shorted GND
These failures are detected while transmitting a dominant signal on the CAN bus. If one of these fault conditions
persists for four consecutive dominant bit transmissions, the nFAULT indicates a CAN bus failure flag in Normal
mode by driving the nFAULT pin low. The CAN bus driver remains active.
The bus fault failure circuitry is able to detect bus faults for a range of differential resistance loads (RCBF) and for
any time greater than tCBF_MIN.
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9.3.7 Local Faults
Local faults are detected in both Normal mode and Silent mode, but are only indicated via the nFAULT pin when
transitioned form Normal mode to Silent mode. All other mode transitions clear the local fault flag indicators.
9.3.7.1 TXD Dominant Timeout (TXD DTO)
During Normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local
node from blocking network communication in event of a hardware or software failure where TXD is held
dominant longer than the time out period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If
no rising edge is seen before the time out constant of the circuit, tTXD_DTO, expires, the CAN driver is disabled.
This keeps the bus free for communication between other nodes on the network. The CAN driver is re-activated
when a recessive signal is seen on the TXD terminal, thus clearing the dominant time out. The receiver and RXD
terminal reflects what is on the CAN bus and the bus terminals is biased to recessive level during a TXD DTO.
This fault is indicated via the TXDDTO flag shown on the nFAULT terminal.
TXD fault stuck dominant: example PCB
failure or bad software
TXD
(driver)
tTXD_DTO
Fault is repaired & transmission
capability restored
Driver disabled freeing bus for other nodes
%XV ZRXOG EH ³VWXFN GRPLQDQW´ EORFNLQJ FRPPXQLFDWLRQ IRU WKH
whole network but TXD DTO prevents this and frees the bus for
communication after the time tTXD_DTO.
Normal CAN
communication
CAN
Bus
Signal
tTXD_DTO
Communication from
other bus node(s)
Communication from
repaired node
Communication from
other bus node(s)
Communication from
repaired local node
RXD
(receiver)
Communication from
local node
Figure 9-1. Example Timing Diagram for TXD DTO
Note
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible
transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive
dominant bits (on TXD) for the worst case, where five successive dominant bits are followed
immediately by an error frame. The minimum transmitted data rate may be calculated by: Minimum
Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps.
9.3.7.2 TXD Shorted to RXD Fault
The TXDRXD flag is set if the device detects that the TXD and RXD lines have been shorted together for t
≥tTXD_DTO. This fault is then indicated via the nFAULT terminal. The CAN driver is disabled until the TXDRXD
fault is cleared.
This fault is only indicated in Normal mode and Silent mode.
9.3.7.3 CAN Bus Dominant Fault
The CAN bus dominant fault detects if the CAN bus is stuck in a permanent dominant (low) state. This fault is
detected when the device detects a dominant on the bus for time ≥ tBUS_DOM. This fault is then indicated via the
CANDOM flag shown on the nFAULT terminal.
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This fault is only indicated on the nFAULT pin in Silent mode. This fault can also be seen on the RXD pin as a
dominant pulse for a time ≥ tBUS_DOM.
9.3.7.4 Thermal Shutdown (TSD)
If the junction temperature of the device exceeds the thermal shut down threshold, the device turns off the CAN
driver circuits thus blocking the TXD to the bus transmission path. The shutdown condition is cleared when the
junction temperature of the device drops below the thermal shutdown temperature of the device. If the fault
condition that caused the thermal shutdown is still present, the temperature may rise again causing the device to
reenter thermal shut down. Prolonged operation with thermal shutdown conditions may affect device reliability.
The thermal shutdown circuit includes hysteresis to avoid oscillation of the driver output. This fault is indicated
via the TSD flag shown on the nFAULT terminal.
9.3.7.5 RXD Recessive Fault
The RXD recessive fault detects if the RXD terminal is stuck (clamped) in a permanent recessive state. This fault
is detected when the device transmits four dominant bits to the bus via TXD but the RXD output does not follow.
This fault is then indicated via the RXDREC flag shown on the nFAULT terminal.
9.3.7.6 Undervoltage Lockout (UVLO)
The supply terminals have under voltage detection which puts the device in protected mode if one of the supply
rails drop below the threshold voltage. This protects the bus and system during an under voltage event on either
VSUP, VCC or VIO supply terminals. These faults are internal fault flags and are not indicated via the nFAULT
terminal.
During an undervoltage event on VCC or VIO the device goes into protected mode and the driver is disabled.
After the UV timer expires, the device transitions into sleep mode and the INH pin goes into a high impedance
state. In the event of a UV on VIO where the mode pins are no longer driven, the device transitions into standby
mode (due to internal fail safe biasing on the NSTB and EN pins) until the UV timer expires and the device
transitions into sleep mode.
The VCC and VIO undervoltage detection circuits share the same timer. Therefore, if an undervoltage on one
supply occurs and the timers starts, and then during the undervoltage the other supply has an undervoltage
event before the first supply recovers the timer does not reset.
Once an under voltage condition is cleared and the supplies have returned to valid levels the device typically
needs 200 µs to transition to normal operation.
9.3.7.7 Unpowered Device
The device is designed to be an "ideal passive" or “no load” to the CAN bus if it is unpowered. The bus terminals
(CANH, CANL) have extremely low leakage currents when the device is un-powered so they do not load down
the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains in
operation.
Logic terminals also have extremely low leakage currents when the device is un-powered so they do not load
down other circuits which may remain powered.
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9.3.7.8 Floating Terminals
These devices have internal pull ups on critical terminals to place the device into known states if the terminals
float. See Table 9-2 for details on terminal bias conditions.
Table 9-2. Terminal Failsafe Biasing
TERMINAL
PULL UP or PULL DOWN
COMMENT
TXD
Pull up
Weakly biases TXD toward recessive to prevent bus blockage or
TXD DTO triggering
nSTB
Pull down
Weakly biases nSTB terminal towards low power Standby mode to
prevent excessive system power
EN
Pull down
Weakly biases EN terminal towards low power mode to prevent
excessive system power
Note
The internal bias should not be relied on by design, especially in noisy environments but should be
considered a fall back protection. Special care needs to be taken when the device is used with MCUs
using open drain outputs. TXD is weakly internally pulled up. The TXD pull up strength and CAN bit
timing require special consideration when this device is used with an open drain TXD output on the
microprocessor CAN controller. An adequate external pull up resistor must be used to ensure that the
TXD output of the microprocessor maintains adequate bit timing input to the CAN transceiver.
9.3.7.9 CAN Bus Short Circuit Current Limiting
The TCAN1043xx-Q1 has several protection features that limit the short circuit current when a CAN bus line is
shorted. These include CAN driver current limiting (dominant and recessive). The device has TXD dominant time
out which prevents permanently having the higher short circuit current of dominant state in case of a system
fault. During CAN communication the bus switches between dominant and recessive states, thus the short circuit
current may be viewed either as the current during each bus state or as a DC average current. For system
current and power considerations in the termination resistors and common mode choke ratings, the average
short circuit current should typically be used. The percentage dominant is limited by the TXD dominant time out
and CAN protocol which has forced state changes and recessive bits such as bit stuffing, control fields, and
interframe space. These ensure there is a minimum recessive amount of time on the bus even if the data field
contains a high percentage of dominant bits.
The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short
circuit currents. The average short circuit current may be calculated with Equation 1.
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive ×
IOS(SS)_REC]
(1)
Where:
• IOS(AVG) is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current
Note
The short circuit current and possible fault cases of the network should be taken into consideration
when sizing the power ratings of the termination resistance and other network components.
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9.4 Device Functional Modes
The device has four main operating modes: Normal mode, Standby mode, Silent mode and Sleep mode, and
one transitional mode called Go-to-Sleep mode. Operating mode selection is made via the nSTB and EN input
terminals in conjunction with supply conditions and wake events.
Table 9-3. Operating Modes
VCC and VIO
VSUP
EN
nSTB
WAKERQ
Flag
Mode
Driver
Receiver
RXD
Bus Bias
INH
> UVVCC & >
UVVIO
> UVVSUP
H
H
X
Normal
Enabled
Enabled
Mirrors Bus
State
VCC/2
ON
> UVVCC & >
UVVIO
> UVVSUP
L
H
X
Silent
Disabled
(OFF)
Enabled
Mirrors Bus
State
VCC/2
ON
> UVVCC & >
UVVIO
> UVVSUP
H
L
Cleared
Go-to-Sleep(1)
Disabled
(OFF)
Low Power
Bus Monitor
Enabled (ON)
High or High Z
(no VIO)
Weak pull to
GND
ON(2)
Cleared
Sleep(3)
Disabled
(OFF)
Low Power
Bus Monitor
Enabled (ON)
High or High Z
(no VIO)
Weak pull to
GND
OFF
Set
Standby
Disabled
(OFF)
Low Power
Bus Monitor
Enabled (ON)
LOW signals
wake up
Weak pull to
GND
ON
> UVVCC & >
UVVIO
> UVVSUP
L
L
X
Standby
Disabled
(OFF)
Low Power
Bus Monitor
Enabled (ON)
LOW signals
wake up
Weak pull to
GND
ON
< UVVCC &
UVVSUP
X
X
X
Sleep
Disabled
(OFF)
Low Power
Bus Monitor
Enabled (ON)
High or High Z
(no VIO)
Weak pull to
GND
OFF (High Z)
X
< UVVSUP
X
X
X
Protected
Disabled
(OFF)
Disabled
(OFF)
High Z
High Z
OFF (High Z)
(1)
(2)
(3)
Go-to-sleep: Transitional mode for EN = H, nSTB = L until tgo_to_sleep timer has expired
The INH pin transitions to high Z (off) after tgo_to_sleep timer has expired
Mode change from Go-to-Sleep mode to sleep mode once tgo_to_sleep timer has expired
9.4.1 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. See Figure 9-2 and Figure 9-3.
In the recessive bus state the bus is biased to a common mode of approximately VCC/2 (2.5 V) via the high
resistance internal input resistors of the receiver of each node on the bus. Recessive is equivalent to a logic high
and is typically a differential voltage on the bus of approximately 0 V.
The dominant bus state is when the bus is driven differentially by one or more drivers. Current flows through the
termination resistors and generates a differential voltage on the bus. Dominant is equivalent to a logic low and is
a differential voltage on the bus greater than the minimum threshold for a CAN dominant. A dominant state
overwrites the recessive state.
During arbitration, multiple CAN nodes may transmit a dominant bit at the same time. In this case, the differential
voltage of the bus is greater than the differential voltage of a single driver.
The host microprocessor of the CAN node uses the TXD terminal to drive the bus and receives data from the
bus on the RXD terminal.
The TCAN1043xx-Q1 transceivers has a third bus state in low power standby mode where the bus terminals are
weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 9-2 and Figure 9-3.
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Figure 9-2. Bus States (Physical Bit Representation)
CANH
VCC/2
Bias
Unit
A
RXD
GND
B
CANL
A. Normal and Silent Modes
B. Sleep and Standby Modes
Figure 9-3. Bias Unit (Recessive Common Mode Bias) and Receiver
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Power
Off
Power On
Start Up
Standby Mode
EN = L,
NSTB = L
Normal Mode
EN = H,
NSTB = H
EN: H
NSTB: H
CAN: Bi-directional
INH: H
EN = L,
NSTB = H
EN = L,
NSTB = H
EN: L
NSTB: L
CAN: weak ground
Wake Sources: CAN, WAKE
INH: H
Silent Mode
EN = H,
NSTB = H
EN: L
NSTB: H
CAN: Silent (Receive only)
INH: H
EN = H,
NSTB = H
EN = H,
NSTB = L
NSTB = H, EN = L
VCC and VIO supplied
EN = L,
NSTB = H
Go-to-Sleep Mode
EN: H
NSTB: L
CAN: weak ground
Wake Sources: CAN, WAKE
INH: H
EN = L or WAKERQ set)
and NSTB = L
EN = H,
NSTB = L and
WAKERQ Cleared
EN = H,
NSTB = L and
WAKERQ Cleared
Wake-up Event:
CAN bus
or
WAKE Pin
EN = L,
t < tGO-TO-SLEEP
Sleep Mode
EN = H,
t > tGO-TO-SLEEP
NSTB = H, EN = H
VCC and VIO supplied
EN: X*
NSTB: L
CAN: weak ground
Wake Sources: CAN, WAKE
INH: floating
VCC < VCC,UV and / or
VIO < VIO,UV for t > tUV
Under-Voltage
On VCC or VIO
*The enable pin can be in a logical high or low state while in sleep mode but since it has an internal pull-down, the lowest possible power
consumption occurs when the pin is left either floating or pulled low externally.
Figure 9-4. State Diagram
9.4.2 Normal Mode
This is the normal operating mode of the device. The CAN driver and receiver are fully operational and CAN
communication is bi-directional. The driver is translating a digital input on TXD to a differential output on CANH
and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD
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Entering Normal mode clears both the WAKERQ and PWRON flags.
9.4.3 Silent Mode
Silent mode is commonly referred to as listen only and receive only mode. In this mode, the CAN driver is
disabled but the receiver is fully operational and CAN communication is unidirectional into the device. The
receiver is translating the differential signal from CANH and CANL to a digital output on the RXD terminal.
In Silent mode, the PWRON, and Local Failure Flags can be polled.
9.4.4 Standby Mode
Standby mode is a low power mode where the driver and receiver are disabled, reducing current consumption.
However, this is not the lowest power mode of the device since the INH terminal is on, allowing the rest of the
system to resume normal operation.
During standby mode, a wake up request (WAKERQ) is indicated by the RXD terminal being low. The wake up
source is identified via the nFAULT pin after the device is returned to normal mode.
9.4.5 Go-to-Sleep Mode
Go-to-Sleep mode is the transitional mode of the device from any state to sleep. In this state the driver and
receiver are disabled, reducing the current consumption. However, the INH terminal is on allowing the rest of the
system to resume normal operation. If the device is held in this state for time ≥ tgo_to_sleep the device transitions
to sleep mode and the INH is turned off (high Z).
Entering Go-to-Sleep Mode from standby mode is gated if the WAKERQ flag is set. Once this flag is cleared the
transition is no longer gated.
9.4.6 Sleep Mode with Remote Wake and Local Wake Up Requests
Sleep mode is the lowest power mode of the device. The CAN driver and main receiver are turned off and bidirectional CAN communication is not possible.
The low power receiver with bus monitor and WAKE circuits are supplied via the VSUP supply terminal. The low
power receiver is able to monitor the bus for any activity that validates the wake up pattern (WUP) requirements,
and the WAKE monitoring circuit monitors for state changes on the WAKE terminal for a local wake up (LWU)
event. The VCC and VIO supplies may be turned off or be controlled via the INH output for additional system level
current savings.
The valid wake up sources in sleep mode are:
• Remote wake request: CAN bus activity that validates the WUP requirements
• Local wake up (LWU) request: state change on WAKE terminal
Additionally, EN and nSTB can be used to change modes if both VCC and VIO are powered.
If a bus wake up pattern (WUP) or local wake up (LWU) event occurs, the internal WAKERQ flag is set and the
device transitions to standby mode which in turn sets the INH output high. The wake up source recognition flag
(WAKESR) is set either high or low to identify which wake event occurred. This flag can be polled via the
nFAULT pin after the device is returned to normal mode and only until there have been four recessive to
dominant transitions on the TXD pin.
The wake source (WAKESR) flag has two states:
• Low: This indicates that the wake up source was via the WAKE pin.
• High: This indicates that a remote wake request via the CAN bus occurred.
If both a local wake and a remote wake request occur, the device indicates whichever event was completed first.
The device transitions into sleep mode if at any time either or both the VCC or VIO supplies have an under
voltage condition that lasts longer than timer tUV. If VIO remains active in sleep mode, it is recommended to drive
the EN pin low once the device has transitioned into sleep mode to reduce the current consumption due to the
internal pull-down on the EN terminal.
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9.4.6.1 Remote Wake Request via Wake Up Pattern (WUP)
The TCAN1043xx-Q1 use the multiple filtered dominant wake up pattern (WUP) from ISO 11898-2 (2016) to
qualify bus activity. The WUP is active for both sleep and standby modes and results in the RXD terminal being
driven low after a valid pattern is received.
The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second
filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered
recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor
is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon
reception of the second filtered dominant the bus monitor recognizes the WUP and transition to standby mode,
drives the INH output high and sets the RXD terminal low (if VIO is present) to signal the wake up request.
For a dominant or recessive to be considered “filtered”, the bus must be in that state for more than the tWK_FILTER
time. Due to variability in tWK_FILTER the following scenarios are applicable. Bus state times less than
tWK_FILTER(MIN) are never detected as part of a WUP and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a wake request may be
generated. Bus state times greater than tWK_FILTER(MAX) will always be detected as part of a WUP and thus a
wake request will always be generated. See Figure 9-5 for the timing diagram of the WUP.
The pattern and tWK_FILTER time used for the WUP and wake request prevents noise and bus stuck dominant
faults from causing false wake requests while allowing any CAN or CAN FD message to initiate a wake request.
If the device is switched to normal mode or an under voltage event occurs on either the VCC or VIO supplies, the
wake request is lost.
ISO 11898-2 (2016) has two sets of times for a short and long wake up filter times. The tWK_FILTER timing for the
TCAN1043xx-Q1 devices have been picked to be within the min and max values of both filter ranges. This timing
has been chosen such that a single bit time at 500 kbps, or two back to back bit times at 1 Mbps triggers the
filter in either bus state.
Wake
Request
Wake Up Pattern (WUP) received in t < tWK_timeout
Filtered
Dominant
Waiting for
Filtered
Recessive
Filtered
Recessive
Waiting for
Filtered
Dominant
Filtered
Dominant
Bus
Bus VDiff
• tWK_FILTER
• tWK_FILTER
Mode
• tWK_FILTER
Sleep or Standby Mode
Standby Mode
INH
*
RXD
The RXD pin is only driven once VIO is present.
Figure 9-5. Wake Up Pattern (WUP)
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For an additional layer of robustness and to prevent false wake-ups, these devices implement a timeout feature.
For a remote wake up event to successfully occur, the entire WUP must be received within the timeout value t <
tWK_timeout (see Figure 9-5). If not, the internal logic is reset and the part remains in its current state without
waking up. The full pattern must then be retransmitted, conforming to the constraints mentioned in this section
and shown in figure Figure 9-5.
9.4.6.2 Local Wake Up (LWU) via WAKE Input Terminal
The WAKE terminal is a high voltage input terminal which can be used for local wake up (LWU) requests via a
voltage transition. The terminal triggers a local wake up (LWU) event on either a low-to-high, or a high-to-low
transition since it has a bi-directional input threshold (falling or rising edge).
This terminal may be used with a switch to VSUP or to ground. If the terminal is unused it should be pulled to
ground or VSUP to avoid unwanted parasitic wake up events.
RBIAS
Low-Side Switch Configuration
RBIAS
High-Side Switch Configuration
VSUP
RSERIES WAKE
Filter
VTH
GND
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Figure 9-6. TCAN1043xx-Q1 WAKE Circuit Example
Figure 9-6 shows two possible configurations for the WAKE terminal, the low-side and high side switch
configurations. The objective of the series resistor, RSERIES, is to protect the WAKE pin of the transceiver from
over current conditions that may occur in the event of a ground shift or ground loss. The minimum value of
RSERIES can be calculated using the maximum supply voltage, VSUPMAX and the maximum allowable current of
the WAKE pin, IIO(WAKE). RSERIES is calculated using:
RSERIES = VSUPMAX / IIO(WAKE)
(2)
If the battery voltage never exceeds 58 V DC, then the RSERIES value is approximately 20 kΩ.
The RBIAS resistor is used to set the static voltage level of the WAKE pin when the switch is not in use. When the
switch is in use in a high-side switch configuration, the RBIAS resistor in combination with the RSERIES resistor
sets the WAKE pin voltage appropriately above the VIH threshold. The maximum value of RBIAS can be
calculated using the maximum supply voltage, VSUPMAX, the maximum WAKE threshold voltage VIH, the
maximum WAKE input current IIH and the series resistor value RSERIES. RBIAS is calculated using:
RBIAS < ((VSUP - VIH) / IIH) - RSERIES
(3)
If the battery voltage never exceed 58 V DC, then the RBIAS resistor value must be less than 60 kΩ.
For lower current consumption, the low-side switch configuration is the ideal architecture.
The LWU circuitry is active in Section 9.4.6, Section 9.4.4 and Section 9.4.5. If a valid LWU event occurs the
device transitions to standby mode. The LWU circuitry is not active in Normal mode or Silent mode.
To minimize system level current consumption, the internal bias voltages of the terminal follows the state on the
terminal with a delay of tWAKE(min). A constant high level on WAKE has an internal pull-up to VSUP and a constant
low level on WAKE has an internal pull-down to GND. This minimizes the current flowing into the WAKE pin
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under these steady-state conditions so that it does not need to be factored into calculations of the total draw
from VSUP.
W ” WWAKEHT
No Wake
UP
Wake
Threshold
Not Crossed
W • WWAKEHT
Wake UP
Wake
Local Wake Request
INH
*
RXD
Mode
Sleep Mode
Standby Mode
The RXD pin is only driven once VIO is present.
Figure 9-7. Local Wake Up – Rising Edge
W ” WWAKEHT
No Wake
UP
Wake
Threshold
Not Crossed
W • WWAKEHT
Wake UP
Wake
Local Wake Request
INH
*
RXD
Mode
Sleep Mode
Standby Mode
The RXD pin is only driven once VIO is present.
Figure 9-8. Local Wake Up – Falling Edge
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9.4.7 Driver and Receiver Function Tables
Table 9-4. Driver Function Table
DEVICE MODE TXD INPUTS(1)
Normal
BUS OUTPUTS(2)
DRIVEN BUS STATE(3)
CANH
CANL
L
H
L
Dominant
H or Open
Z
Z
Common Mode Biased to VCC/2
Silent
X
Z
Z
Common Mode Biased to VCC/2
Standby
X
Z
Z
Common Mode Biased to GND
Go-to-Sleep
X
Z
Z
Common Mode Biased to GND
Sleep
X
Z
Z
Common Mode Biased to GND
(1)
(2)
(3)
H = high level, L = low level, X = irrelevant.
H = high level, L = low level, Z = high Z receiver bias.
For Bus state and bias see Figure 3 and Figure 4.
Table 9-5. Receiver Function Table
DEVICE MODE
CAN DIFFERENTIAL INPUTS
VID = VCANH – VCANL
BUS STATE
RXD TERMINAL(1)
VID ≥ 0.9 V
Dominant
L
0.5 V < VID < 0.9 V
Indeterminat
e
Indeterminate
VID ≤ 0.5 V
Recessive
H
Open (VID ≈ 0 V)
Open
H
VID ≥ 1.15 V
Dominant
VID ≤ 0.4 V
Indeterminat
e
0.5 V < VID < 1.15 V
Recessive
Open (VID ≈ 0 V)
Open
Normal
Standby
VID ≥ 1.15 V
Sleep and Go-toSleep (WUP Monitor)
0.4 V , VIO < 1.15 V
VID ≤ 0.4 V
Open (VID ≈ 0 V)
(1)
H
L if either remote or
local wake events have
occurred
Dominant
H
L if either remote or
Indeterminat
local wake events have
e
occurred andVIO is
Recessive
present.
Tri-State if VIO or VSUP
Open
are not present
H = high level, L = low level
9.4.8 Digital Inputs and Outputs
All devices have a VIO supply that is used to set the digital input thresholds and digital output levels. The input
thresholds are ratio metric to the VIO supply using CMOS input levels, making them scalable for µPs with digital
IOs from 2.8 V to 5 V. The high level output voltages for the RXD and nFAULT output pins are driven to VIO level
for logic high output.
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9.4.9 INH (Inhibit) Output
The inhibit output terminal is used to control system power management devices allowing for extremely low
system current consumption in sleep mode. This terminal can be used to enable and disable local power
supplies. The pin has two states: driven high and high impedance (High Z).
When high (on), the terminal shows VSUP minus a diode voltage drop. In the high impedance state, the output is
left floating. The INH pin is high for normal, silent, Go-to-Sleep, and standby modes. It is low when in sleep
mode.
Note
This terminal should be considered a “high voltage logic” terminal, not a power output thus should be
used to drive the EN terminal of the system’s power management device and not used as a switch for
the power management supply itself. This terminal is not reverse battery protected and thus should
not be connected outside the system module.
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10 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TCAN1043xx-Q1 transceivers are typically used in applications with a host microprocessor or FPGA that
includes the data link layer portion of the CAN protocol. These types of applications usually also include power
management technology that allows for power to be gated to the application via an enable (EN) or inhibit (INH)
pin. A single 5-V regulator can be used to drive both VCC and VIO as shown in Figure 10-1, or independent 5-V
and 3.3-V regulators can be used to drive VCC and V IO separately as shown in Figure 10-2. The bus termination
is shown for illustrative purposes.
10.2 Typical Application
VBATTERY
3.3 k
100 nF
EN
5V V
OUT
Vreg
VIN
100 nF
VIO
VIO
TPSxxx
Port a
Port b
MCU Port c
INH
7
5
9
TCAN1043
nSTB 14
EN
6
nFAULT 8
33 k
VSUP
10
13
WAKE
CANH
11 NC
TMS570
RXD
TXD
RXD
TXD
4
12
1
3
VCC
CANL
2
GND
100 nF
Copyright © 2017, Texas Instruments Incorporated
Figure 10-1. Typical CAN Bus Application Using TCAN1043xx-Q1 with 5 V µC
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VBATTERY
3.3 k
100 nF
EN
3.3 V V
OUT
Vreg
VIN
VIO
TPSxxx
VSUP
WAKE
10
5
9
VIO
TCAN1043
CANH
nSTB 14
13
EN
6
nFAULT 8
11 NC
INH
100 nF
Port a
Port b
MCU Port c
33 k
7
TMS570
RXD
5V
Vreg
TXD
VIN
EN
TPSxxx
RXD
TXD
4
12
1
3
VCC
CANL
2
GND
VOUT
100 nF
Copyright © 2017, Texas Instruments Incorporated
Figure 10-2. Typical CAN Bus Application Using TCAN1043xx-Q1 with 3.3 V µC
10.2.1 Design Requirements
10.2.1.1 Bus Loading, Length and Number of Nodes
A typical CAN application can have a maximum bus length of 40 meters and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1043xx-Q1
family.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading
of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE
J2284, SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In ISO 11898-2 the driver differential output is specified
with a bus load that can range fro 50 Ω to 65 Ω where the differential output must be greater than 1.5 V. The
TCAN1043xx-Q1 family is specified to meet the 1.5-V requirement down to 50 Ω and is specified to meet 1.4-V
differential output at 45Ω bus load. The differential input resistance of the TCAN1043xx-Q1 is a minimum of 30
kΩ. If 100 TCAN1043xx-Q1 transceivers are in parallel on a bus, this is equivalent to a 300-Ω differential load in
parallel with the nominal 60 Ω bus termination which gives a total bus load of 50 Ω. Therefore, the TCAN1043xxQ1 family theoretically supports over 100 transceivers on a single bus segment. However for CAN network
design margin must be given for signal loss across the system and cabling, parasitic loadings, timing, network
imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is much lower. Bus
length may also be extended beyond 40 meters by careful system design and data rate tradeoffs. For example,
CANopen network design guidelines allow the network to be up to 1 km with changes in the termination
resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility
the CAN network system designer must take the responsibility of good network design to ensure robust network
operation.
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10.2.2 Detailed Design Procedures
10.2.2.1 CAN Termination
The ISO11898-2 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded)
with 120 Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be
used to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs)
connecting nodes to the bus should be kept as short as possible to minimize signal reflections. The termination
may be in a node but is generally not recommended, especially if the node may be removed from the bus.
Termination must be carefully placed so that it is not removed from the bus. System level CAN implementations
such as CANopen allow for different termination and cabling concepts for example to add cable length.
Node n
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
TCAN1043HG-Q1
TCAN1043HG-Q1
TCAN1043HG-Q1
(with termination)
MCU or DSP
CAN Controller
TCAN1043HG-Q1
RTERM
RTERM
Figure 10-3. Typical CAN Bus Application
Termination may be a single 120-Ω resistor at the ends of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common mode voltage of the bus is desired then “split termination” may be used,
see Figure 10-4. Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common mode voltage levels at the start and end of message transmissions.
Standard Termination
CANH
Split Termination
CANH
RTERM/2
CAN
Transceiver
RTERM
CAN
Transceiver
CSPLIT
RTERM/2
CANL
CANL
Copyright © 2016, Texas Instruments Incorporated
Figure 10-4. CAN Bus Termination Concepts
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10.2.3 Application Curves
50
ICC Dominant (mA)
40
30
20
10
0
4.5
4.6
4.7
4.8
4.9
5
5.1
VCC (V)
5.2
5.3
5.4
5.5
D005
VCC = 4.5 V to 5.5 V
VIO = 3.3 V
RL = 60 Ω
CL = Open
Temp = 25°C
STB = 0 V
Figure 10-5. ICC Dominant Current over VCC Supply Voltage
11 Power Supply Recommendations
The TCAN1043xx-Q1 device is designed to operate with a main VCC input voltage supply range between 4.5 V
and 5.5 V. The device also has an IO level shifting supply input, VIO , designed for a range between 2.8 V and
5.5 V. To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a
100 nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage
ripple present on the outputs of switched-mode power supplies and also helps to compensate for the resistance
and inductance of the PCB power planes.
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12 Layout
12.1 Layout
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
12.1.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
Place the protection and filtering circuitry close to the bus connector to prevent transients, ESD and noise
from propagating onto the board. In this layout example a transient voltage suppression (TVS) device, D1,
has been shown as added protection. The production solution can be either bi-directional TVS diode or
varistor with ratings matching the application requirements. This example also shows optional bus filter
capacitors C6 and C8. Additionally (not shown) a series common mode choke (CMC) can be placed on the
CANH and CANL lines between the TCAN1043xx-Q1 transceiver and the connector.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
Use supply (VCC) and ground planes to provide low inductance as high-frequency current will follow the path
of least impedance and not the path of least resistance.
Use at least two vias for supply (VCC, VIO, VSUP) and ground connections of bypass capacitors and protection
devices to minimize trace and via inductance.
Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver,
examples are C4 on the VCC supply net, C5 on the VIO supply net and C9 on the VSUP supply net.
Bus termination: this layout example shows split termination. This is where the termination is split into two
resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C7. Split
termination provides common mode filtering for the bus. When bus termination is placed on the board instead
of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the
bus thus also removing the termination. See the application section for information on power ratings needed
for the termination resistor(s).
To limit current of digital lines, series resistors may be used as in R2, R3 and R5 but are not required.
Terminal 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used,
this is mandatory to ensure the bit timing into the device is met.
Terminal 9: SW1 is oriented in a low-side configuration which is used to implement a local WAKE event. The
series resistor R10 is needed for protection against over current conditions as it limits the current into the
WAKE pin when the ECU has lost its ground connection. The pull-up resistor R9 is required to provide
sufficient current during stimulation of a WAKE event. See the application section for more information on
calculating both the R9 and R10 values.
Terminal 14: Is shown assuming the mode terminal, nSTB, is used. If the device is only be used in normal
mode, R5 is not needed and R4 could be used for the pull-up resistor to VIO
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12.2 Layout Example
R1
R2
VIO
VIO
CAN Controller
1
TXD
nSTB
14
R4
R5
2
GND
CANH
13
R6
CANL
12
R7
NC
11
VSUP
10
TCAN1043HG-Q1
C7
VCC
4
RXD
5
VIO
C8
3
Connector
VCC
D1
C4
C6
CAN Controller
R8
C9
C5
VIO
CAN Controller
6
EN
Regulator EN
7
INH
WAKE
9
nFAULT
8
VBAT
R9
R3
CAN Controller
SW1
LOCAL
WAKE
R10
GND
CAN Controller
Figure 12-1. TCAN1043xx-Q1 Layout Example
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 13-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TCAN1043-Q1
Click here
Click here
Click here
Click here
Click here
TCAN1043H-Q1
Click here
Click here
Click here
Click here
Click here
TCAN1043HG-Q1
Click here
Click here
Click here
Click here
Click here
TCAN1043G-Q1
Click here
Click here
Click here
Click here
Click here
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
13.4 Trademarks
All trademarks are the property of their respective owners.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DMT0014A
VSON - 0.9 mm max height
SCALE 3.200
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
SECTION A-A
SECTION A-A
SCALE 30.000
TYPICAL
C
0.9 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.6 0.1
EXPOSED
THERMAL PAD
SYMM
(0.2) TYP
7
8
A
2X
3.9
A
15
SYMM
4.2 0.1
14
1
12X 0.65
PIN 1 ID
(OPTIONAL)
14X
0.45
0.35
14X
0.35
0.25
0.1
0.05
C A B
C
4223033/B 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DMT0014A
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
14X (0.6)
SYMM
14X (0.3)
1
14
2X
(1.85)
12X (0.65)
15
SYMM
(4.2)
(0.69)
TYP
( 0.2) VIA
TYP
8
7
(R0.05) TYP
(0.55) TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223033/B 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DMT0014A
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.47)
14X (0.6)
1
15
14
14X (0.3)
(1.18)
12X (0.65)
SYMM
(1.38)
(R0.05) TYP
METAL
TYP
8
7
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
77.4% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4223033/B 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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3-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TCAN1043DMTRQ1
ACTIVE
VSON
DMT
14
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-55 to 125
1043
TCAN1043DMTTQ1
ACTIVE
VSON
DMT
14
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-55 to 125
1043
TCAN1043DQ1
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
1043
TCAN1043DRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
1043
TCAN1043GDMTRQ1
ACTIVE
VSON
DMT
14
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-55 to 125
1043
TCAN1043GDMTTQ1
ACTIVE
VSON
DMT
14
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-55 to 125
1043
TCAN1043GDQ1
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
1043
TCAN1043GDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
1043
TCAN1043HDMTRQ1
ACTIVE
VSON
DMT
14
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-55 to 125
1043
TCAN1043HDMTTQ1
ACTIVE
VSON
DMT
14
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-55 to 125
1043
TCAN1043HDQ1
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
1043
TCAN1043HDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
1043
TCAN1043HGDMTRQ1
ACTIVE
VSON
DMT
14
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-55 to 125
1043
TCAN1043HGDMTTQ1
ACTIVE
VSON
DMT
14
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-55 to 125
1043
TCAN1043HGDQ1
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
1043
TCAN1043HGDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
1043
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Dec-2021
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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