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TDP142
SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019
TDP142 DisplayPortTM 8.1 Gbps Linear Redriver
1 Features
3 Description
•
•
•
•
•
•
•
The TDP142 is a DisplayPortTM(DP) linear redriver
that is able to snoop AUX and HPD signals. The
device complies with the VESA DisplayPort standard
Version 1.4, and supports a 1-4 lane Main Link
interface signaling up to HBR3 (8.1 Gbps per lane).
Additionally, this device is position independent. It
can be placed inside source, cable or sink effectively
providing a "negative loss" component to the overall
link budget.
1
•
•
•
DisplayPort™ 1.4 up to 8.1 Gbps (HBR3)
Ultra-low-power architecture
Linear redriver with up to 14 dB equalization
Transparent to DisplayPort link training
Configuration through GPIO or I2C
Hot-Plug capable
Support DisplayPort dual-mode standard version
1.1 (AC-coupled HDMI)
Industrial temperature range: -40ºC to 85ºC
(TDP142I)
Commercial temperature range: 0ºC to 70ºC
(TDP142)
4 mm x 6 mm, 0.4 mm Pitch WQFN package
The TDP142 provides several levels of receive linear
equalization to compensate for cable and board trace
loss due to inter symbol interference (ISI). Operates
on a single 3.3 V supply and comes in a commercial
temperature
range
(TDP142)
and
industrial
temperature range (TDP142I).
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
Tablets, notebooks, desktops, PC
Active cables
Monitors
Docking stations
PACKAGE
BODY SIZE (NOM)
TDP142
WQFN (40)
4.00 mm x 6.00 mm
TDP142I
WQFN (40)
4.00 mm x 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACER
Simplified Schematics
Display
ML0_IN
ML0_OUT
ML1_IN
ML1_OUT
ML2_IN
ML2_OUT
TDP142
x
GPU
ML3_IN
ML3_OUT
DP
Receptacle
GPU
TDP142
TDP142
Scaler
AUX
HPD
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TDP142
SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
5
5
5
5
6
6
7
8
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Supply Characteristics ...................................
DC Electrical Characteristics ....................................
AC Electrical Characteristics.....................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
12
13
15
17
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Revision B (August 2018) to Revision C
•
Page
Added following to pin 11 description: If I2C_EN = “F”, then this pin must be set to “F” or “0”. ........................................... 3
Changes from Revision A (October 2017) to Revision B
Page
•
Changed the appearance of the pinout image in the Pin Configuration and Function section .............................................. 3
•
Added Note 2 To pins 29 and 32 in the Pin Functions table.................................................................................................. 4
Changes from Original (September 2017) to Revision A
•
2
Page
Changed the Human-body model (HBM) value From: ±6000 To: ±5000 in the ESD Ratings ............................................... 5
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SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019
5 Pin Configuration and Functions
OUTDP0p
OUTDP0n
RSVD11
OUTDP1p
OUTDP1n
RSVD10
OUTDP2n
OUTDP2p
HPDIN/RSVD9
OUTDP3n
OUTDP3p
SNOOPENZ/RSVD8
40
39
38
37
36
35
34
33
32
31
30
29
RNQ Package
40-Pin (WQFN)
Top View
VCC
1
28
VCC
DPEQ1
2
27
RSVD7
RSVD1
3
26
RSVD6
RSVD2
4
25
AUXn
24
AUXp
Thermal
Pad
21
TEST1/SCL
VCC
INDP3n
INDP3p
I2C_EN
INDP2n
INDP2p
DPEQ0/A1
INDP1n
INDP1p
A0
INDP0n
INDP0p
20
8
19
RSVD5
18
TEST2/SDA
17
22
16
7
15
RSVD4
14
DPEN/HPDIN
13
23
12
6
11
VCC
10
5
9
RSVD3
Not to scale
Pin Functions
PIN
NAME
VCC
NO.
I/O
DESCRIPTION
1, 6, 20, 28
P
DPEQ1
2
4 Level I
RSVD1
3
I
Reserved. (1)
RSVD2
4
O
Reserved. (1)
RSVD3
5
O
Reserved. (1)
RSVD4
7
I
Reserved. (1)
RSVD5
8
I
Reserved. (1)
INDP0p
9
I
DP Differential positive input for DisplayPort Lane 0.
INDP0n
10
I
DP Differential negative input for DisplayPort Lane 0.
A0
11
4 Level I
INDP1p
12
Diff I
DP Differential positive input for DisplayPort Lane 1.
INDP1n
13
Diff I
DP Differential negative input for DisplayPort Lane 1.
DPEQ0/A1
14
4 Level I
INDP2p
15
Diff I
DP Differential positive input for DisplayPort Lane 2.
INDP2n
16
Diff I
DP Differential negative input for DisplayPort Lane 2.
(1)
3.3-V Power Supply.
DisplayPort Receiver EQ control. This along with DPEQ0 will select the DisplayPort receiver
equalization gain. Refer to Table 2 for equalization settings.
When I2C_EN = 0, leave the pin unconnected. When I2C_EN is not ‘0’, this pin will also set the
TDP142 I2C address. See Table 4. If I2C_EN = “F”, then this pin must be set to “F” or “0”.
DisplayPort Receiver EQ control. This along with DPEQ1 will select the DisplayPort receiver
equalization gain. Refer to Table 2 for equalization settings. When I2C_EN is not ‘0’, this pin will
also set the TDP142 I2C address. See Table 4.
Leave unconnected on PCB.
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Pin Functions (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled).
R = TI Test Mode (I2C enabled at 3.3 V).
F = I2C enabled at 1.8 V.
1 = I2C enabled at 3.3 V.
I2C_EN
17
4 Level I
INDP3p
18
Diff I
DP Differential positive input for DisplayPort Lane 3.
INDP3n
19
Diff I
DP Differential negative input for DisplayPort Lane 3.
TEST1/SCL
21
2 Level I
When I2C_EN=’0’, pull down with 10k or directly connect to ground. Otherwise this pin is I2C
clock. . When used for I2C clock pullup to I2C master's VCC I2C supply.
TEST2/SDA
22
2 Level I
When I2C_EN=’0’ , pull down with 10k or directly connect to ground. Otherwise this pin is I2C data.
When used for I2C data pullup to I2C master's VCC I2C supply.
DP Enable Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort functionality.
Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled through I2C
registers.
L = DisplayPort Disabled. (Pull-down with 10k resistor)
H = DisplayPort Enabled. (Pull-up with10k resistor)
When I2C_EN is not "0" this pin is an input for Hot Plug Detect (HPD) received from DisplayPort
sink. When this HPDIN is low for greater than 2 ms, all DisplayPort lanes are disabled.
DPEN/HPDIN
23
2 Level I
(Failsafe)
(PD)
AUXp
24
I/O, CMOS
This pin along with AUXN is used by the TDP142 for AUX snooping. See the Application and
Implementation section for more detail.
AUXn
25
I/O, CMOS
This pin along with AUXP is used by the TDP142 for AUX snooping. See the Application and
Implementation section for more detail.
RSVD6
26
I/O, CMOS
Reserved. (1)
RSVD7
27
I/O, CMOS
Reserved. (1)
29 (2)
I/O
(PD)
When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0 , this pin is SNOOPENZ (L = AUX
snoop enabled and H = AUX snoop disabled with all lanes active).
OUTDP3p
30
Diff O
DP Differential positive output for DisplayPort Lane 3.
OUTDP3n
31
Diff O
DP Differential negative output for DisplayPort Lane 3.
32 (2)
I/O
(PD)
When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0, this pin is an input for Hot Plug Detect
received from DisplayPort sink. When HPDIN is low for greater than 2ms, all DisplayPort lanes are
disabled.
OUTDP2p
33
Diff O
DP Differential positive output for DisplayPort Lane 2.
OUTDP2n
34
Diff O
DP Differential negative output for DisplayPort Lane 2.
RSVD10
35
I
OUTDP1n
36
Diff O
DP Differential negative output for DisplayPort Lane 1.
OUTDP1p
37
Diff O
DP Differential positive output for DisplayPort Lane 1.
RSVD11
38
I
OUTDP0n
39
Diff O
DP Differential negative output for DisplayPort Lane 0.
OUTDP0p
40
Diff O
DP Differential positive output for DisplayPort Lane 0.
Thermal Pad
G
SNOOPENZ/RSVD8
HPDIN/RSVD9
GND
(2)
4
Reserved. (1)
Reserved. (1)
Ground.
Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
4
V
Differential voltage between positive and
negative inputs
–2.5
2.5
V
Voltage at differential inputs
–0.5
VCC + 0.5
V
CMOS Inputs
–0.5
VCC + 0.5
V
125
°C
150
°C
Supply Voltage Range (2), VCC
Voltage Range at any input or output pin
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±5000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Main power supply
VCC
MIN
NOM
MAX
3
3.3
3.6
V
100
ms
Supply Ramp Requirement
V(12C)
Supply that external resistors are pulled up to on SDA and SCL
V(PSN)
Supply Noise on VCC pins
TA
Operating free-air temperature
1.7
UNIT
3.6
V
100
mV
TDP142
0
70
°C
TDP142I
–40
85
°C
6.4 Thermal Information
TDP142
THERMAL METRIC (1)
RNQ (WQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
37.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.7
°C/W
RθJB
Junction-to-board thermal resistance
9.5
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
9.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Power Supply Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
PCC(ACTIVE--DP)
Average active power
4 Lane DP Only
Four active DP lanes operating at
8.1 Gbps;
DPEN = H; TEST2 = L;
PCC(NC)
Average power with no connection
No device is connected
PCC(SHUTDOWN)
Device Shutdown
DPEN = L; TEST2 = L; I2C_EN = 0;
MIN
TYP
MAX
UNIT
660
mW
2.4
mW
0.85
mW
6.6 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4-State CMOS Inputs(DPEQ[1:0], I2C_EN)
IIH
High level input current
VCC = 3.6 V; VIN = 3.6 V
IIL
Low level input current
VCC = 3.6 V; VIN = 0 V
Threshold 0 / R
VCC = 3.3 V
0.55
V
Threshold R/ Float
VCC = 3.3 V
1.65
V
Threshold Float / 1
VCC = 3.3 V
2.7
V
4-Level VTH
20
80
µA
–160
-40
µA
RPU
Internal pull-up resistance
35
kΩ
RPD
Internal pull-down resistance
95
kΩ
2-State CMOS Input (DPEN, Test1, Test2, SNOOPENZ, HPDIN) DPEN, TEST1 and TEST2 are Failsafe.
VIH
High-level input voltage
2
3.6
VIL
Low-level input voltage
0
0.8
V
RPD
Internal pull-down resistance for DPEN
500
kΩ
R(ENPD)
Internal pull-down resistance for
SNOOPENZ (pin 29), and HPDIN (pin
32)
150
kΩ
IIH
High-level input current
VIN = 3.6 V
–25
25
µA
IIL
Low-level input current
VIN = GND, VCC = 3.6 V
–25
25
µA
V
I2C Control Pins SCL, SDA
VIH
High-level input voltage
I2C_EN = 0
0.7 x V(I2C)
3.6
V
VIL
Low-level input voltage
I2C_EN = 0
0
0.3 x V(I2C)
V
VOL
Low-level output voltage
I2C_EN = 0; IOL = 3 mA
0
0.4
IOL
Low-level output current
I2C_EN = 0; VOL = 0.4 V
20
II(I2C)
Input current on SDA pin
0.1 x V(I2C) < Input voltage < 3.3 V
CI(I2C)
Input capacitance
C(I2C_FM+_BUS)
V
mA
10
µA
10
pF
I2C bus capacitance for FM+ (1MHz)
150
pF
C(I2C_FM_BUS)
I2C bus capacitance for FM (400kHz)
150
pF
R(EXT_I2C_FM+)
External resistors on both SDA and SCL
when operating at FM+ (1MHz)
C(I2C_FM+_BUS) = 150 pF
620
820
910
Ω
R(EXT_I2C_FM)
External resistors on both SDA and SCL
when operating at FM (400kHz)
C(I2C_FM_BUS) = 150 pF
620
1500
2200
Ω
6
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6.7 AC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DisplayPort Transmitter (OUTDP[3:0]p or OUTDP[3:0]n)
VTX(DIFF-PP)
Transmitter dynamic differential voltage swing range.
VTX(RCV-DETECT)
Amount of voltage change allowed during receiver detection
1500
mVPP
600
mV
100
mVPP
VTX(CM-AC-PP-ACTIVE)
Tx AC common-mode voltage active
Max mismatch from Txp + Txn for both
time and amplitude
VTX(IDLE-DIFF-AC-PP)
AC electrical idle differential peak-topeak output voltage
At package pins
0
10
mV
VTX(IDLE-DIFF-DC)
DC electrical idle differential output
voltage
At package pins after low pass filter to
remove AC component
0
14
mV
RTX(DIFF)
Differential impedance of the driver
75
120
Ω
CAC(COUPLING)
AC coupling capacitor
75
265
nF
RTX(CM)
Common-mode impedance of the
driver
Measured with respect to AC ground
over
0–500 mV
18
30
Ω
CTX(PARASITIC)
TX input capacitance for return loss
At package pins, at 2.5GHz
1.25
pF
RLTX(DIFF)
Differential return loss
RLTX(CM)
50 MHz – 1.25 GHz at 90 Ω
-15
dB
2.5 GHz at 90 Ω
-12
dB
Common-mode return loss
50 MHz – 2.5 GHz at 90 Ω
-13
ITX(SHORT)
TX short circuit current
TX± shorted to GND
VTX(DC-CM)
Common-mode voltage bias in the transmitter (DC)
0
dB
67
mA
0
V
AC Characteristics
Crosstalk
Differential crosstalk between TX and
RX signal pairs
at 2.5 GHz
C(P1dB-LF)
Low frequency 1-dB compression
point
C(P1dB-HF)
fLF
–30
dB
at 100 MHz, 200 mVPP < VID
< 2000 mVPP
1300
mVPP
High frequency 1-dB compression
point
at 2.5 GHz, 200 mVPP < VID
< 2000 mVPP
1300
mVPP
Low frequency cutoff
200 mVPP< VID < 2000 mVPP
TX output deterministic jitter
TX output total jitter
20
50
kHz
200 mVPP < VID < 2000 mVPP, PRBS7,
5 Gbps
0.05
UIpp
200 mVPP < VID < 2000 mVPP, PRBS7,
8.1 Gbps
0.08
UIpp
200 mVPP < VID < 2000 mVPP, PRBS7,
5 Gbps
0.08
UIpp
200 mVPP < VID < 2000 mVPP, PRBS7,
8.1 Gbps
0.135
UIpp
DisplayPort Receiver (INDP[3:0]p or INDP[3:0]n)
VID(PP)
Peak-to-peak input differential dynamic voltage range
VIC
Input common mode voltage
2000
V
C(AC)
AC coupling capacitance
EQ(DP)
Receiver equalization
DPEQ[1:0] at 4.05 GHz
14
dB
dR
Data rate
HBR3
8.1
Gbps
R(ti)
Input termination resistance
120
Ω
0
2
V
75
200
nF
80
100
AUXp or AUXn
V(AUXP_DC_CM)
AUX Channel DC common mode
voltage for AUXp
VCC = 3.3 V
0
0.4
V
V(AUXN_DC_CM)
AUX Channel DC common mode
voltage for AUXn
VCC = 3.3 V
2.7
3.6
V
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6.8 Timing Requirements
MIN
tDIFF_DLY
Differential Propagation Delay
See Figure 7
tR, tF
Output Rise/Fall time (see Figure 9)
20%-80% of differential
voltage measured 1 inch
from the output pin
tRF_MM
Output Rise/Fall time mismatch
20%-80% of differential
voltage measured 1 inch
from the output pin
NOM
MAX
UNIT
300
ps
40
ps
2.6
ps
6.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DPEN and HPDIN
tDPEN_DEBOUNCE
DPEN and HPDIN debounce time when transitioning from H to L.
2
10
ms
1
MHz
I2C (Refer to Figure 6)
fSCL
I2C clock frequency
tBUF
Bus free time between START and STOP conditions
tHDSTA
Hold time after repeated START condition. After this period, the first
clock pulse is generated
tLOW
Low period of the I2C clock
2
0.5
µs
0.26
µs
0.5
µs
tHIGH
High period of the I C clock
0.26
µs
tSUSTA
Setup time for a repeated START condition
0.26
µs
tHDDAT
Data hold time
0
μs
tSUDAT
Data setup time
50
tR
Rise time of both SDA and SCL signals
tF
Fall time of both SDA and SCL signals
tSUSTO
Setup time for STOP condition
Cb
Capacitive load for each bus line
8
20 × (V(I2C)/5.5
V)
ns
120
ns
120
ns
150
pF
0.26
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6.10 Typical Characteristics
15
1.6
1.4
Differential Output Voltage (V)
10
SDD21 (dB)
5
0
-5
-10
-15
0.01
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
1.2
1
0.8
0.6
0.4
EQ0
EQ1
EQ2
EQ3
0.2
1
Frequency (GHz)
10
0
0.2
0.4
D001
Figure 1. DisplayPort EQ Settings Curves
EQ12
EQ13
EQ14
EQ15
0.6 0.8
1
1.2 1.4
Differential Input Voltage (V)
1.6
1.8
2
D004
Figure 2. DisplayPort Linearity Curves at 4.05 GHz
0
0
-5
-5
-10
OUT DP0
OUT DP1
OUT DP2
OUT DP3
-10
SD22 (dB)
SDD11 (dB)
EQ8
EQ9
EQ10
EQ11
0
0.1
5
-15
-20
-25
-15
-20
DP0
DP1
DP2
DP3
-30
-35
-40
0.01
EQ4
EQ5
EQ6
EQ7
0.1
1
Frequency (GHz)
10
-25
-30
0.01
20
D003
1
Frequency (GHz)
10
20
D004
Figure 4. Output Return Loss Performance
Output Voltage (75 mV/Div)
Figure 3. Input Return Loss Performance
0.1
Time (20.57 ps/Div)
Figure 5. DisplayPort HBR3 Eye-Pattern Performance with 12-inch Input PCB Trace at 8.1 Gbps
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7 Parameter Measurement Information
70%
SDA
30%
tR
tLOW
tBUF
tHIGH
tHDSTA
tF
70%
SCL
P
30%
S
S
tHDDAT
tHDSTA
P
tSUDAT
tSUSTA
tSUSTO
Figure 6. I2C Timing Diagram Definitions
IN
TDIFF_DLY
TDIFF_DLY
OUT
Figure 7. Propagation Delay
IN+
VRX-LFPS-DET-DIFF-PP
Vcm
INTIDLEExit
TIDLEEntry
OUT+
Vcm
OUT-
Figure 8. Electrical Idle Mode Exit and Entry Delay
80%
20%
tr
tf
Figure 9. Output Rise and Fall Times
10
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8 Detailed Description
8.1 Overview
The TDP142 is a DisplayPortTM linear re-driver that supports up to 8.1 Gbps for each lane. Additionally, its
transparency to the DP link training makes TDP142 a position independent device, suitable for source/sink or
cable application.
The TDP142 helps the system to pass compliance of both transmitter and receiver for DisplayPort version 1.4
HBR3. The re-driver recovers incoming data by applying equalization that compensates for channel loss, and
drives out signals with a high differential voltage. Each channel has a receiver equalizer with selectable gain
settings. The equalization should be set based on the amount of insertion loss before the TDP142 receivers. The
equalization control can be controlled by DPEQ[1:0] pins or I2C registers.
The device ultra-low-power architecture operates at a 3.3-V power supply and achieves enhanced performance.
Also, it comes in a commercial temperature range and industrial temperature range.
8.2 Functional Block Diagram
INDP0n
OUTDP0p
Driver
EQ
Term
Term
INDP0p
OUTDP0n
DPEQ_SEL
INDP1p
Term
Term
OUTDP1p
Driver
EQ
INDP1n
OUTDP1n
DPEQ_SEL
OUTDP2p
INDP2n
EQ
Driver
EQ
Driver
Term
Term
INDP2p
OUTDP2n
DPEQ_SEL
INDP3p
Term
Term
OUTDP3p
INDP3n
OUTDP3n
DPEQ_SEL
DPEQ_SEL
DPEQ0/A1
DPEQ1
A0
I2C_EN
TEST1/SCL
TEST2/SDA
Control Logic and Registers
HPDIN/RSVD9
I2C
Slave
SNOOPENZ/RSVD8
DPEN/HPDIN
AUXp
AUXn
VCC
AUX
Snooping
VREG
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8.3 Feature Description
8.3.1 DisplayPort
The TDP142 supports up to 4 DisplayPort lanes at data rates up to 8.1Gbps (HBR3). The TDP142 monitors the
native AUX traffic as it traverses between DisplayPort source and DisplayPort sink. For the purposes of reducing
power, the TDP142 manages the number of active DisplayPort lanes based on the content of the AUX
transactions. The TDP142 snoops native AUX writes to DisplayPort sink’s DPCD registers 0x00101
(LANE_COUNT_SET) and 0x00600 (SET_POWER_STATE). TDP142 disables/enables lanes based on value
written to LANE_COUNT_SET. The TDP142 disables all lanes when SET_POWER_STATE is in the D3.
Otherwise active lanes will be based on value of LANE_COUNT_SET.
DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE
register. Once AUX snoop is disabled, management of TDP142 DisplayPort lanes are controlled through various
configuration registers. When TDP142 is enabled for GPIO mode (I2C_EN = "0"), the SNOOPENZ pin can be
used to disable AUX snooping. When SNOOPENZ pin is high, the AUX snooping functionality is disabled and all
four DisplayPort lanes will be active.
8.3.2 4-level Inputs
The TDP142 has (I2C_EN, A0, and DPEQ[1:0]) 4-level inputs pins that are used to control the equalization gain
and place TDP142 into different modes of operation. These 4-level inputs utilize a resistor divider to help set the
4 valid levels and provide a wider range of control settings. There are internal pull-up and pull-down and combine
with the external resistor connection to achieve the desired voltage level.
Table 1. 4-Level Control Pin Settings
LEVEL
SETTINGS
0
Option 1: Tie 1 kΩ 5% to GND.
Option 2: Tie directly to GND.
R
Tie 20 kΩ 5% to GND.
F
Float (leave pin open)
1
Option 1: Tie 1 kΩ 5% to VCC.
Option 2: Tie directly to VCC.
spacer
NOTE
All four-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal
pull-up and pull-down resistors will be isolated in order to save power.
8.3.3 Receiver Linear Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system before the input of the TDP142. The receiver overcomes these losses by attenuating the low
frequency components of the signals with respect to the high frequency components. The proper gain setting
should be selected to match the channel insertion loss before the input of the TDP142 receivers. Two 4-level
inputs pins enable up to 16 possible equalization settings. The TDP142 also provides the flexibility of adjusting
settings through I2C registers.
12
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8.4 Device Functional Modes
8.4.1 Device Configuration in GPIO Mode
The TDP142 is in GPIO configuration when I2C_EN = “0”. The DPEN pin controls whether DisplayPort is
enabled and SNOOPENZ pin controls whether AUX snoop mode is enabled.
8.4.2 Device Configuration In I2C Mode
The TDP142 is in I2C mode when I2C_EN is not equal to “0”. The same configurations defined in GPIO mode
are also available in I2C mode. The TDP142 DisplayPort configuration is programmed based on the
Programming section .
8.4.3 Linear EQ Configuration
The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 2
details the gain value for each available combination when TDP142 is in GPIO mode. The I2C mode can do the
same option or even individual lane EQ setting by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL,
and DP3EQ_SEL.
Table 2. TDP142 Receiver Equalization GPIO Control
ALL DISPLAYPORT LANES
Equalization Setting #
DPEQ1 PIN LEVEL
DPEQ0 PIN LEVEL
EQ GAIN at 4.05 GHz (dB)
0
0
0
1.0
1
0
R
3.3
2
0
F
4.9
3
0
1
6.5
4
R
0
7.5
5
R
R
8.6
6
R
F
9.5
7
R
1
10.4
8
F
0
11.1
9
F
R
11.7
10
F
F
12.3
11
F
1
12.8
12
1
0
13.2
13
1
R
13.6
14
1
F
14.0
15
1
1
14.4
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8.4.4 Operation Timing – Power Up
TDP142
VCC
Internal
Power Good
td_pg
tcfg_su
tcfg_hd
CFG pins
Figure 10. Power-Up Timing
Table 3. Power-Up Timing (1) (2)
PARAMETER
MIN
MAX
UNIT
500
µs
td_pg
VCC (minimum) to Internal Power Good asserted high
tcfg_su
CFG(1) pins setup(2)
50
µs
tcfg_hd
CFG(1) pins hold
10
µs
tVCC_RAMP
VCC supply ramp requirement
(1)
(2)
14
100
ms
Following pins comprise CFG pins: I2C_EN, DPEQ[1:0].
Recommend CFG pins are stable when VCC is at min.
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8.5 Programming
For further programmability, the TDP142 can be controlled using I2C. When I2C_EN !=0, the SCL and SDA pins
are used for I2C clock and I2C data respectively.
Table 4. TDP142 I2C Target Address
DPEQ0/A1
PIN LEVEL
A0
PIN LEVEL
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
0
0
1
0
0
0
1
0
0
0/1
0
R
1
0
0
0
1
0
1
0/1
0
F
1
0
0
0
1
1
0
0/1
0
1
1
0
0
0
1
1
1
0/1
R
0
0
1
0
0
0
0
0
0/1
R
R
0
1
0
0
0
0
1
0/1
R
F
0
1
0
0
0
1
0
0/1
R
1
0
1
0
0
0
1
1
0/1
F
0
0
0
1
0
0
0
0
0/1
F
R
0
0
1
0
0
0
1
0/1
F
F
0
0
1
0
0
1
0
0/1
F
1
0
0
1
0
0
1
1
0/1
1
0
0
0
0
1
1
0
0
0/1
1
R
0
0
0
1
1
0
1
0/1
1
F
0
0
0
1
1
1
0
0/1
1
1
0
0
0
1
1
1
1
0/1
The following procedure should be followed to write to TDP142 I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the TDP142 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TDP142 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TDP142) to be written, consisting of one byte of
data, MSB-first.
4. The TDP142 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TDP142 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TDP142.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the TDP142 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the TDP142 7-bit
address and a one-value “W/R” bit to indicate a read cycle.
2. The TDP142 acknowledges the address cycle.
3. The TDP142 transmit the contents of the memory registers MSB-first starting at register 00h or last read subaddress+1. If a write to the T I2C register occurred prior to the read, then the TDP142 shall start at the subaddress specified in the write.
4. The TDP142 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after
each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TDP142 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
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The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the TDP142 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TDP142 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TDP142) to be written, consisting of one byte of
data, MSB-first.
4. The TDP142 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
NOTE
If no sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation. If a I2C address write occurred prior to the read, then the reads start at the
sub-address specified by the address write.
Table 5. Register Legend
16
ACCESS TAG
NAME
MEANING
R
Read
The field may be read by software
W
Write
The field may be written by software
S
Set
C
Clear
U
Update
NA
No Access
The field may be set by a write of one. Writes of zeros to the field have no effect.
The field may be cleared by a write of one. Write of zero to the field have no effect.
Hardware may autonomously update this field.
Not accessible or not applicable
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8.6 Register Maps
8.6.1 General Register (address = 0x0A) [reset = 00000001]
Figure 11. General Registers
7
Reserved
6
5
SWAP_HPDIN
R
R/W
4
EQ_OVERRID
E
R/W
3
HPDIN_OVRRI
DE
R/W
2
Reserved.
1
0
CTLSEL[1:0].
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. General Registers
Bit
Field
Type
Reset
Description
7:6
Reserved
R
00
Reserved.
SWAP_HPDIN
R/W
0
0 – HPDIN is in default location (Default)
1 – HPDIN location is swapped (PIN 23 to PIN 32, or PIN 32 to
PIN 23).
5
4
EQ_OVERRIDE
R/W
0
Setting of this field will allow software to use EQ settings from
registers instead of value sample from pins.
0 – EQ settings based on sampled state of the EQ pins
(DPEQ[1:0]).
1 – EQ settings based on programmed value of each of the EQ
registers
3
HPDIN_OVRRIDE
R/W
0
0 – HPD based on state of HPDIN pin (Default)
1 – HPD high.
2
Reserved
R/W
0
Reserved.
01
Upon power-on, software must write 2'b10 to enable DisplayPort
functionality. If DisplayPort functionality is not required, then
software must write 2'b00 to disable DisplayPort.
00 - Shutdown. DP disabled and lowest power state.
01 - DP disabled but not in lowest power state.
10 - DP enabled
11 - Reserved.
1:0
CTLSEL[1:0]
R/W
8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
Figure 12. DisplayPort Control/Status Registers (0x10)
7
6
5
4
3
DP1EQ_SEL
R/W/U
2
1
0
DP0EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. DisplayPort Control/Status Registers (0x10)
Bit
7:4
3:0
Field
DP1EQ_SEL
DP0EQ_SEL
Type
R/W/U
R/W/U
Reset
Description
0000
Field selects between 0 to 14dB of EQ for DP lane 1. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 1 based on value written to
this field.
0000
Field selects between 0 to 14dB of EQ for DP lane 0. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 0 based on value written to
this field.
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8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
Figure 13. DisplayPort Control/Status Registers (0x11)
7
6
5
4
3
2
DP3EQ_SEL
R/W/U
1
0
DP2EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. DisplayPort Control/Status Registers (0x11)
Bit
7:4
3:0
Field
Type
DP3EQ_SEL
R/W/U
DP2EQ_SEL
R/W/U
Reset
Description
0000
Field selects between 0 to 14dB of EQ for DP lane 3. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 3 based on value written to
this field.
0000
Field selects between 0 to 14dB of EQ for DP lane 2. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 2 based on value written to
this field.
8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
Figure 14. DisplayPort Control/Status Registers (0x12)
7
Reserved
R
6
5
SET_POWER_STATE
RU
4
3
2
LANE_COUNT_SET
RU
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. DisplayPort Control/Status Registers (0x12)
Bit
7
6:5
4:0
18
Field
Type
Reset
Description
Reserved
R
0
Reserved.
00
This field represents the snooped value of the AUX write to
DPCD address 0x00600. When AUX_SNOOP_DISABLE = 1’b0,
the TDP142 will enable/disable DP lanes based on the snooped
value. When AUX_SNOOP_DISABLE = 1’b1, then DP lane
enable/disable are determined by state of DPx_DISABLE
registers, where x = 0, 1, 2, or 3. This field is reset to 2’b00 by
hardware when CTLSEL1 registers changes from a 1’b1 to a
1’b0.
00000
This field represents the snooped value of AUX write to DPCD
address 0x00101 register. When AUX_SNOOP_DISABLE =
1’b0, TDP142 will enable DP lanes specified by the snoop value.
Unused DP lanes will be disabled to save power. When
AUX_SNOOP_DISABLE = 1’b1, then DP lanes enable/disable
are determined by DPx_DISABLE registers, where x = 0, 1, 2, or
3. This field is reset to 0x0 by hardware when CTLSEL1 register
changes from a 1’b1 to a 1’b0.
SET_POWER_STATE
LANE_COUNT_SET
R/U
R/U
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8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
Figure 15. DisplayPort Control/Status Registers (0x13)
7
AUX_SNOOP_
DISABLE
R/W
6
Reserved
5
4
AUX_SBU_OVR
3
DP3_DISABLE
2
DP2_DISABLE
1
DP1_DISABLE
0
DP0_DISABLE
R
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. DisplayPort Control/Status Registers (0x13)
Bit
Field
Type
Reset
Description
7
AUX_SNOOP_DISABLE
R/W
0
0 – AUX snoop enabled. (Default)
1 – AUX snoop disabled.
6
Reserved
R
0
Reserved.
5:4
Reserved
R/W
00
Reserved.
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 3. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 3
functionality.
0 – DP Lane 3 Enabled (default)
1 – DP Lane 3 Disabled.
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 2. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 2
functionality.
0 – DP Lane 2 Enabled (default)
1 – DP Lane 2 Disabled.
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 1. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 1
functionality.
0 – DP Lane 1 Enabled (default)
1 – DP Lane 1 Disabled.
0
DISABLE. When AUX_SNOOP_DISABLE = 1’b1, this field can
be used to enable or disable DP lane 0. When
AUX_SNOOP_DISABLE = 1’b0, changes to this field will have
no effect on lane 0 functionality.
0 – DP Lane 0 Enabled (default)
1 – DP Lane 0 Disabled.
3
2
1
0
DP3_DISABLE
DP2_DISABLE
DP1_DISABLE
DP0_DISABLE
R/W
R/W
R/W
R/W
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TDP142 is a linear redriver designed specifically to compensate the inter-symbol interference (ISI) jitter
caused by signal attenuation through a passive medium like PCB traces and cable. It can be used in Source,
Sink, and cable applications, where the device is transparent to the link training. For illustrating purposes, this
section shows the implementations of Source application and Sink application. Figure 16 and Figure 17 are the
high level block diagram for DisplayPort Source side application and DisplayPort Sink side application
respectively, where the TDP142 is snooping both channels of AUX signal and HPD signal.
PCB trace of Length B
PCB trace of Length A
ML0_IN
ML0_OUT
ML1_IN
ML1_OUT
ML2_OUT
TDP142
ML2_IN
ML3_OUT
ML3_IN
GPU
DP
Receptacle
3.3 V
AUX
HPD
3.3 V
Power
Source
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Figure 16. Source Application for TDP142
20
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Application Information (continued)
PCB trace of Length D
PCB trace of Length C
ML0_OUT
ML0_IN
ML1_OUT
ML1_IN
ML2_OUT
TDP142
ML2_IN
ML3_OUT
ML3_IN
DP
Receptacle
Scaler
3.3 V
AUX
HPD
3.3 V
Power
Source
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Figure 17. The Implementation of Sink Application
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9.2 Typical Application
9.2.1 Source Application Implementation
Figure 18 shows the schematic for the Source side application. The TDP142 is placed between the DisplayPort
Graphics Processor Unit (GPU) and the DisplayPort receptacle. The TDP142 monitors AUX traffic for power
management purposes when SNOOPENZ is low.
3P3V
C1
10uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
3V3P
Board_3P3V
FB
220 ohm
GPU with Dual mode support
1
6
20
28
ML0_P
ML0_N
ML1_P
ML1_N
ML2_P
ML2_N
ML3_P
ML3_N
AUX_N
AUX_P
DDC_EN
C21
C22
DDC_EN
0.1uF
0.1uF
R1
100k
AUX_N
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
C11
0.1uF
C12
0.1uF
C23
0.1uF
9
10
AUX_P
R2
100k
3P3V
INDP1P
INDP1N
OUTDP1P
OUTDP1N
INDP2P
INDP2N
OUTDP2P
OUTDP2N
18
19
INDP3P
INDP3N
OUTDP3P
OUTDP3N
17
I2C_EN
R3
2k
DDC_EN
R4
2k
21
22
10k
10k
1k
A0
DPEQ2
DPEQ1
3V3P
11
14
2
GND
AUX_N
AUX_P
R8
10k
23
HPDIN
32
SNOOPENZ 29
CAD
HPDIN
AUXP
AUXN
OUTDP0P
OUTDP0N
15
16
R5
R6
R7
VCC
VCC
VCC
VCC
INDP0P
INDP0N
12
13
I2C_EN
SCL
HPD
0.1uF
3P3V
SDA
CAD
C6
U1
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD10
RSVD11
TEST1/SCL
TEST2/SDA
A0
DPEQ0/A1
DPEQ1
DPEN/HPDIN
HPDIN/RSVD9
SNOOPENZ/RSVD8
TPAD
AUX_P
AUX_N
24
25
40
39
37
36
33
34
30
31
3
4
5
7
8
26
27
35
38
C13
0.1uF OUTDP0P
C14
0.1uF OUTDP0N
C15
0.1uF OUTDP1P
C16
0.1uF OUTDP1N
C17
0.1uF OUTDP2P
C18
0.1uF OUTDP2N
C19
0.1uF OUTDP3P
C20
0.1uF OUTDP3N
OUTDP1P 4
OUTDP1N 6
OUTDP0P 1
OUTDP0N 3
OUTDP3P10
OUTDP3N12
OUTDP2P 7
OUTDP2N 9
3.3V
20
AUX_P
AUX_N
15
17
HPDIN
18
ML1_P
ML1_N
ML0_P
ML0_N
ML3_P
ML3_N
ML2_P
ML2_N
DP_PWR
AUX_P
AUX_N
CONFIG1
CONFIG2
RTN
GND
GND
GND
GND
GND
GND
GND
GND
GND
13
14
CAD
R9
R10
1M
5M
19
2
5
8
11
16
21
22
23
24
HPD
DisplayPort Receptacle
GND
41
TDP142RNQ
GND
GND
3P3V
3P3V
I2C_EN
R15
1k
DPEQ0
GND
SN74AHC1G125DBVR
U2
DPEQ1
3
R12
1k
SNOOPENZ 4
R13
1k
R14
20k
R16
1k
2
R17
20k
GND
GND
CAD
1
5
R11
1k
3V3P
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 18. The Block Diagram of DisplayPort Source Application
9.2.1.1 Design Requirement
The TDP142 can be designed into many types of applications. All applications have certain requirements for the
system to work properly. For example, source application uses different hardware configuration on the HPD
channel and AUX channel from a sink application. The device can be configured by using I2C. However, the
GPIO configuration is provided as I2C is not available in all cases. Additionally, because sources may have
different naming conventions, please confirm the link between source and receptacle is correctly mapped through
the TDP142.
Table 11. Design Parameters
22
PARAMETER
VALUE
Maximum Operating data rate
(RBR, HBR, HBR2, or HBR3)
HBR3 (8.1 Gbps)
Supply voltage
3.3V
Trace length/width of A
12 inch /6 mil width
Trace length/width of B
2 inch/ 6 mil width
Main link AC decoupling capacitor
(75 nF to 265 nF)
Recommend 100nF
Control mode (I2C or GPIO)
GPIO (I2C_EN = 0)
Dual Mode DisplayPort Support (Yes/No)
Yes. SNOOPENZ must be connected to CONFIG1 thru a buffer.
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9.2.1.2 Detail Design Procedure
Designing in the TDP142 requires the following:
• Determine the loss profile on the DisplayPort input (A) and output (B) channels. See Figure 20 for 6 mil trace
insertion loss.
• Based upon the loss profile, determine the optimal configuration for the TDP142, to pass electrical
compliance. DPEQ[1:0] must be set to appropriate value. For this case, 12-in of FR4 trace approximately
equates to 8 dB loss at 4.05 GHz. Therefore, DPEQ1 should be tied 20k ohms to ground and DPEQ0 should
be tied 1 kΩ to ground.
• See Figure 18 for information of Source application on using the AC coupling capacitors, control pin resistors,
and for recommended decouple capacitors from VCC pins to ground.
– AUX: AUXP should have a 100 kΩ pull-down resistor and AUXN should have a 100 kΩ pull-up resistor.
These 100 kΩ resistors must be on the TDP142 side of the 100 nF capacitors.
– HPDIN is used to enable or disable DisplayPort functionality for power saving. The HPD signal should be
routed to either pin 23 or pin 32 based on the GPIO/I2C mode.
Table 12. HPD GPIO/I2C Selection
•
•
MODE
HPD
GPIO (I2C_EN = 0)
Pin 32
I2C (I2C_EN != 0)
Pin 23
spacer
– For the application supporting Dual mode DisplayPort: SNOOPENZ pin must be connected to the
CONFIG1 on DisplayPort Receptacle through a buffer like the SN74AHC125. The buffer is needed
because the internal pulldown on SNOOPENZ pin is too strong to register a valid VIH when a Dual mode
adapter is plugged into the DisplayPort receptacle.
Configure the TDP142 using the GPIO terminals or the I2C interface:
– GPIO – Using the terminals DPEQ0 and DPEQ1.
– I2C - Refer to the I2C Register Maps and the Programming section for a detail configuration procedures.
The thermal pad must be connected to ground.
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9.2.2 Sink Application Implementation
Figure 19 is the schematic for the Sink application, and the left side of TDP142 is connected to DisplayPort
receptacle and the right side of TDP142 is connected to Scaler or DisplayPort sink.
3P3V
C1
10uF
C2
0.1uF
C3
0.1uF
3V3P
C4
0.1uF
C5
0.1uF
Board_3P3V
DisplayPort Sink
FB
220 ohm
1
6
20
28
Note:
AC-coupled is needed if there is no
ac-coupled on the other end of source side.
24
23
22
21
16
11
8
5
2
19
20
GND
GND
GND
GND
GND
GND
GND
GND
GND
ML3_N
ML3_P
ML2_N
ML2_P
ML1_N
ML1_P
ML0_N
ML0_P
RTN
CONFIG1
CONFIG2
DP_PWR
AUX_P
AUX_N
HPD
1
3
ML3_N
ML3_P
4
6
ML2_N
ML2_P
7
9
ML1_N
ML1_P
10
12
ML0_N
ML0_P
13
14
CAD
U1
ML0_P
9
10
ML0_N
ML1_P
12
13
ML1_N
15
16
ML2_P
ML2_N
R1
R2
18
19
ML3_P
1M
5M
I2C_EN
17
ML3_N
15
17
AUX_N
AUX_P
18
HPDIN
R3
R4
R5
21
22
10k
10k
1k
A0
DPEQ2
DPEQ1
3V3P
DisplayPort Recepticle Sink
GND
R15
10k
11
14
2
23
32
29
HPDIN
CAD
GND
VCC
VCC
VCC
VCC
AUXP
AUXN
INDP0P
INDP0N
OUTDP0P
OUTDP0N
INDP1P
INDP1N
OUTDP1P
OUTDP1N
INDP2P
INDP2N
OUTDP2P
OUTDP2N
INDP3P
INDP3N
OUTDP3P
OUTDP3N
24
25
ML0_P
AUX_P
AUX_N
40
39
37
36
33
34
30
31
ML0_N
C6
0.1uF OUTDP0P
C7
0.1uF OUTDP0N
C8
0.1uF OUTDP1P
C9
0.1uF OUTDP1N
C10
0.1uF OUTDP2P
C11
0.1uF OUTDP2N
C12
0.1uF OUTDP3P
C13
0.1uF OUTDP3N
ML1_P
ML1_N
ML2_P
ML2_N
ML3_P
ML3_N
3P3V
I2C_EN
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD10
RSVD11
TEST1/SCL
TEST2/SDA
A0
DPEQ0/A1
DPEQ1
DPEN/HPDIN
HPDIN/RSVD9
SNOOPENZ/RSVD8
TPAD
3
4
5
7
8
26
27
35
38
R6
1M
AUX_P
AUX_N
R7
1M
C14
0.1uF
C15
0.1uF
AUX_P
AUX_N
HPDIN
HPD
41
TDP142RNQ
GND
GND
GND
3P3V
3P3V
R9
1k
I2C_EN
R12
1k
DPEQ0
R8
1k
GND
DPEQ1
R10
1k
GND
R11
20k
R13
1k
R14
20k
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 19. The Block diagram of DisplayPort Sink Application
9.2.2.1 Design Requirements
For this design example, the parameters listed in Table 13 are used.
Table 13. Design Parameters
24
PARAMETER
VALUE
Maximum Operating data rate
(RBR, HBR, HBR2, or HBR3)
HBR3 (8.1Gbps)
Supply voltage
3.3V
Trace length/width of C
12 inch/ 6 mil
Trace length/width of D
2 inch/ 6 mil
Main link AC decoupling capacitor
(75 nF to 265 nF)
Recommend 100 nF
Control mode (I2C or GPIO)
GPIO (I2C_EN = 0)
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9.2.2.2 Detailed Design Procedure
The design procedure for Sink application is listed as follows:
• Determine the loss profile on the DP input (C) and output (D) channels and cables. See Figure 20 for 6 mil
trace insertion loss.
• Based upon the loss profile, determine the optimal configuration for the TDP142, to pass electrical
compliance.
• See Figure 19 for information of Sink application on using the AC coupling capacitors, control pin resistors,
and for recommended decouple capacitors from VCC pins to ground.
– AUX: AUXP has a 1 MΩ pull-up resistor and AUXN should have a 1 MΩ pull-down resistor. Theses 1 MΩ
resistors must be on the TDP142 side of the 100 nF capacitors.
– HPDIN: The HPD signal should be routed to either pin 23 or pin 32 based on the GPIO/I2C mode. In that
way, the TDP142 will always be able to conserve power when a source is not connected.
Table 14. HPD GPIO/I2C Selection
•
•
MODE
HPD
GPIO (I2C_EN = 0)
Pin 32
I2C (I2C_EN != 0)
Pin 23
spacer
Configure the TDP142 using the GPIO terminals or the I2C interface:
– GPIO – Using the terminals DPEQ0 and DPEQ1.
– It is recommended to start a higher equalization value like 13 dB and 15 dB first and adjust the value if
necessary.
– I2C - Refer to the I2C Register Maps and the Programming section for a detail configuration procedures.
The thermal pad must be connected to ground.
9.2.3 Application Curve
0
Insertion Loss (dB)
-5
-10
-15
-20
6 mil Loss at 2.7 GHz
4 mil Loss at 2.7 GHz
6 mil Loss at 4.05 GHz
4 mil Loss at 4.05 GHz
-25
-30
0
5
10
15
20
25
Length of Trace (inch)
30
35
40
D009
Figure 20. Insertion Loss of FR4 PCB Traces
10 Power Supply Recommendations
The TDP142 is designed to operate with a 3.3-V power supply. Levels above those listed in the Absolute
Maximum Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator
can be used to step down to 3.3 V. Decoupling capacitors should be used to reduce noise and improve power
supply integrity. A 0.1-µF capacitor should be used on each power pin.
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11 Layout
11.1 Layout Guidelines
1. INDP[3:0]P/N and OUTDP[3:0]P/N pairs should be routed with controlled 100-Ω differential impedance
(±10%).
2. Keep away from other high speed signals.
3. Intra-pair routing should be kept to within 5 mils.
4. Inter-pair skew should be kept within 2 UI according to the DisaplyPort Design Guide
5. Length matching should be near the location of mismatch.
6. Each pair should be separated at least by 3 times the signal trace width.
7. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This
will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on
EMI.
8. Route all differential pairs on the same of layer.
9. The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
10. Refer to figure 28, the layout might face signal crossing on OUTDP2 and OUTDP3 due to mismatched
order between the output pins of the device and the connector. One of the solutions is to do polarity swap on
the input of the device when GPU is BGA package. It can minimize the number of VIAS being used.
11. Keep traces on layers adjacent to ground plane.
12. Do NOT route differential pairs over any plane split.
13. Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes a stub on the differential pair.
11.2 Layout Example
DPEQ1
INDP0
OUTDP0
A0
OUTDP1
INDP1
DPEQ0/A1
OUTDP2
INDP2
I2CEN
HPDIN
OUTDP3
INDP3
SNOOPENZ
SCL SDA DPEN AUX
Figure 21. Layout Example
26
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Layout Example (continued)
Figure 22 demonstrates the solution of mismatched order between the output of the device and the DisplayPort
connector for the source using BGA package. Top image of Figure 22 shows the crossing section between
TDP142 and connector. Usually, Vias would be applied to avoid the cross, but using Via can attenuate the signal
integrity. Therefore, the polarity swap would be implemented at the input of TDP142. The bottom image shows
there is no more crossing section between the TDP142 and connector, which can minimize the number of Vias
being used. Note that, the solution is only useful for the source using BGA package.
TDP142
GPU-BGA package
P
N
P
N
P
N
DP0P
DP0P
DP0P
DP0N
DP0N
DP0N
DP0
DP1
DP1P
DP1P
DP1P
DP1N
DP1N
DP1N
DP2P
DP2N
DP2P
DP2
DP2N
DP2P
DP2N
DP3P
DP3N
DP3P
DP3
DP3N
DP3P
DP3N
P
N
TDP142
GPU-BGA package
P
N
Connector
Connector
DP0P
DP0P
DP0P
DP0N
DP0N
DP0N
DP0
DP1P
DP1P
DP1P
DP1N
DP1N
DP1N
P
DP2P
DP2N
DP2P
N
DP2
DP2N
DP2P
DP2N
P
DP3P
DP3N
DP3P
N
DP3
DP3N
DP3P
DP3N
P
N
DP1
Figure 22. Layout Example, Top: signal crossing on the output. Bottom: INDP2 and INDP3 Polarity Swap
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 15. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TDP142
Click here
Click here
Click here
Click here
Click here
TDP142I
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
DisplayPort is a trademark of VESA.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TDP142IRNQR
ACTIVE
WQFN
RNQ
40
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TDP142
TDP142IRNQT
ACTIVE
WQFN
RNQ
40
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TDP142
TDP142RNQR
ACTIVE
WQFN
RNQ
40
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TDP142
TDP142RNQT
ACTIVE
WQFN
RNQ
40
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TDP142
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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