TFP401APZPR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 TFP401x TI PanelBus™ Digital Receiver 1 Features 2 Applications • • • • • • 1 • • • • • • • • • • (1) (2) (3) Supports Pixel Rates up to 165 MHz (Including 1080p and WUXGA at 60 Hz) Digital Visual Interface (DVI) Specification Compliant (1) True-Color, 24-Bit/Pixel, 16.7M Colors at 1 or 2 Pixels per Clock Laser Trimmed Internal Termination Resistors for Optimum Fixed Impedance Matching Skew Tolerant up to One Pixel-Clock Cycle 4× Oversampling Reduced Power Consumption – 1.8-V Core Operation With 3.3-V I/Os and Supplies (2) Reduced Ground Bounce Using Time-Staggered Pixel Outputs Low Noise and Good Power Dissipation Using TI PowerPAD™ Packaging Advanced Technology Using TI 0.18-µm EPIC-5 CMOS Process TFP401A Incorporates HSYNC Jitter Immunity (3) The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays. The TPF401 and TFP401A are compliant with the DVI Specification Rev. 1.0. The TFP401/401A has an internal voltage regulator that provides the 1.8-V core power supply from the external 3.3-V supplies. The TFP401A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the transmitted HSYNC signal. High-Definition TV HD PC Monitors Digital Video HD Projectors DVI/HDMI Receivers (HDMI Video-Only) 3 Description The Texas Instruments TFP401 and TFP401A are TI PanelBus™ flat-panel display products, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP401/401A finds applications in any design requiring high-speed digital interface. The TFP401 and TFP401A supports display resolutions up to 1080p and WUXGA in 24-bit truecolor pixel format. The TFP401/401A offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time-staggered pixel outputs for reduced ground bounce. Device Information(1) PART NUMBER TFP401 TFP401A PACKAGE BODY SIZE (NOM) HTQFP (100) 14.00 mm × 14.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. TFP401 Diagram Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (Continued) ........................................ Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 6 6 6 6 7 7 7 9 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. DC Digital I/O Electrical Characteristics.................... DC Electrical Characteristics .................................... AC Electrical Characteristics..................................... Typical Characteristics .............................................. Parameter Measurement Information ................ 10 Detailed Description ............................................ 12 9.1 Overview ................................................................. 12 9.2 Functional Block Diagram ....................................... 12 9.3 Feature Description................................................. 12 9.4 Device Functional Modes........................................ 15 10 Applications and Implementation...................... 17 10.1 Application Information.......................................... 17 10.2 Typical Application ................................................ 17 11 Power Supply Recommendations ..................... 21 12 Layout................................................................... 21 12.1 Layout Guidelines ................................................. 21 12.2 Layout Example .................................................... 22 13 Device and Documentation Support ................. 25 13.1 13.2 13.3 13.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 25 25 25 25 14 Mechanical, Packaging, and Orderable Information ........................................................... 25 14.1 TI PowerPAD 100-TQFP Package ....................... 25 4 Revision History Changes from Revision F (February 2015) to Revision G • Added tWL(PDL_MIN) and tDEL to the AC Electrical Characteristics table ................................................................................... 8 Changes from Revision E (July 2013) to Revision F • 2 Page Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A TFP401, TFP401A www.ti.com SLDS120G – MARCH 2000 – REVISED MAY 2016 5 Description (Continued) PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint, and ultralow ground inductance. The TFP401 and TFP401A combines PanelBus circuit innovation with TI's advanced 0.18-µm EPIC-5 CMOS process technology, along with TI PowerPAD package technology to achieve a reliable, low-powered, low-noise, high-speed digital interface solution. 6 Pin Configuration and Functions OGND QO23 OVDD AGND Rx2+ Rx2− AVDD AGND AVDD Rx1+ Rx1− AGND AVDD AGND Rx0+ Rx0− AGND RxC+ RxC− AVDD 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 QO22 QO21 QO20 QO19 QO18 QO17 QO16 GND DVDD QO15 QO14 QO13 QO12 QO11 QO10 QO9 QO8 OGND OVDD QO7 QO6 QO5 QO4 QO3 QO2 PZP Package 100-Pin HTQFP Top View RSVD OCK_INV 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 QO1 QO0 HSYNC VSYNC DE OGND ODCK OVDD CTL3 CTL2 CTL1 GND DVDD QE23 QE22 QE21 QE20 QE19 QE18 QE17 QE16 OVDD OGND QE15 QE14 DFO PD ST PIXS GND DVDD STAG SCDT PDO QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 OVDD OGND QE8 QE9 QE10 QE11 QE12 QE13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 EXT_RES PVDD PGND 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Pin Functions PIN I/O DESCRIPTION NAME NO. AGND 79, 83, 87, 89, 92 GND Analog ground – Ground reference and current return for analog circuitry AVDD 82, 84, 88, 95 VDD Analog VDD – Power supply for analog circuitry. Nominally 3.3 V 42, 41, 40 DO General-purpose control signals – Used for user-defined control. CTL1 is not powered down via PDO. DO Output data enable – Used to indicate time of active video display versus non-active display or blank time. During blank, only HSYNC, VSYNC, and CTL[3:1] are transmitted. During times of active display, or non-blank, only pixel data, QE[23:0], and QO[23:0] are transmitted. High: Active display time Low: Blank time CTL[3:1] DE 46 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A 3 TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com Pin Functions (continued) PIN NAME NO. DFO I/O DESCRIPTION Output clock data format – Controls the output clock (ODCK) format for either TFT or DSTN panel support. For TFT support, the ODCK clock runs continuously. For DSTN support, ODCK only clocks when DE is high; otherwise, ODCK is held low when DE is low. High: DSTN support/ODCK held low when DE = low Low: TFT support/ODCK runs continuously. 1 DI DGND 5, 39, 68 GND Digital ground – Ground reference and current return for digital core DVDD 6, 38, 67 VDD Digital VDD – Power supply for digital core. Nominally 3.3 V EXT_RES 96 AI Internal impedance matching – The TFP401/401A is internally optimized for impedance matching at 50 Ω. An external resistor tied to this pin has no effect on device performance. HSYNC 48 DO Horizontal sync output Reserved. Must be tied high for normal operation RSVD 99 DI OVDD 18, 29, 43, 57, 78 VDD Output driver VDD – Power supply for output drivers. Nominally 3.3 V ODCK 44 DO Output data clock – Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode), along with DE, HSYNC, VSYNC and CTL[3:1], are synchronized to this clock. OGND 19, 28, 45, 58, 76 GND OCK_INV PD 100 2 Output driver ground – Ground reference and current return for digital output drivers DI ODCK polarity – Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC, VSYNC, DE, CTL[3:1]) are latched. Normal mode: High: Latches output data on rising ODCK edge Low: Latches output data on falling ODCK edge DI Power down – An active-low signal that controls the TFP401/401A power-down state. During power down, all output buffers are switched to a high-impedance state. All analog circuits are powered down and all inputs are disabled, except for PD. If PD is left unconnected, an internal pullup defaults the TFP401/401A to normal operation. High : Normal operation Low: Power down Output drive power down – An active-low signal that controls the power-down state of the output drivers. During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high-impedance state. When PDO is left unconnected, an internal pullup defaults the TFP401/401A to normal operation. High: Normal operation/output drivers on Low: Output drive power down PDO 9 DI PGND 98 GND PLL GND – Ground reference and current return for internal PLL Pixel select – Selects between one- and two-pixels-per-clock output modes. During the 2pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel). High: 2-pixel/clock Low: 1-pixel/clock PIXS 4 DI PVDD 97 VDD PLL VDD – Power supply for internal PLL DO Even green-pixel output – Output for even and odd green pixels when in 1-pixel/clock mode. Output for even-only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE8/pin 20 MSB: QE15/pin 27 DO Even red-pixel output – Output for even and odd red pixels when in 1-pixel/clock mode. Output for even-only red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE16/pin 30 MSB: QE23/pin 37 DO Odd blue-pixel output – Output for odd-only blue pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO0/pin 49 MSB: QO7/pin 56 QE[8:15] QE[16:23] QO[0:7] 4 20–27 30–37 49–56 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A TFP401, TFP401A www.ti.com SLDS120G – MARCH 2000 – REVISED MAY 2016 Pin Functions (continued) PIN NAME NO. I/O DESCRIPTION DO Odd green-pixel output – Output for odd-only green pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO8/pin 59 MSB: QO15/pin 66 DO Odd red-pixel output – Output for odd-only red pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO16/pin 69 MSB: QO23/pin 77 10–17 DO Even blue-pixel output – Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even-only blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE0/pin 10 MSB: QE7/pin 17 RxC+ 93 AI Clock positive receiver input – Positive side of reference clock. TMDS low-voltage signal differential input pair RxC– 94 AI Clock negative receiver input – Negative side of reference clock. TMDS low-voltage signal differential input pair Rx0+ 90 AI Channel-0 positive receiver input – Positive side of channel-0. TMDS low-voltage signal differential input pair. Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank. Rx0– 91 AI Channel-0 negative receiver input – Negative side of channel-0. TMDS low-voltage signal differential input pair Rx1+ 85 AI Channel-1 positive receiver input – Positive side of channel-1 TMDS low-voltage signal differential input pair Channel-1 receives green-pixel data in active display and CTL1 control signals in blank. Rx1– 86 AI Channel-1 negative receiver input – Negative side of channel-1 TMDS low-voltage signal differential input pair Rx2+ 80 AI Channel-2 positive receiver input – Positive side of channel-2 TMDS low-voltage signal differential input pair Channel-2 receives red-pixel data in active display and CTL2, CTL3 control signals in blank. Rx2– 81 AI Channel-2 negative receiver input – Negative side of channel-2 TMDS low-voltage signal differential input pair QO[8:15] QO[16:23] QE[0:7] 59–66 69–75, 77 SCDT 8 DO Sync detect - Output to signal when the link is active or inactive. The link is considered to be active when DE is actively switching. The TFP401/401A monitors the state of DE to determine link activity. SCDT can be tied externally to PDO to power down the output drivers when the link is inactive. High: Active link Low: Inactive link ST 3 DI Output drive strength select – Selects output drive strength for high- or low-current drive. (See dc specifications for IOH and IOL vs ST state). High: High drive strength Low: Low drive strength STAG 7 DI Staggered pixel select – An active-low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time-staggers the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels simultaneously. High: Normal simultaneous even/odd pixel output Low: Time-staggered even/odd pixel output VSYNC 47 DO Vertical sync output Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A 5 TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) DVDD, AVDD, OVDD, PVDD VI MIN MAX UNIT Supply voltage –0.3 4 V Input voltage range, logic/analog signals –0.3 4 V 0 70 °C Operating ambient temperature Package power dissipation/PowerPAD package Soldered (2) 4.3 Not soldered (3) 2.7 JEDEC latchup (EIA/JESD78) Tstg (1) (2) (3) Storage temperature –65 W 100 mA 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Specified with PowerPAD bond pad on the backside of the package soldered to a 2-oz. (0.071-mm thick) Cu plate PCB thermal plane. Specified at maximum allowed operating temperature, 70°C. PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating temperature, 70°C. 7.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions VDD (DVDD, AVDD, PVDD, OVDD) Supply voltage tpix (1) Pixel time NOM MAX 3 3.3 3.6 V 40 ns 6.06 Rt Single-ended analog-input termination resistance TA Operating free-air temperature (1) MIN UNIT 45 50 55 Ω 0 25 70 °C tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpix when in 1pixel/clock mode and 2tpix when in 2-pixel/clock mode. 7.4 Thermal Information TFP401, TFP401A THERMAL METRIC (1) PZP (HTQFP) UNIT 100 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 12.3 RθJB Junction-to-board thermal resistance 7.3 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 7.2 RθJC(bot) Junction-to-case (bottom) thermal resistance 1.6 (1) 6 26 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A TFP401, TFP401A www.ti.com SLDS120G – MARCH 2000 – REVISED MAY 2016 7.5 DC Digital I/O Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIH High-level digital input voltage (1) VIL Low-level digital input voltage (1) IOH High-level output drive current (2) IOL Low-level output drive current (2) IOZ Hi-Z output leakage current (1) (2) MIN TYP MAX UNIT 2 DVDD V 0 0.8 V ST = high, VOH = 2.4 V 5 10 14 ST = low, VOH = 2.4 V 3 6 9 ST = high, VOL = 0.8 V 10 13 19 ST = low, VOL = 0.8 V 5 7 11 PD = low or PDO = low –1 1 mA mA μA Digital inputs are labeled DI in I/O column of Terminal Functions table. Digital outputs are labeled DO in I/O column of Terminal Functions table. 7.6 DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS (1) VID Analog input differential voltage VIC Analog input common-mode voltage (1) VI(OC) Open-circuit analog input voltage IDD(2PIX) Normal 2-pix/clock power supply current (3) IPD Power-down current IPDO Output drive power-down current (3) (1) (2) (3) (2) MIN TYP MAX UNIT 75 1200 mV AVDD – 300 AVDD – 37 mV AVDD – 10 AVDD + 10 mV 370 mA 10 mA ODCK = 82.5 MHz, 2-pix/clock PD = low PDO = low 35 mA Specified as dc characteristic with no overshoot or undershoot Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE[23:0] and QO[23:0] CL = 10 pF. Analog inputs are open circuit (transmitter is disconnected from TFP401/401A). 7.7 AC Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VID(2) Differential input sensitivity (1) tps Analog input intra-pair (+ to –) differential skew (2) tccs Analog input inter-pair or channel-to-channel skew (2) tijit Worst-case differential input clock jitter tolerance (2) (5) tf1 Fall time of data and control signals (6) (7) tr1 Rise time of data and control signals (6) (7) tr2 Rise time of ODCK clock (6) tf2 Fall time of ODCK clock (6) (1) (2) (3) (4) (5) (6) (7) MIN 150 TYP MAX UNIT 1560 mVp-p 0.4 tbit (3) 1 tpix (4) 50 ps ST = low, CL = 5 pF 2.4 ST = high, CL = 10 pF 1.9 ST = low, CL = 5 pF 2.4 ST = high, CL = 10 pF 1.9 ST = low, CL = 5 pF 2.4 ST = high, CL = 10 pF 1.9 ST = low, CL = 5 pF 2.4 ST = high, CL = 10 pF 1.9 ns ns ns ns Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection. By characterization tbit is 1/10 the pixel time, tpix tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in 2-pixel/clock mode. Measured differentially at 50% crossing using ODCK output clock as trigger Rise and fall times measured as time between 20% and 80% of signal amplitude. Data and control signals are QE[23:0], QO[23:0], DE, HSYNC, VSYNC. and CTL[3:1]. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A 7 TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com AC Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER tsu1 TEST CONDITIONS Setup time, data and control signal to falling edge of ODCK th1 Hold time, data and control signal to falling edge of ODCK tsu2 Setup time, data and control signal to rising edge of ODCK th2 Hold time, data and control signal to rising edge of ODCK fODCK 1.8 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = low 3.8 2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = low 0.7 1 pixel/clock, PIXS = low, OCK_INV = low 0.6 2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = low 2.5 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = low 2.9 1 pixel/clock, PIXS = low, OCK_INV = high 2.1 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high 4 2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = high 1.5 1 pixel/clock, PIXS = low, OCK_INV = high 0.5 2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = high 2.4 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high 2.1 PIX = low (1-PIX/CLK) ODCK frequency MIN 1 pixel/clock, PIXS = low, OCK_INV = low PIX = high (2-PIX/CLK) ODCK duty-cycle TYP MAX ns ns ns ns 25 165 12.5 82.5 40% 50% Propagation delay time from PD low to Hi-Z outputs 9 tpd(PDOL) Propagation delay time from PDO low to Hi-Z outputs 9 tt(HSC) Transition time between DE transition to SCDT low (8) tt(FSC) Transition time between DE transition to SCDT high (8) td(st) Delay time, ODCK latching edge to QE[23:0] data output tWL(PDL_MIN) Minimum time PD is asserted low tDEL Minimum DE low (8) 8 MHz 60% tpd(PDL) STAG = low, PIXS = high UNIT ns ns 1e6 tpix 1600 tpix 0.25 tpix 9 128 ns Tpixel Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A TFP401, TFP401A www.ti.com SLDS120G – MARCH 2000 – REVISED MAY 2016 7.8 Typical Characteristics Figure 1. Imax vs Input Frequency Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A 9 TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com 8 Parameter Measurement Information tr1 QE[23:0], QO[23:0], DE, CTK[3:1], HSYNC, VSYNC tf1 80% 80% 20% 20% Figure 2. Rise and Fall Times of Data and Control Signals tr2 tf2 80% ODCK 1/fODCK ODCK 80% 20% 20% Figure 3. Rise and Fall Times of ODCK Figure 4. ODCK Frequency t(su1) t(su2) t(h1) t(h2) VOH ODCK VOH VOL VOH VOL QE[23:0], QO[23:0] DE, CTL[3:1], HSYNC, VSYNC VOL VOH VOL VOH VOL VOH VOL OCK_INV Figure 5. Data Setup and Hold Times to Rising and Falling Edges of ODCK tps VOH ODCK Rx+ 50% td(st) QE[23:0] Rx– 50% Figure 6. ODCK High to QE[23:0] Staggered Data Output PD Figure 7. Analog Input Intra-Pair Differential Skew PDO VIL tpd(PDL) QE[23:0], QO[23:0], ODCK, DE, CTL[3:1], HSYNC, VSYNC, SCDT VIL tpd(PDOL) QE[23:0], QO[23:0], ODCK, DE, CTL[3:2], HSYNC, VSYNC Figure 8. Delay From PD Low to Hi-Z Outputs Figure 9. Delay From PDO Low to Hi-Z Outputs twL(PDL_MIN) VIH PD tp(PDH-V) PD VIL DFO, ST, PIXS, STAG, Rx[2:0]+, Rx[2:0]–, OCK_INV Figure 10. Delay From PD Low to High Before Inputs Are Active 10 Figure 11. Minimum Time PD Low Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A TFP401, TFP401A www.ti.com SLDS120G – MARCH 2000 – REVISED MAY 2016 Parameter Measurement Information (continued) TX2 50% TX1 tccs TX0 50% Figure 12. Analog Input Channel-to-Channel Skew tt(HSC) tt(FSC) DE SCDT Figure 13. Time Between DE Transitions to SCDT Low and SCDT High tDEL tDEH DE Figure 14. Minimum DE Low and Maximum DE High Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A 11 TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com 9 Detailed Description 9.1 Overview The TFP401/401A is a digital visual interface (DVI)-compliant TMDS digital receiver that is used in digital flat panel display systems to receive and decode TMDS-encoded RGB pixel data streams. In a digital display system a host, usually a PC or workstation, contains a TMDS-compatible transmitter that receives 24-bit pixel data along with appropriate control signals and encodes them into a high-speed low-voltage differential serial bit stream fit for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, requires a TMDS-compatible receiver like the TI TFP401/401A to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat-panel drive circuitry to produce an image on the display. Because the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. To support modern display resolutions up to UXGA, a high-bandwidth receiver with good jitter and skew tolerance is required. 9.2 Functional Block Diagram 3.3 V 3.3 V 1.8 V Regulator Internal 50-W Termination 3.3 V RED(0-7) Rx2+ Rx2- + _ Channel 2 Latch CTL2 Channel 1 Rx1+ Rx1- + _ Latch Rx0+ Rx0- + _ Latch RxC+ RxC- + _ PLL QE(0-23) QO(0-23) CTL3 CH2(0-9) Data Recovery CH1(0-9) TMDS and Decoder Synchronization Channel 0 GRN(0-7) CTL1 BLU(0-7) VSYNC HSYNC CH0(0-9) Panel Interface ODCK DE SCDT CTL3 CTL2 CTL1 VSYNC HSYNC Copyright © 2016, Texas Instruments Incorporated 9.3 Feature Description 9.3.1 TMDS Pixel Data and Control Signal Encoding TMDS stands for transition-minimized differential signaling. Only one of two possible TMDS characters for a given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent, and transmits the character that minimizes the number of transitions to approximate a dc balance of the transmission line. Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three channels also receive control signals, HSYNC, VSYNC, and user-defined control signals CTL[3:1]. These control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. Table 1 maps the received input data to the appropriate TMDS input channel in a DVI-compliant system. 12 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A TFP401, TFP401A www.ti.com SLDS120G – MARCH 2000 – REVISED MAY 2016 Table 1. TMDS Pixel Data and Control Signal Encoding RECEIVED PIXEL DATA ACTIVE DISPLAY DE = HIGH OUTPUT PINS (VALID FOR DE = HIGH) INPUT CHANNEL Red[7:0] Channel-2 (Rx2 ±) QE[23:16] QO[23:16] Green[7:0] Channel-1 (Rx1 ±) QE[15:8] QO[15:8] Blue[7:0] Channel-0 (Rx0 ±) QE[7:0] QO[7:0] RECEIVED CONTROL DATA BLANKING DE = LOW CTL[3:2] CTL[1: 0] (1) HSYNC, VSYNC (1) OUTPUT PINS (VALID FOR DE = LOW) INPUT CHANNEL Channel-2 (Rx2 ±) CTL[3:2] Channel-1 (Rx1 ±) CTL1 Channel-0 (Rx0 ±) HSYNC, VSYNC Some TMDS transmitters transmit a CTL0 signal. The TFP401/401A decodes and transfers CTL[3:1] and ignores CTL0 characters. CTL0 is not available as a TFP401/401A output. The TFP401/401A discriminates between valid pixel TMDS characters and control TMDS characters to determine the state of active display versus blanking, i.e., the state of DE. 9.3.2 TFP401/401A Clocking and Data Synchronization The TFP401/401A receives a clock reference from the DVI transmitter that has a period equal to the pixel time, tpix. The frequency of this clock is also referred to as the pixel rate. Because the TMDS encoded data on Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example, the required pixel rate to support a UXGA resolution with 60-Hz refresh rate is 165 MHz. The TMDS serial bit rate is 10× the pixel rate, or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on three separate channels (or twisted-pair wires) of long distances (3–5 meters), phase synchronization between the data steams and the input reference clock is not assured. In addition, skew between the three data channels is common. The TFP401/401A uses a 4× oversampling scheme of the input data streams to achieve reliable synchronization with up to 1-tpix channel-to-channel skew tolerance. Accumulated jitter on the clock and data lines due to reflections and external noise sources is also typical of high-speed serial data transmission; hence, the TFP401/401A design for high jitter tolerance. The input clock to the TFP401/401A is conditioned by a phase-locked loop (PLL) to remove high-frequency jitter from the clock. The PLL provides four 10× clock outputs of different phase to locate and sync the TMDS data streams (4× oversampling). During active display, the pixel data is encoded to be transition-minimized, whereas in blank, the control data is encoded to be transition-maximized. A DVI-compliant transmitter is required to transmit in blank for a minimum period of time, 128 tpix, to ensure sufficient time for data synchronization when the receiver sees a transition-maximized code. Synchronization during blank, when the data is transitionmaximized, ensures reliable data-bit boundary detection. Phase synchronization to the data streams is unique for each of the three input channels and is maintained as long as the link remains active. 9.3.3 TFP401/401A TMDS Input Levels and Input Impedance Matching The TMDS inputs to the TFP401/401A receiver have a fixed single-ended termination to AVDD. The TFP401/401A is internally optimized using a laser trim process to precisely fix the impedance at 50 Ω. The device functions normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets. The fixed impedance eliminates the need for an external resistor while providing optimum impedance matching to standard 50-Ω DVI cables. Figure 15 shows a conceptual schematic of a DVI transmitter and TFP401/401A receiver connection. A transmitter drives the twisted-pair cable via a current source, usually achieved with an open-drain type output driver. The internal resistor, which is matched to the cable impedance at the TFP401/401A input, provides a pullup to AVDD. Naturally, when the transmitter is disconnected and the TFP401/401A DVI inputs are left unconnected, the TFP401/401A receiver inputs pull up to AVDD. The single-ended differential signal and fulldifferential signal is shown in Figure 16. The TFP401/401A is designed to respond to differential signal swings ranging from 150 mV to 1.56 V with common-mode voltages ranging from (AVDD – 300 mV) to (AVDD – 37 mV). Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A 13 TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com DVI Transmitter TI TFP401/401A Receiver AVDD DVI Compliant Cable Internal Termination at 50 W DATA DATA + _ Current Source Figure 15. TMDS Differential Input and Transmitter Connection VIDIFF AVCC 1/2 VIDIFF +1/2 VIDIFF –1/2 VIDIFF AVCC – 1/2 VIDIFF a) Single-Ended Input Signal b) Differential Input Signal Figure 16. TMDS Inputs 9.3.4 TFP401A Incorporates HSYNC Jitter Immunity Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver, and if the position of HSYNC shifts continuously, the receiver can lose track of the input timing, causing pixel noise to occur on the display. For this reason, a DVI-compliant receiver with HSYNC jitter immunity should be used in all displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem. The TFP401A integrates HSYNC regeneration circuitry that provides a seamless interface to these noncompliant transmitters. The position of the data enable (DE) signal is always fixed in relation to data, irrespective of the location of HSYNC. The TFP401A receiver uses the DE and clock signals to recreate stable vertical and horizontal sync signals. The circuit filters the HSYNC output of the receiver, and HSYNC is shifted to the nearest eighth bit boundary, producing a stable output with respect to data, as shown in Figure 17. This ensures accurate data synchronization at the input of the display timing controller. This HSYNC regeneration circuit is transparent to the monitor and need not be removed even if the transmitted HSYNC is stable. For example, the PanelBus line of DVI 1.0 compliant transmitters, such as the TFP6422 and TFP420, do not have the HSYNC jitter problem. The TFP401A operates correctly with either compliant or noncompliant transmitters. In contrast, the TFP401 is ideal for customers who have control over the transmit portion of the design, such as bundled system manufacturers and for internal monitor use (the DVI connection between monitor and panel modules). 14 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A TFP401, TFP401A www.ti.com SLDS120G – MARCH 2000 – REVISED MAY 2016 ODCK HSYNC Shift by ± 1 Clock HSYNC IN DE HSYNC OUT Figure 17. HSYNC Regeneration Timing Diagram 9.4 Device Functional Modes 9.4.1 TFP401/401A Modes of Operation The TFP401/401A provides system design flexibility and value by providing the system designer with configurable options or modes of operation to support varying system architectures. Table 2 outlines the various panel modes that can be supported, along with appropriate external control pin settings. Table 2. TFP401/401A Modes of Operation PIXEL RATE ODCK LATCH EDGE ODCK DFO PIXS OCK_INV TFT or 16-bit DSTN PANEL 1 pix/clock Falling Free run 0 0 0 TFT or 16-bit DSTN 1 pix/clock Rising Free run 0 0 1 TFT 2 pix/clock Falling Free run 0 1 0 TFT 2 pix/clock Rising Free run 0 1 1 24-bit DSTN 1 pix/clock Falling Gated low 1 0 0 NONE 1 pix/clock Rising Gated low 1 0 1 24-bit DSTN 2 pix/clock Falling Gated low 1 1 0 24-bit DSTN 2 pix/clock Rising Gated low 1 1 1 9.4.2 TFP401/401A Output Driver Configurations The TFP401/401A provides flexibility by offering various output driver features that can be used to optimize power consumption, ground bounce, and power-supply noise. The following sections outline the output driver features and their effects. 9.4.2.1 Output Driver Power Down (PDO = low). Pulling PDO low places all the output drivers, except CTL1 and SCDT, into a high-impedance state. The SCDT output, which indicates link-disabled or link-inactive, can be tied directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected. An internal pullup on the PDO pin defaults the TFP401/401A to the normal nonpower-down output drive mode if left unconnected. 9.4.2.2 Drive Strength (ST = high for high drive strength, ST = low for low drive strength). The TFP401/401A allows for selectable output drive strength on the data, control, and ODCK outputs. See the DC Electrical Characteristics table for the values of IOH and IOL current drives for a given ST state. The high output drive strength offers approximately two times the drive as the low-output drive strength. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A 15 TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com 9.4.2.3 Time-Staggered Pixel Output This option works only in conjunction with the 2-pixel/clock mode (PIXS = high). Setting STAG = low timestaggers the even- and odd-pixel outputs so as to reduce the amount of instantaneous current surge from the power supply. Depending on the PCB layout and design, this can help reduce the amount of system ground bounce and power-supply noise. The time stagger is such that in 2-pixel/clock mode, the even pixel is delayed from the latching edge of ODCK by 0.25 tcip. (tcip is the period of ODCK. The ODCK period is 2 tpix when in 2pixel/clock mode). Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the TFP401/401A drive-strength and staggered-pixel options allow flexibility to reduce system power-supply noise, ground bounce, and EMI. 9.4.2.4 Power Management The TFP401/401A offers several system power-management features. The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode, all output drivers except SCDT and CTL1 are driven to a high-impedance state while the rest of the device circuitry remains active. The TFP401/401A power down (PD = low) is a complete power down in that it powers down the digital core, the analog circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except for the PD input. The TFP401/401A does not respond to any digital or analog inputs until PD is pulled high. Both PDO and PD have internal pullups, so if left unconnected they default the TFP401/401A to normal operating modes. 9.4.2.5 Sync Detect The TFP401/401A offers an output, SCDT, to indicate link activity. The TFP401/401A monitors activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the TFP401/401A considers the link inactive, and SCDT is driven low. While SCDT is low, if two DE transitions are detected within 1600 pixel clock periods, the link is considered active, and SCDT is pulled high. SCDT can be used to signal a system power management circuit to initiate a system power down when the link is considered inactive. The SCDT can also be tied directly to the TFP401/401A PDO input to power down the output drivers when the link is inactive. It is not recommended to use SCDT to drive the PD input, because once in complete power-down, the analog inputs are ignored and the SCDT state does not change. An external system power-management circuit to drive PD is preferred. 16 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A TFP401, TFP401A www.ti.com SLDS120G – MARCH 2000 – REVISED MAY 2016 10 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The TFP401 is a DVI (Digital Visual Interface) compliant digital receiver that is used in digital flat panel display systems to receive and decode TMDS encoded RGB pixel data streams. A digital display system a host, usually a PC or workstation, contains a DVI compliant transmitter that receives 24-bit pixel data along with appropriate control signals and encodes them into a high-speed low voltage differential serial bit stream fit for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will require a DVI compliant receiver like the TI TFP401 to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. The TFP401 will support resolutions up to UXGA. 10.2 Typical Application Figure 18. Typical Application 10.2.1 Design Requirements For this design example, use the parameters listed in Table 3 as the input parameters. Table 3. Design Parameters PARAMETER VALUE Power supply 3.3 V-DC @ 1 A Input clock Single-ended Input clock frequency range 25 MHz – 165 MHz Output format 24 bits/pixel Input clock latching Rising edge I2C EEPROM support No De-skew No Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A 17 TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com 10.2.2 Detailed Design Procedure 10.2.2.1 Data and Control Signals The trace length of data and control signals out of the receiver should be kept as close to equal as possible. Trace separation should be ~5X Height. As a general rule, traces also should be less than 2.8 inches if possible (longer traces can be acceptable). Delay = 85 × SQRT ER where • ER = 4.35 • Relative permittivity of 50% resin FR-4 @ 1 GHz • Delay = 177 pS/inch Length of rising edge = TR(picoseconds) ÷ Delay (1) where • TR = 3 nS • = 3000 ps ÷ 177 ps per inch • = 16.9 inches Length of rising edge ÷ 6 = Max length of trace for lumped circuit (2) where • 16.9 ÷ 6 = 2.8 inches (3) Figure 19. Data and Control Signals Design 18 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A TFP401, TFP401A www.ti.com SLDS120G – MARCH 2000 – REVISED MAY 2016 10.2.2.2 Configuration Options The TFP401 can be configured in several modes depending on the required output format, for example 1byte/clock, 2-bytes/clock, falling/rising clock edge. You can leave place holders for future configuration changes. Figure 20. Configuration Options Design 10.2.2.3 Power Supplies Decoupling Digital, analog, and PLL supplies must be decoupled from each other to avoid electrical noise on the PLL and the core. Figure 21. Power Supplies Decoupling Design Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A 19 TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com 10.2.3 Application Curve Sometimes the panel does not support the same format as the graphics processor unit (GPU). In these cases the user must decide how to connect the unused bits. Figure 22 and Figure 23 plots show the mismatches between the 18-bit GPU and a 24-bit LCD where “x” and “y” represent the 2 LSB of the panel. Figure 22. 16-bit GPU to 24-bit LCD 20 Figure 23. 18-bit GPU to 24-bit LCD Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A TFP401, TFP401A www.ti.com SLDS120G – MARCH 2000 – REVISED MAY 2016 11 Power Supply Recommendations Use solid ground planes and tie ground planes together with as many vias as is practical. This will provide a desirable return path for current. Each supply should be on separate split power planes, where each power plane should be as large an area as possible. Connect PanelBus receiver power and ground pins and all bypass caps to appropriate power or ground plane with via. Vias should be as fat and short as practical, the goal is to minimize the inductance. • DVDD: Place one 0.01 uF capacitor as close as possible between each DVDD device pin (Pins 6, 38, 67) and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A ferrite bead should be used between the source and the 22 uF capacitor. • OVDD: Place one 0.01 uF capacitor as close as possible between each OVDD device pin (Pins 18, 29, 43, 57, 78) and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A ferrite bead should be used between the source and the 22 uF capacitor. • AVDD: Place one 0.01 uF capacitor as close as possible between each AVDD device pin (Pins 82, 84, 88, 95) and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A ferrite bead should be used between the source and the 22 uF capacitor. • PVCC: Place three 0.01 uF capacitors in parallel as close as possible between the PVDD device pin (Pin 97) and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A ferrite bead should be used between the source and the 22 uF capacitor. 12 Layout 12.1 Layout Guidelines 12.1.1 Layer Stack The pinout of Texas Instruments High Speed Interface (HSI) devices features differential signal pairs and the remaining signals comprise the supply rails, VCC and ground, and lower speed signals such as control pins. As an example, consider a device X which is a repeater/re-driver, so both its inputs and outputs are high-speed differential signals. These guidelines can be applied to other high-speed devices such as drivers, receivers, multiplexers, etc. A minimum of four layers is required to accomplish a low EMI PCB design. Layer stacking should be in the following order (top-to-bottom): high-speed differential signal layer, ground plane, power plane and control signal layer. Figure 24. Layer Stack Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: TFP401 TFP401A 21 TFP401, TFP401A SLDS120G – MARCH 2000 – REVISED MAY 2016 www.ti.com Layout Guidelines (continued) 12.1.2 Routing High-Speed Differential Signal Traces (RxC–, RxC+, Rx0–, Rx0+, Rx1–, Rx1+, Rx2–, Rx2+) Trace impedance should be controlled for optimal performance. Each differential pair should be equal in length and symmetrical and should have equal impedance to ground with a trace separation of 2X to 4X Height. A differential trace separation of 4X Height yields about 6% cross-talk (6% effect on impedance). It is recommended that differential trace routing should be side by side, though it is not important that the differential traces be tightly coupled together because tight coupling is not achievable on PCB traces. Typical ratios on PCBs are only 20-50%, and 99.9% is the value of a well-balanced twisted pair cable. Each differential trace should be as short as possible (