THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
10-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
FEATURES
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
High-Speed 6 MSPS ADC
4 Analog Inputs
Simultaneous Sampling of 4 Single-Ended
Signals or 2 Differential Signals or
Combination of Both
Differential Nonlinearity Error: ±1 LSB
Integral Nonlinearity Error: ±1.5 LSB
Signal-to-Noise and Distortion Ratio: 59 dB
at fI = 2 MHz
Auto-Scan Mode for 2, 3, or 4 Inputs
3-V or 5-V Digital Interface Compatible
Low Power: 216 mW Max
5-V Analog Single Supply Operation
Internal Voltage References . . . 50 PPM/°C
and ±5% Accuracy
Glueless DSP Interface
Parallel µC/DSP Interface
Integrated FIFO
Available in TSSOP Package
Pin Compatible With 12-Bit THS1206
APPLICATIONS
D
D
D
D
D
Radar Applications
Communications
Control Applications
High-Speed DSP Front-End
Automotive Applications
DESCRIPTION
The THS10064 is a CMOS, low-power, 10-bit, 6 MSPS
analog-to-digital converter (ADC). The speed, resolution,
bandwidth, and single-supply operation are suited for
applications in radar, imaging, high-speed acquisition, and
communications. A multistage pipelined architecture with
output error correction logic provides for no missing codes
over the full operating temperature range. Internal control
registers are used to program the ADC into the desired
mode. The THS10064 consists of four analog inputs,
which are sampled simultaneously. These inputs can be
selected individually and configured to single-ended or
differential inputs. An integrated 16 word deep FIFO allows
the storage of data in order to improve data transfers to the
processor. Internal reference voltages for the ADC (1.5 V
and 3.5 V) are provided.
An external reference can also be chosen to suit the dc
accuracy and temperature drift requirements of the
application. Two different conversion modes can be
selected. In single conversion mode, a single and
simultaneous conversion of up to four inputs can be
initiated by using the single conversion start signal
(CONVST). The conversion clock in single conversion
mode is generated internally using a clock oscillator
circuit. In continuous conversion mode, an external clock
signal is applied to the CONV_CLK input of the
THS10064. The internal clock oscillator is switched off in
continuous conversion mode.
The THS10064C is characterized for operation from 0°C
to 70°C, and the THS10064I is characterized for operation
from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
These devices have limited built-in ESD protection. The
leads should be shorted together or the device placed in
conductive foam during storage or handling to prevent
electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICE
TA
TSSOP
(DA)
0°C to 70°C
THS10064CDA
–40°C to 85°C
THS10064IDA
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
THS10064
Supply voltage range
DGND to DVDD
–0.3 V to 6.5 V
BGND to BVDD
–0.3 V to 6.5 V
AGND to AVDD
–0.3 V to 6.5 V
Analog input voltage range
AGND –0.3 V to AVDD + 1.5 V
Reference input voltage
–0.3 V + AGND to AVDD + 0.3 V
Digital input voltage range
–0.3 to BVDD/DVDD + 0.3 V
Operating virtual junction temperature range, TJ
Operating free-air
free air temperature range,
range TA
–40°C to 150°C
THS10064C
0°C to 70°C
THS10064I
–40°C to 85°C
Storage temperature range, Tstg
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
POWER SUPPLY
Supply voltage
MIN
NOM
MAX
AVDD
DVDD
4.75
5
5.25
3
3.3
5.25
BVDD
3
3.3
5.25
ANALOG AND REFERENCE INPUTS
MIN
Analog input voltage in single-ended configuration
MAX
V
2.5
VREFP
4
3.5
AVDD–1.2
V
External reference voltage,VREFP (optional)
External reference voltage, VREFM (optional)
1.4
Input voltage difference, REFP – REFM
DIGITAL INPUTS
V
NOM
VREFM
1
Common-mode input voltage VCM in differential configuration
UNIT
MIN
UNIT
V
1.5
V
2
V
NOM
MAX
High level input voltage,
High-level
voltage VIH
Low level input voltage,
Low-level
voltage VIL
BVDD = 3.3 V
BVDD = 5.25 V
Input CONV_CLK frequency
DVDD = 3 V to 5.25 V
0.1
CONV_CLK pulse duration, clock high, tw(CONV_CLKH)
DVDD = 3 V to 5.25 V
80
83
5000
ns
CONV_CLK pulse duration, clock low, tw(CONV_CLKL)
DVDD = 3 V to 5.25 V
80
83
5000
ns
Operating free-air
free air temperature,
temperature TA
2
THS10064CDA
THS10064IDA
2
UNIT
BVDD = 3.3 V
BVDD = 5.25 V
V
2.6
V
0.6
V
0.6
V
6
0
70
–40
85
MHz
°C
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, DVDD = 3.3 V, AVDD = 5 V, VREF = internal (unless otherwise noted)
DIGITAL SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital inputs
IIH
IIL
High-level input current
DVDD = digital Inputs
–50
50
µA
Low-level input current
Digital input = 0 V
–50
50
µA
Ci
Input capacitance
5
pF
Digital outputs
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = –50 µA,
IOL = 50 µA,
BVDD = 3.3 V, 5 V
BVDD = 3.3 V, 5 V
IOZ
CO
High-impedance-state output current
CS1 = DGND,
CS0 = DVDD
CL
Load capacitance at databus D0 – D9
BVDD–0.5
V
–10
Output capacitance
0.4
V
10
µA
5
pF
30
pF
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, AVDD = 5 V, DVDD = BVDD = 3.3 V, fs = 6 MSPS, VREF = internal (unless otherwise noted)
DC SPECIFICATIONS
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP
MAX
10
UNIT
Bits
Accuracy
Integral nonlinearity, INL
±1
LSB
Differential nonlinearity, DNL
±1
LSB
Offset error
±5
After calibration in single-ended mode
After calibration in differential mode
Gain error
LSB
–10
10
LSB
–10
10
LSB
Analog input
Input capacitance
Input leakage current
15
VAIN = VREFM to VREFP
pF
±10
µA
V
Internal voltage reference
Accuracy, VREFP
3.3
3.5
3.7
Accuracy, VREFM
1.4
1.5
1.6
Temperature coefficient
50
Reference noise
µV
100
Accuracy, REFOUT
2.475
V
PPM/°C
2.5
2.525
V
Power supply
IDDA
IDDD
Analog supply current
IDDB
IDD_P
Buffer supply current
Digital supply current
Supply current in power-down mode
Power dissipation
Power dissipation in power down
AVDD = 5 V, BVDD = DVDD = 3.3 V
AVDD = 5 V, BVDD = DVDD = 3.3 V
AVDD = 5 V, BVDD = DVDD = 3.3 V
AVDD = 5 V, BVDD = DVDD = 3.3 V
AVDD = 5 V, DVDD = BVDD = 3.3 V
AVDD = 5 V, DVDD = BVDD = 3.3 V
36
40
mA
0.5
1
mA
1.5
4
mA
186
30
7
mA
216
mW
mW
3
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal, fs = 6 MHz, fI = 2 MHz at –1 dBFS (unless otherwise noted)
AC SPECIFICATIONS, AVDD =5 V, BVDD = DVDD = 3.3 V, CL < 30 pF
PARAMETER
SINAD
Signal to noise ratio + distortion
Signal-to-noise
SNR
Signal to noise ratio
Signal-to-noise
THD
ENOB
(SNR)
SFDR
Total harmonic distortion
Effective number of bits
Spurious free dynamic range
MIN
TYP
Differential mode
TEST CONDITIONS
56
59
MAX
dB
Single-ended mode(1)
55
59
dB
Differential mode
59
61
dB
Single-ended mode(1)
58
60
dB
Differential mode
–64
–61
Single-ended mode
–63
–60
Differential mode
Single-ended mode(1)
UNIT
dB
dB
9
9.5
Bits
8.85
9.35
Bits
Differential mode
61
65
dB
Single-ended mode
60
64
dB
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
differential configuration.
Full scale sinewave, –3 dB
96
MHz
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.
Full scale sinewave, –3 dB
54
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
differential configuration.
100 mVpp sinewave, –3 dB
96
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.
100 mVpp sinewave, –3 dB
54
MHz
(1) The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling
clock.
TIMING SPECIFICATIONS(1)
AVDD = 5 V, DVDD = BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(DATA_AV)
td(o)
Delay time
5
ns
Delay time
5
ns
tpipe
Latency
5
CONV
CLK
(1) See Figure 27.
4
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
TIMING SPECIFICATION OF THE SINGLE CONVERSION MODE(1) (2)
PARAMETER
tc
TEST CONDITIONS
Clock cycle of the internal clock oscillator
1 analog input
t1
Pulse duration,
duration CONVST
td(A)
Aperture time
2 analog inputs
3 analog inputs
UNIT
175
ns
ns
1
Delayy time between consecutive start of single
g
conversion
2 analog inputs
3 analog inputs
1 analog input,
Delayy time,, DATA_AV
becomes active for the
_
trigger level condition: TRIG0 = 0, TRIG1 = 0
TL = 1
3 analog inputs, TL = 3
4 analog inputs, TL = 4
Delayy time,, DATA_AV
_
becomes active for the
trigger level condition: TRIG0 = 1, TRIG1 = 0
TL = 4
2 analog inputs, TL = 4
3 analog inputs, TL = 6
4 analog inputs, TL = 8
1 analog input,
Delayy time,, DATA_AV
_
becomes active for the
trigger level condition: TRIG0 = 0, TRIG1 = 1
TL = 8
2 analog inputs, TL = 8
3 analog inputs, TL = 9
4 analog inputs, TL = 12
1 analog input,
Delay
D
l titime, DATA
DATA_AV
AV b
becomes active
ti ffor th
the
trigger level condition: TRIG0 = 1,
1 TRIG1 = 1
ns
4×tc
5×tc
2 analog inputs, TL = 2
1 analog input,
ns
2×tc
3×tc
4 analog inputs
td(DATA_AV)
(
_ )
MAX
167
3.5×tc
4.5×tc
1 analog input
td(DATA_AV)
d(DATA AV)
TYP
151
1.5×tc
2.5×tc
4 analog inputs
td2
MIN
TL = 14
6.5×tc + 15
7.5×tc +15
8.5×tc +15
9.5×tc +15
3×t2 +6.5×tc+15
t2 +7.5×tc+15
t2 +8.5×tc+15
t2 +9.5×tc+15
7×t2 +6.5×tc+15
3×t2 +7.5×tc+15
2×t2 +8.5×tc+15
2×t2 +9.5×tc+15
2 analog inputs, TL = 12
13×t2 +6.5×tc+15
5×t2 +7.5×tc+15
3 analog inputs, TL = 12
3×t2 +8.5×tc+15
ns
ns
ns
ns
(1) Timing parameters are ensured by design but are not tested.
(2) See Figure 26.
PIN ASSIGNMENTS
DA (TSSOP) PACKAGE
(TOP VIEW)
D0
D1
D2
D3
D4
D5
1
32
2
31
3
30
4
29
5
28
6
27
BVDD
BGND
D6
D7
D8
D9
RA0
RA1
CONV_CLK (CONVST)
DATA_AV
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
AINP
AINM
BINP
BINM
REFIN
REFOUT
REFP
REFM
AGND
AVDD
CS0
CS1
WR (R/W)
RD
DVDD
DGND
5
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AINP
32
I
Analog input, single-ended or positive input of differential channel A
AINM
31
I
Analog input, single-ended or negative input of differential channel A
BINP
30
I
Analog input, single-ended or positive input of differential channel B
BINM
29
I
Analog input, single-ended or negative input of differential channel B
AVDD
23
I
Analog supply voltage
AGND
24
I
Analog ground
BVDD
7
I
Digital supply voltage for buffer
BGND
8
I
Digital ground for buffer
CONV_CLK
(CONVST)
15
I
Digital input. This input is used to apply an external conversion clock in continuous conversion mode. In single
conversion mode, this input functions as the conversion start (CONVST) input. A high to low transition on this input
holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog
inputs.
CS0
22
I
Chip select input (active low)
CS1
21
I
Chip select input (active high)
DATA_AV
16
O
Data available signal, which can be used to generate an interrupt for processors and as a level information of the
internal FIFO. This signal can be configured to be active low or high and can be configured as a static level or pulse
output. See Table 14.
DGND
17
I
Digital ground. Ground reference for digital circuitry.
Digital supply voltage
DVDD
18
I
1–6,
9–12
I/
O/Z
RA0
13
I
Digital input. RA0 is used as an address line for the control register. This is required for writing to the control
register 0 and control register 1. See Table 8.
RA1
14
I
Digital input. RA1 is used as an address line for the control register. This is required for writing to control register 0
and control register 1. See Table 8.
REFIN
28
I
Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the
reference output REFOUT.
REFP
26
I
Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage.
An external reference voltage at this input can be applied. This option can be programmed through control
register 0. See Table 9.
REFM
25
I
Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage.
An external reference voltage at this input can be applied. This option can be programmed through control
register 0. See Table 9.
REFOUT
27
O
Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output requires
a capacitor of 10 µF to AGND for filtering and stability.
RD†
19
I
The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active
low as a data read select from the processor. See timing section.
WR (R/W)†
20
I
This input is programmable. It functions as a read-write input R/W and can also be configured as a write-only input
WR, which is active low and used as data write select from the processor. In this case, the RD input is used as a
read input from the processor. See timing section.
D0 – D9
Digital input, output; D0 = LSB
(1) The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
6
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
2.5 V
3.5 V
REFP
1.225 V
REF
1.5 V
REFOUT
REFM
REFIN
AINP
VREFM
S/H
DATA_AV
VREFP
AINM
BINP
S/H
S/H
Single
Ended
and/or
Differential
MUX
+
–
BVDD
10 Bit
Pipeline
ADC
10
FIFO
16 × 10
10
Buffers
BINM
CONV_CLK (CONVST)
CS0
CS1
RD
S/H
Logic
and
Control
Control
Register
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
RA0
RA1
BGND
WR (R/W)
AGND
DGND
7
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
80
SINAD – Signal-to-Noise and Distortion – dB
THD – Total Harmonic Distortion – dB
90
80
70
60
50
40
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –0.5 dB FS
30
20
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –0.5 dB FS
70
60
50
40
30
20
0
1
2
3
4
5
6
7
0
1
fs – Sampling Frequency – MHz
2
Figure 1
5
6
7
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
80
90
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –0.5 dB FS
80
70
SNR – Signal-to-Noise – dB
SFDR – Spurious Free Dynamic Range – dB
4
Figure 2
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
70
60
50
40
60
50
40
30
30
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –0.5 dB FS
20
20
0
1
2
3
4
5
fs – Sampling Frequency – MHz
Figure 3
8
3
fs – Sampling Frequency – MHz
6
7
0
1
2
3
4
5
fs – Sampling Frequency – MHz
Figure 4
6
7
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
80
SINAD – Signal-to-Noise and Distortion – dB
THD – Total Harmonic Distortion – dB
90
80
70
60
50
40
30
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –0.5 dB FS
20
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –0.5 dB FS
70
60
50
40
30
20
0
1
2
3
4
5
6
7
0
1
fs – Sampling Frequency – MHz
2
Figure 5
4
5
6
7
Figure 6
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
80
100
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –0.5 dB FS
90
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –0.5 dB FS
70
SNR – Signal-to-Noise – dB
SFDR – Spurious Free Dynamic Range – dB
3
fs – Sampling Frequency – MHz
80
70
60
60
50
40
30
50
20
40
0
1
2
3
4
5
fs – Sampling Frequency – MHz
Figure 7
6
7
0
1
2
3
4
5
6
7
fs – Sampling Frequency – MHz
Figure 8
9
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
80
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –1 dB FS
80
SINAD – Signal-to-Noise and Distortion – dB
THD – Total Harmonic Distortion – dB
90
70
60
50
40
30
20
0
1
2
3
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –1 dB FS
70
60
50
40
30
20
4
0
1
fi – Input Frequency – MHz
4
Figure 10
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (SINGLE-ENDED)
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (SINGLE-ENDED)
80
90
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –1 dB FS
75
70
80
SNR – Signal-to-Noise – dB
SFDR – Spurious Free Dynamic Range – dB
3
fi – Input Frequency – MHz
Figure 9
70
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –1 dB FS
60
50
40
65
60
55
50
45
40
35
30
30
25
20
20
0
0.5
1.0
1.5
2.0
2.5
fi – Input Frequency – MHz
Figure 11
10
2
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
fi – Input Frequency – MHz
Figure 12
3.0
3.5
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
80
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –0.5 dB FS
80
SINAD – Signal-to-Noise and Distortion – dB
THD – Total Harmonic Distortion – dB
90
70
60
50
40
30
20
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –0.5 dB FS
70
60
50
40
30
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
fi – Input Frequency – MHz
1.5
2.0
2.5
3.0
3.5
Figure 14
Figure 13
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (DIFFERENTIAL)
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (DIFFERENTIAL)
80
90
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –0.5 dB FS
70
80
SNR – Signal-to-Noise – dB
SFDR – Spurious Free Dynamic Range – dB
1.0
fi – Input Frequency – MHz
70
60
50
40
60
50
40
30
30
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –0.5 dB FS
20
20
0
0
0.5
1.0
1.5
2.0
2.5
fi – Input Frequency – MHz
3.0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
fi – Input Frequency – MHz
Figure 16
Figure 15
11
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
12
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –0.5 dB FS
ENOB – Effective Number of Bits – Bits
ENOB – Effective Number of Bits – Bits
12
11
10
9
8
7
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –0.5 dB FS
11
10
9
8
7
6
6
0
1
2
3
4
5
6
0
7
1
2
fs – Sampling Frequency – MHz
5
6
7
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (DIFFERENTIAL)
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (SINGLE-ENDED)
12
12
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –1 dB FS
ENOB – Effective Number of Bits – Bits
ENOB – Effective Number of Bits – Bits
4
Figure 18
Figure 17
11
10
9
8
7
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –0.5 dB FS
11
10
9
8
7
6
6
0
0.5
1.0
1.5
2.0
2.5
fi – Input Frequency – MHz
Figure 19
12
3
fs – Sampling Frequency – MHz
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
fi – Input Frequency – MHz
Figure 20
3.0
3.5
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
TEMPERATURE
INTEGRAL NONLINEARITY
vs
TEMPERATURE
0.70
0.64
0.68
DNL – Differential Nonlinearity – LSB
0.66
AVDD = 5 V,
BVDD = DVDD = 3.3 V,
Differential Mode,
Internal Reference,
Internal Oscillator
0.62
0.60
0.58
0.56
0.54
0.52
0.5
–40
0.66
0.64
0.62
0.60
0.58
0.56
0.54
AVDD = 5 V,
BVDD = DVDD = 3.3 V,
Differential Mode,
Internal Reference,
Internal Oscillator
0.52
–15
10
35
60
85
0.5
–40
–15
10
35
60
85
TA – Temperature – °C
TA – Temperature – °C
Figure 21
Figure 22
GAIN
vs
INPUT FREQUENCY (SINGLE-ENDED)
5
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –0.5 dB FS
0
–5
G – Gain – dB
INL – Integral Nonlinearity – LSB
0.68
0.70
–10
–15
–20
–25
–30
0
10 20 30 40 50 60 70 80 90 100 110 120
fi – Input Frequency – MHz
Figure 23
13
THS10064
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM (4096 POINTS)
(SINGLE-ENDED)
vs
FREQUENCY
0
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –0.5 dB FS, fin = 1 MHz
Magnitude – dB
–20
–40
–60
–80
–100
–120
–140
0
0.5
1.0
1.5
2.0
2.5
3.0
f – Frequency – MHz
Figure 24
FAST FOURIER TRANSFORM (4096 POINTS)
(DIFFERENTIAL)
vs
FREQUENCY
0
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = –0.5 dB FS, fin = 1 MHz
Magnitude – dB
–20
–40
–60
–80
–100
–120
–140
0
0.5
1.0
1.5
f – Frequency – MHz
Figure 25
14
2.0
2.5
3.0
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
DETAILED DESCRIPTION
Reference Voltage
The THS10064 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V
and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and
REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the
upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
Analog Inputs
The THS10064 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
Analog-to-Digital Converter
The THS10064 uses a 10-bit pipelined multistage architecture with 4 1-bit stages followed by 4 2-bit stages, which
achieves a high sample rate with low power consumption. The THS10064 distributes the conversion over several
smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results
from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a
traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate
on a new input sample while the second through the eighth stages operate on the seven preceding samples.
Conversion Modes
The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion
is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous
conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started
with every falling edge of the applied clock signal.
Sampling Rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1
shows the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate in Continuous Conversion Mode
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel
1
6 MSPS
2 single-ended channels
2
3 MSPS
3 single-ended channels
3
2 MSPS
4 single-ended channels
4
1.5 MSPS
1 differential channel
1
6 MSPS
2 differential channels
2
3 MSPS
1 single-ended and 1 differential channel
2
3 MSPS
2 single-ended and 1 differential channels
3
2 MSPS
CHANNEL CONFIGURATION
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
fc
MSPS
+ #6channels
DATA_AV
In continuous conversion mode, the first DATA_AV signal is delayed by (7+TL) cycles of the CONV_CLK after a FIFO
reset. This is due to the latency of the pipeline architecture of the THS10064.
15
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
Table 2 shows the maximum conversion rate in the single conversion mode.
Table 2. Maximum Conversion Rate in Single Conversion Mode(1)
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel
1
3 MSPS
2 single-ended channels
2
2 MSPS
3 single-ended channels
3
1.5 MSPS
4 single-ended channels
4
1.2 MSPS
1 differential channel
1
3 MSPS
2 differential channels
2
2 MSPS
1 single-ended and 1 differential channel
2
2 MSPS
2 single-ended and 1 differential channels
3
1.5 MSPS
CHANNEL CONFIGURATION
(1) Maximum conversion rate with respect to the typical internal clock speed (i.e. 6 MPS * (tc/t2).
SINGLE CONVERSION MODE
In single conversion mode, a single conversion of the selected analog input channels is performed. The single
conversion mode is selected by setting bit 1 of control register 0 to 1.
A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold
stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the
selected channels is started.
The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal
DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted
sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode can be
selected according to Table 13.
Figure 26 shows the timing of the single conversion mode. In this mode, up to four analog input channels can be
selected to be sampled simultaneously (see Table 2).
td2
CONVST
t1
t1
td(A)
AIN
Sample N
td(DATA_AV)
DATA_AV,
Trigger Level = 1
Figure 26. Timing of Single Conversion Mode
The time (td2) between consecutive starts of single conversions is dependent on the number of selected analog input
channels. The time td(DATA_AV), until DATA_AV becomes active is given by: td(DATA_AV) = tpipe + n × tc. This equation
is valid for a trigger level which is equivalent to the number of selected analog input channels. For all other trigger
level conditions refer to the timing specifications of single conversion mode.
CONTINUOUS CONVERSION MODE
The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In
continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock
signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO.
16
THS10064
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
Figure 27 shows the timing of continuous conversion mode when one analog input channel is selected. The
maximum throughput rate is 6 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case of
a trigger level set to 1 or 4.
Sample N
Channel 1
Sample N+1
Channel 1
Sample N+2
Channel 1
Sample N+3
Channel 1
Sample N+4
Channel 1
Sample N+5
Channel 1
Sample N+6
Channel 1
Sample N+7
Channel 1
Sample N+8
Channel 1
AIN
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
50%
CONV_CLK
50%
td(O)
tc
Data Into
FIFO
Data N–5
Channel 1
Data N–4
Channel 1
Data N–3
Channel 1
Data N–2
Channel 1
Data N–1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
Data N+2
Channel 1
Data N+3
Channel 1
td(DATA_AV)
DATA_AV,
Trigger Level = 1
td(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 27. Timing of Continuous Conversion Mode (1-channel operation)
Figure 28 shows the timing of continuous conversion mode when two analog input channels are selected. The
maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the
order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level
set to 2 or 4.
Sample N
Channel 1,2
Sample N+1
Channel 1,2
Sample N+2
Channel 1,2
Sample N+3
Channel 1,2
Sample N+4
Channel 1,2
AIN
td(A)
tw(CONV_CLKH)
CONV_CLK
50%
td(Pipe)
tw(CONV_CLKL)
50%
tc
Data Into
FIFO
Data N–3
Channel 2
td(O)
Data N–2
Channel 1
Data N–2
Channel 2
Data N–1
Channel 1
Data N–1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
Data N+1
Channel 2
td(DATA_AV)
DATA_AV,
Trigger Level = 2
td(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 28. Timing of Continuous Conversion Mode (2-channel operation)
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THS10064
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
Figure 29 shows the timing of continuous conversion mode when three analog input channels are selected. The
maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in
which order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger
level set to 3.
Sample N
Channel 1,2,3
Sample N+1
Channel 1,2,3
Sample N+2
Channel 1,2,3
AIN
td(A)
td(Pipe)
tw(CONV_CLKL)
tw(CONV_CLKH)
CONV_CLK
50%
50%
tc
Data Into
FIFO
td(O)
Data N–2
Channel 2
Data N–2
Channel 3
Data N–1
Channel 1
Data N–1
Channel 2
Data N–1
Channel 3
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
td(DATA_AV)
DATA_AV,
Trigger Level = 3
Figure 29. Timing of Continuous Conversion Mode (3-channel operation)
Figure 30 shows the timing of continuous conversion mode when four analog input channels are selected. The
maximum throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows
in which order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger
level of 4.
Sample N
Channel 1,2,3,4
Sample N+1
Channel 1,2,3,4
Sample N+2
Channel 1,2,3,4
AIN
td(A)
td(Pipe)
tw(CONV_CLKL)
50%
tw(CONV_CLKH)
50%
CONV_CLK
tc
Data Into
FIFO
Data N–2
Channel 4
td(O)
Data N–1
Channel 1
Data N–1
Channel 2
Data N–1
Channel 3
Data N–1
Channel 4
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
Data N
Channel 4
td(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 30. Timing of Continuous Conversion Mode (4-channel operation)
18
THS10064
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
DIGITAL OUTPUT DATA FORMAT
The digital output data format of the THS10064 can either be in binary format or in twos complement format. The
following tables list the digital outputs for the analog input voltages.
Table 3. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
AIN = VREFP
3FFh
AIN = (VREFP + VREFM)/2
200h
AIN = VREFM
000h
Table 4. Twos Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
AIN = VREFP
1FFh
AIN = (VREFP + VREFM)/2
000h
AIN = VREFM
200h
Table 5. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
Vin = AINP – AINM
VREF = VREFP – VREFM
Vin = VREF
Vin = 0
3FFh
Vin = –VREF
000h
200h
Table 6. Twos Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
Vin = AINP – AINM
VREF = VREFP – VREFM
Vin = VREF
Vin = 0
1FFh
Vin = –VREF
200h
000h
19
THS10064
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
FIFO DESCRIPTION
In order to facilitate an efficient connection to today’s processors, the THS10064 is supplied with a FIFO. This
integrated FIFO enables a problem-free processing of data with today’s processors. The FIFO is provided as a
flexible circular buffer. The circular buffer integrated in the THS10064 can store up to 16 conversion values.
Therefore, the amount of interrupts to be served by a processor can be reduced significantly.
16
1
15
2
Read Pointer
14
3
13
4
12
5
Trigger Pointer
6
11
7
10
9
8
Data in FIFO
Free
Write Pointer
Figure 31. Circular Buffer
The converted data of the THS10064 is automatically written into the FIFO. To control the writing and reading
process, a write pointer, a read pointer and a trigger pointer are used. The read pointer always shows the location
which is read next. The write pointer indicates the location which contains the last written sample. With a selection
of multiple analog input channels, the converted values are written in a predefined sequence to the circular buffer
(autoscan mode). In this way, the channel information for the reading processor is continually maintained.
The FIFO can be programmed through the control register of the ADC. The user has the ability to select a specific
trigger level according to Table 13 in order to choose the configuration which best fits the application. The FIFO
provides the signal DATA_AV, which signals the processor to read the amount of data equal to the trigger level
selected in Table 13. The signal DATA_AV becomes active when the trigger condition is satisfied. The trigger
condition is satisfied when as many values as selected for the trigger level where written into the FIFO.
The signal DATA_AV could be connected to an interrupt input of a processor. In every interrupt service routine call,
the processor must read the amount of data equal to the trigger level from the ADC. The first data represents the
first channel according to the autoscan mode, which is shown in Table 10. The channel information is therefore
always maintained.
20
THS10064
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
READING DATA FROM THE FIFO
The THS10064 informs the connected processor via the digital output DATA_AV (data available) that a block of
conversion values are ready to be read. The block size to be read is always equal to the setting of the trigger level.
The selectable trigger levels depend on the number of selected analog input channels. For example, when choosing
one analog input, a trigger level of 1, 4, 8, and 14 can be selected. The following figures demonstrate the principle
of reading the data (the READ signal is asynchronous to CONV_CLK).
In Figure 32, a trigger level of 1 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 32. Trigger Level 1 Selected
In Figure 33, a trigger level of 4 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 33. Trigger Level 4 Selected
In Figure 34, a trigger level of 8 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 34. Trigger Level 8 Selected
In Figure 35, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 35. Trigger Level 14 Selected
READ is always the logical combination of CS0, CS1 and RD.
21
THS10064
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
ADC CONTROL REGISTER
The THS10064 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired
mode. The bit definitions of both control registers are shown in Table 7.
Table 7. Bit Definitions of Control Register CR0 and CR1
REG
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CR0
TEST1
TEST0
SCAN
DIFF1
DIFF0
CHSEL1
CHSEL0
PD
MODE
VREF
CR1
RESERVED
OFFSET
BIN/2s
R/W
DATA_P
DATA_T
TRIG1
TRIG0
FRST
RESET
Writing to Control Register 0 and Control Register 1
The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control
register and writing the register value to the ADC. The addressing is performed with the upper bits RA0 and RA1.
During this write process, the data bits D0 to D9 contain the desired control register value. Table 8 shows the
addressing of each control register.
Table 8. Control Register Addressing
22
D0 – D9
RA0
RA1
Addressed Control Register
Desired register value
0
0
Control register 0
Desired register value
1
0
Control register 1
Desired register value
0
1
Reserved for future
Desired register value
1
1
Reserved for future
THS10064
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
INITIALIZATION OF THE THS10064
The initialization of the THS10064 should be done according to the configuration flow shown in Figure 36.
Start
Use Default
Values?
No
Yes
Write 0x401 to
THS10064
(Set Reset Bit in CR1)
Clear RESET By
Writing 0x400 to
CR1
Write 0x401 to
THS10064
(Set Reset Bit in CR1)
Clear RESET By
Writing 0x400 to
CR1
Write The User
Configuration to
CR0
Write The User
Configuration to
CR1 (Can Include
FIFO Reset, Must
Exclude RESET)
Continue
Figure 36. THS10064 Configuration Flow
23
THS10064
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
ADC CONTROL REGISTERS
Control Register 0, Write Only (see Table 8)
RA1
RA0
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
TEST1
TEST0
SCAN
DIFF1
DIFF0
CHSEL1
CHSEL0
PD
MODE
VREF
Table 9. Control Register 0 Bit Functions
BITS
RESET
VALUE
NAME
0
0
VREF
Vref select:
Bit 0 = 0 → The internal reference is selected
Bit 0 = 1 → The external reference voltage is selected
1
0
MODE
Continuous conversion mode/single conversion mode
Bit 1 = 0 → Continuous conversion mode is selected
FUNCTION
An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the
CONV_CLK signal a new converted value is written into the FIFO.
Bit 1 = 1 → Single conversion mode is selected
In this mode, the CONV_CLK input functions as a CONVST input. A single conversion is initiated on the
THS10064 by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the
selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected
channels is started. The signal DATA_AV (data available) becomes active when the trigger condition is
satisfied.
2
0
PD
Power down.
Bit 2 = 0 → The ADC is active
Bit 2 = 1 → Power down
The reading and writing to and from the digital outputs is possible during power down. It is also possible to
read out the FIFO.
3, 4
0,0
CHSEL0,
CHSEL1
Channel select
Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10.
5,6
1,0
DIFF0, DIFF1
7
0
SCAN
Autoscan enable
Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 10.
8,9
0,0
TEST0,
TEST1
Test input enable
Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This
feedback allows the check of all hardware connections and the ADC operation.
Number of differential channels
Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 10.
Refer to Table 11 for selection of the three different test voltages. The control signal DATA_AV is disabled in
the test mode. Test voltage readings have to be done independent from DATA_AV. To get the THS10064
back to the normal operating mode, apply the initialization routine.
24
THS10064
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SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
ANALOG INPUT CHANNEL SELECTION
The analog input channels of the THS10064 can be selected via bits 3 to 7 of control register 0. One single channel
(single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between
single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel
is selected. Table 10 shows the possible selections.
Table 10. Analog Input Channel Configurations
BIT 7
SCAN
BIT 6
DIFF1
BIT 5
DIFF0
BIT 4
CHSEL1
BIT 3
CHSEL0
0
0
0
0
0
Analog input AINP (single ended)
0
0
0
0
1
Analog input AINM (single ended)
0
0
0
1
0
Analog input BINP (single ended)
0
0
0
1
1
Analog input BINM (single ended)
0
0
1
0
0
Differential channel (AINP–AINM)
0
0
1
0
1
Differential channel (BINP–BINM)
1
0
0
0
1
Autoscan two single ended channels: AINP, AINM, AINP, …
1
0
0
1
0
Autoscan three single ended channels: AINP, AINM, BINP, AINP, …
1
0
0
1
1
Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP, …
1
0
1
0
1
Autoscan one differential channel and one single ended channel AINP,
(BINP–BINM), AINP, (BINP–BINM), …
1
0
1
1
0
Autoscan one differential channel and two single ended channel AINP,
AINM, (BINP–BINM), AINP, …
1
1
0
0
1
Autoscan two differential channels (AINP–AINM), (BINP–BINM),
(AINP–AINM), …
0
0
1
1
0
Reserved
0
0
1
1
1
Reserved
1
0
0
0
0
Reserved
1
0
1
0
0
Reserved
1
0
1
1
1
Reserved
1
1
0
0
0
Reserved
1
1
0
1
0
Reserved
1
1
0
1
1
Reserved
1
1
1
0
0
Reserved
1
1
1
0
1
Reserved
1
1
1
1
0
Reserved
1
1
1
1
1
Reserved
DESCRIPTION OF THE SELECTED INPUTS
Test Mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in
Table 11.
Table 11. Test Mode
BIT 9
TEST1
BIT 8
TEST0
OUTPUT RESULT
0
0
Normal mode
0
1
1
0
1
1
VREFP
((VREFM)+(VREFP))/2
VREFM
Three different options can be selected. This feature allows support testing of hardware connections between the
ADC and the processor.
25
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
Control Register 1, Write Only (see Table 8)
RA1
RA0
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
1
RESERVED
OFFSET
BIN/2s
R/W
DATA_P
DATA_T
TRIG1
TRIG0
OVFL/FRST
RESET
Table 12. Control Register 1 Bit Functions
BITS
RESET
VALUE
NAME
0
0
RESET
FUNCTION
Reset
Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.
In addition the FIFO pointer and offset register is reset. After reset, it takes 5 clock cycles until the first value is
converted and written into the FIFO.
1
0
FRST
2, 3
0,0
TRIG0,
TRIG1
FIFO trigger level
DATA_T
DATA_AV type
4
1
FRST: FIFO reset
By writing a 1 into this bit, the FIFO is reset.
Bit 2 and bit 3 of control register 1 are used to set the trigger level for the FIFO. If the trigger level is reached, the
signal DATA_AV (data available) becomes active according to the settings of DATA_T and DATA_P. This
indicates to the processor that the ADC values can be read. Refer to Table 13.
Bit 4 of control register 1 controls whether the DATA_AV signal is a pulse or static (e.g for edge or level sensitive
interrupt inputs). If it is set to 0, the DATA_AV signal is static. If it is set to 1, the DATA_AV signal is a pulse. Refer
to Table 14.
5
1
DATA_P
DATA_AV polarity
Bit 5 of control register 1 controls the polarity of DATA_AV. If it is set to 1, DATA_AV is active high. If it is set to 0,
DATA_AV is active low. Refer to Table 14.
6
0
R/W
R/W, RD/WR selection
Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to
1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with
R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR
becomes a write input.
7
0
BIN/2s
Complement select
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of
control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 3 through Table 6.
8
0
OFFSET
Offset cancellation mode
Bit 8 = 0 → normal conversion mode
Bit 8 = 1 → offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conversion. The conversion result is stored in an offset register and subtracted from all conversions in order to
reduce the offset error.
9
0
RESERVED
Always write 0.
FIFO TRIGGER LEVEL
Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the
trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of the signal
DATA_AV to indicate to the processor that the ADC values can be read.
26
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can
be selected, is dependent on the number of input channels. Both, a differential or a single-ended input is considered
as one channel. The processor therefore always reads the data from the FIFO in the same order and is able to
distinguish between the channels.
Table 13. FIFO Trigger Level
BIT 3
TRIG1
BIT 2
TRIG0
TRIGGER LEVEL
FOR 1 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 2 CHANNELS
(ADC values)
TRIGGER LEVEL
FOR 3 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 4 CHANNELS
(ADC values)
0
0
01
02
03
04
0
1
04
04
06
08
1
0
08
08
09
12
1
1
14
12
12
Reserved
TIMING AND SIGNAL DESCRIPTION OF THE THS10064
The reading from the THS10064 and writing to the THS10064 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W).
This is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The
two chip select inputs can be used to interface easily to a processor.
Reading from the THS10064 takes place by an internal RDint signal, which is generated from the logical combination
of the external signals CS0, CS1 and RD (see Figure 37). This signal is then used to strobe the words out of the FIFO
and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes RDint active
while the write input (WR) is inactive. The first of those external signals going to its inactive state then deactivates
RDint again.
Writing to the THS10064 takes place by an internal WRint signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers
0 and 1. The last external signal (either CS0, CS1 or WR) to become valid makes WRint active while the read input
(RD) is inactive. The first of those external signals going to its inactive state then deactivates WRint again.
CS0
Read Enable
CS1
RD
Write Enable
WR
Control/Data
Registers
Data Bits
Figure 37. Logical Combination of CS0, CS1, RD, and WR
27
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
DATA_AV TYPE
Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of
control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines
the polarity of DATA_AV. This is shown in Table 14.
Table 14. DATA_AV Type
BIT 5
DATA_P
BIT 4
DATA_T
0
0
Active low level
0
1
Active low pulse
1
0
Active high level
1
1
Active high pulse
DATA_AV TYPE
The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive dependent of the
DATA_T selection (pulse or level).
If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling edge
of READ). The trigger condition is checked again after TL reads. For single conversion mode, DATA_AV type should
be programmed to active level mode.
If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in continuous
conversion mode. The next DATA_AV pulse (when the trigger condition is satisfied) is sent out the earliest, when the
TL values, written into the FIFO before, were read out by the processor.
Read Timing (using R/W, CS0-controlled)
Figure 38 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input
R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0
is the last external signal of CS0, CS1, and R/W which becomes valid.
tw(CS)
90%
CS0
10%
10%
CS1
ÓÓÓ
ÓÓÓ
ÓÓÓ
R/W
RD
tsu(R/W)
th(R/W)
90%
ÔÔÔ
ÔÔÔ
ÔÔÔ
90%
ta
th
90%
90%
D(0–9)
td(CSDAV)
DATA_AV
90%
Figure 38. Read Timing Diagram Using R/W (CS0-controlled)
28
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
Read Timing Parameter (CS0-controlled)†
PARAMETER
MIN
tsu(R/W)
ta
Setup time, R/W high to last CS valid
0
Access time, last CS valid to data valid
0
td(CSDAV)
th
Delay time, last CS valid to DATA_AV inactive
th(R/W)
tw(CS)
† CS = CS0
TYP
MAX
UNIT
ns
10
12
ns
ns
Hold time, first CS invalid to data invalid
0
Hold time, first external CS invalid to R/W change
5
ns
10
ns
Pulse duration, CS active
5
ns
Write Timing (using R/W, CS0-controlled)
Figure 39 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input
R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0
is the last external signal of CS0, CS1, and R/W which becomes valid.
tw(CS)
90%
CS0
10%
10%
CS1
ÓÓÓÓ
ÓÓÓÓ
ÓÓÓÓ
tsu(R/W)
ÓÓÓ
ÓÓÓ
ÓÓÓ
th(R/W)
WR
RD
tsu
th
90%
90%
D(0–9)
ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
DATA_AV
Figure 39. Write Timing Diagram Using R/W (CS0-controlled)
Read Timing Parameter (CS0-controlled)†
PARAMETER
MIN
TYP
MAX
UNIT
tsu(R/W)
tsu
Setup time, R/W stable to last CS valid
0
ns
Setup time, data valid to first CS invalid
5
ns
th
th(R/W)
Hold time, first CS invalid to data invalid
2
ns
Hold time, first CS invalid to R/W change
5
ns
10
ns
tw(CS)
† CS = CS0
Pulse duration, CS active
29
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
INTERFACING THE THS10064 TO THE TMS320C30/31/33 DSP
The following application circuit shows an interface of the THS10064 to the TMS320C30/31/33 DSPs. The read and
write timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
THS10064
TMS320C30/31/33
DVDD
CS0
CS1
RD
R/W
DATA_AV
CONV_CLK
DATA
STRB
A23
R/W
INTX
TOUT
DATA
INTERFACING THE THS10064 TO THE TMS320C54X USING I/O STROBE
The following application circuit shows an interface of the THS10064 to the TMS320C54x. The read and write timings
(using R/W, CS0-controlled) shown before are valid for this specific interface.
THS10064
TMS320C54x
DVDD
CS0
CS1
RD
R/W
DATA_AV
CONV_CLK
DATA
30
I/O STRB
A15
R/W
INTX
BCLK
DATA
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
Read Timing (using RD, RD-controlled)
Figure 40 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input
RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external
signal of CS0, CS1, and RD which becomes valid.
CS0
CS1
WR
tsu(CS)
ÓÓÓÓ
ÓÓÓÓ
th(CS)
tw(RD)
10%
RD
ÔÔÔ
ÔÔÔ
10%
ta
th
90%
90%
D(0–9)
td(CSDAV)
90%
DATA_AV
Figure 40. Read Timing Diagram Using RD (RD-controlled)
Read Timing Parameter (RD-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CS)
ta
Setup time, RD low to last CS valid
0
Access time, last CS valid to data valid
0
td(CSDAV)
th
Delay time, last CS valid to DATA_AV inactive
Hold time, first CS invalid to data invalid
0
th(CS)
tw(RD)
Hold time, RD change to first CS invalid
5
ns
10
ns
Pulse duration, RD active
ns
10
12
ns
ns
5
ns
31
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
Write Timing (using WR, WR-controlled)
Figure 41 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The
input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last
external signal of CS0, CS1, and WR which becomes valid.
CS0
CS1
tsu(CS)
th(CS)
tw(WR)
WR
10%
10%
ÓÓÓÓÓ
ÓÓÓÓÓ
RD
tsu
ÔÔÔÔ
ÔÔÔÔ
th
90%
90%
D(0–9)
DATA_AV
ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
Figure 41. Write Timing Diagram Using WR (WR-controlled)
Write Timing Parameter Using WR (WR-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CS)
tsu
Setup time, CS stable to last WR valid
0
ns
Setup time, data valid to first WR invalid
5
ns
th
th(CS)
Hold time, WR invalid to data invalid
2
ns
5
ns
tw(WR)
Pulse duration, WR active
10
ns
32
Hold time, WR invalid to CS change
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
INTERFACING THE THS10064 TO THE TMS320C6201 DSP
The following application circuit shows an interface of the THS10064 to the TMS320C6201. The read (using RD,
RD-controlled) and write timings (using WR, WR-controlled) shown before are valid for this specific interface.
THS10064–1
TMS320C6201
CS0
CS1
RD
WR
DATA_AV
DATA
CONV_CLK
CE1
EA20
ARE
AWE
EXT_INT6
DATA
TOUT1
TOUT2
EA21
EXT_INT7
THS10064–2
CS0
CS1
RD
WR
DATA_AV
DATA
CONV_CLK
ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE
The THS10064 features four analog input channels. These can be configured for either single-ended or differential
operation. Best performance is achieved in differential mode. Figure 42 shows a simplified model, where a
single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are VREFP and
VREFM (either internal or external reference voltage). The analog input voltage range goes from VREFM to VREFP. This
means that VREFM defines the minimum voltage, which can be applied to the ADC. VREFP defines the maximum
voltage, which can be applied to the ADC. The internal reference source provides the voltage VREFM of 1.5 V and
the voltage VREFP of 3.5 V. The resulting analog input voltage swing of 2 V can be expressed by:
V
REFM
v AINP v VREFP
(1)
VREFP
AINP
10-Bit
ADC
VREFM
Figure 42. Single-Ended Input Stage
33
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
A differential operation is desired for many applications. Figure 43 shows a simplified model for the analog inputs
AINM and AINP, which are configured for differential operation. This configuration has a few advantages, which are
discussed in the following paragraphs.
VREFP
AINP
+
Σ
VADC
10-Bit
ADC
–
AINM
VREFM
Figure 43. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage, VADC, which is applied at the input
of the ADC is the difference between the input AINP and AINM. This means that VREFM defines the minimum voltage
(VADC) which can be applied to the ADC. VREFP defines the maximum voltage (VADC) which can be applied to the
ADC. The voltage VADC can be calculated as follows:
V
ADC
+ ABS(AINP–AINM)
(2)
An advantage to single-ended operation is that the common-mode voltage
V
CM
+ AINM )2 AINP
(3)
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
v AINM, AINP v AVDD
v4 V
1 VvV
CM
AGND
(4)
(5)
In addition to the common-mode voltage rejection, the differential operation allows a dc-offset rejection which is
common to both analog inputs. See Figure 45.
SINGLE-ENDED MODE OF OPERATION
The THS10064 can be configured for single-ended operation using dc- or ac-coupling. In either case, the input of
the THS10064 must be driven from an operational amplifier that does not degrade the ADC performance. Because
the THS10064 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar signals to comply
with its input requirements. This can be achieved with dc- and ac-coupling. An application example is shown for
dc-coupled level shifting in the following section, dc-coupling.
34
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
DC COUPLING
An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the
THS10064. The analog input voltage range of the THS10064 goes from 1.5 V to 3.5 V. An op-amp specified for 5-V
single supply can be used as shown in Figure 44.
Figure 44 shows an application example where the analog input signal in the range from –1 V up to 1 V is shifted
by an op-amp to the analog input range of the THS10064 (1.5 V to 3.5 V). The op-amp is configured as an inverting
amplifier with a gain of –1. The required dc voltage of 1.25 V at the noninverting input is derived from the 2.5-V output
reference REFOUT of the THS10064 by using a resistor divider. Therefore, the op-amp output voltage is centered
at 2.5 V. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors.
R
3.5 V
2.5 V
1.5 V
5V
1V
0V
R
_
THS10064
RS
AINP
–1 V
1.25 V
+
REFIN
REFOUT
R
R
Figure 44. Level-Shift for DC-Coupled Input
DIFFERENTIAL MODE OF OPERATION
For the differential mode of operation, a conversion from single-ended to differential is required. A conversion to
differential signals can be achieved by using an RF-transformer, which provides a center tap. Best performance is
achieved in differential mode.
Mini Circuits
T4–1
49.9 Ω
THS10064
R
AINP
200 Ω
C
R
AINM
C
REFOUT
Figure 45. Transformer Coupled Input
35
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The
point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB
beyond the last code transition. The deviation is measured from the center of each particular code to the true straight
line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A
differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation
of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N
+ (SINAD6.02* 1.76)
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective number
of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal
and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
36
THS10064
www.ti.com
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
MECHANICAL DATA
DA (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
38 PINS SHOWN
0,30
0,19
0,65
38
0,13 M
20
6,20
NOM
8,40
7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°– 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
32
38
A MAX
9,80
11,10
11,10
12,60
A MIN
9,60
10,90
10,90
12,40
DIM
4040066 / D 11/98
NOTES:A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
37
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
THS10064CDA
ACTIVE
TSSOP
DA
32
46
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
THS10064
Samples
THS10064CDAR
ACTIVE
TSSOP
DA
32
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
THS10064
Samples
THS10064IDA
ACTIVE
TSSOP
DA
32
46
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS10064I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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