THS1030CDWG4

 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 D 10-Bit Resolution, 30 MSPS D D D D D D D D 28-PIN TSSOP/SOIC PACKAGE (TOP VIEW) Analog-to-Digital Converter Configurable Input: Single-Ended or Differential Differential Nonlinearity: ±0.3 LSB Signal-to-Noise: 57 dB Spurious Free Dynamic Range: 60 dB Adjustable Internal Voltage Reference Out-of-Range Indicator Power-Down Mode Pin Compatible With TLC876 AGND DVDD I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 OVR DGND description 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 AVDD AIN VREF REFBS REFBF MODE REFTF REFTS 876M AGND REFSENSE STBY OE CLK The THS1030 is a CMOS, low-power, 10-bit, 14 15 30 MSPS analog-to-digital converter (ADC) that can operate with a supply range from 3 V to 5.5 V. The THS1030 has been designed to give circuit developers flexibility. The analog input to the THS1030 can be either single-ended or differential. The THS1030 provides a wide selection of voltage references to match the user’s design requirements. For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output is used to monitor any out-of-range condition in THS1030’s input range. The speed, resolution, and single-supply operation of the THS1030 are suited for applications in STB, video, multimedia, imaging, high-speed acquisition, and communications. The speed and resolution ideally suit charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and camcorders. A wide input voltage range between REFBS and REFTS allows the THS1030 to be applied in both imaging and communications systems. The THS1030C is characterized for operation from 0°C to 70°C, while the THS1030I is characterized for operation from −40°C to 85°C AVAILABLE OPTIONS SPECIFIED TEMPERATURE RANGE PACKAGE MARKINGS 0°C to 70°C TH1030 THS1030I −40°C to 85°C TJ1030 THS1030C 0°C to 70°C TH1030 −40°C to 85°C TJ1030 PRODUCT PACKAGE LEAD PACKAGE DESGIGNATOR† THS1030C TSSOP−28 SOP−28 PW DW THS1030I ORDERING NUMBER TRANSPORT MEDIA, QUANTITY THS1030CPW Tube, 50 THS1030CPWR Tube and Reel, 2000 THS1030IPW Tube, 50 THS1030IPWR Tube and Reel, 2000 THS1030CDW Tube, 20 THS1030CDWR Tube and Reel, 1000 THS1030IDW Tube, 20 THS1030IDWR Tube and Reel, 1000 † For the most current specification and package information, refer to the TI web site at www.ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1999 − 2003, Texas Instruments Incorporated  
  
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 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 functional block diagram AIN REFTS REFBS Core Sample and Hold ADC 10 Output Buffer I/O(0−9) OVR OE Internal Reference B Buffer A MODE REFTF REFBF Timing Circuit VBG ORG GND REFSENSE VREF STBY CLK Terminal Functions TERMINAL NAME AGND NO. I/O DESCRIPTION 1, 19 I Analog ground AIN 27 I Analog input AVDD CLK 28 I Analog supply 15 I Clock input DGND 14 I Digital ground DVDD 2 I Digital driver supply I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 3 4 5 6 7 8 9 10 11 12 O Digital I/O bit 0 (LSB) Digital I/O bit 1 Digital I/O bit 2 Digital I/O bit 3 Digital I/O bit 4 Digital I/O bit 5 Digital I/O bit 6 Digital I/O bit 7 Digital I/O bit 8 Digital I/O bit 9 (MSB) MODE 23 I Mode input OE 16 I High to 3-state the data bus, low to enable the data bus OVR 13 O Out-of-range indicator REFBS 25 I Reference bottom sense REFBF 24 I Reference bottom decoupling REFSENSE 18 I Reference sense REFTF 22 I Reference top decoupling REFTS 21 I Reference top sense STBY 17 I High = power-down mode, low = normal operation mode VREF 26 I/O 876M 20 I 2 Internal and external reference High = THS1030 mode, low = TLC876 mode (see section 4 for TLC876 mode) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range: AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −6.5 V to 6.5 V Mode input voltage range, MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Reference voltage input range, REFTF, REFTB, REFTS, REFBS to AGND . . . . . . . −0.3 V to AVDD + 0.3 V Analog input voltage range, AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Reference input voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Reference output voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Clock input voltage range, CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Digital input voltage range, digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V Digital output voltage range, digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions digital inputs MIN High-level input voltage, VIH Low-level input voltage, VIL Clock input 0.8 × AVDD All other inputs 0.8 × DVDD NOM MAX UNIT V Clock input 0.2 × AVDD All other inputs 0.2 × DVDD V analog inputs MIN Analog input voltage, VI(AIN) Reference input voltage NOM MAX UNIT REFBS REFTS V VI(VREF) VI(REFTS) 1 2 V 1 V VI(REFBS) 0 AVDD AVDD−1 V power supply Supply voltage Maximum sampling rate = 30 MSPS MIN NOM MAX 3 3.3 5.5 3 3.3 5.5 AVDD DVDD UNIT V REFTS, REFBS reference voltages (MODE = AVDD) MIN MAX UNIT V 0 AVDD AVDD−1 1 2 V Reference input voltage (top) REFTS 1 Reference input voltage (bottom) REFBS Differential input voltage (REFTS − REFBS) Switched sampling input capacitance on REFTS or REFBS POST OFFICE BOX 655303 NOM 0.6 • DALLAS, TEXAS 75265 V pF 3 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 recommended operating conditions (continued) sampling rate and resolution PARAMETER fs MIN Sample frequency NOM 5 Resolution MAX UNIT 30 MSPS 10 Bits electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2-V input span from 0.5 V to 2.5 V, external reference, TA = Tmin to Tmax (unless otherwise noted) analog inputs PARAMETER MIN TYP MAX REFBS UNIT VI(AIN) CI Analog input voltage REFTS Switched sampling input capacitance 1.2 pF V BW Full power bandwidth (−3 dB) 150 MHz Ilkg DC leakage current (input = ± FS) 60 µA VREF reference voltages MIN TYP MAX UNIT Internal 1-V reference voltage (REFSENSE = VREF) PARAMETER 0.95 1 1.05 V Internal 2-V reference voltage (REFSENSE = AGND) 1.90 2 2.10 V 2 V External reference voltage (REFSENSE = AVDD) 1 Reference input resistance Ω 680 REFTF, REFBF reference voltages PARAMETER TEST CONDITIONS MIN TYP MAX Differential input voltage (REFTF − REFBF) (REFSENSE = VREF) 0.9 1 1.1 V Differential input voltage (REFTF − REFBF) (REFSENSE = AGND) 1.9 2 2.1 V 1.3 1.5 1.7 2 2.5 3 AVDD = 3 V AVDD = 5 V Input common mode voltage (REFTF + REFBF)/2 AVDD = 3 V AVDD = 5 V 2 VREF = 1 V AVDD = 3 V AVDD = 5 V 2.5 VREF = 2 V AVDD = 3 V AVDD = 5 V 1 VREF = 1 V AVDD = 3 V AVDD = 5 V 0.5 VREF = 2 V REFTF voltage (MODE = AVDD) REFBF voltage (MODE = AVDD) Input resistance between REFTF and REFBF 3 3.5 2 1.5 600 Power up time for valid ADC conversions (tPUconv) See Note 1 1.2 NOTES: 1. Time from control register STBY pin returning low to the ADC conversion to be accurate within 0.1% of fullscale. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V V V V Ω µs 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2-V input span from 0.5 V to 2.5 V, external reference, TA = Tmin to Tmax (unless otherwise noted) (continued) dc accuracy PARAMETER INL Integral nonlinearity (see Note 2) DNL Differential nonlinearity (see Note 3) MIN TYP MAX UNIT ±1 ±2 LSB ± 0.3 ±1 LSB Offset error (see Note 4) 0.4 1.4 %FSR Gain error (see Note 5) 1.4 3.5 %FSR Missing code No missing code assured NOTES: 2. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two endpoints. 3. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last transition level – first transition level) ÷ (2 n – 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than –1 LSB ensures no missing codes. 4. Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024). 5. Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024). dynamic performance (See Note 6) PARAMETER TEST CONDITIONS f = 3.5 MHz ENOB MIN TYP 8.4 9 f = 3.5 MHz, AVDD = 5 V Effective number of bits Spurious free dynamic range 7.7 56 64.6 f = 15 MHz 48.5 −60 f = 3.5 MHz, AVDD = 5 V −66.9 f = 15 MHz −47.5 f = 15 MHz, AVDD = 5 V f = 3.5 MHz SNR f = 3.5 MHz, AVDD = 5 V Signal-to-noise and distortion f = 15 MHz f = 15 MHz, AVDD = 5 V NOTES: 6. Input amplitude of single tone sine wave for dynamic tests is −0.5 dBFS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57 dB 53.1 f = 15 MHz, AVDD = 5 V SINAD dB 56 f = 15 MHz f = 3.5 MHz −56 −53.1 53 f = 3.5 MHz, AVDD = 5 V Signal-to-noise ratio dB 53 f = 3.5 MHz Total harmonic distortion 60.6 f = 3.5 MHz, AVDD = 5 V f = 15 MHz, AVDD = 5 V THD Bits 7.8 f = 15 MHz, AVDD = 5 V SFDR UNIT 9 f = 15 MHz, 3 V f = 3.5 MHz MAX 49.4 52.5 56 56 48.6 dB 48.1 5 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2-V input span from 0.5 V to 2.5 V, external reference, TA = Tmin to Tmax (unless otherwise noted) (continued) clock PARAMETER MIN TYP MAX UNIT tc tw(CKH) Clock cycle 33 Pulse duration, clock high 15 16.5 110 ns tw(CKL) td(o) Pulse duration, clock low 15 16.5 110 ns Clock to data valid, delay time 25 ns td(DZ) td(DEN) Output disable to Hi-Z output, disable time 20 ns Output enable to output valid, enable time 20 ns td(AP) ns Pipeline latency 3 Cycles Aperture delay time 4 ns Aperture uncertainty (jitter) 2 ps power supply (See Note 7) PARAMETER ICC Operating supply current PD Power dissipation TYP MAX AVDD = DVDD = 3 V, MODE = AVDD AVDD = DVDD = 3 V TEST CONDITIONS MIN 29 40 87 120 AVDD = DVDD = 5 V AVDD = DVDD = 3 V, MODE = AVDD 150 UNIT mA mW PD(STBY) Standby power 3 5 mW NOTES: 7. Mode and REFSENSE are set to AVDD. The internal reference buffer is powered up to buffer the externally applied 0.5 V REFBS and 2.5 V REFTS. 1.5 VDC is applied at AIN while converting data at 30 MSPS. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION Sample 2 Sample 3 Sample 1 Sample 5 Sample 4 Analog Input tc tw(CKL) tw(CKH) Input Clock See Note A td(o) Pipeline Latency Digital Output Sample 1 Sample 2 NOTE A: All timing measurements are based on 50% of edge transition. Figure 1. Digital Output Timing Diagram OE See Note A td(DZ) td(DEN) I/O Hi-Z Output Output NOTE A: All timing measurements are based on 50% of edge transition. Figure 2. Output Enable Timing Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS POWER vs SAMPLING FREQUENCY 90 AVDD = DVDD = 3 V fi = 3.5 MHz, −0.5 dBFS TA = 25°C Power − mW 88 86 84 82 80 78 76 5 10 15 20 25 30 60 85 fs − Sampling Frequency − MHz Figure 3 EFFECTIVE NUMBER OF BITS vs TEMPERATURE Effective Number of Bits 10.0 9.5 9.0 AVDD = DVDD = 3 V fi = 3.5 MHz, −0.5 dBFS fs = 30 MSPS 8.5 8.0 7.5 7.0 −40 −15 10 35 TA − Temperature − °C Figure 4 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY Effective Number of Bits 10.0 9.5 9.0 8.5 8.0 AVDD = DVDD = 3 V fi = 3.5 MHz, −0.5 dBFS TA = 25°C 7.5 7.0 5 10 15 20 25 30 25 30 fs − Sampling Frequency − MSPS Figure 5 EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY Effective Number of Bits 10.0 9.5 9.0 8.5 8.0 AVDD = 5 V DVDD = 3 V fi = 3.5 MHz, −0.5 dBFS TA = 25°C 7.5 7.0 5 10 15 20 fs − Sampling Frequency − MSPS Figure 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY Effective Number of Bits 10.0 AVDD = DVDD = 5 V fi = 3.5 MHz, −0.5 dBFS TA = 25°C 9.5 9.0 8.5 8.0 7.5 7.0 5 10 15 20 25 30 fs − Sampling Frequency − MSPS Figure 7 DNL − Differential Nonlinearity − LSB DIFFERENTIAL NONLINEARITY vs INPUT CODE 1.0 0.8 0.6 0.4 0.2 −0.0 −0.2 −0.4 −0.6 −0.8 −1.0 AVDD = 3 V DVDD = 3 V fs = 30 MSPS 0 128 256 384 512 640 Input Code Figure 8 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 768 896 1024 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY vs INPUT CODE 2.0 AVDD = 3 V DVDD = 3 V fs = 30 MSPS 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 0 128 256 384 512 640 768 896 1024 Input Code Figure 9 FFT vs FREQUENCY 0 AVDD = 3 V DVDD = 3 V fi = 3.5 MHz, −0.5dBFS −20 FFT − dB −40 −60 −80 −100 −120 −140 0 2 4 6 8 10 12 14 f − Frequency − MHz Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION The analog input AIN is sampled in the sample and hold unit, the output of which feeds the ADC core, where the process of analog to digital conversion is performed against ADC reference voltages, REFTF and REFBF. Connecting the MODE pin to one of three voltages, AGND, AVDD or AVDD/2 sets up operating configurations. The three settings open or close internal switches to select one of the three basic methods of ADC reference generation. Depending on the user’s choice of operating configuration, the ADC reference voltages may come from the internal reference buffer or may be fed from completely external sources. Where the reference buffer is employed, the user can choose to drive it from the onboard reference generator (ORG), or may use an external voltage source. A specific configuration is selected by connections to the REFSENSE, VREF, REFTS and REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user. The ADC core drives out through output buffers to the data pins D0 to D9. The output buffers can be disabled by the OE pin. A single, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is sampled on the rising edge of CLK, and corresponding data is output after following third rising edge. The STBY pin controls the THS1030 power down. The user-chosen operating configuration and reference voltages determine what input signal voltage range the THS1030 can handle. The following sections explain: D The internal signal flow of the device, and how the input signal span is related to the ADC reference voltages D The ways in which the ADC reference voltages can be buffered internally, or externally applied D How to set the onboard reference generator output, if required, and several examples of complete configurations signal processing chain (sample and hold, ADC) Figure 11 shows the signal flow through the sample and hold unit to the ADC core. REFTF VP+ AIN 1 REFTS −1/2 REFBS −1/2 Sample and Hold ADC Core VP− REFBF Figure 11. Analog Input Signal Flow 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION sample and hold The analog input signal AIN is applied to the AIN pin, either dc-coupled or ac-coupled. The differential sample and hold processes AIN with respect to the voltages applied to the REFTS and REFBS pins, to give a differential output VP+ − VP − = VP given by: VP + A IN * VM Where: VM + (REFTS ) REFBS) 2 (1) For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale input voltage. However if MODE = AVDD/2 then REFTS and REFBS can be connected together to operate with AIN as a complementary pair of differential inputs (see Figures 16 and 17). analog-to-digital converter In all operating configurations, VP is digitized against ADC reference voltages REFTF and REFBF, full-scale values of VP being given by: VPFS )+ ) (REFTF * REFBF) 2 VPFS *+ * (REFTF * REFBF) 2 (2) VP voltages outside the range VPFS− to VPFS+ lie outside the conversion range of the ADC. Attempts to convert out-of-range inputs are signaled to the application by driving the OVR output pin high. VP voltages less than VPFS− give ADC output code 0. VP voltages greater than VPFS+ give output code 1023. complete system Combining the above equations, the analog full scale input voltages at AIN which give VPFS+ and VPFS− at the sample and hold output are: A IN + FS )+ VM ) (REFTF * REFBF) 2 (3) IN + FS *+ VM * (REFTF * REFBF) 2 (4) and A The analog input span (voltage range) that lies within the ADC conversion range is: Input span + [(FS )) * (FS *)] + (REFTF * REFBF) (5) The REFTF and REFBF voltage difference sets the device input range. The next sections describe in detail the various methods available for setting voltages REFTF and REFBF to obtain the desired input span and ADC performance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION ADC reference generation The THS1030 has three primary modes of ADC reference generation, selected by the voltage level applied to the MODE pin. Connecting the MODE pin to AGND gives full external reference mode. In this mode, the user supplies the ADC reference voltages directly to pins REFTF and REFBF. This mode is used where there is need for minimum power drain or where there are very tight tolerances on the ADC reference voltages. This mode also offers the possibility of Kelvin connection of the reference inputs to the THS1030 to eliminate any voltage drops from remote references that may occur in the system. Only single-ended input is possible in this mode. Connecting the MODE pin to AVDD/2 gives differential mode. In this mode, the ADC reference voltages REFTF and REFBF are generated by the internal reference buffer from the voltage applied to the VREF pin. This mode is suitable for handling differentially presented inputs, which are applied to the AIN and REFTS/REFBS pins. A special case of differential mode is center span mode, in which the user applies a single-ended signal to AIN and applies the mid-scale input voltage (VM) to the REFTS and REFBS pins. Connecting the MODE pin to AVDD gives top/bottom mode. In this mode, the ADC reference voltages REFTF and REFBF are generated by the internal reference buffer from the voltages applied to the REFTS and REFBS pins. Only single-ended input is possible in top/bottom mode. When MODE is connected to AGND, the internal reference buffer is powered down, its inputs and outputs disconnected, and REFTS and REFBS internally connected to REFTF and REFBF respectively. These nodes are connected by the user to external sources to provide the ADC reference voltages. The internal connections are designed for use in kelvin connection mode (Figure 14). When using external reference mode as shown in Figure 13, REFTS must be shorted to REFTF and REFBS must be shorted to REFBF externally. The mean of REFTF and REFBF must be equal to AVDD/2. See Figure 13. Table 1. Typical Set of Reference Connections REFERENCE MODE External Internal MODE AGND AVDD/2 External (through internal reference buffer) Output of VREF can be externally tied to REFTS or REFBS to provide one of the reference voltages 14 AVDD REFSENSE VREF VOLTAGE AVDD Disabled VREF 1V AGND 2V External divider 1 + Ra/Rb (see Figure 22) AVDD Disabled VREF 1V AGND 2V External divider 1 + Ra/Rb (see Figure 22) POST OFFICE BOX 655303 REFTS, REFBS ANALOG INPUT FIGURES Reference buffer powered down, reference voltage provided directly by REFT and REFB Single-ended 12, 13, 14 Externally connect REFTS to REFBS. This pair then forms AIN− to the ADC. Differential or center span 15, 16, 17 REFTS = VFS+ REFBS = VFS− Single-ended (top-bottom mode) 18, 19 • DALLAS, TEXAS 75265 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION full external reference mode (mode = AGND) REFTF 1 AIN+ REFTS −1/2 REFBS −1/2 Sample and Hold ADC Core REFBF Internal Reference Buffer Figure 12. ADC Reference Generation, Full External Reference Mode (MODE = AGND) It is also possible to use REFTS and REFBS as sense lines to drive the REFTF and REFBF lines (Kelvin mode) to overcome any voltage drops within the system. See Figure 14. AVDD +FS AVDD 2 −FS AIN DC SOURCE = + FS REFTS DC SOURCE = −FS REFBS 0.1 µF 0.1 µF REFSENSE REFTF 10 µF 0.1 µF REFBF MODE Figure 13. Full External Reference Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION full external reference mode (mode = AGND) (continued) AVDD +FS AVDD 2 −FS AIN REFSENSE REFTS REFBS _ REFTF REFT = +FS + 0.1 µF 10 µF 0.1 µF _ REFB = −FS REFBF + MODE 0.1 µF Figure 14. Full External Reference With Kelvin Connections differential input mode (MODE = AVDD/2) REFTF = AIN+ AIN− 1 REFTS −1/2 REFBS −1/2 VREF AGND Sample and Hold Internal Reference Buffer AVDD + VREF 2 ADC Core REFBF = AVDD − VREF 2 Figure 15. ADC Reference Generation, MODE = AVDD/2 When MODE = AVDD/2, the internal reference buffer is enabled, its outputs internally switched to REFTF and REFBF and inputs internally switched to VREF and AGND as shown in Figure 15. The REFTF and REFBF voltages are centered on AVDD/2 by the internal reference buffer and the voltage difference between REFTF and REFBF equals the voltage at VREF. The internal REFTS to REFBS and REFTF to REFBF switches are open in this mode, allowing REFTS and REFBS to form the AIN− to the sample and hold. Depending on the connection of the REFSENSE pin, the voltage on VREF may be externally driven, or set to an internally generated voltage of 1 V, 2 V, or an intermediate voltage (see the section on onboard reference generator configuration). 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION differential input mode (MODE = AVDD/2) (continued) AVDD 2 +FS AIN+ −FS AIN +FS MODE REFTS AIN− −FS REFBS REFSENSE 0.1 µF 0.1 µF REFTF 10 µF VREF 0.1 µF REFBF Figure 16. Differential Input Mode, 1-V Reference Span AVDD 2 +FS VM −FS AIN REFTS DC SOURCE = VM VM + _ REFBS 0.1 µF 0.1 µF MODE REFTF 10 µF 0.1 µF REFBF REFSENSE Figure 17. Center Span Mode, 2-V Reference Span POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION top/bottom mode (MODE = AVDD) REFTF = AVDD + (REFTS − REFBS) 2 1 AIN+ REFTS −1/2 REFBS −1/2 Sample and Hold ADC Core REFBF = AVDD − (REFTS + REFBS) Internal Reference Buffer 2 Figure 18. ADC Reference Generation Mode = AVDD Connecting MODE to AVDD enables the internal reference buffer. Its inputs are internally switched to the REFTS and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections (REFTS to REFTF) and (REFBS to REFBF) are broken. The REFTS and REFBS voltages set the analog input span limits FS+ and FS− respectively. Any voltages at AIN greater than REFTS or less than REFBS will cause ADC over-range, which is signaled by OVR going high when the conversion result is output. Typically, REFSENSE is tied to AVDD to disable the ORG output to VREF (as in Figure 19), but the user can choose to use the ORG output to VREF as either REFTS or REFBS. AVDD +FS AIN −FS MODE DC SOURCE = FS+ REFTS REFSENSE DC SOURCE = FS− REFBS 0.1 µF 0.1 µF REFTF 10 µF 0.1 µF REFBF Figure 19. Top/Bottom Reference Mode 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION onboard reference generator configuration The onboard reference generator (ORG) can provide a supply-voltage-independent and temperatureindependent voltage on pin VREF. External connections to REFSENSE control the ORG’s output to the VREF pin as shown in Table 2. Table 2. Effect of REFSENSE Connection on VREF Value REFSENSE CONNECTION ORG OUTPUT TO VREF REFER TO: VREF pin 1V Figure 20 AGND 2V Figure 21 External divider junction (1 + RA/RB) Figure 22 AVDD Open circuit Figure 23 REFSENSE = AVDD powers the ORG down, saving power when the ORG function is not required. If MODE = AVDD/2, the voltage on VREF determines the ADC reference voltages: REFTF + REFBF + AV DD ) VREF 2 2 (6) AV DD * VREF 2 2 REFTF * REFBF + VREF Internal Reference Buffer VBG + _ + _ Mode = AVDD 2 VREF = 1 V 0.1 µF REFSENSE 1 µF Tantalum AGND Figure 20. 1-V VREF Using ORG POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION onboard reference generator configuration (continued) Internal Reference Buffer VBG + _ Mode = AVDD 2 + _ VREF = 2 V 0.1 µF 10 kΩ 1 µF Tantalum REFSENSE 10 kΩ AGND Figure 21. 2-V VREF Using ORG Internal Reference Buffer VBG + _ + _ Mode = AVDD 2 VREF = 1 + (Ra/Rb) Ra REFSENSE Rb AGND Figure 22. External Divider Mode 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.1 µF 1 µF Tantalum 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION onboard reference generator configuration (continued) Internal Reference Buffer VBG + _ Mode = AVDD 2 + _ VREF = External REFSENSE AVDD AGND Figure 23. Drive VREF Mode operating configuration examples This section provides examples of operating configurations. Figure 24 shows the operating configuration in top/bottom mode for a 2-V span single-ended input, using VREF to drive REFTS. Connecting the mode pin to AVDD puts the THS1030 in top/bottom mode. Connecting pin REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are user-connected to VREF and AGND respectively to match the AIN pin input range to the voltage range of the input signal. AVDD 2V 1V 0V AIN MODE VREF = 2 V REFTS 0.1 µF REFTF REFSENSE 0.1 µF 10 µF 0.1 µF REFBF REFBS Figure 24. Operation Configuration in Top/Bottom Mode In Figure 25 the input signal is differential, so mode = AVDD/2 (differential mode) is set to allow the inverse signal to be applied to REFTS and REFBS. The differential input goes from −0.8 V to 0.8 V, giving a total input signal span of 1.6 V, REFTF−REFBF should therefore equal 1.6 V. REFSENSE is connected to resistors RA and RB (external divider mode) to make VREF = 1.6 V, that is RA/RB = 0.6 (see Figure 22). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION operating configuration examples (continued) AVDD 2 1.4 V 1V AIN+ 0.6 V AIN− AIN 1.4 V 1V 0.6 V MODE REFTS VREF = 1.6 V RA REFBS REFSENSE 0.1 µF REFTF 10 µF 0.1 µF RB 0.1 µF REFBF Figure 25. Differential Operation Figure 26 shows a center span configuration for an input waveform swinging between 0.2 V and 1.9 V. Pins REFTS and REFBS are connected to a voltage source of 1.05 V, equal to the mid-scale of the input waveform. REFTF−REFBF should be set equal to the span of the input waveform, 1.7 V, so VREF is connected to an external source of 1.7 V. REFSENSE must be connected to AVDD to disable the ORG output to VREF (see Figure 23) to allow this external source to be applied. AVDD 2 1.9 V 1.05 V 0.2 V AIN AVDD MODE REFTS REFSENSE DC SOURCE = 1.05 V REFBS 0.1 µF 0.1 µF REFTF 10 µF VREF 0.1 µF REFBF Figure 26. Center Span Operation 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DC SOURCE = 1.7 V 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION power management In power-sensitive applications (such as battery-powered systems) where the THS1030 ADC is not required to convert continuously, power can be saved between conversion intervals by placing the THS1030 into power-down mode. This is achieved by setting pin 17 (STBY) to 1. In power-down mode, the device typically consumes less than 1 mW of power (from AVDD and DVDD) in either top/bottom mode or center-span mode. On power up, the THS1030 typically requires 5 ms of wake-up time before valid conversion results are available in either top/bottom or center span modes. Disabling the ORG in applications where the ORG output is not required can also reduce power dissipation by 1 mA analog IDD. This is achieved by connecting the REFSENSE pin to AVDD. output format and digital I/O While the OE pin is held low, ADC conversion results are output at pins D0 (LSB) to D9 (MSB). The ADC input over-range indicator is output at pin OVR. OVR is also disabled when OE is held high. The ADC output data format is unsigned binary (output codes 0 to 1023). driving the THS1030 analog inputs driving AIN Figure 26 shows an equivalent circuit for the THS1030 AIN pin. The load presented to the system at the AIN pin comprises the switched input sampling capacitor, CSAMPLE, and various stray capacitances, CP1 and CP2. AVDD CLK 1.2 pF AIN C(Sample) C2 1.2 pF C1 8 pF AGND CLK + _ VLAST Figure 27. Equivalent Circuit of Analog Input AIN In any single-ended input mode, VLAST = the average of the previously sampled voltage at AIN and the average of the voltages on pins REFTS and REFBS. In any differential mode, VLAST = the common mode input voltage. The external source driving AIN must be able to charge and settle into CSAMPLE and the CP1 and CP2 strays to within 0.5 LSB error while sampling (CLK pin low) to achieve full ADC resolution. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION AIN input current and input load modeling When CLK goes low, the source driving AIN must charge the total switched capacitance CS = CSAMPLE + CP2. The total charge transferred depends on the voltage at AIN and is given by: Q CHARGING + (AIN * V LAST ) C . S (7) For a fixed voltage at AIN, so that AIN and VLAST do not change between samples, the maximum amount of charge transfer occurs at AIN = FS− (charging current flows out of THS1030) and AIN = FS+ (current flows into THS1030). If AIN is held at the voltage FS+, VLAST = [(FS+) + VM]/2, giving a maximum transferred charge: Q(FS) + (FS )) * [(FS )) ) VM] 2 C + S + (1ń4 of the input voltage span) C [(FS )) * VM] C S 2 (8) S If the input voltage changes between samples, then the maximum possible charge transfer is Q(max) + 3 Q(FS) (9) which occurs for a full-scale input change (FS+ to FS− or FS− to FS+) between samples. The charging current pulses can make the AIN source jump or ring, especially if the source is slightly inductive at high frequencies. Inserting a small series resistor of 20 Ω or less in the input path can damp source ringing (see Figure 31). This resistor can be made larger than 20 Ω if reduced input bandwidth or distortion performance is acceptable. R < 20 Ω AIN VS Figure 28. Damping Source Ringing Using a Small Resistor 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION equivalent input resistance at AIN and ac-coupling to AIN Some applications may require ac-coupling of the input signal to the AIN pin. Such applications can use an ac-coupling network such as shown in Figure 29. AVDD R(Bias1) Cin AIN R(Bias2) Figure 29. AC-Coupling the Input Signal to the AIN Pin Note that if the bias voltage is derived from the supplies, as shown in Figure 29, then additional filtering should be used to ensure that noise from the supplies does not reach AIN. Working with the input current pulse equations given in the previous section is awkward when designing ac-coupling input networks. For such design, it is much simpler to model the AIN input as an equivalent resistance, RAIN, from the AIN pin to a voltage source VM where VM = (REFTS + REFBS)/2 and RAIN = 1 / (CS x fclk) where fclk is the CLK frequency. The high-pass −3 dB cutoff frequency for the circuit shown in Figure 29 is: f (*3 dB) + ǒ2 1 p R Ǔ tot IN (10) where RINtot is the parallel combination of Rbias1, Rbias2, and RAIN. This approximation is good provided that the clock frequency, fclk, is much higher than f(−3 dB). Note also that the effect of the equivalent RAIN and VM at the AIN pin must be allowed for when designing the bias network dc level. details The above value for RAIN is derived by noting that the average AIN voltage must equal the bias voltage supplied by the ac coupling network. The average value of VLAST in equation 8 is thus a constant voltage VLAST = V(AIN bias) – VM For an input voltage Vin at the AIN pin, Qin = (Vin – VLAST) x Cs Provided that f (−3 dB) is much lower than fclk, a constant current flowing over the clock period can approximate the input charging pulse Iin = Qin / tclk = Qin x fclk = (Vin – VLAST) x CS x fclk POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION details (continued) The ac input resistance RAIN is then RAIN = dIin / dVin = 1 / (dVin / dIin) = 1 / (CS x fclk) driving the VREF pin (differential mode) Figure 30 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin (MODE = AVDD/2 and REFSENSE = AVDD ). AVDD RIN VREF REFSENSE = AVDD, Mode = AVDD 2 14 kΩ AGND + _ AVDD + VREF 4 Figure 30. Equivalent Circuit of VREF The current flowing into IIN is given by I IN + ǒ3 VREF * AV ǒ4 R Ǔ Ǔ DD IN (11) Note that the actual IIN may differ from this value by up to ±50% due to device-to-device processing variations and allowing for operating temperature variations. The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analog ground and capable of driving IIN. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION driving the internal reference buffer (top/bottom mode) Figure 31 shows the load present on the REFTS and REFBS pins in top/bottom mode due to the internal reference buffer only. The sample and hold must also be driven via these pins, which adds additional load. AVDD RIN REFTS REFBS 14 kΩ Mode = AVDD AGND AVDD + REFTS + REFBS 4 + _ Figure 31. Equivalent Circuit of Inputs to Internal Reference Buffer Equations for the currents flowing into REFTS and REFBS are: I I TS + IN BS + IN ǒ3 REFTS * AV ǒ4 ǒ3 R DD Ǔ IN REFBS * AV ǒ4 Ǔ * REFBS R DD (12) Ǔ * REFTS Ǔ IN (13) These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving the sample and hold. Tolerance on these currents are ±50%. driving REFTS and REFBS AVDD CLK 0.6 pF REFTS REFBS CSAMPLE C2 0.6 pF C1 7 pF AGND Mode = AVDD CLK + _ Internal Reference Buffer VLAST Figure 32. Equivalent Circuit of REFTS and REFBS Inputs This is essentially a combination of driving the ADC internal reference buffer (if in top/bottom mode) and also driving a switched capacitor load like AIN, but with the sampling capacitor and CP2 on each pin now being 0.6 pF and about 0.6 pF respectively. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION driving REFTF and REFBF (full external reference mode) AVDD REFTF To REFBS (For Kelvin Connection) AGND AVDD 680 R REFBF To REFTS (For Kelvin Connection) AGND Figure 33. Equivalent Circuit of REFTF and REFBF Inputs Note the need for off-chip decoupling. driving the clock input Obtaining good performance from the THS1030 requires care when driving the clock input. Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as possible in which to operate. The CLK pin should be driven from a low jitter source for best dynamic performance. To maintain low jitter at the CLK input, any clock buffers external to the THS1030 should have fast rising edges. Use a fast logic family such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter. The CLK input threshold is nominally around AVDD/2—ensure that any clock buffers have an appropriate supply voltage to drive above and below this level. digital output loading and circuit board layout The THS1030 outputs are capable of driving rail-to-rail with up to 20 pF of load per pin at 30-MHz clock and 3-V digital supply. Minimizing the load on the outputs will improve THS1030 signal-to-noise performance by reducing the switching noise coupling from the THS1030 output buffers to the internal analog circuits. The output load capacitance can be minimized by buffering the THS1030 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks between the THS1030 and this buffer. Noise levels at the output buffers, and hence coupling to the analog circuits within THS1030, becomes worse as the THS1030 digital supply voltage is increased. Where possible, consider using the lowest DVDD that the application can tolerate. Use good layout practices when designing the application PCB to ensure that any off-chip return currents from the THS1030 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any sensitive analog circuits. The THS1030 should be soldered directly to the PCB for best performance. Socketing the device will degrade performance by adding parasitic socket inductance and capacitance to all pins. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
   
      

  
 SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 PRINCIPLES OF OPERATION user tips for obtaining best performance from the THS1030 D D D D D D Voltages on AIN, REFTF and REFBF and REFTS and REFBS must all be inside the supply rails. ORG modes offer the simplest configurations for ADC reference generation. Choose differential input mode for best distortion performance. Choose a 2-V ADC input span for best noise performance. Choose a 1-V ADC input span for best distortion performance. If the ORG is not used to provide ADC reference voltages, its output may be used for other purposes in the system. Care should be taken to ensure noise is not injected into the THS1030. D Use external voltage sources for ADC reference generation where there are stringent requirements on accuracy and drift. D Drive clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB traces. TLC876 mode The THS1030 is pin compatible with the TI TLC876 and thus enables users of TLC876 to upgrade to higher speed by dropping the THS1030 into their sockets. Grounding the 1876M pin effectively puts the THS1030 into 876 mode using the external ADC reference. The MODE pin should either be grounded or left floating. The REFSENSE pin is connected to DVDD when the THS1030 is dropped into a TLC876 socket. For DVDD = 5-V applications, this will disable the ORG. For TLC876 applications using DVDD = 3.3 V, the VREF pin will be driven to AVSS. In TLC876/AD876 mode, the pipeline latency is increased to 3.5 clock cycles to match the TLC876 latency. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 PACKAGE OPTION ADDENDUM www.ti.com 26-Oct-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) THS1030CDW OBSOLETE SOIC DW 28 TBD Call TI Call TI 0 to 70 THS1030CDWG4 OBSOLETE SOIC DW 28 TBD Call TI Call TI 0 to 70 TH1030 THS1030CDWR OBSOLETE SOIC DW 28 TBD Call TI Call TI 0 to 70 TH1030 THS1030CPW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TH1030 THS1030CPWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TH1030 THS1030IDW OBSOLETE SOIC DW 28 TBD Call TI Call TI -40 to 85 TJ1030 THS1030IPW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TJ1030 THS1030IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TJ1030 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Oct-2016 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Apr-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant THS1030CPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 THS1030IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Apr-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS1030CPWR TSSOP PW 28 2000 367.0 367.0 38.0 THS1030IPWR TSSOP PW 28 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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