THS1040IPWR

Not Recommended For New Designs
 SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004     

  
 bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output indicates any out-of-range condition in THS1040’s input signal. FEATURES D Analog Supply 3 V D Digital Supply 3 V D Configurable Input Functions: D D D D D D D D The speed, resolution, and single-supply operation of the THS1040 are suited to applications in set-top-box (STB), video, multimedia, imaging, high-speed acquisition, and communications. The speed and resolution ideally suit charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and camcorders. A wide input voltage range allows the THS1040 to be applied in both imaging and communications systems. − Single Ended − Differential Differential Nonlinearity: ± 0.45 LSB Signal-to-Noise: 60 dB Typ f(IN) at 4.8 MHz Spurious Free Dynamic Range: 72 dB Adjustable Internal Voltage Reference On-Chip Voltage Reference Generator Unsigned Binary Data Output Out-of-Range Indicator Power-Down Mode The THS1040C is characterized for operation from 0°C to 70°C, while the THS1040I is characterized for operation from −40°C to 85°C. APPLICATIONS D Video/CCD Imaging D Communications D Set-Top Box D Medical 28-PIN TSSOP/SOIC PACKAGE (TOP VIEW) DESCRIPTION The THS1040 is a CMOS, low power, 10-bit, 40-MSPS analog-to-digital converter (ADC) that operates from a single 3-V supply. The THS1040 has been designed to give circuit developers flexibility. The analog input to the THS1040 can be either single-ended or differential. The THS1040 provides a wide selection of voltage references to match the user’s design requirements. For more design flexibility, the internal reference can be AGND DVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OVR DGND 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 AVDD AIN+ VREF AIN− REFB MODE REFT BIASREF TEST AGND REFSENSE STBY OE CLK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 
 
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 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 AVAILABLE OPTIONS PRODUCT PACKAGE LEAD PACKAGE DESGIGNATOR† SPECIFIED TEMPERATURE RANGE PACKAGE MARKINGS 0°C to 70°C TH1040 THS1040C TSSOP−28 PW THS1040I −40°C to 85°C TJ1040 THS1040C 0°C to 70°C TH1040 −40°C to 85°C TJ1040 SOP−28 DW THS1040I ORDERING NUMBER TRANSPORT MEDIA, QUANTITY THS1040CPW Tube, 50 THS1040CPWR Tube and Reel, 2000 THS1040IPW Tube, 50 THS1040IPWR Tube and Reel, 2000 THS1040CDW Tube, 20 THS1040CDWR Tube and Reel, 1000 THS1040IDW Tube, 20 THS1040IDWR Tube and Reel, 1000 † For the most current specification and package information, refer to the TI web site at www.ti.com. functional block diagram Digital Control STBY BIASREF AIN+ SHA 10-Bit ADC AIN− 3-State Output Buffers D (0−9) OVR OE MODE ADC Reference Resistor Mode Detection DVDD DGND Timing Circuit VREF CLK + A2 A1 AVDD 0.5 V − AGND REFB NOTE: A1 − Internal bandgap reference A2 − Internal ADC reference generator 2 www.ti.com REFT VREF REFSENSE Not Recommended For New Designs
 SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 Terminal Functions TERMINAL NAME AGND NO. I/O DESCRIPTION 1, 19 I Analog ground AIN+ 27 I Positive analog input AIN− 25 I Negative analog input AVDD 28 I Analog supply BIASREF 21 O When the MODE pin is at AVDD, a buffered AVDD/2 is present at this pin that can be used by external input biasing circuits. The output is high impedance when MODE is AGND or AVDD/2. CLK 15 I Clock input DGND 14 I Digital ground DVDD 2 I Digital supply D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 3 4 5 6 7 8 9 10 11 12 O Digital data bit 0 (LSB) Digital data bit 1 Digital data bit 2 Digital data bit 3 Digital data bit 4 Digital data bit 5 Digital data bit 6 Digital data bit 7 Digital data bit 8 Digital data bit 9 (MSB) MODE 23 I Operating mode select (AGND, AVDD/2, or AVDD) OE 16 I High to 3-state the data bus, low to enable the data bus OVR 13 O Out-of-range indicator REFB 24 I/O Bottom ADC reference voltage REFSENSE 18 I REFT 22 I/O STBY 17 I Drive high to power-down the THS1040 TEST 20 I Production test pin. Tie to DVDD or DGND VREF 26 I/O VREF mode control Top ADC reference voltage Internal or external reference www.ti.com 3 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range: AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −4 V to 4 V MODE input voltage range, MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Reference voltage input range, REFT, REFB, to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Analog input voltage range, AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Reference input voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Reference output voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Clock input voltage range, CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Digital input voltage range, digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V Digital output voltage range, digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions over operating free-air temperature range TA, (unless otherwise noted) PARAMETER CONDITION MIN NOM MAX UNIT 3 3.6 V Power Supply Supply voltage AVDD, DVDD 3 Analog and Reference Inputs VREF input voltage REFT input voltage REFB input voltage Reference input voltage Reference common mode voltage Analog input voltage differential (see Note 1) VI(VREF) VI(REFT) REFSENSE = AVDD 0.5 1 V MODE = AGND 1.75 2 V 1.25 V 1 V (AVDD/2) + 0.05 1 V VI(REFB) MODE = AGND VI(REFT) − VI(REFB) MODE = AGND 1 (VI(REFT) +VI(REFB))/2 MODE = AGND REFSENSE = AGND VI(AIN) REFSENSE = VREF (AVDD/2) − 0.05 −1 0.5 −0.5 Analog input capacitance, CI Clock input (see Note 2) 0 V 0.5 V 10 pF AVDD V Digital Outputs Maximum digital output load resistance RL Maximum digital output load capacitance CL 100 kΩ 10 pF DVDD V 0.8 V 200 nS 13.75 nS Digital Inputs High-level input voltage, VIH 2.4 Low-level input voltage, VIL DGND Clock frequency (see Note 3) Clock pulse duration Operating free-air temperature, TA tc tw(CKL), tw(CKH) f(CLK) = 5 MHz to 40 MHz f(CLK) = 40 MHz 25 THS1040C 0 70 THS1040I −40 85 11.25 12.5 °C NOTE 1: VI(AIN) is AIN+ − AIN− range, based on VI(REFT) − VI(REFB) = 1 V. Varies proportional to the VI(REFT) − VI(REFB) value. Input common mode voltage is recommended to be AVDD/2. NOTE 2: The clock pin is referenced to AVSS and powered by AVDD. NOTE 3: Clock frequency can be extended to this range without degradation of performance. 4 www.ti.com 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 VPP and 2 VPP, TA = Tmin to Tmax (unless otherwise noted) power supply PARAMETER AVDD DVDD TEST CONDITIONS Supply voltage MIN TYP MAX 3 3.6 3 3.6 UNIT V ICC PD Operating supply current See Note 4 33 40 mA Power dissipation See Note 4 100 120 mW PD(STBY) Standby power t(WU) Power up time for all references from standby, t(PU) 10 µF bypass Wake-up time See Note 5 75 µW 770 µs 45 µs REFT, REFB internal ADC reference voltages outputs (MODE = AVDD or AVDD/2) (See Note 6) PARAMETER TEST CONDITIONS MIN VREF = 0.5 V Reference voltage top, REFT VREF = 1 V VREF = 1 V Input resistance between REFT and REFB MAX UNIT 1.75 AVDD = 3 V V 2 VREF = 0.5 V Reference voltage bottom, REFB TYP 1.25 AVDD = 3 V V 1 1.4 1.9 2.5 kΩ VREF (on-chip voltage reference generator) MIN TYP MAX UNIT Internal 0.5-V reference voltage (REFSENSE = VREF) PARAMETER 0.45 0.5 0.55 V Internal 1-V reference voltage (REFSENSE = AGND) 0.95 1 1.05 V 7 14 21 kΩ TYP MAX UNIT LSB Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2 or AVDD) dc accuracy PARAMETER MIN Resolution 10 Bits INL Integral nonlinearity (see definitions) −1.5 ± 0.75 1.5 DNL Differential nonlinearity (see definitions) −0.9 ± 0.45 0.9 LSB Zero error (see definitions) −1.5 0.7 1.5 %FSR Full-scale error (see definitions) −3 2.2 3 %FSR Missing code No missing code assured NOTE 4: Apply a −1 dBFS 10-KHz triangle wave at AIN+ and AIN− with an internal bandgap reference and ADC reference enabled, and BIASREF enabled at AVDD/2. Any additional load at BIASREF or VREF may require additional current. NOTE 5: Wake-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AGND with external reference sources applied to the device at the time of release of power-down, and an applied 40-MHz clock. Circuits that need to power up are the bandgap, bias generator, ADC, and SHA. NOTE 6: External reference values are listed in the Recommended Operating Conditions Table. www.ti.com 5 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 VPP and 2 VPP, TA = Tmin to Tmax (unless otherwise noted) (continued) dynamic performance (ADC) PARAMETER TEST CONDITIONS f = 4.8 MHz, −0.5 dBFS ENOB Effective number of bits SFDR Spurious free dynamic range THD Total harmonic distortion SNR Signal-to-noise ratio SINAD Signal-to-noise and distortion BW Full power bandwidth (−3 dB) MIN TYP 8.8 9.6 MAX Bits 9.5 f = 20 MHz, −0.5 dBFS f = 4.8 MHz, −0.5 dBFS 60.5 72 f = 20 MHz, −0.5 dBFS 70 f = 4.8 MHz, −0.5 dBFS −72.5 f = 20 MHz, −0.5 dBFS −71.6 f = 4.8 MHz, −0.5 dBFS 55.7 dB −61.3 dB 60 dB 57 f = 20 MHz, −0.5 dBFS f = 4.8 MHz, −0.5 dBFS UNIT 55.6 59.7 dB 59.6 f = 20 MHz, −0.5 dBFS 900 MHz digital specifications PARAMETER MIN NOM MAX UNIT Digital Inputs 0.8 × AVDD 0.8 × DVDD Clock input VIH High-level input voltage VIL Low-level input voltage IIH IIL High-level input current Ci Input capacitance All other inputs V Clock input All other inputs Low-level input current 0.2 × AVDD 0.2 × DVDD V 1 µA |−1| µA 5 pF Digital Outputs VOH High-level output voltage Iload = 50 µA VOL Low-level output voltage Iload = −50 µA DVDD−0.4 V High-impedance output current Rise/fall time Cload = 15 pF 0.4 V ±1 µA 3.5 ns Clock Input tc tw(CKH) Clock cycle time 25 200 ns tw(CKL) Pulse duration, clock high 11.25 110 ns Pulse duration, clock low 11.25 110 ns Clock duty cycle td(o) 45% Clock to data valid, delay time 50% 55% 9.5 16 Pipeline latency td(AP) 4 Aperture delay time ns Cycles 0.1 ns 1 ps Aperture uncertainty (jitter) timing PARAMETER td(DZ) td(DEN) 0 Output enable to output valid, delay time VO(BIASREF) Output voltage 6 MIN Output disable to Hi-Z output, delay time 0 MODE = AVDD www.ti.com (AVDD/2) − 0.1 TYP MAX UNIT 10 ns 10 ns (AVDD/2) + 0.1 V 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION Sample 2 Sample 3 Sample 1 Analog Input Sample 7 Sample 5 tc tw(CKL) tw(CKH) Input Clock Sample 6 Sample 4 See Note A td(o) (I/O Pad Delay or Propagation Delay) Pipeline Latency Digital Output Sample 1 Sample 2 td(DZ) td(DEN) OE NOTE A: All timing measurements are based on 50% of edge transition. Figure 1. Digital Output Timing Diagram www.ti.com 7 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 DNL − Differential Nonlinearity − LSB TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY vs INPUT CODE 1.0 AVDD = 3 V DVDD = 3 V fs = 40 MSPS Vref = 1 V 0.5 0.0 −0.5 −1.0 0 128 256 384 512 640 768 896 1024 768 896 1024 768 896 1024 Input Code INL − Integral Nonlinearity − LSB Figure 2 INTEGRAL NONLINEARITY vs INPUT CODE 1.0 0.5 0.0 AVDD = 3 V DVDD = 3 V fs = 40 MSPS Vref = 1 V −0.5 −1.0 0 128 256 384 512 640 Input Code Figure 3 INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY vs INPUT CODE 1.0 AVDD = 3 V DVDD = 3 V fs = 40 MSPS Vref = 0.5 V 0.5 0.0 −0.5 −1.0 0 128 256 384 512 Input Code Figure 4 8 www.ti.com 640 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY −80 −85 2-V FS Differential Input Range −75 −0.5 dBFS −70 −6 dBFS −65 −60 −55 −20 dBFS −50 −80 THD − Total Harmonic Distortion − dB THD − Total Harmonic Distortion − dB 1-V FS Differential Input Range −45 −75 −0.5 dBFS −70 −65 −6 dBFS −60 −20 dBFS −55 −50 −45 See Note See Note −40 0 −40 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120 fi − Input Frequency − MHz fi − Input Frequency − MHz Figure 5 Figure 6 SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 61 SFDR − Spurious Free Dynamic Range − dB Diff Input = 2 V SE Input = 2 V 59 SNR − Signal-to-Noise Ratio − dB SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY Diff Input = 1 V 57 55 53 SE Input = 1 V 51 49 See Note 47 0 10 20 30 40 50 60 70 80 90 100 110 120 fi − Input Frequency − MHz Figure 7 82 Diff Input = 2 V 72 Diff Input = 1 V 62 52 42 SE Input = 1 V See Note 32 0 10 SE Input = 2 V 20 30 40 50 60 70 80 90 100 110 120 fi − Input Frequency − MHz Figure 8 NOTE: AVDD = DVDD = 3 V, fS = 40 MSPS, 20-pF capacitors AIN+ to AGND and AIN− to AGND, Input series resistor = 25 Ω, 2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V, −0.5 dBFS 1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V, −0.5 dBFS www.ti.com 9 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY Diff Input = 2 V 57 −82 Diff Input = 1 V THD − Total Harmonic Distortion − dB SINAD − Signal-to-Noise Plus Distortion − dB SIGNAL-TO-NOISE PLUS DISTORTION vs INPUT FREQUENCY 52 47 SE Input = 1 V 42 SE Input = 2 V 37 Diff Input = 2 V Diff Input = 1 V −72 −62 −52 −42 SE Input = 1 V SE Input = 2 V See Note See Note 32 −32 0 10 20 30 40 50 60 70 80 90 100 110 120 fi − Input Frequency − MHz 0 10 20 30 40 50 60 70 80 90 100 110 120 fi − Input Frequency − MHz Figure 9 Figure 10 NOTE: AVDD = DVDD = 3 V, fS = 40 MSPS, 20-pF capacitors AIN+ to AGND and AIN− to AGND, Input series resistor = 25 Ω, 2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V, −0.5 dBFS 1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V, −0.5 dBFS SIGNAL-TO-NOISE RATIO vs SAMPLE RATE −75 75 −70 70 SNR − Signal-To-Noise Ratio − dB THD − Total Harmonic Distortion − dB TOTAL HARMONIC DISTORTION vs SAMPLE RATE −65 −60 −55 −50 −45 fi = 20 MHz, −0.5 dBFS 0 5 10 15 20 25 30 35 40 45 55 50 50 Diff Input = 2 V fi = 20 MHz, −0.5 dBFS 40 55 Sample Rate − MSPS 0 5 10 15 20 25 30 35 Sample Rate − MSPS Figure 12 Figure 11 10 60 45 Diff Input = 2 V −40 65 www.ti.com 40 45 50 55 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS TOTAL CURRENT vs CLOCK FREQUENCY POWER DISSIPATION vs SAMPLE RATE 110 Int. Ref TA = 25°C Ext. Ref TA = 25°C 90 AVDD = 3 V Vref = 1 V 36 I DD − Total Current − mA PD − Power Dissipation − mW AVDD = 3 V, Vref = 1 V 34 Int. Ref TA = 25°C 32 30 28 Ext. Ref TA = 25°C 26 70 24 4 8 12 16 20 24 28 32 36 fs − Sample Rate − MSPS 40 44 0 5 10 15 20 25 30 35 40 45 fclk − Clock Frequency − MHz Figure 13 Figure 14 INPUT BANDWIDTH 4 Amplitude − dB 2 AVDD = 3 V DVDD = 3 V fs = 40 MSPS 0 −2 −4 −6 See Note −8 10 100 300 500 700 900 fi − Input Frequency − MHz 1100 Figure 15 NOTE: No series resistors and no bypass capacitors at AIN+ and AIN− inputs. www.ti.com 11 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS ADC CODES vs WAKE-UP SETTLING TIME POWER-UP TIME FOR INTERNAL REFERENCE VOLTAGE FROM STANDBY 125 Vref = 1 V, Reft = 10 µF, Refb = 10 µF, AVDD = 3 V MODE = AGND, fS = 40 MSPS, Ext. REF = 1 V and 2 V, AVDD = 3 V 120 2 115 Vreft 1.6 1.2 ADC Codes Reft, Refb Reference Voltage − V 2.4 Vrefb 0.8 110 105 100 0.4 95 90 −10 1170 990 1080 Power-Up Time − µs 900 810 720 630 540 450 360 270 90 0 180 See Note 0 20 35 50 65 80 Wake-Up Settling Time − µs Figure 17 Figure 16 12 5 www.ti.com 95 110 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS FFT 20 fi= 10 MHz, −0.5 dBFS fS = 40 MSPS, Diff Input = 2 V Amplitude − dB 0 −20 −40 −60 −80 −100 −120 −140 0 5 10 15 20 f − Frequency − MHz Figure 18 FFT 20 Amplitude − dB 0 −20 fi = 4.5 MHz, −0.5 dBFS fS = 40 MSPS, Diff Inpt = 2 V −40 −60 −80 −100 −120 −140 0 5 10 15 20 f − Frequency − MHz Figure 19 www.ti.com 13 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PRINCIPLES OF OPERATION functional overview See the functional block diagram. A single-ended, sample rate clock is required at pin CLK for device operation. Analog inputs AIN+ and AIN− are sampled on each rising edge of CLK in a switched capacitor sample and hold unit, the output of which feeds the ADC core, where analog-to-digital conversion is performed against the ADC reference voltages REFT and REFB. Internal or external ADC reference voltage configurations are selected by connecting the MODE pin appropriately. When MODE = AGND, the user must provide external sources at pins REFB and REFT. When MODE = AVDD or MODE = AVDD/2, an internal ADC references generator (A2) is enabled which drives the REFT and REFB pins using the voltage at pin VREF as its input. The user can choose to drive VREF from the internal bandgap reference, or disable A1 and provide their own reference voltage at pin VREF. On the fourth rising CLK edge following the edge that sampled AIN+ and AIN−, the conversion result is output via data pins D0 to D9. The output buffers can be disabled by pulling pin OE high. The following sections explain further: D How signals flow from AIN+ and AIN− to the ADC core, and how the reference voltages at REFT and REFB set the ADC input range and hence the input range at AIN+ and AIN−. D How to set the ADC references REFT and REFB using external sources or the internal reference buffer (A2) to match the device input range to the input signal. D How to set the output of the internal bandgap reference (A1) if required. signal processing chain (sample and hold, ADC) Figure 20 shows the signal flow through the sample and hold unit to the ADC core. REFT VQ+ AIN+ X1 AIN− X−1 Sample and Hold ADC Core VQ− REFB Figure 20. Analog Input Signal Flow 14 www.ti.com Not Recommended For New Designs
 SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PRINCIPLES OF OPERATION sample-and-hold Differential input signal sources can be connected directly to the AIN+ and AIN− pins using either dc- or ac-coupling. For single-ended sources, the signal can be dc- or ac-coupled to one of AIN+ or AIN−, and a suitable reference voltage (usually the midscale voltage, see operating configuration examples) must be applied to the other pin. Note that connecting the signal to AIN− results in it being inverted during sampling. The sample and hold differential output voltage VQ = (VQ+) − (VQ−) is given by: VQ = (AIN+) − (AIN−) (1) analog-to-digital converter VQ is digitized by the ADC, using the voltages at pins REFT and REFB to set the ADC zero-scale (code 0) and full-scale (code 1023) input voltages. VQ(ZS) + * (REFT * REFB) (2) VQ(FS) + (REFT * REFB) (3) Any inputs at AIN+ and AIN− that give VQ voltages less than VQ(ZS) or greater than VQ(FS) lie outside the ADC’s conversion range and attempts to convert such voltages are signalled by driving pin OVR high when the conversion result is output. VQ voltages less than VQ(ZS) digitize to give ADC output code 0 and VQ voltages greater than VQ(FS) give ADC output code 1023. complete system and system input range Combining the above equations to find the input voltages [(AIN+) − (AIN−)] that correspond to the limits of the ADC’s valid input range gives: (REFB * REFT) v [(AIN)) * (AIN*)] v (REFT * REFB) (4) For both single-ended and differential inputs, the ADC can thus handle signals with a peak-to-peak input range [(AIN+) − (AIN−)] of: [(AIN+) − (AIN−)] pk-pk input range = 2 x (REFT − REFB) (5) The REFT and REFB voltage difference and the gain sets the device input range. The next sections describe in detail the various methods available for setting voltages REFT and REFB to obtain the desired input span and device performance. www.ti.com 15 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PRINCIPLES OF OPERATION ADC reference generation The THS1040 ADC references REFT and REFB can be driven from external (off-chip) sources or from the internal (on-chip) reference buffer A2. The voltage at the MODE pin determines the ADC references source. Connecting MODE to AGND enables external ADC references mode. In this mode the internal buffer A2 is powered down and the user must provide the REFT and REFB voltages by connecting external sources directly to these pins. This mode is useful where several THS1040 devices must share common references for best matching of their ADC input ranges, or when the application requires better accuracy and temperature stability than the on-chip reference source can provide. Connecting MODE to AVDD or AVDD/2 enables internal ADC references mode. In this mode the buffer A2 is powered up and drives the REFT and REFB pins. External reference sources should not be connected in this mode. Using internal ADC references mode when possible helps to reduce the component count and hence the system cost. When MODE is connected to AVDD, a buffered AVDD/2 voltage is available at the BIASREF pin. This voltage can be used as a dc bias level for any ac-coupling networks connecting the input signal sources to the AIN+ and AIN− pins. MODE PIN REFERENCE SELECTION BIASREF PIN FUNCTION AGND External High impedance AVDD/2 AVDD Internal High impedance Internal AVDD/2 for AIN± bias external reference mode (MODE = AGND) AIN+ X1 AIN− X−1 VREF Sample and Hold ADC Core Internal Reference Buffer REFT REFB Figure 21. ADC Reference Generation, MODE = AGND Connecting pin MODE to AGND powers down the internal references buffer A2 and disconnects its outputs from the REFT and REFB pins. The user must connect REFT and REFB to external sources to provide the ADC reference voltages required to match the THS1040 input range to their application requirements. The common-mode reference voltage must be AVDD/2 for correct THS1040 operation: (6) AV (REFT ) REFB) DD + 2 2 16 www.ti.com 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PRINCIPLES OF OPERATION internal reference mode (MODE = AVDD or AVDD/2) AVDD + VREF 2 AIN+ X1 AIN− X−1 Sample and Hold Internal Reference Buffer VREF AGND ADC Core AVDD − VREF 2 Figure 22. ADC Reference Generation, MODE = AVDD/2 Connecting MODE to AVDD or AVDD/2 enables the internal ADC references buffer A2. The outputs of A2 are connected to the REFT and REFB pins and its inputs are connected to pins VREF and AGND. The resulting voltages at REFT and REFB are: REFT + REFB + ǒAVDD ) VREFǓ (7) 2 ǒAVDD * VREFǓ (8) 2 Depending on the connection of the REFSENSE pin, the voltage on VREF may be driven by an off-chip source or by the internal bandgap reference A1 (see onboard reference generator) to match the THS1040 input range to their application requirements. When MODE = AVDD the BIASREF pin provides a buffered, stabilized AVDD/2 output voltage that can be used as a bias reference for ac coupling networks connecting the signal sources to the AIN+ or AIN− inputs. This removes the need for the user to provide a stabilized external bias reference. www.ti.com 17 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PRINCIPLES OF OPERATION internal reference mode (MODE = AVDD or AVDD/2) (continued) AVDD or +FS AIN+ AIN+ AVDD 2 MODE −FS +FS AIN− AIN− −FS REFSENSE 0.1 µF 0.1 µF REFT 10 µF 0.1 µF 1 V (Output) VREF VMID if MODE = AVDD BIASREF High-Impedance if MODE = REFB Figure 23. Internal Reference Mode, 1-V Reference Span AVDD 2 +FS VM −FS AIN+ + _ 0.1 µF 0.1 µF 10 µF MODE AIN− DC SOURCE = VM VM or AVDD REFT VREF REFB REFSENSE 0.5 V (Output) 0.1 µF Figure 24. Internal Reference Mode, 0.5-V Reference Span, Single-Ended Input 18 www.ti.com AVDD 2 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PRINCIPLES OF OPERATION onboard reference generator configuration The internal bandgap reference A1 can provide a supply-voltage-independent and temperature-independent voltage on pin VREF. External connections to REFSENSE control A1’s output to the VREF pin as shown in Table 1. Table 1. Effect of REFSENSE Connection on VREF Value REFSENSE CONNECTION A1 OUTPUT TO VREF SEE: VREF pin 0.5 V Figure 25 AGND 1V Figure 26 External divider junction (1 + Ra/Rb)/2 V Figure 27 AVDD Open circuit Figure 28 REFSENSE = AVDD powers the internal bandgap reference A1 down, saving power when A1 is not required. If MODE is connected to AVDD or AVDD/2, then the voltage at VREF determines the ADC reference voltages: REFT + AV (9) DD ) VREF 2 2 AV (10) REFT–REFB + VREF (11) REFB + DD * VREF 2 2 ADC References Buffer A2 VBG + _ + _ MODE = AVDD or AVDD 2 VREF = 0.5 V 0.1 µF 1 µF REFSENSE AGND Figure 25. 0.5-V VREF Using the Internal Bandgap Reference A1 www.ti.com 19 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PRINCIPLES OF OPERATION onboard reference generator configuration (continued) ADC References Buffer A2 VBG + _ MODE = AVDD or AV DD 2 + _ VREF = 1 V 0.1 µF 10 kΩ 1 µF REFSENSE 10 kΩ AGND Figure 26. 1-V VREF Using the Internal Bandgap Reference A1 ADC References Buffer A2 VBG + _ + _ MODE = AVDD or AVDD 2 VREF = (1 + Ra/Rb)/2 Ra REFSENSE Rb AGND Figure 27. External Divider Mode 20 www.ti.com 0.1 µF 1 µF 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PRINCIPLES OF OPERATION onboard reference generator configuration (continued) ADC References Buffer A2 VBG + _ MODE = AVDD or AVDD 2 + _ VREF = External REFSENSE AVDD AGND Figure 28. Drive VREF Mode operating configuration examples Figure 29 shows a configuration using the internal ADC references for digitizing a single-ended signal with span 0 V to 2 V. Tying REFSENSE to ground gives 1 V at pin VREF. Tying MODE to AVDD/2 then sets the REFT and REFB voltages via the internal reference generator for a 2-Vp-p ADC input range. The VREF pin provides the 1-V mid-scale bias voltage required at AIN−. VREF should be well decoupled to AGND to prevent sample-and-hold switching at AIN− from corrupting the VREF voltage. 2V 20 Ω 1V 0V AVDD/2 AIN+ MODE 20 pF 20 Ω AIN− 20 pF 10 µF VREF = 1 V 0.1 µF REFT 10 µF 0.1 µF 0.1 µF REFSENSE REFB Figure 29. Operating Configuration: 2-V Single-Ended Input, Internal ADC References www.ti.com 21 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PRINCIPLES OF OPERATION operating configuration examples (continued) Figure 30 shows a configuration using the internal ADC references for digitizing a dc-coupled differential input with 1.5-Vp-p span and 1.5-V common-mode voltage. External resistors are used to set the internal bandgap reference output at VREF to 0.75 V. Tying MODE to AVDD then sets the REFT and REFB voltages via the internal reference generator for a 1.5-Vp-p ADC input range. If a transformer is used to generate the differential ADC input from a single-ended signal, then the BIASREF pin provides a suitable bias voltage for the secondary windings center tap when MODE = AVDD. 1.875 V AVDD 20 Ω AIN+ 1.5 V 1.125 V 20 pF 20 Ω 1.875 V 1.5 V 1.125 V MODE AIN− 20 pF VREF = 0.75 V 5 kΩ 0.1 µF REFSENSE REFT 10 µF 10 µF 10 kΩ 0.1 µF REFB 0.1 µF Figure 30. Operating Configuration: 1.5-V Differential Input, Internal ADC References Figure 31 shows a configuration using the internal ADC references and an external VREF source for digitizing a dc-coupled single-ended input with span 0.5 V to 2 V. A 1.25-V external source provides the bias voltage for the AIN− pin and also, via a buffered potential divider, the 0.75 VREF voltage required to set the input range to 1.5 Vp-p MODE is tied to AVDD to set internal ADC references configuration. AVDD 2V 20 Ω 1.25 V 0.5 V 20 Ω 1.25 Source 10 µF AIN+ MODE AIN− REFT 20 pF 0.1 µF 20 pF 10 kΩ _ (0.75 V) + 0.1 µF VREF 10 µF REFB 0.1 µF 15 kΩ REFSENSE AVDD Figure 31. Operating Configuration: 1.5-V Single-Ended Input, External VREF Source 22 www.ti.com Not Recommended For New Designs
 SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 PRINCIPLES OF OPERATION power management In power-sensitive applications (such as battery-powered systems) where the THS1040 is not required to convert continuously, power can be saved between conversion intervals by placing the THS1040 into power-down mode. This is achieved by pulling the STBY pin high. In power-down mode, the device typically consumes less than 0.1 mW of power. If the internal VREF generator (A1) is not required, it can be powered down by tying pin REFSENSE to AVDD, saving approximately 1.2 mA of supply current. If the BIASREF function is not required when using internal references then tying MODE to AVDD/2 powers the BIASREF buffer down, saving approximately 1.2 mA. digital I/O While the OE pin is held low, ADC conversion results are output at pins D0 (LSB) to D9 (MSB). The ADC input over-range indicator is output at pin OVR. OVR is also disabled when OE is held high. The only ADC output data format supported is unsigned binary (output codes 0 to 1023). Twos complement output (output codes −512 to 511) can be obtained by using an external inverter to invert the D9 output. www.ti.com 23 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 APPLICATION INFORMATION driving the THS1040 analog inputs driving the clock input Obtaining good performance from the THS1040 requires care when driving the clock input. Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as possible in which to operate. The CLK pin should also be driven from a low jitter source for best dynamic performance. To maintain low jitter at the CLK input, any clock buffers external to the THS1040 should have fast rising edges. Use a fast logic family such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter. As the CLK input threshold is nominally around AVDD/2, any clock buffers need to have an appropriate supply voltage to drive above and below this level. driving the sample and hold inputs driving the AIN+ and AIN− pins Figure 32 shows an equivalent circuit for the THS1040 AIN+ and AIN− pins. The load presented to the system at the AIN pins comprises the switched input sampling capacitor, CSample, and various stray capacitances, C1 and C2. AVDD CLK 1.2 pF AIN CSample C2 1.2 pF C1 8 pF AGND CLK + _ VCM = AIN+/AIN− Common Mode Voltage Figure 32. Equivalent Circuit for Analog Input Pins AIN+ and AIN− The input current pulses required to charge CSample and C2 can be time averaged and the switched capacitor circuit modelled as an equivalent resistor: R IN2 + (12) 1 C S f CLK where CS is the sum of CSample and C2. This model can be used to approximate the input loading versus source resistance for high impedance sources. 24 www.ti.com Not Recommended For New Designs
 SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 APPLICATION INFORMATION AVDD R2 = 1/CS fCLK AIN IIN C1 8 pF + _ AGND VCM = AIN+/AIN− Common Mode Voltage Figure 33. Equivalent Circuit for the AIN Switched Capacitor Input AIN input damping The charging current pulses into AIN+ and AIN− can make the signal sources jump or ring, especially if the sources are slightly inductive at high frequencies. Inserting a small series resistor of 20 Ω or less and a small capacitor to ground of 20 pF or less in the input path can damp source ringing (see Figure 34). The resistor and capacitor values can be made larger than 20 Ω and 20 pF if reduced input bandwidth and a slight gain error (due to potential division between the external resistors and the AIN equivalent resistors) are acceptable. Note that the capacitors should be soldered to a clean analog ground with a common ground point to prevent any voltage drops in the ground plane appearing as a differential voltage at the ADC inputs. R < 20 Ω AIN VS C < 20 pF Figure 34. Damping Source Ringing Using a Small Resistor and Capacitor driving the VREF pin Figure 35 shows the equivalent load on the VREF pin when driving the ADC internal references buffer via this pin (MODE = AVDD/2 or AVDD and REFSENSE = AVDD). AVDD RIN VREF 10 kΩ MODE = AVDD REFSENSE = AVDD, MODE = AVDD/2 or AVDD AGND + _ (AVDD + VREF) /4 Figure 35. Equivalent Circuit of VREF The nominal input current IREF is given by: I REF + 3V * AV REF DD 4 R IN (13) www.ti.com 25 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 APPLICATION INFORMATION driving the VREF pin (continued) Note that the maximum current may be up to 30% higher. The user should ensure that VREF is driven from a low noise, low drift source, well decoupled to analog ground and capable of driving the maximum IREF. driving REFT and REFB (external ADC references, MODE = AGND) AVDD To ADC Core REFT AGND AVDD 2 kΩ To ADC Core REFB AGND Figure 36. Equivalent Circuit of REFT and REFB Inputs reference decoupling VREF pin When the on-chip reference generator is enabled, the VREF pin should be decoupled to the circuit board’s analog ground plane close to the THS1040 AGND pin via a 1-µF capacitor and a 0.1-µF ceramic capacitor. REFT and REFB pins In any mode of operation, the REFT and REFB pins should be decoupled as shown in Figure 37. Use short board traces between the THS1040 and the capacitors to minimize parasitic inductance. 0.1 µF REFT 10 µF 0.1 µF THS1040 REFB 0.1 µF Figure 37. Recommended Decoupling for the ADC Reference Pins REFT and REFB BIASREF pin When using the on-chip BIASREF source, the BIASREF pin should be decoupled to the circuit board’s analog ground plane close to the THS1040 AGND pin via a 1-µF capacitor and a 0.1-µF ceramic capacitor. 26 www.ti.com Not Recommended For New Designs
 SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 APPLICATION INFORMATION supply decoupling The analog (AVDD, AGND) and digital (DVDD, DGND) power supplies to the THS1040 must be separately decoupled for best performance. Each supply needs at least a 10-µF electrolytic or tantalum capacitor (as a charge reservoir) and a 100-nF ceramic type capacitor placed as close as possible to the respective pins (to suppress spikes and supply noise). digital output loading and circuit board layout The THS1040 outputs are capable of driving rail-to-rail with up to 10 pF of load per pin at 40-MHz clock frequency and 3-V digital supply. Minimizing the load on the outputs improves THS1040 signal-to-noise performance by reducing the switching noise coupling from the THS1040 output buffers to the internal analog circuits. The output load capacitance can be minimized by buffering the THS1040 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks between the THS1040 and this buffer. Inserting small resistors in the range 100 Ω to 300 Ω between the THS1040 I/O outputs and their loads can help minimize the output-related noise in noise-critical applications. Noise levels at the output buffers, which may affect the analog circuits within THS1040, increase with the digital supply voltage. Where possible, consider using the lowest DVDD that the application can tolerate. Use good layout practices when designing the application PCB to ensure that any off-chip return currents from the THS1040 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any sensitive analog circuits. The THS1040 should be soldered directly to the PCB for best performance. Socketing the device degrades performance by adding parasitic socket inductance and capacitance to all pins. user tips for obtaining best performance from the THS1040 D D D D Choose differential input mode for best distortion performance. Choose a 2-V ADC input span for best noise performance. Choose a 1-V ADC input span for best distortion performance. Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB traces. D Use a small RC filter (typically 20 Ω and 20 pF) between the signal source(s) the AIN+ (and AIN−) input(s) when the systems bandwidth requirements allow this. www.ti.com 27 
 Not Recommended For New Designs SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 APPLICATION INFORMATION definitions D Integral nonlinearity (INL)—Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two endpoints. D Differential nonlinearity (DNL)—An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last transition level – first transition level) ÷ (2n – 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than –1 LSB ensures no missing codes. D Zero-error—Zero-error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that switches the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024). D Full-scale error—Full-scale error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that switches the ADC output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024). D Wake-up time—Wake-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AGND with external reference sources applied to the device at the time of release of power-down, and an applied 40-MHz clock. Circuits that need to power up are the bandgap, bias generator, ADC, and SHA. D Power-up time—Power-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AVDD/2 or AVDD and an applied 40-MHz clock. Circuits that need to power up include VREF reference generation (A1), bias generator, ADC, the SHA, and the on-chip ADC reference generator (A2). D Aperture delay—The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. D Aperture uncertainty (Jitter)—The sample-to-sample variation in aperture delay. 28 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 5-Jul-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) THS1040CDW OBSOLETE SOIC DW 28 TBD Call TI Call TI 0 to 70 THS1040CDWG4 OBSOLETE SOIC DW 28 TBD Call TI Call TI 0 to 70 THS1040CPW OBSOLETE TSSOP PW 28 TBD Call TI Call TI 0 to 70 TH1040 THS1040IDW OBSOLETE SOIC DW 28 TBD Call TI Call TI -40 to 85 TJ1040 THS1040IPW OBSOLETE TSSOP PW 28 TBD Call TI Call TI -40 to 85 TJ1040 THS1040IPWR OBSOLETE TSSOP PW 28 TBD Call TI Call TI -40 to 85 TJ1040 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 5-Jul-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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