THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
DA PACKAGE
(TOP VIEW)
features
D
D
D
D
D
D
D
D
D
D
D
Simultaneous Sampling of 2 Single-Ended
Signals or 1 Differential Signal
Integrated 16 Word FIFO
Signal-to-Noise and Distortion Ratio: 66 dB
at fI = 2 MHz
Differential Nonlinearity Error: ±1 LSB
Integral Nonlinearity Error: ±1.5 LSB
Auto-Scan Mode for 2 Inputs
3-V or 5-V Digital Interface Compatible
Low Power: 216 mW Max
5-V Analog Single Supply Operation
Internal Voltage References . . . 50 PPM/°C
and ±5% Accuracy
Parallel µC/DSP Interface
applications
D
D
D
D
D
D0
D1
D2
D3
D4
D5
1
32
2
31
3
30
4
29
5
28
6
27
BVDD
BGND
D6
D7
D8
D9
RA0/D10
RA1/D11
CONV_CLK (CONVST)
DATA_AV
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
OV_FL
RESET
AINP
AINM
REFIN
REFOUT
REFP
REFM
AGND
AVDD
CS0
CS1
WR (R/W)
RD
DVDD
DGND
Radar Applications
Communications
Control Applications
High-Speed DSP Front-End
Automotive Applications
description
The THS12082 is a CMOS, low-power, 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed,
resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed
acquisition, and communications. A multistage pipelined architecture with output error correction logic provides
for no missing codes over the full operating temperature range. Internal control registers allow for programming
the ADC into the desired mode. The THS12082 consists of two analog inputs, which are sampled
simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs.
An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor
connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.
An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the
application. Two different conversion modes can be selected. In the single conversion mode, a single and
simultaneous conversion can be initiated by using the single conversion start signal (CONVST). The conversion
clock in the single conversion mode is generated internally using a clock oscillator circuit. In the continuous
conversion mode, an external clock signal is applied to the CONV_CLK input of the THS12082. The internal
clock oscillator is switched off in the continuous conversion mode.
The THS12082C is characterized for operation from 0°C to 70°C, and the THS12082I is characterized for
operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
AVAILABLE OPTIONS
PACKAGED DEVICE
TA
TSSOP
(DA)
0°C to 70°C
THS12082CDA
–40°C to 85°C
THS12082IDA
functional block diagram
AVDD
DVDD
3.5 V
REFP
1.5 V
2.5 V
1.225 V
REF
REFOUT
REFM
DATA_AV
REFP
REFIN
S/H
AINP
AINM
Single-Ended
and/or
Differential
MUX
+
–
REFM
OV_FL
BVDD
12-Bit
Pipeline
ADC
12
FIFO
16 × 12
12
S/H
Buffers
CONV_CLK (CONVST)
CS0
CS1
RD
Logic
and
Control
Control
Register
BGND
WR (R/W)
RESET
AGND
2
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D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10/RA0
D11/RA1
• DALLAS, TEXAS 75265
DGND
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AINP
30
I
Analog input, single-ended or positive input of differential channel A
AINM
29
I
Analog input, single-ended or negative input of differential channel A
AVDD
AGND
23
I
Analog supply voltage
24
I
Analog ground
BVDD
BGND
7
I
Digital supply voltage for buffer
8
I
Digital ground for buffer
CONV_CLK
(CONVST)
15
I
Digital input. This input is used to apply an external conversion clock in the continuous conversion mode.
In the single conversion mode, this input functions as the conversion start (CONVST) input. A high to low
transition on this input holds simultaneously the selected analog input channels and initiates a single
conversion of all selected analog inputs.
CS0
22
I
Chip select input (active low)
CS1
21
I
Chip select input (active high)
DATA_AV
16
O
Data available signal, which can be used to generate an interrupt for processors and as a level
information of the internal FIFO. This signal can be configured to be active low or high and can be
configured as a static level or pulse output. See Table 14.
DGND
17
I
Digital ground. Ground reference for digital circuitry.
DVDD
18
I
Digital supply voltage
D0 – D9
1–6, 9–12
I/O/Z
Digital input, output; D0 = LSB
RA0/D10
13
I/O/Z
Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This
is required for writing to control register 0 and control register 1. See Table 8.
RA1/D11
14
I/O/Z
Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control
register. This is required for writing to control register 0 and control register 1. See Table 8.
OV_FL
32
O
Overflow output. Indicates whether an overflow in the FIFO occurred. OV_FL is set to active high level if
an overflow occurs. It is set back to low level with a reset of the THS12082 or a reset of the FIFO.
REFIN
28
I
Common-mode reference input for the analog input channels. It is recommended that this pin be
connected to the reference output REFOUT.
REFP
26
I
Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference
voltage. An external reference voltage at this input can be applied. This option can be programmed
through control register 0. See Table 9.
REFM
25
I
Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference
voltage. An external reference voltage at this input can be applied. This option can be programmed
through control register 0. See Table 9.
RESET
31
I
Hardware reset of the THS12082. Sets the control register to default values.
REFOUT
27
O
Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference
output requires a capacitor of 10 µF to AGND for filtering and stability.
RD†
19
I
The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input,
active low as a data read select from the processor. See timing section.
WR (R/W)†
20
I
This input is programmable. It functions as a read-write input (R/W) and can also be configured as a
write-only input (WR), which is active low and used as data write select from the processor. In this case,
the RD input is used as a read input from the processor. See timing section.
† The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range: DGND to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
BGND to BVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
AGND to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to AVDD + 1.5 V
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 + AGND to AVDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to BVDD/DVDD + 0.3 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
Operating free-air temperature range: THS12082C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
THS12082I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supply
Supply voltage
MIN
NOM
MAX
AVDD
DVDD
4.75
5
5.25
3
3.3
5.25
BVDD
3
3.3
5.25
UNIT
V
analog and reference inputs
MIN
Analog input voltage in single-ended configuration
NOM
MAX
V
2.5
VREFP
4
3.5
AVDD–1.2
V
VREFM
1
Common-mode input voltage VCM in differential configuration
External reference voltage,VREFP (optional)
External reference voltage, VREFM (optional)
1.4
Input voltage difference, REFP – REFM
UNIT
V
1.5
V
2
V
digital inputs
MIN
NOM
MAX
UNIT
High level input voltage
High-level
voltage, VIH
BVDD = 3 V
BVDD = 5.25 V
Low level input voltage
Low-level
voltage, VIL
BVDD = 3 V
BVDD = 5.25 V
Input CONV_CLK frequency
DVDD = 3 V to 5.25 V
0.1
CONV_CLK pulse duration, clock high, tw(CONV_CLKH)
DVDD = 3 V to 5.25 V
62
83
5000
ns
CONV_CLK pulse duration, clock low, tw(CONV_CLKL)
DVDD = 3 V to 5.25 V
62
83
5000
ns
THS12082CDA
Operating free-air
free air temperature,
temperature TA
4
THS12082IDA
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2
V
2.6
V
0.6
0.6
8
0
70
–40
85
V
V
MHz
°C
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
electrical characteristics over recommended operating conditions, VREFP = 3.5 V, VREFM = 1.5 V
(unless otherwise noted)
digital specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital inputs
IIH
IIL
High-level input current
DVDD = digital inputs
–50
50
µA
Low-level input current
Digital input = 0 V
–50
50
µA
Ci
Input capacitance
5
pF
Digital outputs
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = –50 µA,
IOL = 50 µA,
BVDD = 3.3 V, 5 V
BVDD = 3.3 V, 5 V
IOZ
CO
High-impedance-state output current
CS1 = DGND,
CS0 = DVDD
CL
Load capacitance at databus D0–D11
BVDD–0.5
V
–10
Output capacitance
0.4
V
10
µA
5
pF
30
pF
electrical characteristics over recommended operating conditions, AVDD = 5 V,
DVDD = BVDD = 3.3-V, fs = 8 MSPS, VREF = internal (unless otherwise noted)
dc specifications
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP
MAX
12
UNIT
Bits
Accuracy
Integral nonlinearity, INL
Differential nonlinearity, DNL
After calibration in single-ended mode
Offset error
After calibration in differential mode
Gain error
±1.5
LSB
±1
LSB
20
LSB
–20
20
LSB
–20
20
LSB
±10
µA
V
Analog input
Input capacitance
15
Input leakage current
VAIN = VREFM to VREFP
pF
Internal voltage reference
Accuracy, VREFP
3.3
3.5
3.7
Accuracy, VREFM
1.4
1.5
1.6
Temperature coefficient
Reference noise
Accuracy, REFOUT
2.475
V
50
PPM/°C
100
µV
2.5
2.525
V
Power supply
IDDA
Analog supply current
AVDD =5 V,
BVDD = DVDD = 3.3 V
36
40
mA
IDDD
Digital supply current
AVDD = 5 V
BVDD = DVDD = 3.3 V
0.5
1
mA
IDDB
Buffer supply current
AVDD = 5 V,
BVDD = DVDD = 3.3 V
1.5
4
mA
IDD_AP
Analog supply current in power-down mode
AVDD = 5 V,
BVDD = DVDD = 3.3 V
8
mA
Power dissipation
AVDD = 5 V,
DVDD = BVDD = 3.3 V
186
216
mW
Power dissipation in power down
AVDD = 5 V,
DVDD = BVDD = 3.3 V
30
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mW
5
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
electrical characteristics over recommended operating conditions, VREF = internal, fs = 8 MSPS,
fI = 2 MHz at –1dBFS (unless otherwise noted)
ac specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF
PARAMETER
SINAD
SNR
TEST CONDITIONS
Differential mode
Signal to noise ratio + distortion
Signal-to-noise
Total harmonic distortion
ENOB
(SNR)
Effective number of bits
SFDR
Spurious free dynamic range
TYP
63
65
dB
64
dB
69
dB
Single-ended mode (see Note 1)
Differential mode
Signal to noise ratio
Signal-to-noise
THD
MIN
64
Single-ended mode (see Note 1)
MAX
68
UNIT
dB
Differential mode
–70
Single-ended mode
–68
dB
Differential mode
10.17
Single-ended mode (see Note 1)
Differential mode
67
–67
dB
10.5
Bits
10.34
Bits
71
dB
Single-ended mode
69
dB
Full-power bandwidth with a source impedance of 150 Ω
in differential configuration.
Full scale sinewave, –3 dB
96
MHz
Full-power bandwidth with a source impedance of 150 Ω
in single-ended configuration.
Full scale sinewave, –3 dB
54
MHz
Small-signal bandwidth with a source impedance of
150 Ω in differential configuration.
100 mVpp sinewave, –3 dB
96
MHz
Small-signal bandwidth with a source impedance of
150 Ω in single-ended configuration.
100 mVpp sinewave, –3 dB
54
MHz
Analog Input
NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the
sampling clock.
6
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
timing specifications (AVDD = BVDD = DVDD = 5 V, VREFP = 3.5 V, VREFM = 1.5 V, CL < 30 pF )†
PARAMETER
td(DATA_AV)
td(o)
td(pipe)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time
5
Delay time
5
ns
5
CONV
CLK
Latency
ns
† Refer to Figure 2
timing specification of the single conversion mode‡
PARAMETER
tc
Clock cycle of the internal clock oscillator
t1
duration CONVST
Pulse duration,
tdA
Aperture time
t2
TEST CONDITIONS
1 analog input
2 analog inputs
TYP
MAX
UNIT
117
125
133
ns
1.5×tc
2.5×tc
ns
1
Time between consecutive start of single
g
conversion
1 analog input
2 analog inputs
1 analog input, TL = 1
2 analog inputs, TL = 2
1 analog input, TL = 4
td(DATA_AV)
d(DATA AV)
MIN
Delayy time,, DATA_AV
_
becomes active for the
trigger level condition: TRIG0 = 1, TRIG1 = 1
2 analog inputs, TL = 4
1 analog input, TL = 8
2 analog inputs, TL = 8
1 analog input, TL = 14
2 analog inputs, TL = 12
ns
2×tc
3×tc
ns
6.5×tc+15
7.5×tc+15
ns
3×t2 +6.5×tc+15
t2 +7.5×tc+15
ns
7×t2 +6.5×tc+15
3×t2 +7.5×tc+15
ns
13×t2 +6.5×tc+15
5×t2 +7.5×tc+15
ns
‡ Refer to Figure 1
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
detailed description
reference voltage
The THS12082 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to
3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP
and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
analog inputs
The THS12082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
analog-to-digital converter
The THS12082 uses a 12-bit pipelined multistaged architecture with four 1-bit stages followed by four 2-bit
stages, which achieves a high sample rate with low power consumption. The THS12082 distributes the
conversion over several smaller ADC subblocks, refining the conversion with progressively higher accuracy as
the device passes the results from stage to stage. This distributed conversion requires a small fraction of the
number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the
stages permits the first stage to operate on a new input sample while the second through the eighth stages
operate on the seven preceding samples.
data_av
In continuous conversion mode, the first DATA_AV signal is delayed by (7+TL) cycles of CONV_CLK after a
FIFO reset command. This is due to the latency of the pipeline architecture of the THS12082.
conversion modes
The conversion can be performed in two different conversion modes. In the single conversion mode, the
conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In
the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new
conversion is started with every falling edge of the applied clock signal.
sampling rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels.
Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate
NUMBER OF CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel
1
8 MSPS
2 single-ended channels
2
4 MSPS
1 differential channel
1
8 MSPS
CHANNEL CONFIGURATION
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
fc
MSPS
+ #8channels
Table 2 shows the maximum conversion rate in the single conversion mode.
8
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
sampling rate (continued)
Table 2. Maximum Conversion Rate in Single Conversion Mode†
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel
1
4 MSPS
2 single-ended channels
2
2.67 MSPS
CHANNEL CONFIGURATION
1 differential channel
1
4 MSPS
† Maximum conversion rate with respect to the typical internal oscillator speed [i.e., 8 MHz × (tc/t2)].
In single conversion mode, a single conversion of the selected analog input channels is performed. The single
conversion mode is selected by setting bit 1 of control register 0 to 1.
A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and
hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence
for the selected channels is started.
The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal
DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted
sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode
can be selected according to Table 13.
Figure 1 shows the timing of the single conversion mode. In this mode, up to two analog input channels can be
selected to be sampled simultaneously (see Table 2).
t2
CONVST
t1
t1
td(A)
AIN
Sample N
tDATA_AV
DATA_AV,
Trigger Level = 1
Figure 1. Timing of Single Conversion Mode
The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog
input channels. The time tDATA_AV, until DATA_AV becomes active is given by: tDATA_AV = tpipe + n × tc. This
equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all
other trigger level conditions refer to the timing specifications of single conversion mode.
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
continuous conversion mode
The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode.
In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running
external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is
written into the FIFO.
Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The
maximum throughput rate is 8 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case
of a trigger level set to 1 or 4.
Sample N
Channel 1
Sample N+1
Channel 1
Sample N+2
Channel 1
Sample N+3
Channel 1
Sample N+4
Channel 1
Sample N+5
Channel 1
Sample N+6
Channel 1
Sample N+7
Channel 1
Sample N+8
Channel 1
AIN
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
50%
CONV_CLK
50%
td(O)
tc
Data Into
FIFO
Data N–5
Channel 1
Data N–4
Channel 1
Data N–3
Channel 1
Data N–2
Channel 1
Data N–1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
Data N+2
Channel 1
Data N+3
Channel 1
td(DATA_AV)
DATA_AV,
Trigger Level = 1
td(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 2. Timing of Continuous Conversion Mode (1-channel operation)
Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The
maximum throughput rate per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows
the order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger
level set to 2 or 4.
Sample N
Channel 1,2
Sample N+1
Channel 1,2
Sample N+2
Channel 1,2
Sample N+3
Channel 1,2
Sample N+4
Channel 1,2
AIN
td(A)
tw(CONV_CLKH)
CONV_CLK
50%
td(Pipe)
tw(CONV_CLKL)
50%
tc
Data Into
FIFO
Data N–3
Channel 2
td(O)
Data N–2
Channel 1
Data N–2
Channel 2
Data N–1
Channel 1
Data N–1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
Data N+1
Channel 2
td(DATA_AV)
DATA_AV,
Trigger Level = 2
td(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 3. Timing of Continuous Conversion Mode (2-channel operation)
10
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
digital output data format
The digital output data format of the THS12082 can be in either binary format or in twos complement format.
The following tables list the digital outputs for the analog input voltages.
Table 3. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
AIN = VREFP
FFFh
AIN = (VREFP + VREFM)/2
800h
AIN = VREFM
000h
Table 4. Twos Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
AIN = VREFP
7FFh
AIN = (VREFP + VREFM)/2
000h
AIN = VREFM
800h
Table 5. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
Vin = AINP – AINM
VREF = VREFP – VREFM
Vin = VREF
Vin = 0
FFFh
Vin = –VREF
000h
800h
Table 6. Twos Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
Vin = AINP – AINM
VREF = VREFP – VREFM
Vin = VREF
Vin = 0
7FFh
Vin = –VREF
800h
000h
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
FIFO description
In order to facilitate an efficient connection to today’s processors, the THS12082 is supplied with a FIFO. This
integrated FIFO enables a problem-free processing of data. The FIFO is provided as a flexible circular buffer.
The circular buffer integrated in the THS12082 can store up to 16 conversion values. Therefore, the number
of interrupts to be served by a processor can be reduced significantly.
16
1
15
2
Read Pointer
14
3
13
4
12
5
Trigger Pointer
6
11
7
10
9
8
Data in FIFO
Free
Write Pointer
Figure 4. Circular Buffer
The converted data of the THS12082 is automatically written into the FIFO. To control the writing and reading
process, a write pointer, a read pointer, and a trigger pointer are used. The read pointer always shows the
location which will be read next. The write pointer indicates the location which contains the last written sample.
With a selection of multiple analog input channels, the converted values are written in a predefined sequence
to the circular buffer (autoscan mode). In this way, the channel information for the reading processor is
continually maintained.
The FIFO can be programmed through the control register of the ADC. The user has the ability to select a
specific trigger level from Table 13 in order to choose the configuration which best fits the application. The FIFO
provides the signal DATA_AV, which signals the processor to read the amount of data equal to the trigger level
selected in Table 13. The signal DATA_AV becomes active when the trigger condition is satisfied. The trigger
condition is satisfied when as many values as selected for the trigger level where written into the FIFO.
The signal DATA_AV could be connected to an interrupt input of a processor. In every interrupt service routine
call, the processor must read the amount of data equal to the trigger level from the ADC. The first data represents
the first channel according to the autoscan mode, which is shown in Table 10. The channel information is
therefore always maintained.
12
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
reading data from the FIFO
The THS12082 informs the connected processor via the digital output DATA_AV (data available) that a block
of conversion values is ready to be read. The block size to be read is always equal to the setting of the trigger
level. The selectable trigger levels depend on the number of selected analog input channels. For example, when
choosing one analog input, a trigger level of 1, 4, 8, and 14 can be selected. The following figures demonstrate
the principle of reading the data.
In Figure 5, a trigger level of 1 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 5. Trigger Level 1 Selected
In Figure 6, a trigger level of 4 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 6. Trigger Level 4 Selected
In Figure 7, a trigger level of 8 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 7. Trigger Level 8 Selected
In Figure 8, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 8. Trigger Level 14 Selected
READ is always the logical combination of CS0, CS1 and RD.
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13
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
ADC control register
The THS12082 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the
desired mode. The bit definitions of both control registers are shown in Table 7.
Table 7. Bit Definitions of Control Register CR0 and CR1
REG
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CR0
TEST1
TEST0
SCAN
DIFF1
DIFF0
CHSEL1
CHSEL0
PD
MODE
VREF
CR1
RBACK
OFFSET
BIN/2’s
R/W
DATA_P
DATA_T
TRIG1
TRIG0
OVFL/FRST
RESET
writing to control register 0 and control register 1
The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control
register and writing the register value to the ADC. The addressing is performed with the upper data bits D10
and D11, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0
to D9 contain the desired control register value. Table 8 shows the addressing of each control register.
Table 8. Control Register Addressing
14
D0 – D9
D10/RA0
D11/RA1
Addressed Control Register
Desired register value
0
0
Control register 0
Desired register value
1
0
Control register 1
Desired register value
0
1
Reserved for future
Desired register value
1
1
Reserved for future
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
initialization of the THS12082
The initialization of the THS12082 should be done according to the configuration flow shown in Figure 9.
Start
Use Default
Values?
No
Yes
Write 0x401 to
THS12082
(Set Reset Bit in CR1)
Write 0x401 to
THS12082
(Set Reset Bit in
CR1)
Clear RESET By
Writing 0x400 to
CR1
Clear RESET By
Writing 0x400 to
CR1
Write the User
Configuration to
CR0
Write the User
Configuration to
CR1 (Can Include
FIFO Reset, Must
Exclude RESET)
Continue
Figure 9. THS12082 Configuration Flow
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15
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
ADC control registers
control register 0 (see Table 8)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
TEST1
TEST0
SCAN
DIFF1
DIFF0
CHSEL1
CHSEL0
PD
MODE
VREF
Table 9. Control Register 0 Bit Functions
BITS
RESET
VALUE
NAME
0
0
VREF
Vref select:
Bit 0 = 0 → The internal reference is selected.
Bit 0 = 1 → The external reference voltage is selected.
1
0
MODE
Continuous conversion mode/single conversion mode
Bit 1 = 0 → Continuous conversion mode is selected.
FUNCTION
An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the
CONV_CLK signal a new converted value is written into the FIFO.
Bit 1 = 1 → Single conversion mode is selected.
In this mode, the CONV_CLK input functions as a CONVST input. A single conversion is initiated on the
THS12082 by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of
the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the
selected channels is started. The signal DATA_AV (data available) becomes active when the trigger
condition is satisfied.
2
0
PD
Power down.
Bit 2 = 0 → The ADC is active.
Bit 2 = 1 → Power down
The reading and writing to and from the digital outputs is possible during power down. It is also possible to
read out the FIFO.
3, 4
0,0
CHSEL0,
CHSEL1
Channel select
Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10.
5,6
1,0
DIFF0, DIFF1
7
0
SCAN
Autoscan enable
Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 10.
8,9
0,0
TEST0,
TEST1
Test input enable
Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This
feedback allows the check of all hardware connections and the ADC operation.
Number of differential channels
Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 10.
Refer to Table 11 for selection of the three different test voltages.
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
analog input channel selection
The analog input channels of the THS12082 can be selected via bits 3 to 7 of control register 0. One single
channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the
selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more
than one input channel is selected. Table 10 shows the possible selections.
Table 10. Analog Input Channel Configurations
BIT 7
AS
BIT 6
DF1
BIT 5
DF0
BIT 4
CHS1
BIT 3
CHS0
0
0
0
0
0
Analog input AINP (single ended)
0
0
0
0
1
Analog input AINM (single ended)
0
0
0
1
0
Reserved
0
0
0
1
1
Reserved
0
0
1
0
0
Differential channel (AINP–AINM)
0
0
1
0
1
Reserved
1
0
0
0
1
Autoscan two single ended channels: AINP, AINM, AINP, …
1
0
0
1
0
Reserved
1
0
0
1
1
Reserved
1
1
0
0
1
Reserved
1
0
1
0
1
Reserved
1
0
1
1
0
Reserved
0
0
1
1
0
Reserved
0
0
1
1
1
Reserved
1
0
0
0
0
Reserved
1
0
1
0
0
Reserved
1
0
1
1
1
Reserved
1
1
0
0
0
Reserved
1
1
0
1
0
Reserved
1
1
0
1
1
Reserved
1
1
1
0
0
Reserved
1
1
1
0
1
Reserved
1
1
1
1
0
Reserved
1
1
1
1
1
Reserved
DESCRIPTION OF THE SELECTED INPUTS
test mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown
in Table 11.
Table 11. Test Mode
BIT 9
TEST1
BIT 8
TEST0
OUTPUT RESULT
0
0
Normal mode
0
1
1
0
1
1
VREFP
((VREFM)+(VREFP))/2
VREFM
Three different options can be selected. This feature allows support testing of hardware connections between
the ADC and the processor.
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
analog input channel selection (continued)
control register 1 (see Table 8)
BIT11
BIT10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
1
RBACK
OFFSET
BIN/2s
R/W
DATA_P
DATA_T
TRIG1
TRIG0
OVFL/FRST
RESET
Table 12. Control Register 1 Bit Functions
BITS
RESET
VALUE
NAME
0
0
RESET
FUNCTION
Reset
Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset
values. In addition the FIFO pointer and offset register is reset. After reset, it takes 5 clock cycles until the first
value is converted and written into the FIFO.
1
2, 3
4
0
0,0
1
OVFL
(read only)
Overflow flag (read only)
Bit 1 of control register 1 indicates an overflow in the FIFO.
Bit 1 = 0 → no overflow occurred.
Bit 1 = 1 → an overflow occurred. This bit is reset to 0, after this control register is read from the processor.
FRST
(write only)
FRST: FIFO reset (write only)
By writing a 1 into this bit, the FIFO is reset.
TRIG0,
TRIG1
FIFO trigger level
DATA_T
DATA_AV type
Bit 2 and bit 3 of control register 1 are used to set the trigger level for the FIFO. If the trigger level is reached,
the signal DATA_AV (data available) becomes active according to the settings of DATA_T and DATA_P. This
indicates to the processor that the ADC values can be read. Refer to Table 13.
Bit 4 of control register 1 controls whether the DATA_AV signal is a pulse or static (e.g for edge or level
sensitive interrupt inputs). If it is set to 0, the DATA_AV signal is static. If it is set to 1, the DATA_AV signal is a
pulse. Refer to Table 14.
5
1
DATA_P
DATA_AV polarity
Bit 5 of control register 1 controls the polarity of DATA_AV. If it is set to 1, DATA_AV is active high. If it is set to 0,
DATA_AV is active low. Refer to Table 14.
6
0
R/W
R/W, RD/WR selection
Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set
to 1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write
with R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input
WR becomes a write input.
7
0
BIN/2s
Complement select
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of
control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 3 through Table 6.
8
0
OFFSET
Offset cancellation mode
Bit 8 = 0 → normal conversion mode
Bit 8 = 1 → offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conversion. The conversion result is stored in an offset register and subtracted from all conversions in order
to reduce the offset error.
9
0
RBACK
Debug mode
Bit 9 = 0 → normal conversion mode
Bit 9 = 1 → enable debug mode
When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control
register 0 and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of
control register 0. The second read after bit 9 is set to 1 contains the value of control register 1.
18
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
FIFO trigger level
Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13).
If the trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of
the signal DATA_AV to indicate to the processor that the ADC values can be read.
Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which
can be selected, is dependent on the number of input channels. Either a differential or a single-ended input is
considered as one channel. The processor, therefore, always reads the data from the FIFO in the same order
and is able to distinguish between the channels.
Table 13. FIFO Trigger Level
BIT 3
TRIG1
BIT 2
TRIG0
TRIGGER LEVEL
FOR 1 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 2 CHANNELS
(ADC values)
0
0
01
02
0
1
04
04
1
0
08
8
1
1
14
12
timing and signal description of the THS12082
The reading from the THS12082 and writing to the THS12082 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input
(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal
(R/W). The two chip select inputs can be used to interface easily to a processor.
Reading from the THS12082 takes place by an internal RDint signal, which is generated from the logical
combination of the external signals CS0, CS1 and RD (see Figure 10). This signal is then used to strobe the
words out of the FIFO and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to
become valid will make RDint active while the write input (WR) is inactive. The first of those external signals going
to its inactive state will then deactivate RDint again.
Writing to the THS12082 takes place by an internal WRint signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control
registers 0 and 1. The last external signal (either CS0, CS1 or WR) to become valid will make WRint active while
the read input (RD) is inactive. The first of those external signals going to its inactive state will then deactivate
WRint again.
Read Enable
CS0
CS1
RD
Write Enable
WR
Control/Data
Registers
Data Bits
Figure 10. Logical Combination of CS0, CS1, RD, and WR
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THS12082
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DATA_AV type
Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of
control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register
determines the polarity of DATA_AV. This is shown in Table 14.
Table 14. DATA_AV Type
BIT 5
DATA_P
BIT 4
DATA_T
0
0
Active low level
0
1
Active low pulse
1
0
Active high level
1
1
Active high pulse
DATA_AV TYPE
The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive dependent of
the DATA_T selection (pulse or level).
If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling
edge of READ). The trigger condition is checked again after TL reads. For single conversion mode, DATA_AV
type should be programmed to active level mode (set bit 4 of CR1 to zero).
If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in
continuous conversion mode. When the TL values previously written into the FIFO were read out by the
processor, the next DATA_AV pulse (when the trigger condition is satisfied) is sent out first.
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timing and signal description of the THS12082
read timing (using R/W, CS0-controlled)
Figure 11 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W that becomes valid.
tw(CS)
90%
CS0
10%
10%
CS1
R/W
RD
ÎÎÎ
ÎÎÎ
ÎÎÎ
tsu(R/W)
th(R/W)
90%
ÏÏÏ
ÏÏÏ
ÏÏÏ
90%
ta
th
90%
90%
D(0–11)
td(CSDAV)
90%
DATA_AV
Figure 11. Read Timing Diagram Using R/W (CS0-controlled)
read timing parameter (CS0-controlled)†
PARAMETER
MIN
tsu(R/W)
ta
Setup time, R/W high to last CS valid
0
Access time, last CS valid to data valid
0
td(CSDAV)
th
Delay time, last CS valid to DATA_AV inactive
th(R/W)
tw(CS)
† CS = CSO
MAX
0
Hold time, first external CS invalid to R/W change
Pulse duration, CS active
• DALLAS, TEXAS 75265
UNIT
ns
10
12
Hold time, first CS invalid to data invalid
POST OFFICE BOX 655303
TYP
ns
ns
5
ns
5
ns
10
ns
21
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
timing and signal description of the THS12082 (continued)
write timing (using R/W, CS0-controlled)
Figure 12 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W that becomes valid.
tw(CS)
90%
CS0
10%
10%
CS1
WR
ÎÎÎ
ÎÎÎ
tsu(R/W)
ÎÎÎ
ÎÎÎ
th(R/W)
RD
tsu
th
DATA_AV
90%
90%
D(0–11)
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
Figure 12. Write Timing Diagram Using R/W (CS0-controlled)
write timing parameter (CSO-controlled)†
PARAMETER
MIN
TYP
MAX
UNIT
tsu(R/W)
tsu
Setup time, R/W stable to last CS valid
0
ns
Setup time, data valid to first CS invalid
5
ns
th
th(R/W)
Hold time, first CS invalid to data invalid
2
ns
5
ns
10
ns
tw(CS)
† CS = CSO
22
Hold time, first CS invalid to R/W change
Pulse duration, CS active
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THS12082
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timing and signal description of the THS12082 (continued)
interfacing the THS12082 to the TMS320C30/31/33 DSP
The following application circuit shows an interface of the THS12082 to the TMS320C30/31/33 DSPs. The read
and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
THS12082
TMS320C30/31/33
DVDD
STRB
A23
R/W
INTX
TOUT
DATA
CS0
CS1
RD
R/W
DATA_AV
CONV_CLK
DATA
interfacing the THS12082 to the TMS320C54x using I/O strobe
The following application circuit shows an interface of the THS12082 to the TMS320C54x. The read and write
timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
THS12082
TMS320C54x
DVDD
CS0
CS1
RD
R/W
DATA_AV
CONV_CLK
DATA
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I/O STRB
A15
R/W
INTX
BCLK
DATA
• DALLAS, TEXAS 75265
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
timing and signal description of the THS12082 (continued)
read timing (using RD, RD-controlled)
Figure 13 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The
input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last
external signal of CS0, CS1, and RD that becomes valid.
CS0
CS1
ÎÎÎÎÎ
ÎÎÎÎÎ
tsu(CS)
ÏÏÏÏ
ÏÏÏÏ
th(CS)
WR
tw(RD)
10%
RD
10%
ta
th
90%
90%
D(0–11)
td(CSDAV)
90%
DATA_AV
Figure 13. Read Timing Diagram Using RD (RD-controlled)
read timing parameter (RD-controlled)
PARAMETER
MIN
tsu(CS)
ta
Setup time, RD low to last CS valid
0
Access time, last CS valid to data valid
0
td(CSDAV)
th
Delay time, last CS valid to DATA_AV inactive
th(CS)
tw(RD)
Hold time, RD change to first CS invalid
24
MAX
0
Pulse duration, RD active
• DALLAS, TEXAS 75265
UNIT
ns
10
12
Hold time, first CS invalid to data invalid
POST OFFICE BOX 655303
TYP
ns
ns
5
ns
5
ns
10
ns
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
timing and signal description of the THS12082 (continued)
write timing (using WR, WR-controlled)
Figure 14 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only.
The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is
the last external signal of CS0, CS1, and WR that becomes valid.
CS0
CS1
tsu(CS)
th(CS)
tw(WR)
WR
RD
10%
10%
ÎÎÎÎ
ÎÎÎÎ
tsu
ÏÏÏÏ
ÏÏÏÏ
th
90%
90%
D(0–11)
DATA_AV
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
Figure 14. Write Timing Diagram Using WR (WR-controlled)
write timing parameter using WR (WR-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CS)
tsu
Setup time, CS stable to last WR valid
0
ns
Setup time, data valid to first WR invalid
5
ns
th
th(CS)
Hold time, WR invalid to data invalid
2
ns
Hold time, WR invalid to CS change
5
ns
tw(WR)
Pulse duration, WR active
10
ns
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25
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
interfacing the THS12082 to the TMS320C6201 DSP
The following application circuit shows an interface of the THS12082 to the TMS320C6201. The read (using
RD, RD-controlled) and write timings (using WR, WR-controlled) shown before are valid for this specific
interface.
THS12082–1
TMS320C6201
CS0
CS1
RD
WR
DATA_AV
DATA
CONV_CLK
CE1
EA20
ARE
AWE
EXT_INT6
DATA
TOUT1
TOUT2
EA21
EXT_INT7
THS12082–2
CS0
CS1
RD
WR
DATA_AV
DATA
CONV_CLK
analog input configuration and reference voltage
The THS12082 features two analog input channels. These can be configured for either single-ended or
differential operation. Best performance is achieved in differential mode. Figure 15 shows a simplified model,
where a single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are
VREFP and VREFM (either internal or external reference voltage). The analog input voltage range goes from
VREFM to VREFP. This means that VREFM defines the minimum voltage, which can be applied to the ADC. VREFP
defines the maximum voltage, which can be applied to the ADC. The internal reference source provides the
voltage VREFM of 1.5 V and the voltage VREFP of 3.5 V. The resulting analog input voltage swing of 2 V can be
expressed by:
V
REFM
v AINP v VREFP
(1)
VREFP
AINP
12-Bit
ADC
VREFM
Figure 15. Single-Ended Input Stage
26
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
analog input configuration and reference voltage (continued)
A differential operation is desired for many applications. Figure 16 shows a simplified model for the analog
inputs AINM and AINP, which are configured for differential operation. This configuration has a few advantages,
which are discussed in the following paragraphs.
VREFP
AINP
+
Σ
VADC
12-Bit
ADC
–
AINM
VREFM
Figure 16. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage, VADC, which is applied at the
input of the ADC, is the difference between the input AINP and AINM. This means that VREFM defines the
minimum voltage (VADC), which can be applied to the ADC. VREFP defines the maximum voltage (VADC), which
can be applied to the ADC. The voltage VADC can be calculated as follows:
V
ADC
+ ABS(AINP–AINM)
(2)
An advantage to single-ended operation is that the common-mode voltage
V
CM
+ AINM )2 AINP
(3)
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
v AINM, AINP v AVDD
1 VvV
v4 V
CM
AGND
(4)
(5)
In addition to the common-mode voltage rejection, the differential operation allows a dc-offset rejection, which
is common to both analog inputs. See also Figure 18.
single-ended mode of operation
The THS12082 can be configured for single-ended operation using dc or ac coupling. In either case, the input
of the THS12082 must be driven from an operational amplifier that does not degrade the ADC performance.
Because the THS12082 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar
signals to comply with its input requirements. This can be achieved with dc- and ac-coupling. An application
example is shown for dc-coupled level shifting in the following section, dc-coupling.
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27
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
dc coupling
An operational amplifier can be configured to shift the signal level according to the analog input voltage range
of the THS12082. The analog input voltage range of the THS12082 goes from 1.5 V to 3.5 V. An operational
amplifier specified for 5-V single supply can be used as shown in Figure 17.
Figure 17 shows an application example where the analog input signal in the range from –1 V up to 1 V is shifted
by an operational amplifier to the analog input range of the THS12082 (1.5 V to 3.5 V). The operational amplifier
is configured as an inverting amplifier with a gain of –1. The required dc voltage of 1.25 V at the noninverting
input is derived from the 2.5-V output reference REFOUT of the THS12082 by using a resistor divider.
Therefore, the op-amp output voltage is centered at 2.5 V. The use of ratio matched, thin-film resistor networks
minimizes gain and offset errors.
R
3.5 V
2.5 V
1.5 V
5V
1V
0V
R
_
THS12082
RS
AINP
–1 V
1.25 V
+
REFIN
REFOUT
R
R
Figure 17. Level-Shift for DC-Coupled Input
differential mode of operation
For the differential mode of operation, a conversion from single-ended to differential is required. A conversion
to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best
performance is achieved in differential mode.
Mini Circuits
T4–1
49.9 Ω
THS12082
R
AINP
200 Ω
C
R
AINM
C
REFOUT
Figure 18. Transformer Coupled Input
28
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
70
SINAD – Signal-to-Noise and Distortion – dB
THD – Total Harmonic Distortion – dB
80
75
70
65
60
55
50
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –1 dBFS
45
40
65
60
55
50
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –1 dBFS
45
40
0
1
2
3
4
5
6
7
8
9
0
1
fs – Sampling Frequency – MHz
2
Figure 19
4
5
6
7
8
9
Figure 20
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
70
90
85
65
80
SNR – Signal-to-Noise – dB
SFDR – Spurious Free Dynamic Range – dB
3
fs – Sampling Frequency – MHz
75
70
65
60
55
50
60
55
50
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –1 dBFS
45
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –1 dBFS
45
40
40
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
fs – Sampling Frequency – MHz
fs – Sampling Frequency – MHz
Figure 21
Figure 22
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29
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
85
SINAD – Signal-to-Noise and Distortion – dB
80
THD – Total Harmonic Distortion – dB
80
75
70
65
60
55
50
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –1 dBFS
45
40
75
70
65
60
55
50
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –1 dBFS
45
40
0
1
2
3
4
5
6
7
8
9
0
1
fs – Sampling Frequency – MHz
2
Figure 23
5
6
7
8
9
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
80
100
95
75
90
SNR – Signal-to-Noise – dB
SFDR – Spurious Free Dynamic Range – dB
4
Figure 24
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
85
80
75
70
65
60
55
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –1 dBFS
50
70
65
60
55
50
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –1 dBFS
45
45
40
40
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
Figure 25
Figure 26
POST OFFICE BOX 655303
6
7
fs – Sampling Frequency – MHz
fs – Sampling Frequency – MHz
30
3
fs – Sampling Frequency – MHz
• DALLAS, TEXAS 75265
8
9
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
80
SINAD – Signal-to-Noise and Distortion – dB
THD – Total Harmonic Distortion – dB
80
75
70
65
60
55
50
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
45
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
75
70
65
60
55
50
45
40
4.0
0
0.5
fi – Input Frequency – MHz
1.0
2.0
2.5
3.0
3.5
4.0
fi – Input Frequency – MHz
Figure 28
Figure 27
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (SINGLE-ENDED)
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (SINGLE-ENDED)
80
100
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
95
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
75
90
SNR – Signal-to-Noise – dB
SFDR – Spurious Free Dynamic Range – dB
1.5
85
80
75
70
65
60
55
50
70
65
60
55
50
45
45
40
40
0
0.5
1.0
1.5
2.0
2.5
3.0
fi – Input Frequency – MHz
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
fi – Input Frequency – MHz
Figure 29
Figure 30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
80.00
SINAD – Signal-to-Noise and Distortion – dB
THD – Total Harmonic Distortion – dB
80.00
75.00
70.00
65.00
60.00
55.00
50.00
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
45.00
40.00
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
75.00
70.00
65.00
60.00
55.00
50.00
45.00
40.00
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
2.0
2.5
3.0
3.5
4.0
Figure 32
Figure 31
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (DIFFERENTIAL)
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (DIFFERENTIAL)
100.00
80.00
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
95.00
90.00
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
75.00
SNR – Signal-to-Noise – dB
SFDR – Spurious Free Dynamic Range – dB
1.5
fi – Input Frequency – MHz
fi – Input Frequency – MHz
85.00
80.00
75.00
70.00
65.00
60.00
55.00
70.00
65.00
60.00
55.00
50.00
50.00
45.00
45.00
40.00
40.00
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
fi – Input Frequency – MHz
1.0
1.5
2.0
Figure 34
POST OFFICE BOX 655303
2.5
3.0
fi – Input Frequency – MHz
Figure 33
32
1.0
• DALLAS, TEXAS 75265
3.5
4.0
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
12
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –1 dBFS
ENOB – Effective Number of Bits – Bits
ENOB – Effective Number of Bits – Bits
12
11
10
9
8
7
11
10
9
8
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –1 dBFS
7
6
6
0
1
2
3
4
5
6
7
8
0
9
1
2
fs – Sampling Frequency – MHz
4
5
6
7
8
9
Figure 36
Figure 35
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (DIFFERENTIAL)
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (SINGLE-ENDED)
12
12
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
ENOB – Effective Number of Bits – Bits
ENOB – Effective Number of Bits – Bits
3
fs – Sampling Frequency – MHz
11
10
9
8
7
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
11
10
9
8
7
6
6
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
fi – Input Frequency – MHz
fi – Input Frequency – MHz
Figure 38
Figure 37
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33
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
DNL – Differential Nonlinearity – LSB
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
ADC CODE
1.00
AVDD = 5 V
DVDD = BVDD = 3 V
fs = 8 MSPS
0.80
0.60
0.40
0.20
–0.00
–0.20
–0.40
–0.60
–0.80
–1
0
500
1000
1500
2000
2500
3000
3500
4000
3000
3500
4000
ADC Code
Figure 39
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY
vs
ADC CODE
1.00
0.80
0.60
0.40
0.20
–0.00
–0.20
–0.40
AVDD = 5 V
DVDD = BVDD = 3 V
fs = 8 MSPS
–0.60
–0.80
–1
0
500
1000
1500
2000
2500
ADC Code
Figure 40
34
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM (4096 POINTS)
(SINGLE-ENDED)
vs
FREQUENCY
0
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
fin = 1.25 MHz
Magnitude – dB
–20
–40
–60
–80
–100
–120
–140
0
1000000
2000000
3000000
4000000
f – Frequency – Hz
Figure 41
FAST FOURIER TRANSFORM (4096 POINTS)
(DIFFERENTIAL)
vs
FREQUENCY
0
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
fin = 1.25 MHz
Magnitude – dB
–20
–40
–60
–80
–100
–120
–140
0
1000000
2000000
3000000
4000000
f – Frequency – Hz
Figure 42
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35
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
definitions of specifications and terminology
integral nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
differential nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
signal-to-noise ratio + distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N
+ (SINAD6.02* 1.76)
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal
and is expressed as a percentage or in decibels.
spurious free dynamic range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
36
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
MECHANICAL DATA
DA (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
38 PINS SHOWN
0,30
0,19
0,65
38
0,13 M
20
6,20
NOM
8,40
7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°– 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
32
38
A MAX
9,80
11,10
11,10
12,60
A MIN
9,60
10,90
10,90
12,40
DIM
4040066 / D 11/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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37
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THS12082CDA
ACTIVE
TSSOP
DA
32
46
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
THS12082
THS12082CDAR
ACTIVE
TSSOP
DA
32
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
THS12082
THS12082IDA
ACTIVE
TSSOP
DA
32
46
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS12082I
THS12082IDAR
ACTIVE
TSSOP
DA
32
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS12082I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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