THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL
CONVERTER WITH POWER DOWN
FEATURES
•
•
•
•
•
•
•
12-Bit Resolution, 30 MSPS
Analog-to-Digital Converter
Input Configurations:
– Differential (0.5x)
– Differential (1x)
3.3-V Supply Operation
Internal Voltage Reference
Out-of-Range Indicator
Power-Down Mode
IF Undersampling
APPLICATIONS
•
•
•
•
•
•
•
Set Top Box (STB)
Camcorders
Digital Cameras
Copiers
Communications
Test Instruments
IF and Baseband Digitization
DW OR PW PACKAGE
(TOP VIEW)
AGND
CON1
CON0
EXTREF
AIN+
AIN−
AGND
AVDD
REFT
REFB
OVRNG
D11
D10
D9
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
CLK
AVDD
OE
D0
D1
D2
D3
D4
DVDD
DGND
D5
D6
D7
D8
DESCRIPTION
The THS1230 is a CMOS, low-power, 12-bit, 30 MSPS analog-to-digital converter (ADC) that operates with a
3.3-V supply. The THS1230 gives circuit developers complete flexibility. The analog input to the THS1230 is
differential with a gain of 0.5 for Mode 2 and 1.0 for Mode 1. The THS1230 provides a wide selection of voltage
references to match the user's design requirements. For more design flexibility, the internal reference can be
bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the
application. The out-of-range output is used to monitor any out-of-range condition in the THS1230's input range.
The speed, resolution, and single-supply operation of the THS1230 are suited for applications in set top box
(STB), video, multimedia, high-speed acquisition, and communications. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as digital copiers, digital cameras, and camcorders. The wide
input voltage range between VREFB and VREFT allows the THS1230 to be designed into multiple systems.
The THS1230C is characterized for operation from 0°C to 70°C. The THS1230I is characterized for operation
from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2004, Texas Instruments Incorporated
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
(1)
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
THS1230
TSSOP-28
PW
0°C to 70°C
TH1230
THS1230CPW
Tube, 50
THS1230
TSSOP-28
PW
0°C to 70°C
TH1230
THS1230CPWR
Tape and reel, 2000
THS1230
TSSOP-28
PW
-40°C to 85°C
TJ1230
THS1230IPW
Tube, 50
THS1230
TSSOP-28
PW
-40°C to 85°C
TJ1230
THS1230IPWR
Tape and reel, 2000
THS1230
SOP-28
DW
0°C to 70°C
TH1230
THS1230CDW
Tube, 20
THS1230
SOP-28
DW
0°C to 70°C
TH1230
THS1230CDWR
Tape and reel, 1000
THS1230
SOP-28
DW
-40°C to 85°C
TJ1230
THS1230IDW
Tube, 20
THS1230
SOP-28
DW
-40°C to 85°C
TJ1230
THS1230IDWR
Tape and reel, 1000
(1)
For the most current specifictions and package information refer to our Web site at www.ti.com.
FUNCTIONAL BLOCK DIAGRAM
DVDD
CLK
Timing Circuitry
OVRNG
AIN+
AIN−
Sample
and Hold
3-State
Output
Buffers
12-Bit ADC
D[11:0]
OE
CON0
CON1
Configuration
Control
Circuit
Internal
Reference
Circuit
EXTREF REFT REFB
2
AVDD
AGND
DGND
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
1, 7
I
Analog ground
AVDD
8, 27
I
Analog supply
AIN+
5
I
Positive analog input
AIN-
6
I
Negative analog input
CLK
28
I
ADC conversion clock
CON1
2
I
Configuration input 1
CON0
3
I
Configuration input 0
DGND
19
I
Digital ground
DVDD
20
I
Digital supply
D11
12
O
ADC data bit 11
D10
13
O
ADC data bit 10
D9
14
O
ADC data bit 9
D8
15
O
ADC data bit 8
D7
16
O
ADC data bit 7
D6
17
O
ADC data bit 6
D5
18
O
ADC data bit 5
D4
21
O
ADC data bit 4
D3
22
O
ADC data bit 3
D2
23
O
ADC data bit 2
D1
24
O
ADC data bit 1
D0
25
O
ADC data bit 0
EXTREF
4
I
Reference select input (high = external, low = internal)
OVRNG
11
O
Out of range indicator (high = out of range)
OE
26
I
Output enable (high = disable, low = enable)
REFT
9
I/O
Upper ADC reference voltage
REFB
10
I/O
Lower ADC reference voltage
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
Supply voltage range
AVDD to AGND, DVDD to DGND
AGND to DGND
–0.3 V to 4 V
–0.3 V to 0.3 V
Reference voltage input range, REFT, REFB to AGND
–0.3 to AVDD + 0.3 V
Analog input voltage range, AIN+, AIN- to AGND
–0.3 to AVDD + 0.3 V
Clock input voltage range, CLK to AGND
–0.3 to AVDD + 0.3 V
Digital input voltage range, digital input to DGND
–0.3 to DVDD + 0.3 V
Digital output voltage range, digital output to DGND
–0.3 to DVDD + 0.3 V
Operating junction temperature range, TJ
–40°C to 150°C
Storage temperature range, TSTG
– 65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds
(1)
300°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range, TA (unless otherwise noted)
MIN
NOM
MAX
UNIT
3.0
3.3
3.6
V
2.5
V
POWER SUPPLY
Supply voltage
AVDD
DVDD
ANALOG AND REFERENCE INPUTS
Reference input voltage
VREFT
fCLK = 5 MHz to 30 MHz
2.0
2.15
VREFB
fCLK = 5 MHz to 30 MHz
1.05
1.15
1.3
Reference voltage differential, VREFT – VREFB
fCLK = 5 MHz to 30 MHz
0.95
1.0
1.05
V
Analog input voltage differential, (AIN+) – (AIN–) (1)
CON1 = 0, CON0 = 1
–1.0
1.0
V
CON1 = 1, CON0 = 0
–2.0
2.0
10
pF
0
AVDD
V
Analog input capacitance, Ci
Clock input
(2)
DIGITAL OUTPUTS
Minimum digital output load resistance, RL
100
Maximum digital output load capacitance, Ci
0
kΩ
10
15
pF
V
DIGITAL INPUTS
High-level input voltage, VIH
Low-level input voltage, VIL
Clock frequency, fCLK (3)
2.4
DVDD
DGND
0.8
V
5
30
MHz
Clock pulse duration, tw(CLKL), tw(CLKH)
fCLK = 30 MHz
18.3
ns
Operating free-air temperature, TA
TH1230
0
70
°C
TJ1230
–40
85
(1)
(2)
(3)
4
15
16.7
Based on VREFT – VREFB = 1.0 V, varies proportional to the VREFT – VREFB value. AIN+ and AIN– inputs must always be greater than 0 V
and less than AVDD.
Clock pin is referenced to AGND and powered by AVDD.
Clock frequency can be extended to this range without degradation of performance.
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (AVDD = DVDD = 3.3 V, fs = 30 MHz/50% duty cycle, MODE = 1, 1-V input span,
internal reference, Tmin to Tmax) (unless otherwise noted)
DIGITAL INPUTS AND OUTPUTS (ALL SUPPLIES = 3.3 V)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
All other inputs
0.8 × DVDD
CLK
0.8 × AVDD
VIH
High level input voltage
V
VIL
Low level input voltage
IIH
High level input current
1
µA
IIL
Low level input current
–1
µA
Ci
Input capacitance
All other inputs
0.2 × DVDD
CLK
0.2 × AVDD
5
V
pF
DIGITAL OUTPUTS
VOH
High level output voltage
Iload = 50 µA
VOL
Low level output voltage
Iload = –50 µA
DVDD–0.4
0.4
±1
High impedance output current
tr/tf
Rise/fall time
CL = 10 pF
V
µA
4.5
ns
ANALOG INPUTS
Ci
Switched input capacitance
6
pF
td(ap)
Aperture delay time
2
ns
Aperture uncertainty (jitter)
2
ps
10
µA
DC leakage current (input = ±FS)
POWER SUPPLY (CLK = 30 MHz)
XVDD
Supply voltage (all supplies)
3.3
3.6
IDD
Supply current active - total
48
66
I(analog)
Supply current active - analog
35
I(digital)
Supply current active - digital
II(standby)
Standby supply current
t(PU)
Power-up time for references from standby
t(PUconv)
Power-up time for valid ADC conversions
PD
Power dissipation
PD(STBY)
Standby power dissipation
PSRR
Power supply rejection ratio
(1)
(2)
(3)
(4)
3
V
mA
13
CLK = 0 MHz
1 µF Bypass
10
(1)
10 µF Bypass
(1)
µA
770
µs
6.2
ms
See Note
(2)
720
See Note
(3)
168
See Note
(4)
188
CLK = 0 MHz
ns
220
36
±0.1
mW
µW
%FS
Time for reference to recover to 1% of its final voltage level.
Time for ADC conversions to be accurate to within 0.1% of fullscale, INT ckts.
Clock = 30 MHz, AIN+ and AIN– at Common Mode or 1.65 V DC.
Clock = 30 MHz, fin = 3.58 MHz at –1 dBFS.
5
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
over recommended operating conditions (AVDD = DVDD = 3.3 V, fs = 30 MHz/50% duty cycle, MODE = 1, 1-V input span,
internal reference, Tmin to Tmax) (unless otherwise noted)
REFT, REFB REFERENCE VOLTAGES (all supplies = 3.3 V)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE (1)
VREFT
Upper reference voltage
2.15
VREFB
Lower reference voltage
VREF
Differential reference voltage, VREFT – VREFB
0.95
Differential reference voltage, VREFT – VREFB accuracy
–5%
5%
Externally applied VREFT reference voltage range
2
2.5
Externally applied VREFB reference voltage range
1.05
1.3
Externally applied (VREFT – VREFB) reference voltage range
0.75
1.05
1.15
1
V
1.05
EXTERNAL REFERENCE
External mode VREFT to VREFB impedance
9
V
kΩ
INTERNAL OR EXTERNAL REFERENCE
CT
VREFT decoupling capacitor value
0.1
CB
VREFB decoupling capacitor value
0.1
CTB
Decoupling capacitor VREFT to VREFB
10
(1)
The internal reference voltage is not intended for use driving off chip.
THS1230
REFT
CT
1.5 V
BAND
GAP
CTB
REFB
CB
Figure 1. Reference Generation
6
µF
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
over recommended operating conditions (AVDD = DVDD = 3.3 V, fs = 30 MHz/50% duty cycle, MODE = 1, 1-V input span,
internal reference, Tmin to Tmax) (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
0
codes
±0.4
±1
LSB
±1.2
2
DC ACCURACY (LINEARITY)
Number of missing codes
All modes
DNL
Differential nonlinearity
All modes
INL
Integral nonlinearity
All modes
Offset error
All modes
0.7
1.2
%FSR
Gain error
All modes
1.1
3.5
%FSR
–2.5
LSB
DYNAMIC PERFORMANCE (1)
fi = 3.58 MHz
ENOB
THD
Effective number of bits
Total harmonic distortion
fi = 10 MHz
10.9
10.4
fi = 15 MHz
10.4
fi = 3.58 MHz
–76
fi = 10 MHz
–74
fi = 15 MHz
–72.5
fi = 3.58 MHz
SNR
Signal-to-noise ratio
fi = 10 MHz
fi = 10 MHz
fi = 10 MHz
dB
65
dB
78.1
67
fi = 15 MHz
G(diff)
65.6
64.5
fi = 3.58 MHz
Spurious free dynamic range
dB
67.4
64
fi = 15 MHz
SFDR
–65
64.6
fi = 3.58 MHz
Signal-to-noise + distortion
Bits
68
64.5
fi = 15 MHz
SINAD
10.6
74
dB
72
Analog input bandwidth
180
MHz
Differential phase, DP
0.12
degree
Differential gain
0.01%
TIMING (all supplies = 3.3 V)
Clock frequency (2)
fCLK
Clock duty cycle
5
45%
30
50%
55%
7
19
td(O)
Output delay time
td(PZ)
Delay time, output disable to Hi-Z output
3.2
td(EN)
Delay time, output enable to output valid
5
Latency
(1)
(2)
MHz
ns
ns
19
ns
5
cycles
Input amplitudes for all single tone dynamic tests are at –1 dBFS, all supplies = 3.3 V.
The clock frequency may be extended to 5 MHz without degradation in specified performance.
7
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
TIMING DIAGRAM
S1
S2
S3
Analog
1
2
3
4
5
6
7
8
9
CLK
t PIPELINE
t d(O)
D[9:0]
S1
S2
S3
Figure 2. Analog Input and Data Output Timing
OE
t d(EN)
t d(PZ)
Hi−Z
D[9:0]
Hi−Z
Data
Data
Data
Figure 3. Output Enable Timing
8
10
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS
POWER
vs
TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs
TEMPERATURE
200
70
190.2
186.8
187.2
187.4
188
SNR − Signal-to-Noise Ratio − dB
Power − mW
190
189.2
fin = 3.58 MHz @ −1dBFS
180
AIN− = AIN+ = 1.65 V
170
AVDD = DVDD = 3.3 V,
fs = 30 MSPS
Mode 1
160
150
−40
−15
10
35
60
69
68
67
66
65
−40
85
AVDD = DVDD = 3.3 V
fs = 30 MSPS
fi = 3.58 MHz, −1dBFS
Mode 1
−15
TA − Temperature − °C
60
Figure 5.
SPURIOUS FREE DYNAMIC RANGE
vs
TEMPERATURE
TOTAL HARMONIC DISTORTION
vs
TEMPERATURE
85
−65
AVDD = DVDD = 3.3 V
fs = 30 MSPS
fi = 3.58 MHz, −1dBFS
Mode 1
−66
THD − Total Harmonic Distortion − dB
SFDR − Spurious Free Dynamic Range − dB
35
Figure 4.
80
79
10
TA − Temperature − °C
78
77
76
−67
AVDD = DVDD = 3.3 V
fs = 30 MSPS
fi = 3.58 MHz, −1dBFS
Mode 1
−68
−69
−70
−71
−72
−73
−74
75
−40
−15
10
35
TA − Temperature − °C
Figure 6.
60
85
−75
−40
−15
10
35
60
85
TA − Temperature − °C
Figure 7.
9
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE AND DISTORTION
vs
TEMPERATURE
EFFECTIVE NUMBER OF BITS
vs
TEMPERATURE
69
12
AVDD = DVDD = 3.3 V
fs = 30 MSPS
fi = 3.58 MHz, −1dBFS
Mode 1
ENOB −Effective Number of Bits − Bits
SINAD − Signal-to-Noise and Distortion − dB
70
68
67
66
65
−40
−15
10
35
60
AVDD = DVDD = 3.3 V
fs = 30 MSPS
fi = 3.58 MHz, −1dBFS
Mode 1
11
10
9
−40
85
TA − Temperature − °C
−15
10
35
60
TA − Temperature − °C
Figure 8.
Figure 9.
DNL − Differential Nonlinearity − LSB
DIFFERENTIAL NONLINEARITY
1
0.8
0.6
AVDD = DVDD = 3.3 V
fs = 30 MSPS
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
500
1000
1500
2000
2500
3000
3500
4000
3000
3500
4000
ADC Code
Figure 10.
INL − Integral Nonlinearity − LSB
INTEGRAL NONLINEARITY
2
AVDD = DVDD = 3.3 V
fs = 30 MSPS
1.5
1
0.5
0
−0.5
−1
−1.5
−2
0
500
1000
1500
2000
ADC Code
Figure 11.
10
2500
85
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
FAST FOURIER TRANSFORM - MODE 1
0
AVDD = DVDD = 3.3 V,
fs = 30 MSPS,
fi = 3.58 MHz, −1 dBFS,
Mode 1 Differential
Power − dBFS
−20
−40
−60
−80
−100
14.1
15
14.1
15
13.2
12.3
11.5
10.6
9.69
8.81
7.93
7.05
6.17
5.29
4.41
3.53
2.64
1.76
0.88
−140
0
−120
f − Frequency − MHz
Figure 12.
FAST FOURIER TRANSFORM - MODE 2
0
AVDD = DVDD = 3.3 V,
fs = 30 MSPS,
fi = 3.58 MHz, −1 dBFS,
Mode 2 Differential
Power − dBFS
−20
−40
−60
−80
−100
−120
13.2
12.3
11.5
10.6
9.69
8.81
7.93
7.05
6.17
5.29
4.41
3.53
2.64
1.76
0.88
0
−140
f − Frequency − MHz
Figure 13.
PRINCIPLES OF OPERATION
Analog Input
The analog input AIN is sampled in the sample and hold unit, the output of which feeds the ADC CORE, where
the process of analog to digital conversion is performed against ADC reference voltages, VREFT and VREFB.
Connecting the EXTREF pin to one of two voltages, DGND or DVDD selects one of the two configurations of ADC
reference generation. The ADC reference voltages come from either the internal reference buffer or completely
external sources. Connect EXTREF to DGND for internal reference generation or to DVDD for external reference
generation.
CON0 and CON1 as described below, select the input configuration mode or place the device in powerdown.
The ADC core drives out through output buffers to the data pins D0 to D11. The output buffers can be disabled
by the OE pin.
A single, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is sampled on the
rising edge of CLK, and corresponding data is output after the fifth following rising edge.
The THS1230 can operate in differential Mode 1 or differential Mode 2, controlled by the configuration pins
CON0 and CON1 as shown in Table 1. Mode 0 places the device in power-down state or standby for reduced
power consumption.
11
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
Table 1. Input Modes of Operation
MODE
CON1
CON0
0
0
0
MODE OF OPERATION
Device powered down
1
0
1
Differential mode × 1
2
1
0
Differential mode × 0.5
3
1
1
Not used
Modes 1 and 2 are shown in Figure 14.
AIN−
1V
AIN+
OUTPUT
CODE
4095
0
AIN−
2V
AIN+
OUTPUT CODE
4095
0
MODE 2, CON[1:0] = 10
MODE 1, CON[1:0] = 01
Figure 14. Input Mode Configurations
The gain of the sample and hold changes with the CON1 and the CON0 inputs. Table 2 shows the gain of the
sample and hold and the levels applied at the AIN+ and AIN– analog inputs for Mode 1 and Mode 2. The
common mode level for the two analog inputs is at AVDD/2.
Table 2. Input Mode Switching
MODE
CON1
CON0
(AIN+) – (AIN–)
MIN
(AIN+) – (AIN–)
MAX
1
0
1
–1 V
1V
×1
2
1
0
–2 V
2V
×0.5
S/H GAIN
Table 2 assumes that the delta in ADC reference voltages VREFT and VREFB is set to 1 V, i.e., VREFT – VREFB = 1
V. Note that VREFB and VREFT can be set externally, which will scale the numbers given in this table.
The user-chosen operating configuration and reference voltages determine what input signal voltage range the
THS1230 can handle.
The following sections explain both the internal signal flow of the device and how the input signal span is related
to the ADC reference voltages, as well as the ways in which the ADC reference voltages can be buffered
internally or externally applied.
Signal Processing Chain (Sample and Hold, ADC)
Figure 15 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
12
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
REFT
VP+
+1
AIN+
SAMPLE
AND
−1
HOLD
AIN−
ADC
CORE
VP−
REFB
Figure 15. Analog Input Signal Flow
Sample and Hold
The differential sample and hold processes AIN with respect to the voltages applied to the REFT and REFB pins,
to give a differential output (VP+) – (VP–) = VP given by:
• VP = (AIN+) – ( AIN–)
Analog-to-Digital Converter
No matter what operating configuration is chosen, VP is digitized against ADC reference voltages VREFT and
VREFB. The VREFT and VREFB voltages set the analog input span limits FS+ and FS–, respectively. Any voltages at
AIN greater than REFT or less than REFB causes ADC over-range, which is signaled by OVR going high when
the conversion result is output.
Analog Input
A first-order approximation for the equivalent analog input circuit of the THS1230 is shown in Figure 16. The
equivalent input capacitance CI is 5 pF typical. The input must charge/discharge this capacitance within the
sample period of one half of a clock cycle. When a full-scale voltage step is applied, the input source provides
the charging current through the switch resistance RSW (200 Ω) of S1 and quickly settles. In this case the input
impedance is low. Alternatively, when the source voltage equals the value previously stored on CI, the hold
capacitor requires no input current and the equivalent input impedance is very high.
VS+
VS −
VCM
RS
THS1230
RSW
RS
RSW
CI
CI
+
_
VCM
+
_
Figure 16. Simplified Equivalent Input Circuit
To maintain the frequency performance outlined in the specifications, the total source impedance should be
limited to the following equation with fCLK = 30 MHz, CI = 5 pF, RSW = 200 Ω:
R
S
2f
1
–R
C In(256) SW
CLK
I
So, for applications running at a lower fCLK, the total source resistance can increase proportionally.
13
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
The analog input of the THS1230 is a differential input that can be configured in various ways depending on the
signal source and the required level of performance. A fully differential connection (see Figure 17) delivers the
best performance from the converter.
AVDD
2
R2
VIN+
C1
THS1230
R1
−
AIN+
+
R2
C2
VIN−
C1
R1
−
+
AIN−
C2
REFT
REFB
Figure 17. AC-Coupled Differential Input
The analog input can be dc-coupled (see Figure 18) as long as the inputs are within the analog input common
mode voltage range. For example (see Figure 18), V+ and V– are signals centered on GND with a peak-to-peak
voltage of 2 V, and the circuit in Figure 18 is used to interface it with the THS1230. Assume AVDD of the
converter is 3 V. Two problems have to be solved. The first is to shift common mode level (CML) from 0 V to 1.5
V (AVDD/2). To do that, a V bias voltage and an adequate ratio of R1 and R2 have to be selected. For instance, if
V bias = AVDD = 3 V, then R1 = R2. The second is that the differential voltage has to be reduced from 4 V (2 x 2
V) to 1 V, and for that an attenuation of 4 to1 is needed. The attenuation is determined by the relation:
(R3||2R2)/((R3||2R2) + 2R1). One possible solution is R1 = R2 = R3 = 150 Ω. In this case, moreover, the input
impedance (2R1 + (R3||2R2)) will be 400 Ω. The values can be changed to match any other input impedance. A
capacitor, C, connected from AIN+ to AIN– helps filter any high frequency noise on the inputs, also improving
performance. Note that the chosen value of capacitor C must take into account the highest frequency component
of the analog input signal.
14
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
VBIAS
THS1230
VIN+
R1
R2
AIN+
R3
VIN−
R1
AIN−
R2
REFT
VBIAS
REFB
Figure 18. DC-Coupled Differential Input Circuit
A single-ended source may give better overall system performance when it is converted to a differential signal
before driving the THS1230. The configuration in Figure 19 takes a VIN of 1 V and drives the 1:1 transformer
ratio so that value of AIN+ and AIN– converts to fullscale value at the ADC digital output. With VIN at –1 V the
value at AIN+ and AIN– converts to 0 at the ADC digital outputs.
AV DD
2
THS1230
V IN
AIN+
AIN−
REFT
REFB
Figure 19. Transformer Coupled Single-Ended Input
Digital Outputs
The output of THS1230 is in unsigned binary code. The ADC input over-range indicator is output on pin OVRNG.
Capacitive loading on the output should be kept as low as possible (a maximum loading of 10 pF is
recommended) to ensure best performance. Higher output loading causes higher dynamic output currents and
can therefore increase noise coupling into the part's analog front end. To drive higher loads the use of an output
buffer is recommended.
15
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
When clocking output data from THS1230, it is important to observe its timing relation to CLK. The pipeline ADC
delay is 5 clock cycles to which the maximum output propagation delay needs to be added.
THS1230
SN74ALVCH16841
DA11
DA0
12
1D9
1Q9
1D0
1Q0
2D1
2Q1
2D0
2Q0
2D7
2Q9
2D2
2Q2
ASIC
or
DSP
12
LE
OE
Figure 20. Buffered Output Connection
THS1230
FIFO
DA11
DA0
CLK
12
DSP
D11
1Q15
D0
D15
1Q0
D12
HF flag
16
INTR
WRTCLK
30 MHz
Clock
Figure 21. FIFO Connection
Layout, Decoupling and Grounding Rules
Proper grounding and layout of the PCB on which THS1230 is populated is essential to achieve the stated
performance. It is advised to use separate analog and digital ground planes that are spliced underneath the IC.
THS1230 has digital and analog pins on opposite sides of the package to make this easier. Because there is no
connection internally between analog and digital grounds, they have to be joined on the PCB. It is advised to do
this at one point in close proximity to THS1230.
Because of the high sampling rate and switched-capacitor architecture, THS1230 generates transients on the
supply and reference lines. Proper decoupling of these lines is therefore essential. Decoupling is recommended
as shown in the schematic of the THS1230 evaluation module in Figure 22.
16
THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
+3.3VA
+3.3VD
+3.3VD +3.3VA
U1
THS1230PW
+3.3VD
8
LNK3
LNK4
OEB
EXTREF
OEB
R2
R23
47K
47K
AGND
DVDD
DGND
27
CLKVDD AGND
EXTREF
D0
ADCCLK
28
OEB
26
ADCCLK
OEB
CON0
3
CON1
2
EXTREF
4
CON0
CON1
EXTREF
+3.3VD
AVDD
20
CLK
D1
LNK2
CON1
VINP
47K
VINM
CON0
CON1
R1
47K
VINP
5
VINM
6
9
10
LNK5
TP1
25
ADCD00
24
ADCD01
23
ADCD02
CON0
D3
22
ADCD03
CON1
D4
21
ADCD04
EXTREF
D5
18
ADCD05
D6
17
ADCD06
D7
16
ADCD07
AIN+
D8
15
ADCD08
AIN−
D9
14
ADCD09
13
ADCD10
REFT
D11
REFB
OVRNG
12
11
TP2
C28
ADCD11
ADCOVRNG
ADCD [00:11]
VRB
+
VRT
VRT
1
D2
D10
CON0
19
OE
+3.3VD
R24
7
VRB
10uF
24
AVDD
AGND
27
DVDD
14
D0
13
12
ADCDB01
11
ADCDB02
10
D4
ADCDB03
9
D5
ADCDB04
8
ADCDB05
7
ADCDB06
6
ADCDB07
5
ADCDB08
4
ADCDB09
3
ADCDB10
2
ADCDB11
1
DACCLK 28
25
DGND
26
IOUT1
22
IOUT1
IOUT2
21
IOUT2
D2
C26
0.1uF
_3.3VA
IOUT1
D3
+3.3VD
C62
470pF
C63
0.1uF
C64
470pF
C65
0.1uF
C66
470pF
C67
0.1uF
IOUT2
D6
D7
EXTLO
+3.3VA
16
D8
+3.3VD
D9
REFIO
D10
FSADJ
17
C16
C5
0.01uF
0.1uF
D12
+
C17
C18
0.1uF
0.1uF
10uF
R10
2K
D13
+3.3VA
CLK
C15
MODE
SLEEP
C19
18
D11
COMP1
15
0.1uF
C25
0.1uF
20
D1
ADCDB00
DACCLK
C27
U3
THS5671AIPW
+3.3VD +3.3VA
COMP2
ADCDB[00:11]
19
23
0.1uF
C6
0.1uF
Figure 22. EVM Schematic
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2
LSB beyond the last code transition. The deviation is measured from the center of each particular code to the
true straight line between these two end-points.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
Therefore, this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined
here as the step size for the device under test, i.e. (last transition level - first transition level)/(2n –2). Using this
definition for DNL separates the effects of gain and offset error. A minimum DNL better than –1 LSB ensures no
missing codes.
Offset and Gain Error
Offset error (in LSBs) is defined as the average offset for all inputs, and gain error is defined as the maximum
error (in LSBs) caused by the angular deviation from the offset corrected straight line.
17
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
www.ti.com
Analog Input Bandwidth
The analog input bandwidth is defined as the maximum frequency of a 1-dBFS input sine wave that can be
applied to the device for which an extra 3-dB attenuation is observed in the reconstructed output signal.
Output Timing
Output timing td(O) is measured from the 50% level of the CLK input falling edge to the 10%/90% level of the
digital output. The digital output load is not higher than 10 pF.
Output hold time th(O) is measured from the 50% level of the CLK input falling edge to the10%/90% level of the
digital output. The digital output load is not less than 2 pF.
Aperture delay td(A) is measured from the 50% level of the CLK input to the actual sampling instant.
The OE signal is asynchronous.
OE timing td(PZ) is measured from the VIH(min) level of OE to the high-impedance state of the output data. The
digital output load is not higher than 10 pF.
OE timing td(EN) is measured from the VIL(max) level of OE to the instant when the output data reaches VOH(min) or
VOL(max) output levels. The digital output load is not higher than 10 pF.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
• N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
18
PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS1230IDW
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
-40 to 85
TJ1230
THS1230IPW
OBSOLETE
TSSOP
PW
28
TBD
Call TI
Call TI
-40 to 85
TJ1230
THS1230IPWG4
OBSOLETE
TSSOP
PW
28
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
工商网监
湘ICP备2023018690号
