DGN−8
THS3001
D−8
www.ti.com................................................................................................................................................. SLOS217H – JULY 1998 – REVISED SEPTEMBER 2009
420-MHz HIGH-SPEED CURRENT-FEEDBACK AMPLIFIER
Check for Samples: THS3001
FEATURES
APPLICATIONS
•
•
•
•
1
2
•
•
•
•
•
•
High Speed:
– 420-MHz Bandwidth (G = 1, -3 dB)
– 6500-V/μs Slew Rate
– 40-ns Settling Time (0.1%)
High Output Drive: IO = 100 mA
Excellent Video Performance
– 115-MHz Bandwidth (0.1 dB, G = 2)
– 0.01% Differential Gain
– 0.02° Differential Phase
Low 3-mV (max) Input Offset Voltage
Very Low Distortion:
– THD = –96 dBc at f = 1 MHz
– THD = –80 dBc at f = 10 MHz
Wide Range of Power Supplies:
– VCC = ±4.5 V to ±16 V
Evaluation Module Available
Communication
Imaging
High-Quality Video
THS3001
D OR DGN PACKAGE
(TOP VIEW)
NC
IN−
IN+
1
8
2
7
3
6
VCC−
4
5
NC
VCC+
OUT
NC
NC − No internal connection
RELATED DEVICES
THS4011 /2
290-MHz VFB High-Speed Amplifier
THS6012
500-mA CFB HIgh-Speed Amplifier
THS6022
250-mA CFB High-Speed Amplifier
DESCRIPTION
The THS3001 is a high-speed current-feedback operational amplifier, ideal for communication, imaging, and
high-quality video applications. This device offers a very fast 6500-V/μs slew rate, a 420-MHz bandwidth, and
40-ns settling time for large-signal applications requiring excellent transient response. In addition, the THS3001
operates with a very low distortion of –96 dBc, making it well suited for applications such as wireless
communication basestations or ultrafast ADC or DAC buffers.
HARMONIC DISTORTION
vs FREQUENCY
−75
−80
8
Gain = 2
VCC = ±15 V
VO = 2 VPP
RL = 150 Ω
RF = 750 Ω
−85
6
3rd Harmonic
−90
2nd Harmonic
−95
5
1M
f − Frequency − Hz
10M
VCC = ±5 V
RF = 750 Ω
4
3
2
1
0
−100
100k
VCC = ±15 V
RF = 680 Ω
7
Output Amplitude − dB
Harmonic Distortion − dBc
−70
OUTPUT AMPLITUDE
vs FREQUENCY
G=2
RL = 150 Ω
VI = 200 mV RMS
−1
100k
1M
10M
100M
f − Frequency − Hz
1G
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2009, Texas Instruments Incorporated
THS3001
SLOS217H – JULY 1998 – REVISED SEPTEMBER 2009................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS (1)
PACKAGED DEVICE
TA
SOIC
(D)
0°C to 70°C
MSOP
(DGN)
THS3001CD
THS3001CDGN
THS3001CDR
THS3001CDGNR
MSOP
SYMBOL
ADP
THS3001HVCDGN
BNK
THS3001HVCDGNR
-40°C to 85°C
THS3001ID
THS3001IDGN
THS3001IDR
THS3001IDGNR
ADQ
THS3001HVIDGN
BNJ
THS3001HVIDGNR
(1)
TRANSPORT MEDIA,
QUANTITY
EVALUATION
MODULE
Rails, 75
THS3001EVM
Tape and Reel, 2500
--
Rails, 75
--
Tape and Reel, 2500
--
Rails, 75
--
Tape and Reel, 2500
--
Rails, 75
--
Tape and Reel, 2500
--
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
THS3001
VSS
Supply voltage, VCC+ to VCC-
VI
Input voltage
IO
VID
TJ
TA
Tstg
(1)
(2)
(3)
UNITS
V
33
37
±VCC
±VCC
V
Output current
175
175
mA
Differential input voltage
±6
±6
V
Continuous total power dissipation
TJ
THS3001HV
Maximum junction temperature
See Dissipation Rating Table
(2)
Maximum junction temperature, continuous operation, long term reliability
Operating free-air temperature
(3)
150
150
°C
125
125
°C
THS3001C,
THS3001HVC
0 to 70
0 to 70
°C
THS3001I,
THS3001HVI
–40 to 85
–40 to 85
°C
–65 to 125
–65 to 125
°C
Storage temperature
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
DISSIPATION RATING TABLE
(1)
(2)
2
POWER RATING
(2)
θJA (1)
(°C/W)
TA ≤ 25°C
TA = 85°C
38.3
97.5
1.02 W
410 mW
4.7
58.4
1.71 W
685 mW
PACKAGE
θJC
(°C/W)
D (8)
DGN (8)
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long
term reliability.
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RECOMMENDED OPERATING CONDITIONS
MIN
Split supply
VSS
Supply voltage, VCC+ and VCC-
Single supply
Split supply
Single supply
TA
Operating free-air temperature
NOM
MAX
THS3001C,
THS3001I
±4.5
9
32
THS3001HVC,
THS3001HVI
±4.5
±18.5
9
37
0
70
-40
85
THS3001C, THS3001HVC
THS3001I, THS3001HVI
UNIT
±16
V
°C
ELECTRICAL CHARACTERISTICS
At TA = 25°C, RL = 150 Ω , RF = 1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Split supply
VCC
Power supply operating range
Single supply
VCC = ±5 V
ICC
Quiescent current
VCC = ±15 V
VCC = ±18.5 V,
THS3001HV
VCC = ±5 V
VO
Output voltage swing
VCC = ±15 V
VCC = ±5 V or ±15 V
Input offset voltage drift
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
Negative (IN-)
VICR
Common-mode input voltage range
Open loop transresistance
CMRR
Common-mode rejection ratio
THS3001C
THS3001I
9
33
THS3001HVx
9
TA = 25°C
TA = full range
6.6
TA = full range
6.9
TA = full range
9
mA
9.5
10.5
±2.9
±3.2
±3
±3.3
RL = 150 Ω
±12.1
±12.8
RL = 1 kΩ
±12.8
±13.1
V
100
85
TA = 25°C
mA
120
1
TA = full range
3
mV
4
μV/°C
5
2
TA = full range
10
15
TA = 25°C
VCC = ±15 V
1
10
μA
15
±3
±3.2
±12.9
±13.2
VCC = ±5 V, VO = ±2.5 V, RL = 1 kΩ
1.3
VCC = ±15 V, VO = ±7.5 V, RL = 1 kΩ
2.4
VCC = ±5 V, VCM = ±2.5 V
62
70
VCC = ±15 V, VCM = ±10 V
65
73
TA = 25°C
65
76
TA = full range
63
TA = 25°C
69
TA = full range
67
Power supply rejection ratio
7.5
10
TA = 25°C
RL = 1 kΩ
V
8.5
TA = 25°C
RL = 150 Ω
UNIT
37
5.5
TA = full range
VCC = ±15 V
(1)
(2)
±18.5
VCC = ±5 V
VCC = ±5 V
PSRR
±4.5
TA = 25°C
Positive (IN+)
Input bias current
THS3001HVx
RL = 75 Ω
Input offset voltage
MAX
±16.5
VCC = ±15 V,
VIO
TYP
±4.5
RL = 20 Ω
Output current (2)
MIN
THS3001C
THS3001I
VCC = ±5 V,
IO
IIB
(1)
76
V
MΩ
dB
dB
dB
Full range = 0°C to 70°C for the THS3001C and -40°C to 85°C for the THS3001I.
Observe power dissipation ratings to keep the junction temperature below absolute maximum when the output is heavily loaded or
shorted. See Absolute Maximum Ratings table.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = 25°C, RL = 150 Ω , RF = 1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
Positive (IN+)
1.5
MΩ
Negative (IN-)
15
Ω
7.5
pF
RI
Input resistance
CI
Differential input capacitance
RO
Output resistance
Open loop at 5 MHz
10
Ω
Vn
Input voltage noise
VCC = ±5 V or ±15 V, f = 10 kHz, G = 2
1.6
nV/√Hz
In
Input current noise
Positive (IN+)
Negative (IN-)
13
VCC = ±5 V or ±15 V, f = 10 kHz, G = 2
pA/√Hz
16
OPERATING CHARACTERISTICS
TA = 25°C, RL = 150 Ω , RF = 1 kΩ (unless otherwise noted)
PARAMETER
SR
Slew rate
(1)
VCC = ±5 V,
VO(PP) = 4 V
G=5
1300
VCC = ±15 V,
VO(PP) = 20 V
G = –5
6500
G=5
6300
Settling time to 0.1%
Gain = –1,
40
Settling time to 0.1%
VCC = ±5 V,
0 V to 2 V Step,
Gain = –1,
25
Total harmonic distortion
VCC = ±15 V,
fc = 10 MHz,
VO(PP) = 2 V,
G=2
Differential gain error
G = 2, 40 IRE modulation,
±100 IRE Ramp, NTSC and PAL
VCC = ±5 V
0.015%
VCC = ±15 V
0.01%
Differential phase error
G = 2, 40 IRE modulation,
±100 IRE Ramp, NTSC and PAL
VCC = ±5 V
0.01°
VCC = ±15 V
0.02°
Small signal bandwidth (-3 dB)
BW
Bandwidth for 0.1 dB flatness
Full power bandwidth (2)
4
TYP
1700
G = 1, RF = 1 kΩ
(1)
(2)
MIN
G = –5
VCC = ±15 V,
0 V to 10 V Step
ts
THD
TEST CONDITIONS
MAX
UNIT
V/μs
ns
–80
dBc
VCC = ±5 V
330
MHz
MHz
VCC= ±15 V
420
G = 2, RF = 750 Ω,
VCC = ±5 V
300
G = 2, RF = 680 Ω,
VCC = ±15 V
385
G = 5, RF = 560 Ω,
VCC = ±15 V
350
G = 2, RF = 750 Ω,
VCC = ±5 V
85
G = 2, RF = 680 Ω,
VCC = ±15 V
115
VCC = ±5 V, VO(PP) = 4 V,
RL = 500 Ω
G = –5
65
G=5
62
VCC = ±15 V, VO(PP) = 20 V,
RL = 500 Ω
G = –5
32
G=5
31
MHz
MHz
MHz
Slew rate is measured from an output level range of 25% to 75%.
Full power bandwidth is defined as the frequency at which the output has 3% THD.
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PARAMETER MEASUREMENT INFORMATION
RG
RF
VCC+
−
VO
+
VI
50 Ω
VCC−
RL
Figure 1. Test Circuit, Gain = 1 + (RF/RG)
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
|VO|
Output voltage swing
vs Free-air temperature
2
ICC
Current supply
vs Free-air temperature
3
IIB
Input bias current
vs Free-air temperature
4
VIO
Input offset voltage
vs Free-air temperature
5
vs Common-mode input voltage
6
vs Common-mode input voltage
7
vs Frequency
8
CMRR Common-mode rejection ratio
Transresistance
vs Free-air temperature
9
Closed-loop output impedance
vs Frequency
10
Vn
Voltage noise
vs Frequency
11
In
Current noise
vs Frequency
11
vs Frequency
12
vs Free-air temperature
13
PSRR
SR
Power supply rejection ratio
Slew rate
Normalized slew rate
vs Supply voltage
vs Output step peak-to-peak
vs Gain
14
15, 16
17
vs Peak-to-peak output voltage swing
18, 19
vs Frequency
20, 21
Differential gain
vs Loading
22, 23
Differential phase
vs Loading
24, 25
Output amplitude
vs Frequency
26-30
Normalized output response
vs Frequency
Harmonic distortion
Small and large signal frequency response
31-34
35, 36
Small signal pulse response
37, 38
Large signal pulse response
39 - 46
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TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
14
9
VCC = ±15 V
No Load
8
13
VCC = ±15 V
RL = 150 Ω
12.5
ICC − Supply Current − mA
VO − Output Voltage Swing − V
13.5
CURRENT SUPPLY
vs
FREE-AIR TEMPERATURE
12
4
3.5
VCC = ±5 V
No Load
3
VCC = ±5 V
RL = 150 Ω
2.5
2
−40
−20
0
40
20
60
VCC = ±15 V
7
6
VCC = ±10 V
5
VCC = ±5 V
4
80
3
−40
100
60
Figure 3.
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
80
100
0
IIB+
VCC = ±5 V
−1
VCC = ±15 V
−1.5
VCC = ±5 V
−0.2
VIO − Input Offset Voltage − mV
I IB − Input Bias Current − µ A
40
Figure 2.
IIB+
IIB−
−2
VCC = ±15 V
−2.5
−20
0
20
40
60
80
VCC = ±5 V
−0.4
−0.6
VCC = ±15 V
−0.8
−1
Gain = 1
RF = 1 kΩ
IIB−
100
−1.2
−40
TA − Free-Air Temperature − °C
Figure 4.
6
20
TA − Free-Air Temperature − °C
−0.5
−3
−40
0
−20
TA − Free-Air Temperature − °C
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
COMMON-MODE REJECTION RATIO
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE REJECTION RATIO
vs
COMMON-MODE INPUT VOLTAGE
80
TA = −40°C
70
CMRR − Common-Mode Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
80
TA = 85°C
TA = 25°C
60
50
40
VCC = ±15 V
30
TA = −40°C
70
TA = 85°C
TA = 25°C
60
50
40
30
VCC = ±5 V
20
0
2
4
6
8
10
12
14
0
0.5
|VIC| − Common-Mode Input Voltage − V
3
Figure 7.
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
TRANSRESISTANCE
vs
FREE-AIR TEMPERATURE
3.5
4
2.8
VCC = ±15 V
2.6
VCC = ±5 V
VCC = ±15 V
2.4
60
50
40
30
1 kΩ
2.2
2
VCC = ±10 V
1.8
1.6
1 kΩ
20
−
+
VI
0
1k
2.5
2
|VIC| − Common-Mode Input Voltage − V
70
10
1.5
Figure 6.
Transresistance − M Ω
CMRR − Common-Mode Rejection Ratio − dB
80
1
1 kΩ
10k
1.4
VO
1 kΩ
100k
1.2
1M
10M
100M
VCC = ±5 V
VO = VCC/2
RL = 1 kΩ
1
−40
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
f − Frequency − Hz
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
1
VO
750 Ω
750 Ω
1 kΩ
−
0.1
+
50 Ω
VI
THS3001
1000
VO
Zo =
−1
VI
(
0.01
100k
10M
100M
f − Frequency − Hz
In+
10
1k
10k
Figure 10.
Figure 11.
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO
vs
FREE-AIR TEMPERATURE
VCC = ±15 V
VCC = ±15 V
VCC = ±5 V
+PSRR
30
20
G=1
RF = 1 kΩ
10k
100k
1M
100k
90
VCC = ±5 V
10M
100M
85
VCC = −5 V
VCC = −15 V
80
VCC = +5 V
75
VCC = +15 V
70
−40
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
f − Frequency − Hz
Figure 12.
8
100
f − Frequency − Hz
40
0
1k
10
1G
−PSRR
10
In−
Vn
60
50
100
)
80
70
VCC = ±15 V and ±5 V
TA = 25°C
1
1M
90
PSRR − Power Supply Rejection Ratio − dB
Vn − Voltage Noise − nV/ Hz and
I n − Current Noise − pA/ Hz
10
1000
VCC = ±15 V
RF = 750 Ω
Gain = +2
TA = 25°C
VI(PP) = 2 V
PSRR − Power Supply Rejection Ratio − dB
Closed-Loop Output Impedance − Ω
100
VOLTAGE NOISE AND CURRENT NOISE
vs
FREQUENCY
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
SLEW RATE
vs
SUPPLY VOLTAGE
SLEW RATE
vs
OUTPUT STEP
7000
10000
G = +5
RL = 150 Ω
tr/tf = 300 ps
RF = 1 kΩ
SR − Slew Rate − V/µs
SR − Slew Rate − V/µs
6000
+SR
5000
4000
3000
+SR
2000
−SR
1000
VCC = ±15 V
G = +5
RL = 150 Ω
tr/tf = 300 ps
RF = 1 kΩ
−SR
100
1000
5
7
9
11
13
0
15
5
10
15
20
VO(PP) − Output Step − V
|VCC| − Supply Voltage − V
Figure 14.
Figure 15.
SLEW RATE
vs
OUTPUT STEP
NORMALIZED SLEW RATE
vs
GAIN
2000
1.5
VCC = ±5 V
VO(PP) = 4 V
RL = 150 Ω
RF = 1 kΩ
tr/tf = 300 ps
+SR
SR − Normalized Slew Rate − V/ µs
1.4
SR − Slew Rate − V/µs
1000
−SR
VCC = ±5 V
G = +5
RL = 150 Ω
tr/tf = 300 ps
RF= 1 kΩ
1.3
1.2
−Gain
1.1
1
+Gain
0.9
0.8
0.7
100
0
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
G − Gain − V/V
VO(PP) − Output Step − V
Figure 16.
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
HARMONIC DISTORTION
vs
PEAK-TO-PEAK OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
PEAK-TO-PEAK OUTPUT VOLTAGE SWING
−50
−50
8 MHz
Gain = 2
VCC = ±15 V
RL = 150 Ω
RF = 750 Ω
−60
−60
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−55
4 MHz
Gain = 2
VCC = ±15 V
RL = 150 Ω
RF = 750 Ω
−55
3rd Harmonic
−65
−70
2nd Harmonic
−75
3rd Harmonic
−65
−70
−75
−80
2nd Harmonic
−85
−80
−90
−85
−95
0
2
4
6
8
10
12
14
16
18
20
0
VO(PP) − Peak-to-Peak Output Voltage Swing − V
6
8
10
12
Figure 18.
Figure 19.
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
14
16
18
20
−60
Gain = 2
VCC = ±15 V
VO = 2 VPP
RL = 150 Ω
RF = 750 Ω
−65
Harmonic Distortion − dBc
Harmonic Distortion − dBc
4
VO(PP) − Peak-to-Peak Output Voltage Swing − V
−70
−75
2
−80
3rd Harmonic
−85
−90
2nd Harmonic
−95
−70
Gain = 2
VCC = ±5 V
VO = 2 VPP
RL = 150 Ω
RF = 750 Ω
−75
−80
−85
2nd Harmonic
−90
−95
3rd Harmonic
−100
100k
1M
10M
−100
100k
f − Frequency − Hz
10M
f − Frequency − Hz
Figure 20.
10
1M
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL GAIN
vs
LOADING
DIFFERENTIAL GAIN
vs
LOADING
0.04
0.04
Gain = 2
RF = 750 Ω
40 IRE NTSC Modulation
Worst Case: ±100 IRE Ramp
Gain = 2
RF = 750 Ω
40 IRE PAL Modulation
Worst Case: ±100 IRE Ramp
0.03
Differential Gain − %
Differential Gain − %
0.03
VCC = ±15 V
0.02
VCC = ±5 V
0.01
VCC = ±15 V
0.02
VCC = ±5 V
0.01
0
0
1
2
3
4
5
6
7
8
1
2
Number of 150 Ω Loads
4
5
6
7
8
Number of 150 Ω Loads
Figure 22.
Figure 23.
DIFFERENTIAL PHASE
vs
LOADING
DIFFERENTIAL PHASE
vs
LOADING
0.35
0.3
Gain = 2
RF = 750 Ω
40 IRE NTSC Modulation
Worst Case: ±100 IRE Ramp
Gain = 2
RF = 750 Ω
40 IRE PAL Modulation
Worst Case: ±100 IRE Ramp
0.3
Differential Phase − Degrees
0.25
Differential Phase − Degrees
3
0.2
0.15
VCC = ±15 V
0.1
VCC = ±5 V
0.05
0.25
0.2
0.15
VCC = ±15 V
0.1
VCC = ±5 V
0.05
0
0
1
2
3
4
5
6
7
8
1
Number of 150 Ω Loads
2
3
4
5
6
7
8
Number of 150 Ω Loads
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
3
Output Amplitude − dB
1
RF = 750 Ω
2
1
Output Amplitude − dB
2
3
Gain = 1
VCC = ±15 V
RL = 150 Ω
VI = 200 mV RMS
0
−1
−2
RF = 1 kΩ
−3
RF = 1.5 kΩ
−1
−2
RF = 1.5 kΩ
−5
−5
10M
100M
RF = 1 kΩ
−3
−4
1M
−6
100k
1G
Figure 27.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
8
RF = 560 Ω
7
Output Amplitude − dB
Output Amplitude − dB
9
Gain = 2
VCC = ±15 V
RL = 150 Ω
VI = 200 mV RMS
5
4
RF = 680 Ω
3
RF = 1 kΩ
2
5
4
RF = 1 kΩ
2
0
0
100M
1G
RF = 750 Ω
3
1
10M
RF = 560 Ω
6
1
1M
Gain = 2
VCC = ±5 V
RL = 150 Ω
VI = 200 mV RMS
−1
100k
f − Frequency − Hz
1M
10M
100M
1G
f − Frequency − Hz
Figure 28.
12
1G
f − Frequency − Hz
6
−1
100k
100M
Figure 26.
9
7
10M
1M
f − Frequency − Hz
8
RF = 750 Ω
0
−4
−6
100k
Gain = 1
VCC = ±5 V
RL = 150 Ω
VI = 200 mV RMS
Figure 29.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT AMPLITUDE
vs
FREQUENCY
NORMALIZED OUTPUT RESPONSE
vs
FREQUENCY
3
70
2
50
Normalized Output Response − dB
Output Amplitude − dB
60
VCC = ±15 V
40
30
VCC = ±5 V
20
10
0
G = +1000
RF = 10 kΩ
RL = 150 Ω
VO = 200 mV RMS
−10
100k
0
−1
RF = 680 Ω
−2
−3
RF = 1 kΩ
−4
100M
−6
100k
1G
Figure 31.
NORMALIZED OUTPUT RESPONSE
vs
FREQUENCY
NORMALIZED OUTPUT RESPONSE
vs
FREQUENCY
3
Gain = −1
VCC = ±5 V
RL = 150 Ω
VI = 200 mV RMS
RF = 390 Ω
RF = 560 Ω
Normalized Output Response − dB
Normalized Output Response − dB
1G
f − Frequency − Hz
0
−1
RF = 750 Ω
−2
−3
RF = 1 kΩ
−4
−5
−6
100k
100M
Figure 30.
3
1
10M
1M
f − Frequency − Hz
2
RF = 560 Ω
−5
10M
1M
1
Gain = −1
VCC = ±15 V
RL = 150 Ω
VI = 200 mV RMS
1M
10M
100M
1G
0
RF = 560 Ω
−3
RF = 1 kΩ
−6
−9
−12
Gain = +5
VCC = ±15 V
RL = 150 Ω
VO = 200 mV RMS
−15
100k
f − Frequency − Hz
1M
10M
100M
1G
f − Frequency − Hz
Figure 32.
Figure 33.
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TYPICAL CHARACTERISTICS (continued)
NORMALIZED OUTPUT RESPONSE
vs
FREQUENCY
−3
RF = 390 Ω
VI = 500 mV
2
−6
0
−9
VI = 250 mV
Output Level − dBV
Normalized Output Response − dB
4
SMALL AND LARGE SIGNAL
FREQUENCY RESPONSE
−2
RF = 620 Ω
−4
−6
RF = 1 kΩ
−8
−12
−15
VI = 125 mV
−18
−21
VI = 62.5 mV
−10
−24
Gain = +5
VCC = ±5 V
RL = 150 Ω
VO = 200 mV RMS
−12
−14
100k
1M
−27
10M
100M
−30
100k
1G
Gain = 1
VCC = ±15 V
RF = 1 kΩ
RL = 150 Ω
f − Frequency − Hz
SMALL AND LARGE SIGNAL
FREQUENCY RESPONSE
SMALL SIGNAL PULSE RESPONSE
VI − Input Voltage − mV
Figure 35.
0
VI = 250 mV
−6
−9
VI = 125 mV
VO − Output Voltage − V
Output Level − dBV
−3
−12
−15
VI = 62.5 mV
−24
100k
Gain = 2
VCC = ±15 V
RF = 680 Ω
RL = 150 Ω
1M
10M
100M
1G
300
100
−100
−200
200
100
0
Gain = 1
VCC = ±5 V
RL = 150 Ω
RF = 1 kΩ
tr/tf = 300 ps
−100
−200
−300
0
f − Frequency − Hz
10
20
30
40
50
60
70
80
90 100
t − Time − ns
Figure 36.
14
1G
f − Frequency − Hz
VI = 500 mV
−21
100M
Figure 34.
3
−18
10M
1M
Figure 37.
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TYPICAL CHARACTERISTICS (continued)
LARGE SIGNAL PULSE RESPONSE
VI − Input Voltage − V
60
20
−20
−60
200
VO − Output Voltage − V
VO− Output Voltage − mV
VI − Input Voltage − mV
SMALL SIGNAL PULSE RESPONSE
100
0
Gain = 5
VCC = ±5 V
RL = 150 Ω
RF = 1 kΩ
tr/tf = 300 ps
−100
−200
3
1
−1
−3
2
1
0
−1
−2
−3
−300
0
10
20
30
40
50
60
70
80
Gain = +1
VCC = ±15 V
RL = 150 Ω
RF = 1 kΩ
tr/tf= 2.5 ns
90 100
0
10
20
30
50
60
70
80
Figure 38.
Figure 39.
LARGE SIGNAL PULSE RESPONSE
LARGE SIGNAL PULSE RESPONSE
VI − Input Voltage − V
3
1
−1
−3
2
VO − Output Voltage − V
VI − Input Voltage − V
t − Time − ns
VO − Output Voltage − V
40
1
0
Gain = 1
VCC = ±5 V
RL = 150 Ω
RF = 1 kΩ
tr/tf= 2.5 ns
−1
−2
90 100
t − Time − ns
−3
3
1
−1
−3
10
5
0
Gain = +5
VCC = ±15 V
RL = 150 Ω
RF = 1 kΩ
tr/tf= 300 ps
−5
−10
−15
0
10
20
30
40
50
60
70
80
90 100
0
t − Time − ns
10
20
30
40
50
60
70
80
90 100
t − Time − ns
Figure 40.
Figure 41.
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TYPICAL CHARACTERISTICS (continued)
LARGE SIGNAL PULSE RESPONSE
VI − Input Voltage − V
600
200
−200
−600
2
VO − Output Voltage − V
VO − Output Voltage − V
VI − Input Voltage − mV
LARGE SIGNAL PULSE RESPONSE
1
0
Gain = 5
VCC = ±5 V
RL = 150 Ω
RF = 1 kΩ
tr/tf= 300 ps
−1
−2
3
1
−1
2
1
Gain = −1
VCC = ±15 V
RL = 150 Ω
RF = 1 kΩ
tr/tf= 2.5 ns
0
−1
−2
−3
−3
0
10
20
30
40
50
60
70
80
0
90 100
10
20
30
70
80
LARGE SIGNAL PULSE RESPONSE
LARGE SIGNAL PULSE RESPONSE
VI − Input Voltage − mV
Figure 43.
3
1
−1
2
1
VO − Output Voltage − V
VI − Input Voltage − V
VO − Output Voltage − V
60
Figure 42.
Gain = −1
VCC = ±5 V
RL = 150 Ω
RF = 1 kΩ
tr/tf= 300 ps
0
−1
−2
−3
10
20
30
40
50
60
90 100
70
80
90 100
600
200
−200
−600
2
1
0
Gain = −5
VCC = ±5 V
RL = 150 Ω
RF = 1 kΩ
tr/tf= 300 ps
−1
−2
−3
0
t − Time − ns
10
20
30
40
50
60
70
80
90 100
t − Time − ns
Figure 44.
16
50
t − Time − ns
t − Time − ns
0
40
Figure 45.
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TYPICAL CHARACTERISTICS (continued)
VO − Output Voltage − V
VI − Input Voltage − V
LARGE SIGNAL PULSE RESPONSE
3
1
−1
−2
10
5
0
Gain = −5
VCC = ±15 V
RL = 150 Ω
RF = 1 kΩ
tr/tf= 300 ps
−5
−10
−15
0
10
20
30
40
50
60
70
80
90 100
t − Time − ns
Figure 46.
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APPLICATION INFORMATION
THEORY OF OPERATION
The THS3001 is a high-speed, operational amplifier configured in a current-feedback architecture. The device is
built using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors
possessing fTs of several GHz. This configuration implements an exceptionally high-performance amplifier that
has a wide bandwidth, high slew rate, fast settling time, and low distortion. A simplified schematic is shown in
Figure 47.
VCC+
7
IIB
IN+
3
2
IN−
6
OUT
IIB
4
VCC−
Figure 47. Simplified Schematic
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RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES
The THS3001 is fabricated using Texas Instruments 30-V complementary bipolar process, HVBiCOM. This
process provides the excellent isolation and extremely high slew rates that result in superior distortion
characteristics.
As with all current-feedback amplifiers, the bandwidth of the THS3001 is an inversely proportional function of the
value of the feedback resistor (see Figures 26 to 34). The recommended resistors for the optimum frequency
response are shown in Table 1. These should be used as a starting point and once optimum values are found,
1% tolerance resistors should be used to maintain frequency response characteristics. For most applications, a
feedback resistor value of 1 kΩ is recommended - a good compromise between bandwidth and phase margin
that yields a stable amplifier.
Consistent with current-feedback amplifiers, increasing the gain is best accomplished by changing the gain
resistor, not the feedback resistor. This is because the bandwidth of the amplifier is dominated by the feedback
resistor value and internal dominant-pole capacitor. The ability to control the amplifier gain independent of the
bandwidth constitutes a major advantage of current-feedback amplifiers over conventional voltage-feedback
amplifiers. Therefore, once a frequency response is found suitable to a particular application, adjust the value of
the gain resistor to increase or decrease the overall amplifier gain.
Finally, it is important to realize the effects of the feedback resistance on distortion. Increasing the resistance
decreases the loop gain and increases the distortion. It is also important to know that decreasing load impedance
increases total harmonic distortion (THD). Typically, the third-order harmonic distortion increases more than the
second-order harmonic distortion.
Table 1. Recommended Resistor Values for Optimum
Frequency Response
GAIN
RF for VCC = ±15 V
1
1 kΩ
RF for VCC = ±5 V
1 kΩ
2, -1
680 Ω
750 Ω
2
620 Ω
620 Ω
5
560 Ω
620 Ω
OFFSET VOLTAGE
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
Figure 48. Output Offset Voltage Model
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NOISE CALCULATIONS
Noise can cause errors on small signals. This is especially true for amplifying small signals coming over a
transmission line or an antenna. The noise model for current-feedback amplifiers (CFB) is the same as for
voltage feedback amplifiers (VFB). The only difference between the two is that CFB amplifiers generally specify
different current-noise parameters for each input, while VFB amplifiers usually only specify one noise-current
parameter. The noise model is shown in Figure 49. This model includes all of the noise sources as follows:
• en = Amplifier internal voltage noise (nV/√Hz)
• IN+ = Nonverting current noise (pA/√Hz)
• IN- = Inverting current noise (pA/√Hz)
• eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
RS
eRs
en
Noiseless
+
_
eni
IN+
eno
eRf
RF
eRg
IN−
RG
Figure 49. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
e
Where:
ni
+
Ǹ
ǒenǓ ) ǒIN )
2
R
Ǔ
S
2
ǒ
) IN–
ǒR F ø R G ǓǓ
2
ǒ
) 4 kTRs ) 4 kT R ø R
F
G
Ǔ
k = Boltzmann’s constant = 1.380658 × 10−23
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and RG
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
e no + e
ni
A
V
ǒ
+ e ni 1 )
Ǔ
RF
(Noninverting Case)
RG
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier.
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SLEW RATE
The slew rate performance of a current-feedback amplifier, like the THS3001, is affected by many different
factors. Some of these factors are external to the device, such as amplifier configuration and PCB parasitics, and
others are internal to the device, such as available currents and node capacitance. Understanding some of these
factors should help the PCB designer arrive at a more optimum circuit with fewer problems.
Whether the THS3001 is used in an inverting amplifier configuration or a noninverting configuration can impact
the output slew rate. As can be seen from the specification tables as well as some of the figures in this data
sheet, slew-rate performance in the inverting configuration is faster than in the noninverting configuration. This is
because in the inverting configuration the input terminals of the amplifier are at a virtual ground and do not
significantly change voltage as the input changes. Consequently, the time to charge any capacitance on these
input nodes is less than for the noninverting configuration, where the input nodes actually do change in voltage
an amount equal to the size of the input step. In addition, any PCB parasitic capacitance on the input nodes
degrades the slew rate further simply because there is more capacitance to charge. Also, if the supply voltage
(VCC) to the amplifier is reduced, slew rate decreases because there is less current available within the amplifier
to charge the capacitance on the input nodes as well as other internal nodes.
Internally, the THS3001 has other factors that impact the slew rate. The amplifier's behavior during the slew-rate
transition varies slightly depending upon the rise time of the input. This is because of the way the input stage
handles faster and faster input edges. Slew rates (as measured at the amplifier output) of less than about
1500 V/μs are processed by the input stage in a linear fashion. Consequently, the output waveform smoothly
transitions between initial and final voltage levels. This is shown in Figure 50. For slew rates greater than 1500
V/μs, additional slew-enhancing transistors present in the input stage begin to turn on to support these faster
signals. The result is an amplifier with extremely fast slew-rate capabilities. Figure 50 and Figure 51 show
waveforms for these faster slew rates. The additional aberrations present in the output waveform with these
faster-slewing input signals are due to the brief saturation of the internal current mirrors. This phenomenon,
which typically lasts less than 20 ns, is considered normal operation and is not detrimental to the device in any
way. If for any reason this type of response is not desired, then increasing the feedback resistor or slowing down
the input-signal slew rate reduces the effect.
SLEW RATE
VI − Input Voltage − V
VI − Input Voltage − V
SLEW RATE
4
2
0
10
2
0
−2
5
VO − Output Voltage − V
5
VO − Output Voltage − V
4
SR = 1500 V/µs
Gain = 5
VCC = ±15 V
RL = 150 Ω
RF = 1 kΩ
tr/tf = 10 ns
0
−5
−10
−15
0
20
40
60
80
100 120 140 160 180 200
SR = 2400 V/µs
Gain = 5
VCC = ±15 V
RL = 150 Ω
RF = 1 kΩ
tr/tf = 5 ns
0
−5
−10
−15
0
t − Time − ns
20
40
60
80
100 120 140 160 180 200
t − Time − ns
Figure 50.
Figure 51.
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DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS3001 has been internally compensated to maximize its bandwidth and
slew-rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device's phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 52. A minimum value of 20Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1 kΩ
1 kΩ
Input
_
20 Ω
Output
THS3001
+
CLOAD
Figure 52. Driving a Capacitive Load
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PCB DESIGN CONSIDERATIONS
Proper PCB design techniques in two areas are important to ensure proper operation of the THS3001. These
areas are high-speed layout techniques and thermal-management techniques. Because the THS3001 is a
high-speed part, the following guidelines are recommended.
• Ground plane - It is essential that a ground plane be used on the board to provide all components with a low
inductive ground connection, but should be removed from below the output and negative input pins as noted
below.
• The DGN package option includes a thermal pad for increased thermal performance. When using this
package, it is recommended to distribute the negative supply as a power plane, and tie the thermal pad to this
supply with multiple vias for proper power dissipation. It is not recommended to tie the thermal pad to ground
when using split supply (±V) as this will cause worse distortion performance than shown in this data sheet.
• Input stray capacitance - To minimize potential problems with amplifier oscillation, the capacitance at the
inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane must be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This is
especially true in the noninverting configuration. An example of this can be seen in Figure 53, which shows
what happens when a 1-pF capacitor is added to the inverting input terminal. The bandwidth increases at the
expense of peaking. This is because some of the error current is flowing through the stray capacitor instead
of the inverting node of the amplifier. Although, while the device is in the inverting mode, stray capacitance at
the inverting input has a minimal effect. This is because the inverting node is at a virtual ground and the
voltage does not fluctuate nearly as much as in the noninverting configuration. This can be seen in Figure 54,
where a 10-pF capacitor adds only 0.35 dB of peaking. In general, as the gain of the system increases, the
output peaking due to this capacitor decreases. While this can initially look like a faster and better system,
overshoot and ringing are more likely to occur under fast transient conditions. So proper analysis of adding a
capacitor to the inverting input node should be performed for stable operation.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
1
7
1 kΩ
Cin
Output Amplitude − dB
5
Vin
Vout
−
+
4
50 Ω
3
RL =
150 Ω
1
0
−1
−3
CI = Stray C Only
−1
2
−2
CI = 10 pF
0
Output Amplitude − dB
6
CI = 1 pF
Cin
−2
Vin
−3
50 Ω
−4
1 kΩ
Vout
−
+
−5
RL =
150 Ω
−6
CI = 0 pF
(Stray C Only)
Gain = 1
VCC = ±15 V
VO = 200 mV RMS
−4
100k
1M
10M
100M
−7
1G
Gain = −1
VCC = ±15 V
VO = 200 mV RMS
−8
100k
1M
10M
100M
1G
f − Frequency − Hz
f − Frequency − Hz
Figure 53.
•
1 kΩ
Figure 54.
Proper power-supply decoupling - Use a minimum 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-μF ceramic capacitor should always be used on the supply terminal of
every amplifier. In addition, the 0.1-μF capacitor should be placed as close as possible to the supply terminal.
As this distance increases, the inductance in the connecting etch makes the capacitor less effective. The
designer should strive for distances of less than 0.1 inch between the device power terminal and the ceramic
capacitors.
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THS3001
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THERMAL INFORMATION
The THS3001 incorporates output-current-limiting protection. Should the output become shorted to ground, the
output current is automatically limited to the value given in the data sheet. While this protects the output against
excessive current, the device internal power dissipation increases due to the high current and large voltage drop
across the output transistors. Continuous output shorts are not recommended and could damage the device.
Additionally, connection of the amplifier output to one of the supply rails (±VCC) is not recommended. Failure of
the device is possible under this condition and should be avoided. But, the THS3001 does not incorporate
thermal-shutdown protection. Because of this, special attention must be paid to the device's power dissipation or
failure may result.
The thermal coefficient θJA is approximately 169°C/W for the SOIC 8-pin D package. For a given θJA, the
maximum power dissipation, shown in Figure 55, is calculated by the following formula:
ǒ
T
P
D
+
–T
MAX A
q
JA
Ǔ
Where:
PD
TMAX
TA
θJA
= Maximum power dissipation of THS3001 (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
= Thermal coefficient from die junction to ambient air (°C/W)
PD − Maximum Power Dissipation − W
1.5
SOIC-D Package:
θJA = 169°C/W
TJ = 150°C
No Airflow
1
0.5
0
−40
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
Figure 55. Maximum Power Dissipation vs Free-Air Temperature
24
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THS3001
www.ti.com................................................................................................................................................. SLOS217H – JULY 1998 – REVISED SEPTEMBER 2009
GENERAL CONFIGURATIONS
A common error for the first-time CFB user is the creation of a unity gain buffer amplifier by shorting the output
directly to the inverting input. A CFB amplifier in this configuration will oscillate and is not recommended. The
THS3001, like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing
capacitors directly from the output to the inverting input is not recommended. This is because, at high
frequencies, a capacitor has a low impedance. This results in an unstable amplifier and should not be considered
when using a current-feedback amplifier. Because of this, integrators and simple low-pass filters, which are
easily implemented on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply
place an RC-filter at the noninverting terminal of the operational-amplifier (see Figure 56).
RG
RF
f
V
O +
V
I
−
VO
+
VI
R1
*3 dB
ǒ
+
1
2pR1C1
R
1)
R
F
G
Ǔǒ
Ǔ
1
1 ) sR1C1
C1
Figure 56. Single-Pole Low-Pass Filter
If a multiple-pole filter is required, the use of a Sallen-Key filter can work well with CFB amplifiers. This is
because the filtering elements are not in the negative feedback loop and stability is not compromised. Because of
their high slew rates and high bandwidths, CFB amplifiers can create accurate signals and help minimize
distortion. An example is shown in Figure 57.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RG =
RF
+
*3 dB
(
1
2pRC
RF
1
2−
Q
)
Figure 57. 2-Pole Low-Pass Sallen-Key Filter
There are two simple ways to create an integrator with a CFB amplifier. The first, shown in Figure 58, adds a
resistor in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant and
the feedback impedance never drops below the resistor value. The second, shown in Figure 59, uses positive
feedback to create the integration. Caution is advised because oscillations can occur due to the positive
feedback.
C1
RF
V
RG
−
VI
+
VO
O +
VI
THS3001
ȡS ) RF1C1ȣ
ǒRGǓȧ S ȧ
Ȣ
Ȥ
R
F
Figure 58. Inverting CFB Integrator
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RG
RF
For Stable Operation:
−
THS3001
VO
+
R2
R1 || RA
≥
(
1+
VO ≅ VI
R1
R2
RF
RG
RF
RG
sR1C1
)
VI
C1
RA
Figure 59. Noninverting CFB Integrator
The THS3001 may also be employed as a good video distribution amplifier. One characteristic of distribution
amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the
number of lines increases and the closed-loop gain increases (see Figures 22 to 25 for more information). Be
sure to use termination resistors throughout the distribution system to minimize reflections and capacitive
loading.
750 Ω
750 Ω
75 Ω
−
75-Ω Transmission Line
VO1
+
VI
75 Ω
75 Ω
THS3001
N Lines
75 Ω
VON
75 Ω
Figure 60. Video Distribution Amplifier Application
26
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THS3001
www.ti.com................................................................................................................................................. SLOS217H – JULY 1998 – REVISED SEPTEMBER 2009
EVALUATION BOARD
An evaluation board is available for the THS3001 (THS3001EVM). The board has been configured for low
parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board
is shown in Figure 61. The circuitry has been designed so that the amplifier may be used in either an inverting or
noninverting configuration. For more detailed information, refer to the THS3001 EVM User's Guide (literature
number SLOU021). The evaluation board can be ordered online through the TI web site, or through your local TI
sales office or distributor.
VCC+
+
C2
0.1 µF
C1
6.8 µF
R1
1 kΩ
IN +
R2
49.9 Ω
+
R3
49.9 Ω
OUT
THS3001
_
R5
1 kΩ
+
C4
0.1 µF
C3
6.8 µF
IN −
R4
49.9 Ω
VCC −
Figure 61. THS3001 Evaluation Board Schematic
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THS3001
SLOS217H – JULY 1998 – REVISED SEPTEMBER 2009................................................................................................................................................. www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (March, 2008) to Revision H ................................................................................................. Page
•
Updated document format to current standards ................................................................................................................... 1
•
Deleted references to HV version in SOIC package; this version is not available ............................................................... 2
•
Updated information about THS3001EVM availability ........................................................................................................ 27
28
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
THS3001CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3001C
Samples
THS3001CDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3001C
Samples
THS3001CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
ADP
Samples
THS3001CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
ADP
Samples
THS3001CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3001C
Samples
THS3001HVCDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
BNK
Samples
THS3001HVIDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BNJ
Samples
THS3001ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
3001I
Samples
THS3001IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
3001I
Samples
THS3001IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
ADQ
Samples
THS3001IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
ADQ
Samples
THS3001IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
Level-1-260C-UNLIM
3001I
Samples
NIPDAU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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