Not Recommended for New Designs
D-8
DBV-5
DGN-8
THS3201
DGK-8
www.ti.com ............................................................................................................................................................. SLOS416C – JUNE 2003 – REVISED JUNE 2009
1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER
FEATURES
DESCRIPTION
1
• Unity-Gain Bandwidth: 1.8 GHz
• High Slew Rate: 6700 V/µs (G = 2 V/V,
RL = 100 Ω, 10-V Step)
• IMD3: –78 dBc at 20 MHz: (G = 10 V/V,
RL = 100 Ω, 2-VPP Envelope)
• Noise Figure: 11 dB (G = 10 V/V, RG = 28 Ω,
RF = 255 Ω)
• Input-Referred Noise (f >10 MHz)
– Voltage Noise: 1.65 nV/√Hz
– Noninverting Current Noise: 13.4 pA/√Hz
– Inverting Current Noise: 20 pA/√Hz
• Output Drive: 100 mA
• Power-Supply Voltage Range: ±3.3 V to ±7.5 V
23
APPLICATIONS
•
•
•
•
Test and Measurement
ATE
High-Resolution, High-Sampling Rate ADC
Drivers
High-Resolution, High-Sampling Rate DAC
Output Buffers
The THS3201 is a wideband, high-speed
current-feedback amplifier, designed to operate over
a wide supply range of ±3.3 V to ±7.5 V for today's
high performance applications.
The wide supply range, combined with low distortion
and high slew rate, makes the THS3201 ideally
suited for arbitrary waveform driver applications. The
distortion
performance
also
enables
driving
high-resolution
and
high-sampling
rate
analog-to-digital converters (ADCs).
Its high voltage operation capabilities make the
THS3201 especially suitable for many test,
measurement, and ATE applications where lower
voltage devices do not offer enough voltage swing
capability. Output rise and fall times are nearly
independent
of
step
size
(to
first-order
approximation), making the THS3201 ideal for
buffering small to large step pulses with excellent
linearity in high dynamic systems.
The THS3201 is offered in a 5-pin SOT-23, 8-pin
SOIC, and an 8-pin MSOP with PowerPAD™
packages.
RELATED DEVICES AND DESCRIPTIONS
DEVICE
DESCRIPTION
THS3202
±7.5-V, 2-GHz Dual Low Distortion CFB Amplifier
THS3001
±15-V, 420-MHz Low Distortion CFB Amplifier
THS3061/2 ±15-V, 300-MHz Low Distortion CFB Amplifier
THS3122
±15-V, Dual CFB Amplifier With 350 mA Drive
OPA695
±5-V, 1.7-GHz Low Distortion CFB Amplifier
Low-Noise, Low-Distortion, Wideband Application Circuit
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
+7.5 V
50 Ω Source
8
7
50 Ω
VI
49.9 Ω
49.9 Ω
THS3201
_
-7.5 V
768 Ω
NOTE:
768 Ω
Power supply decoupling capacitors not shown
50 Ω
Noninverting Gain - dB
RF = 768 Ω
+
6
5
4
3
2
1
0
100 k
Gain = 2.
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
1M
10 M
100 M
1G
10 G
f - Frequency - Hz
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2009, Texas Instruments Incorporated
Not Recommended for New Designs
THS3201
SLOS416C – JUNE 2003 – REVISED JUNE 2009 ............................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted. (1)
UNIT
VS
Supply voltage
VI
Input voltage
IO
Output current
VID
16.5 V
±VS
175 mA
Differential input voltage
±3 V
Continuous power dissipation
See Dissipation Rating Table
TJ
Maximum junction temperature (2)
TJ
Maximum junction temperature, continuous operation, long term reliability (3)
TA
Operating free-air temperature range
–40°C to +85°C
TSTG
Storage temperature range
–65°C to +150°C
HBM
3000 V
ESD ratings
CDM
1500 V
MM
100 V
(1)
(2)
(3)
+150°C
+125°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
PACKAGE DISSIPATION RATINGS (1)
(1)
(2)
(3)
POWER RATING (3)
(TJ = +125°C)
PACKAGE
θJC
(°C/W)
θJA (2)
(°C/W)
TA ≤ +25°C
TA= +85°C
DBV (5)
55
255.4
391 mW
156 mW
D (8)
38.3
97.5
1.02 W
410 mW
DGN (8) (1)
4.7
58.4
1.71 W
685 mW
DGK (8 pin)
54.2
260
385 mW
154 mW
The THS3201 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heat sink
and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so
may result in exceeding the maximum junction temperature which could permanently damage the
device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally enhanced package.
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of +125°C. This is the point where distortion
starts to substantially increase. Thermal management of the final PCB should strive to keep the
junction temperature at or below +125°C for best performance and long term reliability.
RECOMMENDED OPERATING CONDITIONS
Supply voltage
TA
2
MIN
MAX
Dual supply
±3.3
±7.5
Single supply
6.6
15
–40
+85
Operating free-air temperature range
Submit Documentation Feedback
UNIT
V
°C
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
Not Recommended for New Designs
THS3201
www.ti.com ............................................................................................................................................................. SLOS416C – JUNE 2003 – REVISED JUNE 2009
PACKAGE/ORDERING INFORMATION (1)
PART NUMBER
PACKAGE TYPE
PACKAGE MARKING
SOIC-8
—
SOT-23
BEO
MSOP-8-PP
BEN
MSOP-8
BGP
THS3201D
THS3201DR
THS3201DBVT
THS3201DBVR
THS3201DGN
THS3201DGNR
THS3201DGK
THS3201DGKR
(1)
TRANSPORT MEDIA, QUANTITY
Rails, 75
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Rails, 80
Tape and Reel, 2500
Rails, 80
Tape and Reel, 2500
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
PIN ASSIGNMENTS
DBV PACKAGE
SOT23-5
(TOP VIEW)
VOUT
VSIN+
1
5
D, DGN, DGK PACKAGES
SOIC-8, MSOP-8
(TOP VIEW)
VS+
NC
VINVIN+
VS-
2
3
4
IN-
1
8
2
7
3
6
4
5
NC
VS+
VOUTNC
NC = No internal connection.
See Note A.
A.
If a PowerPAD is used, it is electrically
isolated from the active circuitry.
Submit Documentation Feedback
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
3
Not Recommended for New Designs
THS3201
SLOS416C – JUNE 2003 – REVISED JUNE 2009 ............................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±7.5 V
At RF = 768 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.
THS3201
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
–40°C to
+85°C
UNITS
MIN/
TYP/
MAX
AC PERFORMANCE
G = +1, RF = 1.2 kΩ
1.8
G = +2, RF = 768 Ω
850
G = +5, RF = 619 Ω
565
G = +10, RF = 487 Ω
520
G = +2, VO = 200 mVpp
380
MHz
Typ
880
MHz
Typ
V/µs
Typ
ns
Typ
ns
Typ
Small-signal bandwidth, –3 dB
(VO = 200 mVPP)
Bandwidth for 0.1 dB flatness
Large-signal bandwidth
G = +2, VO = 2 Vpp
Slew rate
Rise and fall time
Settling time to 0.1%
Settling time to 0.01%
GHz
MHz
G = +2, VO = 5-V step, Rise/Fall
5400/4000
G = +2, VO = 10-V step, Rise/Fall
9800/6700
G = +2, VO = 4-V step, Rise/Fall
0.7/0.9
20
G = –2, VO = 2-V step
60
Typ
Harmonic distortion
2nd-order harmonic
rd
G = +5, f = 10 MHz,
VO = 2 Vpp
RL = 100 Ω
–64
dBc
Typ
RL = 100 Ω
–73
dBc
Typ
Third-order intermodulation distortion (IMD3)
G = +10, fc = 20 MHz, Δf = 1 MHz,
VO(envelope) = 2 Vpp
–78
dBc
Typ
Noise figure
G = +10, fc = 100 MHz, RF = 255 Ω,
RG = 28
11
dB
Typ
Input voltage noise
f > 10 MHz
3 -order harmonic
Input current noise (noninverting)
Input current noise (inverting)
f > 10 MHz
Differential gain
G = +2, RL = 150 Ω,
RF = 768 Ω
Differential phase
1.65
nV/√Hz
Typ
13.4
pA/√Hz
Typ
20
pA/√Hz
Typ
NTSC
0.008%
Typ
PAL
0.004%
Typ
NTSC
0.007°
Typ
PAL
0.011°
Typ
DC PERFORMANCE
Open-loop transimpedance gain
VO = ±1 V, RL = 1 kΩ
Input offset voltage
300
200
140
±0.7
±3
±3.8
±10
±80
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (–)
VCM = 0 V
Input bias current (noninverting)
Average bias current drift (+)
4
Submit Documentation Feedback
±13
±60
±14
±35
120
kΩ
Min
±4
mV
Max
±13
µV/°C
Typ
±85
µA
Max
±300
±400
nA/°C
Typ
±45
±50
µA
Max
±300
±400
nA/°C
Typ
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
Not Recommended for New Designs
THS3201
www.ti.com ............................................................................................................................................................. SLOS416C – JUNE 2003 – REVISED JUNE 2009
ELECTRICAL CHARACTERISTICS: VS = ±7.5 V (continued)
At RF = 768 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.
THS3201
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
–40°C to
+85°C
UNITS
MIN/
TYP/
MAX
INPUT
Common-mode input range
±5.1
±5
±5
±5
V
Min
71
60
58
58
dB
Min
Common-mode rejection ratio
VCM = ±3.75 V
Inverting input impedance, Zin
Open loop
16
Ω
Typ
Noninverting
780
kΩ
Typ
Inverting
11
Ω
Typ
Noninverting
1
pF
Typ
Input resistance
Input capacitance
OUTPUT
Voltage output swing
Current output, sourcing
Current output, sinking
Closed-loop output impedance
RL = 1 kΩ
RL = 100 Ω
±6
±5.9
±5.8
±5.8
V
Min
±5.8
±5.7
±5.5
±5.5
V
Min
115
105
100
100
mA
Min
100
85
80
80
mA
Min
Ω
Typ
RL = 20 Ω
G = +1, f = 1 MHz
0.01
POWER SUPPLY
Minimum operating voltage
Absolute minimum
±3.3
±3.3
±3.3
V
Min
Maximum operating voltage
Absolute maximum
±8.25
±8.25
±8.25
V
Max
14
18
21
21
mA
Max
Maximum quiescent current
Power-supply rejection (+PSRR)
VS+ = 7 V to 8 V
69
63
60
60
dB
Min
Power-supply rejection (–PSRR)
VS– = –7 V to –8 V
65
58
55
55
dB
Min
Submit Documentation Feedback
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
5
Not Recommended for New Designs
THS3201
SLOS416C – JUNE 2003 – REVISED JUNE 2009 ............................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5 V
At RF = 715 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.
THS3201
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
–40°C to
+85°C
UNITS
MIN/
TYP/
MAX
AC PERFORMANCE
Small-signal bandwidth, –3dB
(VO = 200 mVPP)
G = +1, RF= 1.2 kΩ
1.3
G = +2, RF = 715 Ω
725
G = +5, RF = 576 Ω
540
GHz
MHz
Typ
G = +10, RF = 464 Ω
480
Bandwidth for 0.1 dB flatness
G = +2, VO = 200 mVPP
170
MHz
Typ
Large-signal bandwidth
G = +2, VO = 2 VPP
900
MHz
Typ
Slew rate
G = +2, VO = 5-V step, Rise/Fall
5200/4000
V/µs
Typ
Rise and fall time
G = +2, VO = 4-V step, Rise/Fall
0.7/0.9
ns
Typ
20
ns
Typ
60
ns
Typ
RL = 100 Ω
–69
dBc
Typ
RL = 100 Ω
Settling time to 0.1%
Settling time to 0.01%
G = –2, VO = 2-V step
Harmonic distortion
2nd-order harmonic
rd
G = +5, f = 10 MHz,
VO = 2 Vpp
–75
dBc
Typ
Third-order intermodulation distortion (IMD3)
G = +10, fc = 20 MHz, Δf = 1 MHz,
VO(envelope) = 2 VPP
–81
dBc
Typ
Noise figure
G = +10, fc = 100 MHz, RF = 255 Ω,
RG = 28
11
dB
Typ
Input voltage noise
f > 10 MHz
3 -order harmonic
Input current noise (noninverting)
Input current noise (inverting)
f > 10 MHz
Differential gain
G = +2, RL = 150 Ω,
RF = 768 Ω
Differential phase
1.65
nV/√Hz
Typ
13.4
pA/√Hz
Typ
20
pA/√Hz
Typ
NTSC
0.006%
Typ
PAL
0.004%
Typ
NTSC
0.03°
Typ
PAL
0.04°
Typ
DC PERFORMANCE
Open-loop transimpedance gain
VO = +1 V, RL = 1 kΩ
Input offset voltage
300
200
140
120
kΩ
Min
±0.7
±3
±3.8
±4
mV
Max
±10
±13
±V/°C
Typ
±13
±60
±80
±85
µA
Max
±300
±400
nA/°C
Typ
±14
±35
±45
±50
µA
Max
±300
±400
nA/°C
Typ
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (–)
VCM = 0 V
Input bias current (noninverting)
Average bias current drift (+)
6
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Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
Not Recommended for New Designs
THS3201
www.ti.com ............................................................................................................................................................. SLOS416C – JUNE 2003 – REVISED JUNE 2009
ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)
At RF = 715 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.
THS3201
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
MIN/
TYP/
MAX
+25°C
+25°C
0°C to
+70°C
–40°C to
+85°C
±2.6
±2.5
±2.5
±2.5
V
Min
71
60
58
58
dB
Min
UNITS
INPUT
Common-mode input range
Common-mode rejection ratio
VCM = ±2.5 V
Inverting input impedance, ZIN
Open loop
17.5
Ω
Typ
Noninverting
780
kΩ
Typ
Inverting
11
Ω
Typ
Noninverting
1
pF
Typ
V
Min
Min
Input resistance
Input capacitance
OUTPUT
Voltage output swing
Current output, sourcing
Current output, sinking
Closed-loop output impedance
RL = 1 kΩ
±3.65
±3.5
±3.45
±3.4
RL = 100 Ω
±3.45
±3.33
±3.25
±3.2
115
105
100
100
mA
100
85
80
80
mA
Min
Ω
Typ
RL = 20 Ω
G = +1, f = 1 MHz
0.01
POWER SUPPLY
Minimum operating voltage
Absolute minimum
±3.3
±3.3
±3.3
V
Min
Maximum operating voltage
Absolute maximum
±8.25
±8.25
±8.25
V
Max
14
16.8
19
20
mA
Max
Maximum quiescent current
Power-supply rejection (+PSRR)
VS+ = 4.5 V to 5.5 V
69
63
60
60
dB
Min
Power-supply rejection (–PSRR)
VS– = –4.5 V to –5.5 V
65
58
55
55
dB
Min
Submit Documentation Feedback
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
7
THS3201
Not Recommended for New Designs
SLOS416C – JUNE 2003 – REVISED JUNE 2009 ............................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs (VS = ±7.5 V)
FIGURE
Noninverting small-signal frequency response
1, 2
Inverting small-signal frequency response
3
Noninverting large-signal frequency response
4
Inverting large-signal frequency response
5
0.1 dB gain flatness frequency response
6
Capacitive load frequency response
7
Recommended switching resistance
vs Capacitive Load
2nd harmonic distortion
vs Frequency
9
3rd harmonic distortion
vs Frequency
10
2nd harmonic distortion, G = 2
vs Output voltage
11
3rd harmonic distortion, G = 2
vs Output voltage
12
2nd harmonic distortion, G = 5
vs Output voltage
13
3rd harmonic distortion, G = 5
vs Output voltage
14
2nd harmonic distortion, G = 10
vs Output voltage
15
3rd harmonic distortion, G = 10
vs Output voltage
16
Third-order intermodulation distortion (IMD3)
vs Frequency
17
S-Parameter
vs Frequency
18, 19
Input voltage and current noise
vs Frequency
20
Noise figure
vs Frequency
21
Transimpedance
vs Frequency
22
Input offset voltage
vs Case Temperature
23
Input bias and offset current
vs Case Temperature
24
Slew rate
vs Output voltage step
Settling time
8
25
26, 27
Quiescent current
vs Supply voltage
28
Output voltage
vs Load resistance
29
Rejection ratio
vs Frequency
30
Noninverting small-signal transient response
31
Inverting large-signal transient response
32
Overdrive recovery time
33
Differential gain
vs Number of loads
34
Differential phase
vs Number of loads
35
Closed-loop output impedance
vs Frequency
36
8
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Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
Not Recommended for New Designs
THS3201
www.ti.com ............................................................................................................................................................. SLOS416C – JUNE 2003 – REVISED JUNE 2009
Table of Graphs (VS = ±5 V)
FIGURE
Noninverting small-signal frequency response
37
Inverting small-signal frequency response
38
0.1 dB gain flatness frequency response
39
2nd harmonic distortion
vs Frequency
40
3rd harmonic distortion
vs Frequency
41
2nd harmonic distortion, G = 2
vs Output voltage
42
3rd harmonic distortion, G = 2
vs Output voltage
43
2nd harmonic distortion, G = 5
vs Output voltage
44
3rd harmonic distortion, G = 5
vs Output voltage
45
2nd harmonic distortion, G = 10
vs Output voltage
46
3rd harmonic distortion, G = 10
vs Output voltage
47
Third-order intermodulation distortion (IMD3)
vs Frequency
48
S-Parameter
vs Frequency
49, 50
Slew rate
vs Output voltage step
51
Noninverting small-signal transient response
52
Inverting large-signal transient response
53
Overdrive recovery time
54
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Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
9
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THS3201
SLOS416C – JUNE 2003 – REVISED JUNE 2009 ............................................................................................................................................................. www.ti.com
VS = ±7.5 V Graphs
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Noninverting Gain - dB
RF = 768 Ω
7
6
5
RF = 1 kΩ
4
3
Gain = 2.
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
2
1
0
100 k
1M
10 M
100 M
1G
20
18
16
14
12
10
G = 5, RF = 619 Ω
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
8
6
4
2
0
-2
-4
10 G
G = 2, RF = 768 Ω
G =1, RF = 1.2 kΩ
100 k
1M
10 G
6
RL = 100 Ω,
VO = 2 VPP.
VS = ±7.5 V
10
RL = 100 Ω,
VO = 2 VPP.
VS = ±7.5 V
8
6
4
2
G = -1, RF = 576 Ω
0
1M
10 M
100 M
f - Frequency - Hz
100 k
1G
1M
10 M
100 M
f - Frequency - Hz
100 k
1G
1M
10 M
100 M
f - Frequency - Hz
1G
10 G
CAPACITIVE LOAD
FREQUENCY RESPONSE
RECOMMENDED RISO
vs
CAPACITIVE LOAD
2nd HARMONIC DISTORTION
vs
FREQUENCY
60
-40
Gain = 5,
RF = 619 Ω
RL = 100 Ω,
VS = ±7.5 V
50
Recommended R
- Ω
ISO
12
Gain = 5
RF = 619 Ω
RL = 100 Ω
VS = ±7.5 V
R(ISO) = 15 Ω,
CL = 100 pF
40
30
20
_
+
10
R(ISO) = 20 Ω,
CL = 47 pF
RISO
CL
0
0
5.8
Figure 6.
R(ISO) = 20 Ω,
CL = 50 pF
0
5.9
Figure 5.
14
2
6
Figure 4.
R(ISO) = 30 Ω, CL = 22 pF
4
6.1
5.6
-4
100 k
6.2
5.7
-2
0
10 G
Gain = 2,
RF = 768 Ω,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±7.5 V
6.3
G =-5, RF = 549 Ω
Noninverting Gain - dB
Inverting Gain - dB
G = 2, RF = 715 Ω
6
1G
6.4
14
8
8
100 M
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
10
10
10 M
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
12
16
1M
f - Frequency - Hz
16
2
G = -1, RF = 619 Ω
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
G =-5, RF = 576 Ω
4
G = -2, RF = 576 Ω
2
0
-2
-4
100 k
Figure 3.
12
Inverting Gain - dB
1G
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
Figure 2.
14
Gain - dB
100 M
G = -5, RF = 549 Ω
16
14
12
10
8
6
4
Figure 1.
16
100
200
300
400
500
f - Frequency - MHz
Figure 7.
10
10 M
G = -10, RF = 499 Ω
20
18
f - Frequency - Hz
f - Frequency - Hz
-2
24
22
G = 10, RF = 487 Ω
2nd Order Harmonic Distortion - dBc
Noninverting Gain - dB
24
22
RF = 619 Ω
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Noninverting Gain - dB
8
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
10
100
CL - Capacitive Load - pF
Figure 8.
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G = 10
RF = 499 W, RG = 54.9 W
-50
G=5
RF = 619 W,
-60
RG = 154 W
-70
Vs = ±7.5V
Vout = 2VPP
-80
RL = 100 W
G=2
RF = 768 W, RG = 768 W
-90
-100
1
10
100
f - Frequency - MHz
Figure 9.
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
Not Recommended for New Designs
THS3201
www.ti.com ............................................................................................................................................................. SLOS416C – JUNE 2003 – REVISED JUNE 2009
VS = ±7.5 V Graphs (continued)
2nd HARMONIC DISTORTION
G=2
vs
OUTPUT VOLTAGE
3rd HARMONIC DISTORTION
vs
FREQUENCY
2nd Order Harmonic Distortion - dBc
G=2
RF = 768 W, RG = 768 W
-70
-75
Vs = ±7.5V
Vout = 2VPP
-80
RL = 100 W
-85
G=5
RF = 619 W, RG = 154 W
-90
G = 10
RF = 499 W, RG = 54.9 W
-95
-100
-40
-50
RL = 100 W
-60
10
32MHz
-70
-80
1MHz
-90
-100
-110
1
100
16MHz
0
1
2
2MHz
4MHz
3
4
5
-80
-90
1MHz
8MHz
-100
4MHz
2MHz
16MHz
0
1
2
3
4
5
2nd HARMONIC DISTORTION
G=5
vs
OUTPUT VOLTAGE
3rd HARMONIC DISTORTION
G=5
vs
OUTPUT VOLTAGE
2nd ORDER HARMONIC DISTORTION
G = 10
vs
OUTPUT VOLTAGE
64MHz
-70
-80
1MHz
-90
4MHz
-100
16MHz
1
2
8MHz
3
2MHz
4
5
-40
-50
RL = 100 W
32MHz
64MHz
-60
-70
-80
-90
1MHz
-100
-110
6
-30
Vs = ±7.5V
G=5
RF = 649 W, RG = 154 W
2nd Order Harmonic Distortion - dBc
3rd Order Harmonic Distortion - dBc
32MHz
-60
8MHz
4MHz
16MHz
0
1
2
3
2MHz
4
5
32MHz
64MHz
RL = 100 W
-50
-60
-70
-80
1MHz
-90
4MHz
2MHz
8MHz
16MHz
-100
-110
6
Vs = ±7.5V, G = 10
RF = 499 W, RG = 54.9 W
-40
0
1
2
3
4
5
Vout - Output Voltage - VPP
Vout - Output Voltage - VPP
Vout - Output Voltage - VPP
Figure 13.
Figure 14.
Figure 15.
3rd ORDER HARMONIC DISTORTION
G = 10
vs
OUTPUT VOLTAGE
3rd ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
S-PARAMETER
vs
FREQUENCY
-40
Vs = ±7.5V
G = 10
RF = 499 W, RG = 54.9 W
-50
RL = 100 W
3rd Order Intermodulation Distortion - dBc
-30
32MHz
64MHz
-60
-70
-80
-90
1MHz
-100
-110
8MHz
4MHz
16MHz
0
6
Figure 12.
RL = 100 W
0
-70
Figure 11.
-30
-50
-60
Figure 10.
Vs = ±7.5V
G=5
RF = 619 W, RG = 154 W
-40
64MHz
32MHz
-110
6
RL = 100 W
-50
Vout - Output Voltage - VPP
-30
2nd Order Harmonic Distortion - dBc
8MHz
Vs = ±7.5V
G=2
RF = 768 W, RG = 768 W
-40
Vout - Output Voltage - VPP
f - Frequency - MHz
3rd Order Harmonic Distortion - dBc
64MHz
1
2
3
2MHz
4
5
6
Vout - Output Voltage - VPP
Figure 16.
0
-40
-50
Vs = ±7.5V
Vout = 2VPP
G10
RF = 499 W, RG = 54.9 W
RL = 100W
-60
-70
-80
G2
RF = 768 W, RG = 768 W
-90
-100
10
-20
S-Parameter - dB
3rd Order Harmonic Distortion - dBc
-65
-30
Vs = ±7.5V
G=2
RF = 768 W, RG = 768 W
3rd Order Harmonic Distortion - dBc
-30
-60
-110
3rd HARMONIC DISTORTION
G=2
vs
OUTPUT VOLTAGE
VS = ±7.5 V
Gain = +10
C = 0 pF
6
S11
S22
-40
S12
-60
RG
RF
C
+
-80
G5
RF = 619 W, RG = 154 W
50 Ω
Source
50 Ω
50 Ω
50 Ω
-100
20
30
40
50
60
70
80
90 100
f - Frequency - MHz
Figure 17.
1M
10 M
100 M
1G
f - Frequency - Hz
Figure 18.
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10 G
11
Not Recommended for New Designs
THS3201
SLOS416C – JUNE 2003 – REVISED JUNE 2009 ............................................................................................................................................................. www.ti.com
VS = ±7.5 V Graphs (continued)
INPUT VOLTAGE AND
CURRENT NOISE
vs
FREQUENCY
S22
S12
-60
S11
RG
RF
C
+
-80
50 Ω
Source
-100
50 Ω
50 Ω
50 Ω
Vn
35
10 M
100 M
1G
f - Frequency - Hz
3.5
Hz
13
3
nV/
40
12
2.5
30
1.5
Inverting
Noise Current
25
0.5
20
0
Noninverting
Current Noise
15
10
100 k
1M
14
4
VS = ±7.5 V and ±5 V
TA = 25°C
45
1M
10 M
f - Frequency - Hz
10 G
100 M
6
0
TRANSIMPEDANCE
vs
FREQUENCY
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
80
60
_
+
V
Gain W +
+
_
1M
10 M
O
I IB
100 M
2.5
2
I IB - Input Bias Currents - µ A
100
10 Ω
7
17
VS = ±7.5 V
VOS - Input Offset Voltage - mV
VS = ±7.5 V
1.5
VS = ±5 V
1
0.5
6
16
IIB-
15
IIB+
3
13
2
12
IOS
1
11
0
0 10 20 30 40 50 60 70 80 90
TC - Case Temperature - °C
TC - Case Temperature - °C
Figure 23.
SLEW RATE
vs
OUTPUT VOLTAGE
Figure 24.
SETTLING TIME
SETTLING TIME
1.5
10000
3
2.5
Rising Edge
9000
1
8000
VO - Output Voltage - V
SR+
7000
6000
SR5000
4000
3000
2000
5
4
14
10
-40 -30 -20 -10
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
1G
0.5
VO - Output Voltage - V
Transimpedance Gain -dB Ω
100 150 200 250 300 350 400
f - Frequency - MHz
Figure 21.
Figure 22.
SR± - Slew Rate - V/ms
50
Figure 20.
f - Frequency - Hz
Gain = -2
RL = 100 Ω
RF = 576 Ω
f= 1 MHz
VS = ±7.5 V
0
-0.5
Falling Edge
Rising Edge
2
1.5
1
0.5
Gain = -2
RL = 100 Ω
RF = 576 Ω
f= 1 MHz
VS = ±7.5 V
0
-0.5
-1
-1.5
-2
-1
Falling Edge
-2.5
1000
0
-3
-1.5
1
2
3
4
5
6
7
8
9
10
Vout - Output Voltage - Vstep
Figure 25.
12
Gain = +10
RG = 28 Ω
RF = 255 Ω
VS = ±7.5 V & ±5 V
7
3
0
100 k
9
8
VS = ±5 and ±7.5V
20
10
Figure 19.
120
40
11
I OS - Input Offset Currents - µ A
-40
50
Noise Figure - dB
S-Parameter - dB
-20
I n - Input Current Noise Density -
VS = ±7.5 V
Gain = +10
C = 3.3 pF
NOISE FIGURE
vs
FREQUENCY
V n - Voltage Noise Density -
0
pA Hz
S-PARAMETER
vs
FREQUENCY
0
2
4
6
8
t - Time - ns
Figure 26.
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10
0
2.5
5
7.5
10
12.5
t - Time - ns
Figure 27.
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
Not Recommended for New Designs
THS3201
www.ti.com ............................................................................................................................................................. SLOS416C – JUNE 2003 – REVISED JUNE 2009
VS = ±7.5 V Graphs (continued)
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
TA = 25°C
14
VO - Output Voltage - V
12
TA = -40°C
10
8
6
4
2
2
1
VS = ±7.5 V
TA = -40 to 85°C
0
-1
-2
2 2.5
-3
-4
-5
10
100
40
PSRR+
30
20
RL - Load Resistance - Ω
NONINVERTING SMALL-SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
10
5
8
Gain = -5
RL = 100 Ω
RF = 549 Ω
VS = ±7.5 V
VO - Output Voltage - V
0
Gain = 2
RL = 100 Ω
RF = 715 Ω
VS = ±7.5 V
-0.1
3
2
Input
-1
-2
-3
-0.3
0
0
-2
-1
-4
-2
-3
-8
-4
-6
-10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-5
0
0.2
0.4
0.6
0.8
1
t - Time - µs
Figure 32.
Figure 33.
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
0.040
Differential Phase -
°
0.015
0.010
1000
Gain = 2
RF = 768 kΩ
VS = ±7.5 V
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
0.035
PAL
NTSC
0.005
0.030
0.025
0.020
PAL
0.015
NTSC
0.010
0.005
0
0
1
1
Figure 31.
Gain = 2
RF = 768 Ω
VS = ±7.5 V
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
0
2
2
t - Time - µs
0.030
0.020
3
4
-6
Output
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
t - Time - µs
0.025
4
-5
-4
-0.2
5
G = 2,
RF = 768 Ω,
VS = ±7.5 V
6
1
0
100 M
OVERDRIVE RECOVERY TIME
6
4
10 M
Figure 30.
VO - Output Voltage - V
Output
0.2
1M
f - Frequency - Hz
Figure 29.
Input
0
100 k
1000
Figure 28.
0.1
CMRR
50
10
3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
VS - Supply Voltage - ±V
0.3
Differential Gain - %
60
-6
-7
0
VO - Output Voltage - V
VS = ±7.5 V
70
Closed-Loop Output Impedance - Ω
Quiescent Current - mA
16
80
7
6
5
4
3
VI - Input Voltage - V
TA = 85°C
18
Rejection Ratios - dB
20
REJECTION RATIO
vs
FREQUENCY
2
3
4
5
6
7
8
Number of Loads - 150 Ω
Figure 34.
100
10
Gain = 2
RF = 715 Ω
RL = 100 Ω
VS = ±7.5 V
1
0.1
0.01
0.001
0
1
2
3
4
5
6
7
Number of Loads - 150 Ω
Figure 35.
8
100 k
1M
10 M
1M
Figure 36.
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1G
f - Frequency - Hz
13
Not Recommended for New Designs
THS3201
SLOS416C – JUNE 2003 – REVISED JUNE 2009 ............................................................................................................................................................. www.ti.com
VS = ±5 V Graphs
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±5 V
G = 2, RF = 715 Ω
G =1, RF = 1.2 kΩ
18
16
14
12
G = -5, RF = 549 Ω
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±5 V
10
8
6
4
2
G = -2, RF = 576 Ω
0
100 k
1M
10 M
100 M
1G
10 G
Figure 38.
Figure 39.
2nd HARMONIC DISTORTION
vs
FREQUENCY
3rd ORDER HARMONIC DISTORTION
vs
FREQUENCY
2nd ORDER HARMONIC DISTORTION
G=2
vs
OUTPUT VOLTAGE
3rd Order Harmonic Distortion - dBc
2nd Order Harmonic Distortion - dBc
Vs = ±5V
Vout = 2VPP
-80
RL = 100 W
-90
G=2
RF = 715 W, RG = 715 W
-65
-70
100 k
10 G
-75
Vs = ±5V
Vout = 2VPP
-80
RL = 100 W
-85
G=5
RF = 576 W, RG = 143 W
-90
G = 10
RF = 464 W, RG = 51.1 W
-95
100
1G
-50
-60
32MHz
10 G
-70
1MHz
-80
2MHz
-90
4MHz
-100
10
100
16MHz
0
1
2
8MHz
3
4
5
Figure 40.
Figure 41.
Figure 42.
3rd ORDER HARMONIC
DISTORTION, G = 2
vs
OUTPUT VOLTAGE
2nd ORDER HARMONIC
DISTORTION, G = 5
vs
OUTPUT VOLTAGE
3rd ORDER HARMONIC
DISTORTION, G = 5
vs
OUTPUT VOLTAGE
-50
RL = 100 W
-60
32MHz
-70
2nd Order Harmonic Distortion - dBc
-30
-40
1MHz
-80
2MHz
4MHz
-90
8MHz
-100
16MHz
1
2
3
4
5
6
-30
Vs = ±5V
G=5
RF = 576 W, RG = 143 W
-40
64MHz
RL = 100 W
-50
32MHz
-60
-70
1MHz
-80
2MHz
-90
16MHz
-100
-110
6
Vout - Output Voltage - VPP
f - Frequency - MHz
64MHz
Vs = ±5V
G=2
RF = 715 W, RG = 715 W
0
1M
Vs = ±5V
64MHz
G=2
RF = 715 W, RG = 715 W
RL = 100 W
-40
-110
1
-30
3rd Order Harmonic Distortion - dBc
1G
G=2
RF = 715 W, RG = 715 W
f - Frequency - MHz
14
100 M
-30
-100
10
1
10 M
-60
-70
-110
5.8
Figure 37.
RG = 143 W
-100
5.9
10 M
100 M
f - Frequency - Hz
G=5
RF = 576 W,
-60
6
f - Frequency - Hz
G = 10
RF = 464 W, RG = 51.1 W
-50
6.1
5.6
100 k 1 M
f - Frequency - Hz
-40
6.2
5.7
G =-1, RF = 576 Ω
-2
-4
Gain = 2,
RF = 715 Ω,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±5 V
6.3
Noninverting Gain - dB
G = 5, RF = 576 Ω
6.4
G = -10, RF = 499 Ω
3rd Order Harmonic Distortion - dBc
8
6
4
2
0
-2
-4
24
22
20
G = 10, RF = 464 Ω
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
2nd Order Harmonic Distortion - dBc
24
22
20
18
16
14
12
10
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Inverting Gain - dB
Noninverting Gain - dB
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
0
1
2
8MHz
4MHz
3
4
5
6
-40
Vs = ±5V
G=5
RF = 576 W, RG = 143 W
-50
RL = 100 W
-60
64MHz
32MHz
-70
1MHz
-80
2MHz
4MHz
-90
8MHz
-100
16MHz
-110
0
1
2
3
4
Vout - Output Voltage - VPP
Vout - Output Voltage - VPP
Vout - Output Voltage - VPP
Figure 43.
Figure 44.
Figure 45.
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5
6
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
Not Recommended for New Designs
THS3201
www.ti.com ............................................................................................................................................................. SLOS416C – JUNE 2003 – REVISED JUNE 2009
VS = ±5 V Graphs (continued)
3rd ORDER HARMONIC
DISTORTION, G = 10
vs
OUTPUT VOLTAGE
64MHz
RL = 100 W
-60
-70
1MHz
-80
2MHz
-90
16MHz
-100
1
2
4MHz
3
4
5
-60
-80
-100
16MHz
-110
4
5
-75
-80
G10
RF = 464 W,
-85
RG = 51.1 W
-90
G5
RF = 576 W,
-95
RG = 143 W
-100
10
6
20
30
40
50
60
80
70
S-PARAMETER
vs
FREQUENCY
SLEW RATE
vs
OUTPUT VOLTAGE
0
RF
+
50 Ω
10 M
100 M
1G
f - Frequency - Hz
-40
6000
5000
S22
S12
-60
S11
RG
RF
C
+
-80
50 Ω
50 Ω
Source
50 Ω
-100
10 G
1M
50 Ω
10 M
100 M
1G
f - Frequency - Hz
NONINVERTING SMALL-SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
0
10 G
1
2
2
VO - Output Voltage - V
1.5
1
Gain = -5
RL = 100 Ω
RF = 549 Ω
VS = ±5 V
Input
-0.5
-1
-1.5
-2
Output
5
Figure 51.
OVERDRIVE RECOVERY TIME
6
0.5
0
4
3
Vout - Output Voltage - Vstep
3
2.5
0.2
Gain = 2
RL = 100 Ω
RF = 715 Ω
VS = ±5 V
SR2000
1000
3
0
3000
50 Ω
Figure 50.
Input
SR+
4000
50 Ω
Figure 49.
Output
90 100
f - Frequency - MHz
VS = ±5 V
Gain = +10
C = 3.3 pF
-20
0.3
VO - Output Voltage - V
3
-65
-70
S-PARAMETER
vs
FREQUENCY
50 Ω
Source
-0.2
2
G2
RF = 715 W, RG = 715 W
Figure 48.
-80
-0.1
1
RL = 100W
Figure 47.
C
0.1
0
-60
Figure 46.
RG
1M
4MHz
8MHz
Vs = ±5V
Vout = 2VPP
Vout - Output Voltage - VPP
S11
-100
2MHz
-90
6
S12
-60
1MHz
-55
Vout - Output Voltage - VPP
S22
-40
32MHz
-70
VS = ±5 V
Gain = +10
C = 0 pF
-20
RL = 100 W
-50
SR± - Slew Rate - V/ms
0
0
8MHz
-50
64MHz
G = 2,
RF = 715 Ω,
VS = ±5 V
4
VO - Output Voltage - V
-50
-40
Vs = ±5V
G = 10
RF = 464 W, RG = 51.1 W
3rd Order Intermodulation Distortion - dBc
3rd Order Harmonic Distortion - dBc
-40
-110
S-Parameter - dB
-30
Vs = ±5V, G = 10
32MHz
RF = 464 W, RG = 51.1 W
S-Parameter - dB
2nd Order Harmonic Distortion - dBc
-30
3rd ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
2
2
1
0
0
-2
-1
-4
-2
VI - Input Voltage - V
2nd ORDER HARMONIC
DISTORTION, G = 10
vs
OUTPUT VOLTAGE
-2.5
-0.3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-6
-3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
t - Time - µs
t - Time -µs
Figure 52.
Figure 53.
0
0.2
0.4
0.6
0.8
t - Time - µs
Figure 54.
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-3
1
15
Not Recommended for New Designs
THS3201
SLOS416C – JUNE 2003 – REVISED JUNE 2009 ............................................................................................................................................................. www.ti.com
APPLICATION INFORMATION
WIDEBAND, NONINVERTING OPERATION
The THS3201 is a unity-gain stable, 1.8-GHz
current-feedback operational amplifier, designed to
operate from a ±3.3-V to ±7.5-V power supply.
Figure 55 shows the THS3201 in a noninverting gain
of 2-V/V configuration typically used to generate the
performance curves. Most of the curves were
characterized using signal sources with 50-Ω source
impedance, and with measurement equipment
presenting a 50-Ω load impedance. The 49.9-Ω shunt
resistor at the VI terminal in Figure 55 matches the
source impedance of the test generator.
7.5 V
+
0.1 µF
±7.5
—
1.2 k
±5
—
1.2 k
±7.5
768
768
1
2
5
±5
715
715
±7.5
154.9
619
±5
143
576
±7.5
54.9
487
±5
51.1
464
±7.5
619
619
±5
576
576
6.8 µF
–2
±7.5 and ±5
287
576
–5
±7.5 and ±5
110
549
–10
±7.5 and ±5
49.9
499
49.9 Ω
THS3201
50 Ω
WIDEBAND, INVERTING GAIN OPERATION
768 Ω
0.1 µF
100 pF
-7.5 V
RF
(Ω)
–1
_
RG
RG
(Ω)
+
RF
768 Ω
Supply Voltage
(V)
10
50 Ω Source
49.9 Ω
THS3201 RF for AC When RLOAD = 100 Ω
Gain
(V/V)
+VS
100 pF
VI
Table 1. Recommended Resistor Values for
Optimum Frequency Response
6.8 µF
+
Figure 56 shows the THS3201 in a typical inverting
gain configuration where the input and output
impedances and signal gain from Figure 55 are
retained in an inverting circuit configuration.
-VS
7.5 V +V
S
Figure 55. Wideband, Noninverting
Gain Configuration
+
100 pF
Unlike voltage-feedback amplifiers, current-feedback
amplifiers are highly dependent on the feedback
resistor RF for maximum performance and stability.
Table 1 shows the optimal gain setting resistors RF
and RG at different gains to give maximum bandwidth
with minimal peaking in the frequency response.
Higher bandwidths can be achieved, at the expense
of added peaking in the frequency response, by using
even lower values for RF. Conversely, increasing RF
decreases the bandwidth, but stability is improved.
+
0.1 µF
6.8 µF
49.9 Ω
THS3201
_
50 Ω Source
VI
50 Ω
RG
RF
287 Ω
RM
60.4 Ω
576 Ω
0.1 µF
100 pF
-7.5 V
6.8 µF
+
-VS
Figure 56. Wideband, Inverting Gain
Configuration
16
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SINGLE-SUPPLY OPERATION
768 Ω
The THS3201 has the capability to operate from a
single supply voltage ranging from 6.6 V to 15 V.
When operating from a single power supply, care
must be taken to ensure the input signal and amplifier
are biased appropriately to allow for the maximum
output voltage swing. The circuits shown in Figure 57
demonstrate methods to configure an amplifier in a
manner conducive for single-supply operation.
768 Ω
±7.5 V
THS3201
VI
75-Ω Transmission Line
+
±7.5 V
75 Ω
n Lines
75 Ω
VO(n)
75 Ω
+VS
75 Ω
50 Ω Source
+
VI
49.9 Ω
RT
VO(1)
75 Ω
49.9 Ω
Figure 58. Video Distribution Amplifier
Application
THS3201
_
50 Ω
+VS
2
ADC DRIVER APPLICATION
RF
RG
768 Ω
+VS
2
768 Ω
The THS3201 can be used as a high-performance
ADC driver in applications like radio receiver IF
stages, and test and measurement devices. All
high-performance ADCs have differential inputs. The
THS3201 can be used in conjunction with a
transformer as a drive amplifier in these applications.
Figure 59 and Figure 60 show two different
approaches.
RF
576 Ω
50 Ω Source
VI
60.4 Ω
+VS
2
VS
RG
_
287 Ω
THS3201
RT
49.9 Ω
+
50 Ω
+VS
2
In Figure 59, a transformer is used after the amplifier
to convert the signal to differential. The advantage of
this approach is fewer components are required.
ROUT and RT are required for impedance matching
the transformer.
Figure 57. DC-Coupled Single-Supply Operation
VS+
0.1 µF
VIDEO HDTV DRIVERS
RG
The exceptional bandwidth and slew rate of the
THS3201 matches the demands for professional
video and HDTV. Most commercial HDTV standards
requires a video passband of 30-MHz. To ensure
high signal quality with minimal degradation of
performance, a 0.1-dB gain flatness should be at
least 7x the passband frequency to minimize group
delay
variations—requiring
210-MHz
0.1-dB
frequency flatness from the amplifier. High slew rates
ensure there is minimal distortion of the video signal.
Component video and RGB video signals require fast
transition times and fast settling times to keep a high
signal quality. The THS8135, for example, is a
240-MSPS video digital-to-analog converter (DAC)
and has a transition time approaching 4 ns. The
THS3201 is a perfect candidate for interfacing the
output of such high-performance video components.
RF
ROUT
THS3201
VIN
1:n
24.9 Ω
RT
47pF
24.9 Ω
ADC
VS-
CM
47pF
0.1 µF
0.1 µF
Figure 59. Differential ADC Driver Circuit 1
In Figure 60, a transformer is used before two
amplifiers to convert the signal to differential. The two
amplifiers then amplify the differential signal. The
advantage to this approach is each amplifier is
required to drive half the voltage as before. RT is
used to impedance match the transformer.
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17
Not Recommended for New Designs
THS3201
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Typically, a low value resistor in the range of 10 Ω to
100 Ω provides the required isolation. Together, the
R and C form a real pole in the s-plane located at the
frequency:
fP + 1
2pRC
VS+
0.1 µF
RG
VIN
RF
THS3201
1:n
24.9 Ω
47pF
ADC
RT
RG
THS3201
24.9 Ω
CM
47pF
RF
VS-
0.1 µF
Placing this pole at about 10x the highest frequency
of interest ensures it has no impact on the signal.
Since the resistor is typically a small value, it is very
bad practice to place the pole at (or very near)
frequencies of interest. At the pole frequency, the
amplifiers sees a load with a magnitude of:
Ǹ2 x R
If R is only 10 Ω, the amplifier is very heavily loaded
above the pole frequency, and generates excessive
distortion.
0.1 µF
Figure 60. Differential ADC Driver Circuit 2
It is almost universally recommended to use a
resistor and capacitor between the op amp output
and the ADC input as shown in both figures.
This resistor-capacitor (RC) combination has multiple
functions:
• The capacitor is a local charge reservoir for ADC
• The resistor isolates the amplifier from the ADC
• In conjunction, they form a low-pass noise filter
During the sampling phase, current is required to
charge the ADC input sampling capacitors. By placing
external capacitors directly at the input pins, most of
the current is drawn from them. They are seen as a
very low impedance source. They can be thought of
as serving much the same purpose as a
power-supply bypass capacitor to supply transient
current, with the amplifier then providing the bulk
charge.
Typically, a low-value capacitor in the range of 10 pF
to 100 pF provides the required transient charge
reservoir.
The capacitance and the switching action of the ADC
is one of the worst loading scenarios that a
high-speed amplifier encounters. The resistor
provides a simple means of isolating the associated
phase shift from the feedback network and
maintaining the phase margin of the amplifier.
DAC DRIVER APPLICATION
The THS3201 can be used as a high-performance
DAC output driver in applications like radio transmitter
stages and arbitrary waveform generators. All
high-performance DACs have differential current
outputs. Two THS3201s can be used as a differential
drive amplifier in these applications, as shown in
Figure 61.
RPU on the DAC output is used to convert the output
current to voltage. The 24.9-Ω resistor and 47-pF
capacitor between each DAC output and the op amp
input is used to reduce the images generated at
multiples of the sampling rate. The values shown
form a pole at 136 MHz. ROUT sets the output
impedance of each amplifier.
VS+
0.1 µF
AVDD
RG
RF
RPU
ROUT
24.9 Ω
THS3201
VOUT1
IOUT1
47pF
24.9 Ω
DAC
ROUT
IOUT2
47pF
RPU
RG
THS3201
VOUT2
RF
AVDD
VS-
0.1 µF
Figure 61. Differential DAC Driver Circuit
18
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Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201
Not Recommended for New Designs
THS3201
www.ti.com ............................................................................................................................................................. SLOS416C – JUNE 2003 – REVISED JUNE 2009
PRINTED CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier-like devices in the THS3201 requires careful
attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any power or
ground plane for the negative input and output
pins by voiding the area directly below these pins
and connecting traces and the feedback path.
Parasitic capacitance on the output and negative
input pins can cause instability. To reduce
unwanted capacitance, a window around the
signal I/O pins should be opened in all of the
ground and power planes around those pins and
the feedback path. Otherwise, ground and power
planes should be unbroken elsewhere on the
board.
• Minimize the distance (
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