THS4011
THS4012
www.ti.com
SLOS216E – JUNE 1999 – REVISED APRIL 2010
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
Check for Samples: THS4011, THS4012
FEATURES
1
7
3
6
4
5
1OUT
1IN −
1IN +
−VCC
NULL
VCC+
OUT
NC
1
8
2
7
3
6
4
5
VCC+
2OUT
2IN−
2IN+
NC − No internal connection
Cross-section view showing
PowerPAD option (DGN)
3
2
1
20 19
NC 4
18 NC
IN− 5
17 VCC+
NC 6
16
NC
IN+ 7
15
OUT
NC 8
14
NC
10 11 12 13
NC
9
NC
The THS4011 and THS4012 are high-speed,
single/dual, voltage feedback amplifiers ideal for a
wide range of applications. The devices offer good ac
performance, with 290-MHz bandwidth, 310-V/ms
slew rate, and 37-ns settling time (0.1%). These
amplifiers have a high output drive capability of 110
mA and draw only 7.8-mA supply current per
channel. For applications requiring low distortion, the
THS4011/4012 operate with a total harmonic
distortion (THD) of -80 dBc at f = 1 MHz. For video
applications, the THS4011/4012 offer 0.1-dB gain
flatness to 70 MHz, 0.006% differential gain error,
and 0.01° differential phase error.
NC
DESCRIPTION
NC
This package is in the Product Preview stage of
development. Please contact your local TI sales of fice for
availability.
THS4011
FK PACKAGE
(TOP VIEW)
NULL
†
NC
•
8
2
NULL
•
•
1
V CC−
•
•
•
NULL
IN −
IN +
VCC−
NC
•
THS4012
D OR DGN† PACKAGE
(TOP VIEW)
THS4011
D, DGN, OR JG PACKAGE
(TOP VIEW)
High Speed
– 290-MHz Bandwidth (G = 1, –3 dB)
– 310-V/ms Slew Rate
– 37-ns Settling Time (0.1%)
Low Distortion
– THD = –80 dBc (f = 1 MHz, RL = 150 Ω)
110-mA Output Current Drive (Typical)
7.5-nV/√Hz Voltage Noise
Excellent Video Performance
– 70-MHz Bandwidth (0.1 dB, G = 1)
– 0.006% Differential Gain Error
– 0.01° Differential Phase Error
±5-V to ±15-V Supply Voltage
Available in Standard SOIC, MSOP
PowerPAD™, JG, or FK Packages
Evaluation Module Available
NC
•
2
RELATED DEVICES
DEVICE
DESCRIPTION
THS4011/4012
290-MHz low-distortion high-speed amplifiers
THS4031/4032
100-MHz low-noise high-speed-amplifiers
THS4061/4062
180-MHz high-speed amplifiers
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2010, Texas Instruments Incorporated
THS4011
THS4012
SLOS216E – JUNE 1999 – REVISED APRIL 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DISTORTION
vs
FREQUENCY
−40
Distortion − dB
−50
VCC = ±15 V
RL = 150 Ω
G=2
−60
2nd Harmonic
−70
−80
−90
3rd Harmonic
−100
−110
100k
1M
10M
f − Frequency − Hz
AVAILABLE OPTIONS
NUMBER OF
CHANNELS
TA
(2)
(3)
2
PLASTIC SMALL
OUTLINE (2) (D)
PLASTIC MSOP (2)
(DGN)
MSOP
SYMBOL
PACKAGED DEVICES
CERAMIC DIP
(JG)
CHIP CARRIER
(FK)
EVALUATION
MODULE
0°C to
70°C
1
THS4011CD
THS4011CDGN
TIACI
—
—
THS4011EVM
2
THS4012CD
THS4012CDGN (3)
TIABY
—
—
THS4012EVM
–40°C to
85°C
1
THS4011ID
THS4011DGN
TIACJ
—
—
—
2
THS4012ID
THS4012IDGN (3)
TIABZ
—
—
—
1
—
—
—
THS4011MJG
THS4011MFK
—
–55°C to
125°C
(1)
PACKAGED DEVICES (1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4011CDGNR).
This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
Submit Documentation Feedback
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
www.ti.com
SLOS216E – JUNE 1999 – REVISED APRIL 2010
FUNCTIONAL BLOCK DIAGRAM
Null
1
2
IN−
8
−
6
OUT
3
IN+
+
Figure 1. THS4011 – Single Channel
VCC
1IN−
2
−
8
1
1IN+
2IN−
3
6
−
7
2IN+
1OUT
+
2OUT
5
+
4
−VCC
Figure 2. THS4012 – Dual Channel
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
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3
THS4011
THS4012
SLOS216E – JUNE 1999 – REVISED APRIL 2010
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VCC
Supply voltage
±16.5
V
VI
Input voltage
±VCC
IO
Output current
VID
Differential input voltage
Continuous total power dissipation
TJ
Maximum junction temperature
TA
Operation free-air temperature range
Tstg
175
mA
±4
V
See Dissipation Rating Table
150
°C
THS401xC
0 to 70
°C
THS401xI
–40 to 85
°C
THS4011M
–55 to 125
°C
–65 to 150
°C
Storage temperature range
DISSIPATION RATINGS
(1)
(2)
PACKAGE
qJA
(°C/W)
qJC
(°C/W)
TA = 25°C
POWER RATING
D
167 (1)
38.3
740 mW
DGN (2)
58.4
4.7
2.14 W
JG
119
28
1050 mW
FK
87.7
20
1375 mW
This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC-proposed High-K test
PCB, the qJA is 95°C/W with a power rating at 1.32 W at TA = 25°C.
This data was taken using 2-oz trace and copper pad that is soldered directly to a 3-in × 3-in PC. For
further information, refer to the Application Information section of this data sheet.
RECOMMENDED OPERATING CONDITIONS
VCC
Supply voltage
TA
Operating free-air temperature
Split supply
Single supply
C suffix
4
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MIN
MAX
±4.5
±16
9
32
0
70
I suffix
–40
85
M suffix
–55
125
UNIT
V
°C
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
www.ti.com
SLOS216E – JUNE 1999 – REVISED APRIL 2010
ELECTRICAL CHARACTERISTICS
VCC = ±15 V, RL = 150 Ω, TA = 25°C (unless otherwise noted)
THS4011C/I
THS4012C/I
TEST CONDITIONS (1)
PARAMETER
UNIT
TYP
DYNAMIC PERFORMANCE
BW
290
VCC = ±5 V
270
VCC = ±15 V
70
VCC = ±5 V
35
VCC = ±15 V, RL = 150 Ω
VO(PP) = 20 V
4.9
MHz
VCC = ±5 V, RL = 150 Ω
VO(PP) = 5 V
16
MHz
VCC = ±15 V
310
VCC = ±5 V
260
VCC = ±15 V
37
VCC = ±5 V
35
VCC = ±15 V
90
VCC = ±5 V
70
Gain = 1
Bandwidth for 0.1-dB flatness
Gain = 1
Full-power bandwidth (2)
SR
VCC = ±15 V
Unity-gain bandwidth (–3 dB)
Slew rate
Gain = –1, RL = 150 Ω
Settling time to 0.1%
VI = –2.5 V to 2.5 V, Gain = –12
Settling time to 0.01%
VI = –2.5 V to 2.5 V, Gain = –12
ts
MHz
MHz
V/ms
ns
ns
NOISE/DISTORTION PERFORMANCE
THD
Total harmonic distortion
VCC = ±15 V, fc = 1 MHz,
VO(PP) = 2 V
–80
dBc
Vn
Input voltage noise
VCC = ±5 V or ±15 V,
f = 10 kHz
7.5
nV/√Hz
In
Input current noise
VCC = ±5 V or ±15 V,
f = 10 kHz
1
pA/√Hz
Differential gain error
Differential phase error
(1)
(2)
. Gain = 2, RL = 150 Ω, NTSC
. Gain = 2, RL = 150 Ω, NTSC
VCC = ±15 V
0.01%
VCC = ±5 V
0.01%
VCC = ±15 V
0.01°
VCC = ±5 V
0.001°
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
Full-power bandwidth = Slew rate/2p VO(peak)
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
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5
THS4011
THS4012
SLOS216E – JUNE 1999 – REVISED APRIL 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
VCC = ±15 V, RL = 150 Ω, TA = 25°C (unless otherwise noted)
THS4011C/I
THS4012C/I
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
10
25
UNIT
MAX
DC PERFORMANCE
VCC = ±15 V, VO = ±10 V, RL = 1 kΩ
Open loop gain
VCC = ±5 V, VO = ±2.5 V, RL = 250 Ω
VIO
Input offset voltage
VCC = ±5 V or ±15 V
TA = 25°C
TA = Full range
8
TA = 25°C
7
TA = Full range
5
TA = 25°C
V/mV
12
1
TA = Full range
6
8
Input offset voltage drift
15
IIB
Input bias current
VCC = ±5 V or ±15 V
IIO
Input offset current
VCC = ±5 V or ±15 V
Offset current drift
VCC = ±5 V or ±15 V
TA = 25°C
2
TA = Full range
6
8
TA = 25°C
25
TA = Full range
250
400
0.3
mV
mV/°C
mA
nA
nA/°C
INPUT CHARACTERISTICS
VICR
Common-mode input voltage
range
VCC = ±15 V
±13
±14.1
VCC = ±5 V
±3.8
±4.3
TA = 25°C
82
110
TA = Full range
77
TA = 25°C
90
TA = Full range
83
VCC = ±15 V, VIC = ±12 V
CMRR
Common-mode rejection ratio
VCC = ±5 V, VIC = ±2.5 V
RI
Input resistance
CI
Input capacitance
V
dB
95
2
MΩ
1.2
pF
OUTPUT CHARACTERISTICS
VCC = ±15 V
VO
Output voltage swing
VCC = ±5 V
RL = 1 kΩ
VCC = ±15 V,
RL = 250 Ω
VCC = ±5 V,
RL = 150 Ω
VCC = ±15 V
IO
Output current
IOS
Short-circuit output current
VCC = ±15 V
RO
Output resistance
Open loop
VCC = ±5 V
RL = 20 Ω
±13
±13.5
±3.4
±3.7
±12
±13
±3
±3.4
70
110
50
75
V
mA
150
mA
12
Ω
POWER SUPPLY
VCC
Supply voltage
Dual supply
Single supply
VCC = ±15 V
ICC
Supply current (each amplifier)
VCC = ±5 V
PSRR
(1)
6
Power-supply rejection ratio
VCC = ±5 V to ±15 V
±4.5
±16.5
9
33
TA = 25°C
7.8
9.5
6.9
8.5
TA = Full range
11
TA = 25°C
TA = Full range
V
mA
10
TA = 25°C
75
TA = Full range
68
83
dB
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
Submit Documentation Feedback
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
www.ti.com
SLOS216E – JUNE 1999 – REVISED APRIL 2010
ELECTRICAL CHARACTERISTICS (Continued)
VCC = ±15 V, RL = 150 Ω, TA = 25°C (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
THS4011M
MIN
TYP
160 (2)
200
UNIT
MAX
DYNAMIC PERFORMANCE
Unit-gain bandwidth
Closed loop, RL = 1 kΩ,
VCC = ±15 V
70
VCC = ±5 V
35
VCC = ±2.5 V
30
VCC = ±15 V, RL = 150 Ω,
VO(PP) = 20 V
2.5
VCC = ±5 V, RL = 150 Ω,
VO(PP) = 20 V
Bandwidth for 0.1-dB flatness Gain = 1
BW
Full-power bandwidth (3)
SR
Slew rate
VCC = ±15 V, RL = 1 kΩ
Settling time to 0.1%
VI = –2.5 to 2.5 V, Gain = –1
ts
Settling time to 0.01%
VCC = ±15 V
VI = –2.5 to 2.5 V, Gain = –1
MHz
8
300(2)
400
VCC = ±15 V
37
VCC = ±5 V
35
VCC = ±15 V
90
VCC = ±5 V
70
V/ms
ns
NOISE/DISTORTION PERFORMANCE
THD
Total harmonic distortion
VCC = ±15 V, fc = 1 MHz, VO(PP) = 1 V
Vn
Input voltage noise
VCC = ±5 V or ±15 V,
f = 10 kHz
In
Input current noise
VCC = ±5 V or ±15 V,
f = 10 kHz
(1)
(2)
(3)
Differential gain error
Gain = 2, RL = 150 Ω, NTSC
Differential phase error
Gain = 2, RL = 150 Ω, NTSC
–80
dBc
7.5
nV/√Hz
1
pA/√Hz
VCC = ±15 V
0.006%
VCC = ±5 V
0.001%
VCC = ±15 V
0.01°
VCC = ±5 V
0.002°
Full range = –55°C to 125°C for the M suffix
This parameter is not tested.
Full-power bandwidth = Slew rate/2p VO(peak)
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
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7
THS4011
THS4012
SLOS216E – JUNE 1999 – REVISED APRIL 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
VCC = ±15 V, RL = 1 kΩ, TA = full range (unless otherwise noted)
THS4011M
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
6
14
5
10
MAX
UNIT
DC PERFORMANCE
Open loop gain
VIO
VCC = ±15 V, VO = ±10 V, RL = 1 kΩ
VCC = ±5 V, VO = ±2.5 V, RL = 1 kΩ
Input offset voltage
VCC = ±5 V or ±15 V
Input offset voltage drift
VCC = ±5 V or ±15 V
IIB
Input bias current
VCC = ±5 V or ±15 V
IIO
Input offset current
VCC = ±5 V or ±15 V
Offset current drift
VCC = ±5 V or ±15 V
TA = Full range
V/mV
TA = 25°C
2
6
TA = Full range
2
8
15
mV/°C
TA = 25°C
2
6
TA = Full range
4
8
25
250
TA = 25°C
mV
0.3
mA
nA
nA/°C
INPUT CHARACTERISTICS
VICR
Common-mode input voltage
range
CMRR
Common-mode rejection ratio
RI
Input resistance
CI
Input capacitance
VCC = ±15 V
±13
±14.1
VCC = ±5 V
±3.8
±4.3
VCC = ±15 V, VIC = ±12 V
75
90
VCC = ±5 V, VIC = ±2.5 V
84
95
V
dB
2
MΩ
1.2
pF
OUTPUT CHARACTERISTICS
VCC = ±15 V
VO
Output voltage swing
VCC = ±5 V
RL = 1 kΩ
±13
±13.5
±3.4
±3.7
VCC = ±15 V,
RL = 250 Ω
±12
±13
VCC = ±5 V,
RL = 150 Ω
±3
±3.4
65
115
40
75
VCC = ±15 V
IO
Output current
IOS
Short-circuit output current
VCC = ±15 V,
RO
Output resistance
Open loop
VCC = ±5 V
RL = 20 Ω
TA = 25°C
V
mA
150
mA
12
Ω
POWER SUPPLY
VCC
Supply voltage
Dual supply
Single supply
VCC = ±15 V
ICC
Quiescent current
VCC = ±5 V
PSRR
(1)
8
Power-supply rejection ratio
VCC = ±5 V to ±15 V
±4.5
±16.5
9
33
TA = 25°C
7.8
9.5
6.9
8.5
TA = Full range
11
TA = 25°C
TA = Full range
V
mA
10
TA = 25°C
80
86
TA = Full range
78
83
dB
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
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Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
www.ti.com
SLOS216E – JUNE 1999 – REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION
1.5 kΩ
1.5 kΩ
1.5 kΩ
_
VI1
1.5 kΩ
_
VO1
+
CH1
VO2
150 Ω
150 Ω
50 Ω
VI2
+
CH2
50 Ω
Figure 3. THS4012 Crosstalk Test Circuit
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
14
3
1.4
1
0.8
0.6
0.4
|VO | − Output Voltage Swing − V
1.2
IIB − Input Bias Current − mA
V IO − Input Offset Voltage − mV
TA = 25° C
VCC = ±15 V or ±5 V
VCC = ±15 V
2.5
2
1.5
1
0.5
0.2
0
−40
OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
−20
0
20
40
80
60
0
−40
100
o
12
RL = 1 kΩ
10
RL = 150 Ω
8
6
4
2
−20
0
20
40
60
80
5
100
7
9
11
TA − Free-Air Temperature − C
Figure 4.
Figure 5.
Figure 6.
MAXIMUM OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
PSRR
vs
FREQUENCY
TA = 25° C
VCC = ± 15 V
RL = 1 kW
13
12.5
VCC = ± 15 V
RL = 250 W
12
4.5
4
V IC
− Input Common-Mode Range − V
Maximum Output Voltage Swing − V
PSRR − Power-Supply Rejection Ratio − dB
15
14
13.5
VCC = ± 5 V
RL = 1 kW
3.5
VCC = ± 5 V
RL = 150 Ω
3
2.5
−40
13
11
9
7
5
3
−20
0
20
40
60
80
5
100
7
9
11
13
15
±VCC − Supply Voltage − V
o
TA − Free-Air Temperature − C
Figure 7.
13
15
±VCC − Supply Voltage − V
o
TA − Free-Air Temperature − C
Figure 8.
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
100
VCC = ±15 V or ±5 V
90
80
70
60
50
40
30
20
10
0
1k
10k
100k
1M
10M
100M
f − Frequency − Hz
Figure 9.
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9
THS4011
THS4012
SLOS216E – JUNE 1999 – REVISED APRIL 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
CROSSTALK
vs
FREQUENCY
100
VCC = ±5 V
VCC = ±15 V
VCC = ±15 V
−10
80
100
80
VCC = ±15 V
60
40
Open-Loop Gain − dB
−20
−30
−40
−50
VI = CH2
VO = CH1
−60
VI = CH1
VO = CH2
−70
60
VCC = ±5 V
40
20
0
20
−80
0
1k
10k
100k
1M
10M
−90
100k
100M
1M
f − Frequency − Hz
100M
−20
1k
1G
100K
10K
1M
10M
Figure 11.
Figure 12.
DISTORTION
vs
FREQUENCY
DISTORTION
vs
FREQUENCY
DISTORTION
vs
FREQUENCY
−40
−50
−60
−70
−80
1G
−40
VCC = ±5 V
RL = 1 kΩ
G=2
−50
Distortion − dB
VCC = ±15 V
RL = 1 kΩ
G=2
100M
f − Frequency − Hz
Figure 10.
Distortion − dB
−50
10M
f − Frequency − Hz
−40
Distortion − dB
OPEN-LOOP GAIN RESPONSE
vs
FREQUENCY
0
120
Crosstalk − dB
CMRR − Common-Mode Rejection Ratio − dB
CMRR
vs
FREQUENCY
−60
−70
2nd Harmonic
−80
VCC = ±15 V
RL = 150 Ω
G=2
−60
2nd Harmonic
−70
−80
2nd Harmonic
−90
−90
−90
3rd Harmonic
−100
3rd Harmonic
−100
−100
3rd Harmonic
−110
100k
1M
−110
100k
10M
f − Frequency − Hz
Figure 15.
DISTORTION
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
5
5
RF = 270 Ω
RF = 270 Ω
−60
2nd Harmonic
−70
−80
3rd Harmonic
−100
1M
RF = 100 Ω
−5
−10
−15
−20
0
10M
f − Frequency − Hz
Figure 16.
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Output Amplitude − dB
0
Output Amplitude − dB
Distortion − dB
10M
Figure 14.
VCC = ±5 V
RL = 150 Ω
G=2
−110
100k
1M
f − Frequency − Hz
Figure 13.
−90
10
−110
100k
10M
f − Frequency − Hz
−40
−50
1M
−25
100k
RF = 100 Ω
−5
−10
−15
VCC = ±15 V
RL = 150 Ω
G=1
1M
0
10M
100M
1G
−20
100k
VCC = ±5 V
RL = 150 Ω
G=1
1M
10M
100M
f − Frequency − Hz
f − Frequency − Hz
Figure 17.
Figure 18.
1G
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
www.ti.com
SLOS216E – JUNE 1999 – REVISED APRIL 2010
TYPICAL CHARACTERISTICS (continued)
NOISE SPECTRAL DENSITY
vs
FREQUENCY
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.35°
100
Gain = 2
VCC = ±15 V
RF = 1 kΩ
40 IRE-NTSC Modulation
Worst-Case ±100 IRE Ramp
Differential Phase
Noise Spectral Density
0.3°
10
0.25°
0.2°
0.15°
VCC = ±5 V
0.1°
0.05°
VCC = ±15 V or ±5 V
1
10
100
1k
10k
0°
100k
1
2
f − Frequency − Hz
Figure 19.
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.05
Gain = 2
RF = 1 kΩ
40 IRE-PAL Modulation
Worst-Case ±100 IRE Ramp
Differential Gain − %
Differential Phase
VCC = ±15 V
0.2°
0.15°
VCC = ±5 V
0.1°
0.06
Gain = 2
RF = 1 kΩ
40 IRE-NTSC Modulation
Worst-Case ±100 IRE Ramp
0.04
0.25°
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
Gain = 2
RF = 1 kΩ
40 IRE-PAL Modulation
Worst-Case ±100 IRE Ramp
0.05
Differential Gain − %
0.4°
0.3°
4
Figure 20.
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.35°
3
Number of 150-Ω Loads
0.03
0.02
VCC = ±15 V
0.04
0.03
VCC = ±15 V
0.02
VCC = ±5 V
0.01
0.01
0.05°
VCC = ±5 V
0
0°
1
2
3
0
1
4
2
3
4
Number of 150-Ω Loads
Number of 150-Ω Loads
Figure 21.
Figure 22.
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1
2
3
4
Number of 150-Ω Loads
Figure 23.
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THS4011
THS4012
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APPLICATION INFORMATION
THEORY OF OPERATION
The THS401x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built using
a 30-V, dielectrically isolated, complementary bipolar process, with NPN and PNP transistors possessing fTs of
several GHz. This results in an exceptionally high-performance amplifier that has a wide bandwidth, high slew
rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 24.
7
VCC +
6
OUT
2
IN −
IN +
3
4
1
VCC −
8
NULL
NULL
Pin numbers are for the D, DGN, and JG packages.
Figure 24. THS4011/4012 Simplified Schematic
Noise Calculations and Noise Figure (NF)
Noise can cause errors on very small signals. This is especially true when amplifying small signals. The noise
model for the THS401x is shown in Figure 25. This model includes all of the noise sources as follows:
• en = Amplifier internal voltage noise (nV/√Hz)
• IN+ = Noninverting current noise (pA/√Hz)
• IN– = Inverting current noise (pA/√Hz)
• eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
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eRs
RS
en
Noiseless
+
_
eni
IN+
eno
eRf
RF
eRg
IN−
RG
Figure 25. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
e
ni
+
Ǹ
ǒenǓ ) ǒIN )
2
R
Ǔ
S
2
ǒ
) IN–
ǒR F ø R G ǓǓ
2
ǒ
) 4 kTRs ) 4 kT R ø R
F
G
Ǔ
Where:
k = Boltzmann's constant = 1.380658 × 10-23
T = Temperature in degrees Kelvin (273 + °C)
RF || RG = Parallel resistance of RF and RG
To get the equivalent output noise density of the amplifier, multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV):
e no + e
ni
A
V
ǒ
+ e ni 1 )
Ǔ
RF
(noninverting case)
RG
As the previous equations show, to keep noise at a minimum, small-value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, refer to the Noise Analysis section in the Operational Amplifier Circuits
Applications Report (SLVA043).
This brings up another noise measurement usually preferred in RF applications — the noise figure (NF). NF is a
measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is
typically 50 Ω in RF applications.
NF +
ȱ e 2ȳ
10logȧ ni ȧ
ȧ 2ȧ
ȲǒeRsǓ ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, approximate NF as:
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THS4012
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NF +
www.ti.com
ȱ ȡǒ Ǔ2 ǒ
ȧ en ) IN )
ȧ
ȧ Ȣ
10logȧ1 )
4 kTR
ȧ
S
ȧ
Ȳ
ȣȳ
Ǔ
S ȧȧ
Ȥȧ
ȧ
ȧ
ȧ
ȴ
2
R
Figure 26 shows the NF graph for the THS401x.
NOISE FIGURE
vs
SOURCE RESISTANCE
30
f = 10 kHz
TA = 25°C
NF − Noise Figure − dB
25
20
15
10
5
0
10 k
100
1k
Source Resistance − Ω
10
100 k
Figure 26. Noise Figure vs Source Resistance
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high performance amplifiers is not a problem, as long as certain precautions are
taken. The first precaution is to note that the THS401x has been internally compensated to maximize its
bandwidth and slew-rate performance. When the amplifier is compensated in this manner, capacitive loading
directly on the output decreases the device phase margin leading to high-frequency ringing or oscillations.
Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with
the output of the amplifier, as shown in Figure 27. A minimum value of 20 Ω should work well for most
applications. For example, in 75-Ω transmission systems, setting the series-resistor value to 75 Ω both isolates
any capacitance loading and provides the proper line-impedance matching at the source end.
1.3 kΩ
1.3 kΩ
Input
_
20 Ω
Output
THS401x
+
CLOAD
Figure 27. Driving a Capacitive Load
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OFFSET NULLING
The THS401x has low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided on the THS4011/4012. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply (see
Figure 28).
VCC+
0.1 µF
+
THS4011/4012
_
10 kΩ
0.1 µF
VCC −
Figure 28. Offset Nulling Schematic
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THS4012
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OFFSET VOLTAGE
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
Figure 29. Output Offset Voltage Model
OPTIMIZING UNITY GAIN RESPONSE
Internal frequency compensation of the THS401x was selected to provide very wideband performance, yet
maintain stability when operating in a noninverting unity gain configuration. When amplifiers are compensated in
this manner, there is usually peaking in the closed-loop response and some ringing in the step response for fast
input edges, depending on the application. This is because a minimum phase margin is maintained for the
G = +1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 100 Ω should be
used (see Figure 30). Additional capacitance can also be used in parallel with the feedback resistance if even
finer optimization is required.
Input
+
THS401x
Output
_
100 Ω
Figure 30. Noninverting Unity Gain Schematic
GENERAL CONFIGURATIONS
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see
Figure 31).
Figure 31. Single-Pole Low-Pass Filter
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If even more attenuation is needed, a multiple-pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
1
2 RC
–3dB
RG =
(
RF
1
2−
Q
)
Figure 32. 2-Pole Low-Pass Sallen-Key Filter
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the high-frequency performance levels of the THS401x, follow proper printed circuit board (PCB)
high-frequency design techniques. A general set of guidelines is given in the following paragraphs. In addition, a
THS401x evaluation board is available to use as a guide for layout or for evaluating the device performance.
• Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power-supply decoupling – Use a 6.8-mF tantalum capacitor in parallel with a 0.1-mF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-mF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-mF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 in between the device power terminals and the ceramic capacitors.
• Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins often leads to stability problems. Surface-mount packages soldered directly to
the PCB are the best implementation.
• Short trace runs/compact part placements – Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This minimizes stray capacitance at the
input of the amplifier.
• Surface-mount passive components – Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
GENERAL PowerPAD™ DESIGN CONSIDERATIONS
The THS401x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 33(a) and Figure 33(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 33(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
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The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE: The thermal pad is electrically isolated from all terminals in the package.
Figure 33. Thermally-Enhanced DGN Package Views
Although there are many ways to properly heatsink this device, the following steps show the recommended
approach:
1. Prepare the PCB with a top-side etch pattern as shown in Figure 34. There should be etch for the leads, as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal-pad area. This helps
dissipate the heat generated by the THS401xDGN IC. These additional vias may be larger than the 13-mils
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal-pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the THS401xDGN package should make their connection to the internal ground plane with a
complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal-pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal-pad area. This
prevents solder from pulling away from the thermal-pad area during the reflow process.
7. Apply solder paste to the exposed thermal-pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS401xDGN IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
Thermal-pad area (68 mils x 70 mils) with 5 vias
(via diameter = 13 mils)
Figure 34. PowerPAD™ PCB Etch and Via Pattern
The actual thermal performance achieved with the THS401xDGN in its PowerPAD package depends on the
application. In the previous example, if the size of the internal ground plane is approximately 3 in × 3 in, the
expected thermal coefficient, qJA, is approximately 58.4°C/W. For comparison, the non-PowerPAD version of the
THS401x IC (SOIC) is shown. For a given qJA, the maximum power dissipation is shown in Figure 35 and is
calculated by the following formula:
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SLOS216E – JUNE 1999 – REVISED APRIL 2010
ǒ
T
P
D
+
* T
MAX
A
q
JA
Ǔ
Where:
PD = Maximum power dissipation of THS401x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Free-ambient air temperature (°C)
qJA = qJC + qCA
qJC = Thermal coefficient from junction to case
qCA = Thermal coefficient from case to ambient air (°C/W)
Maximum Power Dissipation − W
3.5
DGN Package
θJA = 58.4°C/W
2-oz Trace and Copper Pad
With Solder
3
2.5
SOIC Package
High-K Test PCB
θJA = 98°C/W
2
DGN Package
θJA = 158°C/W
2-oz Trace and
Copper Pad
Without Solder
1.5
1
SOIC Package
Low-K Test PCB
θJA = 167°C/W
0.5
0
−40
A.
TJ = 150°C
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
100
Results are with no airflow and PCB size = 3 in × 3 in
Figure 35. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal-management techniques can be found
in the TI technical brief, PowerPAD™ Thermally-Enhanced Package. This document can be found at the TI web
site (www.ti.com) by searching on the keyword PowerPAD. The document can also be ordered through your
local TI sales office. Refer to literature number SLMA002 when ordering.
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multiple amplifier devices. Because these devices have linear output stages (Class A-B), most of the
heat dissipation is at low output voltages with high output currents. Figure 36 to Figure 39 show this effect, along
with the quiescent heat, with an ambient air temperature of 50°C. When using VCC = ±5 V, there is generally not
a heat problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC package is severely limited
in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are
mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should
always be soldered to a copper plane to fully use the heat-dissipation properties of the PowerPAD package. The
SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and
copper area is placed around the device, qJA decreases and the heat dissipation capability increases. The
currents and voltages shown in these graphs are for the total package. For the dual amplifier package
(THS4012), the sum of the RMS output currents and voltages should be used to choose the proper package.
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THS4011
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
1000
Maximum Output
Current Limit Line
VCC = ±5 V
Tj = 150°C
TA = 50°C
| IO |− Maximum RMS Output Current − mA
| IO | − Maximum RMS Output Current − mA
200
THS4011
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
160
140
Package With
θJA < = 120°C/W
120
100
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
80
60
40
Safe Operating
Area
20
0
DGN Package
θJA = 58.4°C/W
Maximum Output
Current Limit Line
100
SO-8 Package
θJA = 98°C/W
High-K Test PCB
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
1
2
3
4
|VO| − RMS Output Voltage − V
0
5
Safe Operating
Area
3
6
9
12
|VO| − RMS Output Voltage − V
Figure 36.
Figure 37.
THS4012
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
THS4012
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
160
140
120
100
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
80
60
Safe Operating Area
40
SO-8 Package
θJA = 98°C/W
High-K Test PCB
20
0
0
VCC = ±5 V
TJ = 150°C
TA = 50°C
Both Channels
1
2
3
4
|VO| − RMS Output Voltage − V
5
VCC = ±15 V
TJ = 150°C
TA = 50°C
Both Channels
Maximum Output
Current Limit Line
100
SO-8 Package
θJA = 98°C/W
High-K Test PCB
10
DGN Package
θJA = 58.4°C/W
Safe Operating Area
1
0
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
3
6
9
12
|VO| − RMS Output Voltage − V
Figure 38.
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15
1000
Maximum Output
Current Limit Line
Package With
θJA ≤ 60°C/W
| IO | − Maximum RMS Output Current − mA
200
20
VCC = ±15 V
10
0
| IO | − Maximum RMS Output Current − mA
TJ = 150°C
TA = 50°C
15
Figure 39.
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SLOS216E – JUNE 1999 – REVISED APRIL 2010
EVALUATION BOARD
An evaluation board is available for the THS4011 (literature number SLOP128) and THS4012 (literature number
SLOP230). This board has been configured for low parasitic capacitance in order to realize the full performance
of the amplifier. A schematic of the THS4011 evaluation board is shown in Figure 40. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. For more
information, refer to the THS4011 EVM User's Guide (literature number SLOU028) or the THS4012 EVM User's
Guide (literature number SLOU041) To order the evaluation board, contact your local TI sales office or
distributor.
VCC+
+
C2
0.1 mF
R1
1 kΩ
IN +
C1
6.8 mF
NULL
R2
49.9 Ω
+
R3
49.9 Ω
OUT
THS4011
_
NULL
R5
1 kΩ
+
C4
0.1 mF
C3
6.8 mF
IN −
VCC −
R4
49.9 Ω
Figure 40. THS4011 Evaluation Board
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THS4012
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REVISION HISTORY
Changes from Original (June 1999) to Revision A
Page
•
Changed Feature List item From: 0.006% Differential Gain Error To: 0.01% Differential Gain Error .................................. 1
•
Replaced the HIGH SPEED FAMILY of DEVICES table with the RELATED DEVICES table ............................................. 1
•
Changed the Available Options table, THS4012ID MSOP Symbol From: TAIBG To: TIABZ .............................................. 2
•
Changed the ELECTRICAL CHARACTERISTIC table ......................................................................................................... 5
•
Changed the TYPICAL CHARACTERISTICS section .......................................................................................................... 9
•
Changed Figure 26, Noise Figure vs Source Resistance ................................................................................................... 14
•
Changed Figure 36 through Figure 39 ............................................................................................................................... 20
•
Changed Figure 40, THS4011 Evaluation Board ............................................................................................................... 21
Changes from Revision A (February 2000) to Revision B
Page
•
Changed Feature List item From: 0.01% Differential Gain Error To: 0.006% Differential Gain Error .................................. 1
•
Added THS4011M to the Abs Max table .............................................................................................................................. 4
•
Added the ELECTRICAL CHARACTERISTICS for device number THS4011M .................................................................. 7
Changes from Revision B (February 2000) to Revision C
•
Page
Changed Figure 24, THS4011/4012 Simplified Schematic ................................................................................................ 12
Changes from Revision C (May 2006) to Revision D
•
Page
Changed Figure 29 - Output Offset Voltage Model docato-extra-info-title Output Offset Voltage Model ........................... 16
Changes from Revision D (June 2007) to Revision E
Page
•
Deleted Lead temperature and Case temperature from the Abs Max table ......................................................................... 4
•
Changed Figure 5 label - From: Input Bias Current - A To: Input Bias Current - µA ........................................................... 9
22
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9959301Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629959301Q2A
THS4011MFKB
5962-9959301QPA
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
9959301QPA
THS4011M
Samples
THS4011CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4011C
Samples
THS4011CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
ACI
Samples
THS4011CDGNG4
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
Level-1-260C-UNLIM
0 to 70
ACI
Samples
THS4011CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
ACI
Samples
THS4011CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4011C
Samples
THS4011ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4011I
Samples
THS4011IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4011I
Samples
THS4011IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
ACJ
Samples
THS4011IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
ACJ
Samples
THS4011MFKB
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629959301Q2A
THS4011MFKB
THS4011MJG
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
THS4011MJG
Samples
THS4011MJGB
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
9959301QPA
THS4011M
Samples
THS4012CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4012C
Samples
THS4012CDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4012C
Samples
THS4012CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ABY
Samples
THS4012CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ABY
Samples
Addendum-Page 1
NIPDAU
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
THS4012CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4012C
Samples
THS4012ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4012I
Samples
THS4012IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABZ
Samples
THS4012IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABZ
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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