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THS4031, THS4032
SLOS224I – JULY 1999 – REVISED MAY 2018
THS403x 100-MHz Low-Noise High-Speed Amplifiers
1 Features
3 Description
•
•
The THS4031 and THS4032 are ultra-low voltage
noise, high-speed voltage feedback amplifiers that
are ideal for applications requiring low voltage noise,
including communications and imaging. The single
amplifier THS4031 and the dual amplifier THS4032
offer good AC performance with 100-MHz bandwidth
(G = 2), 100-V/μs slew rate, and 60-ns settling time
(0.1%). The THS4031 and THS4032 are unity-gain
stable with 275-MHz bandwidth. These amplifiers
have a high drive capability of 90 mA and draw only
8.5-mA supply current per channel. With –90 dBc of
total harmonic distortion (THD) at f = 1 MHz and a
very low noise of 1.6 nV/√Hz, the THS4031 and
THS4032 are designed for applications requiring low
distortion and low noise such as buffering analog-todigital converters.
Ultra-Low 1.6 nV/√Hz Voltage Noise
High Speed:
– 100-MHz Bandwidth [G = 2 (–1), –3 dB]
– 100-V/μs Slew Rate
Very Low Distortion
– THD = –72 dBc (f = 1 MHz, RL = 150 Ω)
– THD = –90 dBc (f = 1 MHz, RL = 1 kΩ)
Low 0.5-mV (Typical) Input Offset Voltage
90-mA Output Current Drive (Typical)
Typical Operation from ±5 V to ±15 V
Available in Standard SOIC and MSOPPowerPAD™, Packages
Evaluation Module Available
1
•
•
•
•
•
•
Device Information(1)
2 Applications
•
PART NUMBER
Low-Noise, Wideband Amplifier for Industrial
Applications
Voltage-Controlled Oscillators
Active Filters
Video Amplifiers
Cable Drivers
•
•
•
•
High-Performance, Low-Noise Driver for 16-Bit
SAR ADCs
THS4031,
THS4032
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
MSOP-PowerPAD (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Voltage Noise and Current Noise vs Frequency
20
49.9 Ÿ
VCC = ± 15 V AND ± 5 V
TA = 25°C
-VCC
1000 Ÿ
3
+VIN
+VCC
49.9 Ÿ
8Vpp
0V
+IN
6
0.1 µF
7
Vincm = 0 V
12 Ÿ
6
THS4031
220 pF
ADS8422
8Vpp
C0G
-VIN
-VCC
-4V
time
4
1000 Ÿ
. V
4.096
0.1 µF
2
3 THS4031
6
0.1 µF
7
1000 Ÿ
-VIN = 8 Vpp with
Vincm = 0 V
12 Ÿ
7
-IN
I n − Current Noise − pA/ Hz
1000 Ÿ
Vn − Voltage Noise − nV/ Hz
2
-VIN = 8 Vpp with
+4 V
0.1 µF
4
4.096 V
10
Vn
+VCC
In
1
10
100
1k
10 k
100 k
f − Frequency − Hz
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THS4031, THS4032
SLOS224I – JULY 1999 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information: THS4031................................. 5
Thermal Information: THS4032................................. 5
Electrical Characteristics: RL = 150 Ω....................... 6
Electrical Characteristics: RL = 1 kΩ......................... 8
Typical Characteristics ............................................ 10
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 19
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagrams ..................................... 20
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 24
9
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application .................................................. 25
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
11.3 General PowerPAD™ Design Considerations...... 29
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support ....................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
33
33
33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (March 2016) to Revision I
Page
•
Deleted Available Options table (POA information) ............................................................................................................... 3
•
Corrected mathematical symbols inside square root symbol of Equation 1......................................................................... 21
Changes from Revision G (March 2010) to Revision H
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Removed obselete JG and FK packages .............................................................................................................................. 1
•
Deleted Lead temperature row for JG package and case temperature row for FK package from Absolute Maximum
Ratings ................................................................................................................................................................................... 4
•
Changed Thermal Information tables ..................................................................................................................................... 5
•
Removed the graphs in the General PowerPAD™ Design Considerations section ........................................................... 29
•
Moved the information in the Related Devices table to the Development Support section ................................................ 32
Changes from Revision F (September 2008) to Revision G
•
Page
Changed units for input voltage noise parameter (full range of TA specifications) from nA/√Hz to nV√Hz .......................... 8
Changes from Revision E (June 2007) to Revision F
Page
•
Deleted bullet point for Stable in Gain of 2 (–1) or greater ................................................................................................... 1
•
Editorial changes to paragraph format ................................................................................................................................. 28
2
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Copyright © 1999–2018, Texas Instruments Incorporated
Product Folder Links: THS4031 THS4032
THS4031, THS4032
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SLOS224I – JULY 1999 – REVISED MAY 2018
5 Pin Configuration and Functions
THS4031 D or DGN Package
8-Pin SOIC or HVSSOP
Top View
NULL
1
8
NULL
IN í
2
7
V CC+
IN +
3
6
OUT
V CCí
4
5
NC
NC - No internal connection
Pin Functions: THS4031
PIN
NAME
NO.
I/O
DESCRIPTION
IN–
2
I
Inverting input
IN+
3
I
Noninverting input
NC
5
—
NULL
1, 8
I
No connection
Voltage offset adjust
OUT
6
O
Output of amplifier
VCC+
7
—
Positive power supply
VCC–
4
—
Negative power supply
THS4032 D or DGN Package
8-Pin SOIC or HVSSOP
Top View
1OUT
1IN −
1IN +
−VCC
1
8
2
7
3
6
4
5
VCC+
2OUT
2IN−
2IN+
Cross-Section View Showing
PowerPAD™ Option (DGN)
Pin Functions: THS4032
PIN
I/O
DESCRIPTION
NAME
NO.
1OUT
1
O
Channel 1 output
1IN–
2
I
Channel 1 inverting input
1IN+
3
I
Channel 1 noninverting input
2IN+
5
I
Channel 2 noninverting input
2IN–
6
I
Channel 2 inverting input
2OUT
7
O
Channel 2 output
VCC+
8
—
Positive power supply
–VCC
4
—
Negative power supply
Copyright © 1999–2018, Texas Instruments Incorporated
Product Folder Links: THS4031 THS4032
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
MIN
Supply voltage, VCC+ to VCC–, VCC
Input voltage, VI
MAX
UNIT
33
V
±VCC
Output current, IO
150
mA
Differential input voltage, VIO
±4
V
See General PowerPAD™ Design
Considerations
Continuous total power dissipation
Operating free-air temperature, TA
C-suffix
0
70
I-suffix
–40
85
M-suffix
–55
125
°C
Maximum junction temperature (any condition), TJ
150
°C
Maximum junction temperature, continuous operation, long term reliability (2)
130
°C
300
°C
150
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device. Does not apply to the JG package or FK package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC+ and VCC– Supply voltage
Dual-supply
Single-supply
C-suffix
TA
4
Operating free-air
temperature
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MIN
NOM
MAX
±4.5
±15
±16
9
30
32
0
25
70
I-suffix
–40
25
85
M-suffix
–55
25
125
UNIT
V
°C
Copyright © 1999–2018, Texas Instruments Incorporated
Product Folder Links: THS4031 THS4032
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SLOS224I – JULY 1999 – REVISED MAY 2018
6.4 Thermal Information: THS4031
THS4031
THERMAL METRIC (1)
D (SOIC)
DGN (HVSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
128.9
61.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
80.9
53.9
°C/W
RθJB
Junction-to-board thermal resistance
69.2
43.2
°C/W
ψJT
Junction-to-top characterization parameter
23.7
3.8
°C/W
ψJB
Junction-to-board characterization parameter
68.8
42.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
14.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: THS4032
THS4032
THERMAL METRIC
(1)
D (SOIC)
DGN (HVSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
121.2
56.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
72.8
48.4
°C/W
RθJB
Junction-to-board thermal resistance
61.4
37.7
°C/W
ψJT
Junction-to-top characterization parameter
18.2
2.5
°C/W
ψJB
Junction-to-board characterization parameter
61
37.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
9.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 1999–2018, Texas Instruments Incorporated
Product Folder Links: THS4031 THS4032
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6.6 Electrical Characteristics: RL = 150 Ω
at TA = 25°C, VCC = ±15 V, and RL = 150 Ω for the THS403xC, THS403xI (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
Small-signal bandwidth (–3
dB)
Bandwidth for 0.1-dB flatness
BW
Full power bandwidth
SR
Slew rate
(2)
(3)
Settling time to 0.1%
tS
Settling time to 0.01%
VCC = ±15 V
Gain = –1 or 2
100
VCC = ±5 V
Gain = –1 or 2
90
VCC = ±15 V
Gain = –1 or 2
50
VCC = ±5 V
Gain = –1 or 2
45
VO(pp) = 20 V
VCC = ±15 V
RL = 1 kΩ
2.3
VO(pp) = 5 V
VCC = ±5 V
RL = 1 kΩ
7.2
VCC = ±15 V
20-V step, gain = –1
100
VCC = ±5 V
5-V step, gain = –1
80
VCC = ±15 V
5-V step, gain = –1
60
VCC = ±5 V
2.5-V step, gain = –1
45
VCC = ±15 V
5-V step, gain = –1
90
VCC = ±5 V
2.5-V step, gain = –1
80
MHz
MHz
MHz
V/µs
ns
ns
NOISE AND DISTORTION PERFORMANCE
THD
Total harmonic distortion
THS4031:
VCC = ±5 V or ±15 V, f = 1
MHz
VO(pp) = 2 V, gain = 2
RL = 150 Ω
–81
RL = 1 kΩ
–96
THS4032:
VCC = ±5 V or ±15 V, f = 1
MHz
VO(pp) = 2 V, gain = 2
RL = 150 Ω
–72
RL = 1 kΩ
–90
Vn
Input voltage noise
VCC = ±5 V or ±15 V, f > 10 kHz
In
Input current noise
VCC = ±5 V or ±15 V, f > 10 kHz
Differential gain error
Differential phase error
Channel-to-channel crosstalk
(THS4032 only)
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
dBc
1.6
nV/√Hz
1.2
pA/√Hz
0.015%
Gain = 2
40 IRE modulation
NTSC and PAL
±100 IRE ramp
0.02%
0.025
0.03
VCC = ±5 V or ±15 V, f = 1 MHZ
–61
°
dBc
DC PERFORMANCE
Open loop gain
(1)
(2)
(3)
6
VCC = ±15 V
RL = 1 kΩ
VO = ±10 V
TA = 25°C
93
TA = Full range
92
VCC = ±5 V
RL = 1 kΩ
VO = ±2.5 V
TA = 25°C
90
TA = Full range
89
98
95
dB
Full range = 0°C to 70°C for THS403xC and –40°C to +85°C for THS403xI suffix.
Full power bandwidth = slew rate / [√2 πVOC(Peak)].
Slew rate is measured from an output level range of 25% to 75%.
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Electrical Characteristics: RL = 150 Ω (continued)
at TA = 25°C, VCC = ±15 V, and RL = 150 Ω for the THS403xC, THS403xI (unless otherwise noted)
PARAMETER
VOS
TEST CONDITIONS
(1)
MIN
TA = 25°C
TYP
MAX
30
250
UNIT
Input offset voltage
VCC = ±5 V or ±15 V
Offset voltage drift
VCC = ±5 V or ±15 V
TA = Full range
2
µV/°C
Input offset current drift
VCC = ±5 V or ±15 V
TA = Full range
0.2
nA/°C
TA = Full range
nA
400
INPUT CHARACTERISTICS
VICR
CMRR
Common-mode input voltage
range
VCC = ±15 V
±13.5
±14
VCC = ±5 V
±3.8
±4
95
VCC = ±15 V
VICR = ±12.V
TA = 25°C
85
TA = Full range
80
VCC = ±5 V
VICR = ±2.5 V
TA = 25°C
90
TA = Full range
85
Common-mode rejection ratio
ri
Input resistance
Ci
Input capacitance
V
dB
100
2
MΩ
1.5
pF
OUTPUT CHARACTERISTICS
VCC = ±15 V
VO
Output voltage swing
Output current
ISC
Short-circuit current
RO
Output resistance
±13.6
±3.4
±3.8
±12
±12.9
VCC = ±5 V, RL = 250 Ω
±3
±3.5
60
90
50
70
VCC = ±5 V
(4)
±13
VCC = ±15 V, RL = 150 Ω
VCC = ±15 V
(4)
IO
VCC = ±5 V
RL = 1 kΩ
RL = 20 Ω
VCC = ±15 V
Open loop
V
mA
150
mA
13
Ω
POWER SUPPLY
VCC
Supply voltage operating
range
ICC
Supply current (each
amplifier)
Dual supply
Single supply
VCC = ±15 V
VCC = ±5 V
PSRR
(4)
Power-supply rejection ratio
VCC = ±5 V or ±15 V
±4.5
±16.5
9
33
TA = 25°C
8.5
TA = Full range
10
11
TA = 25°C
7.5
TA = Full range
V
9
mA
10.5
TA = 25°C
85
TA = Full range
80
95
dB
Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily
loaded or shorted. See the Absolute Maximum Ratings in this data sheet for more information.
Copyright © 1999–2018, Texas Instruments Incorporated
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6.7 Electrical Characteristics: RL = 1 kΩ
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
100 (2)
120
MAX
UNIT
DYNAMIC PERFORMANCE
VCC = ±15 V, closed loop
RL = 1 kΩ
Unity-gain bandwidth
Small-signal bandwidth
(–3 dB)
BW
Bandwidth for 0.1-dB flatness
Full power bandwidth
SR
(3)
Slew rate
Settling time to 0.1%
tS
Settling time to 0.01%
VCC = ±15 V
Gain = –1 or 2
100
VCC = ±5 V
Gain = –1 or 2
90
VCC = ±15 V
Gain = –1 or 2
50
VCC = ±5 V
Gain = –1 or 2
45
VO(pp) = 20 V
VCC = ±15 V
RL = 1 kΩ
2.3
VO(pp) = 5 V
VCC = ±5 V
RL = 1 kΩ
7.1
MHz
MHz
MHz
MHz
80 (2)
VCC = ±15 V RL = 1 kΩ
100
VCC = ±15 V
5-V step, gain = –1
60
VCC = ±5 V
2.5-V step, gain = –1
45
VCC = ±15 V
5-V step, gain = –1
90
VCC = ±5 V
2.5-V step, gain = –1
80
V/µs
ns
ns
NOISE AND DISTORTION PERFORMANCE
THD
Total harmonic distortion
VCC = ±5 V or ±15 V
f = 1 MHz, gain = 2
VO(pp) = 2 V
TA = 25°C
Vn
Input voltage noise
VCC = ±5 V or ±15 V
TA = 25°C
f > 10 kHz, RL = 150 Ω
1.6
nV/√Hz
In
Input current noise
VCC = ±5 V or ±15 V
TA = 25°C, f > 10 kHz, RL = 150 Ω
1.2
pA/√Hz
Differential gain error
Differential phase error
Gain = 2, 40 IRE modulation,
TA = 25°C, NTSC and PAL,
±100 IRE ramp, RL = 150 Ω
RL = 150 Ω
–81
RL = 1 kΩ
dBc
96
VCC = ±5 V
0.015%
VCC = ±15 V
0.02%
VCC = ±5 V
0.025
VCC = ±15 V
0.03
°
DC PERFORMANCE
VCC = ±15 V, RL = 1 kΩ, VO =
±10 V
TA = 25°C
93
TA = Full range
92
VCC = ±15 V, RL = 1 kΩ, VO =
±2.5 V
TA = 25°C
92
TA = Full range
91
Open loop gain
VOS
Input offset voltage
VCC =±5 V or ±15 V
IIB
Input bias current
VCC = ±5 V or ±15 V
(1)
(2)
(3)
8
TA = 25°C
98
dB
95
0.5
TA = Full range
2
3
TA = 25°C
3
TA = Full range
6
8
mV
µA
Full range = 0°C to 70°C for THS403xC and –40°C to +85°C for THS403xI suffix.
This parameter is not tested.
Full power bandwidth = slew rate / [√2 πVOC(Peak)].
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SLOS224I – JULY 1999 – REVISED MAY 2018
Electrical Characteristics: RL = 1 kΩ (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
IOS
TEST CONDITIONS
(1)
MIN
TA = 25°C
TYP
MAX
30
250
UNIT
Input offset current
VCC = ±5 V or ±15 V
Offset voltage drift
VCC = ±5 V or ±15 V, TA = full range
2
µV/°C
Input offset current drift
VCC = ±5 V or ±15 V, TA = full range
0.2
nA/°C
TA = Full range
nA
400
INPUT CHARACTERISTICS
VICR
Common-mode input voltage
range
VCC = ±15 V
±13.5
±14.3
VCC = ±5 V
±3.8
±4.3
TA = 25°C
85
95
TA = Full range
80
TA = 25°C
90
TA = Full range
85
VCC = ±15 V, VICR = ±12 V
CMRR Common-mode rejection ratio
VCC = ±5 V, VICR = ±2.5 V
ri
Input resistance
Cd
Input capacitance
V
dB
100
2
MΩ
1.5
pF
OUTPUT CHARACTERISTICS
VO
Output voltage swing
(4)
IO
Output current
ISC
Short-circuit current
RO
Output resistance
(4)
VCC = ±15 V, RL = 1 kΩ
±13
VCC = ±5 V, RL = 1 kΩ
±3.4
±3.8
VCC = ±15 V, RL = 150 Ω
±12
±12.9
VCC = ±5 V, RL = 250 Ω
±3
±3.5
VCC = ±15 V, RL = 20 Ω
60
90
VCC = ±5 V, RL = 20 Ω
50
70
VCC = ±15 V
Open loop
±13.6
V
mA
150
mA
13
Ω
POWER SUPPLY
VCC
Supply voltage operating range
Dual supply
Single supply
VCC = ±15 V
ICC
Supply current (each amplifier)
VCC = ±5 V
PSRR Power supply rejection ratio
(4)
VCC = ±5 V or ±15 V
±4.5
±16.5
9
33
TA = 25°C
8.5
TA = Full range
10
11
TA = 25°C
7.5
TA = Full range
V
9
mA
10
TA = 25°C
85
TA = Full range
80
95
dB
Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily
loaded or shorted. See the Absolute Maximum Ratings in this data sheet for more information.
Copyright © 1999–2018, Texas Instruments Incorporated
Product Folder Links: THS4031 THS4032
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6.8 Typical Characteristics
Table 1. Table of Graphs
FIGURE
Figure 1,
Figure 2
Input Offset Voltage Distribution
Input Offset Voltage
vs Free-Air Temperature
Figure 3
Input Bias Current
vs Free-Air Temperature
Figure 4
Output Voltage Swing
vs Supply Voltage
Figure 5
Maximum Output Voltage Swing
vs Free-Air Temperature
Figure 6
Maximum Output Current
vs Free-Air Temperature
Figure 7
Supply Current
vs Free-Air Temperature
Figure 8
Common-Mode Input Voltage
vs Supply Voltage
Figure 9
Closed-Loop Output Impedance
vs Frequency
Figure 10
Open-Loop Gain and Phase Response
vs Frequency
Figure 11
Power-Supply Rejection Ratio
vs Frequency
Figure 12
Common-Mode Rejection Ratio
vs Frequency
Figure 13
Crosstalk
vs Frequency
Figure 14
Harmonic Distortion
vs Frequency
Figure 15,
Figure 16
Harmonic Distortion
vs Peak-to-Peak Output Voltage
Figure 17,
Figure 18
Slew Rate
vs Free-Air Temperature
Figure 19
0.1% Settling Time
vs Output Voltage Step Size
Figure 20
Small-Signal Frequency Response with Varying Feedback Resistance
Gain = 1, VCC = ±15 V, RL = 1 kΩ
Figure 21
Frequency Response with Varying Output Voltage Swing
Gain = 1, VCC = ±15 V, RL = 1 kΩ
Figure 22
Small-Signal Frequency Response with Varying Feedback Resistance
Gain = 1, VCC = ±15 V, RL = 150 kΩ
Figure 23
Frequency Response with Varying Output Voltage Swing
Gain = 1, VCC = ±15 V, RL = 150 kΩ
Figure 24
Small-Signal Frequency Response with Varying Feedback Resistance
Gain = 1, VCC = ±5 V, RL = 1 kΩ
Figure 25
Frequency Response with Varying Output Voltage Swing
Gain = 1, VCC = ±5 V, RL = 1 kΩ
Figure 26
Small-Signal Frequency Response with Varying Feedback Resistance
Gain = 1, VCC = ±5 V, RL = 150 kΩ
Figure 27
Frequency Response with Varying Output Voltage Swing
Gain = 1, VCC = ±5 V, RL = 150 kΩ
Figure 28
Small-Signal Frequency Response with Varying Feedback Resistance
Gain = 2, VCC = ±5 V, RL = 150 kΩ
Figure 29
Small-Signal Frequency Response with Varying Feedback Resistance
Gain = 2, VCC = ±5 V, RL = 150 kΩ
Figure 30
Small-Signal Frequency Response with Varying Feedback Resistance
Gain = –1, VCC = ±15 V, RL = 150 kΩ
Figure 31
Frequency Response with Varying Output Voltage Swing
Gain = –1, VCC = ±5 V, RL = 150 kΩ
Figure 32
Small-Signal Frequency Response
Gain = 5, VCC = ±15 V, ±5 V
Figure 33
Output Amplitude
vs Frequency, Gain = 2, VS = ±15 V
Figure 34
Output Amplitude
vs Frequency, Gain = 2, VS = ±5 V
Figure 35
Output Amplitude
vs Frequency, Gain = –1, VS = ±15 V
Figure 36
Output Amplitude
vs Frequency, Gain = –1, VS = ±5 V
Figure 37
Differential Phase
vs Number of 150-Ω Loads
Figure 38,
Figure 39
Differential Gain
vs Number of 150-Ω Loads
Figure 40,
Figure 41
1-V Step Response
vs Time
Figure 42,
Figure 43
4-V Step Response
vs Time
Figure 44
20-V Step Response
vs Time
Figure 45
10
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6.9 Typical Characteristics
14
10
8
6
4
2
17.5
15
12.5
10
7.5
5
2.5
0
0
−2
0.4
0.8
−1.6 −1.2 −0.8 −0.4
0
VIO − Input Offset Voltage − mV
1.2
−2
Figure 1. Input Offset Voltage Distribution
−1.6 −1.2 −0.8 −0.4
0
0.4
VIO − Input Offset Voltage − mV
0.8
1.2
Figure 2. Input Offset Voltage Distribution
−0.3
3.10
3.05
−0.35
I IB − Input Bias Current − µ A
V IO − Input Offset Voltage − mV
250 Samples
3 Wafer Lots
TA = 25°C
VCC = ± 5 V
20
Percentage of Amplifiers − %
12
Percentage of Amplifiers − %
22.5
250 Samples
3 Wafer Lots
TA = 25°C
VCC = ± 15 V
VCC = ± 5 V
−0.4
−0.45
VCC = ± 15 V
−0.5
VCC = ± 15 V
3
2.95
2.90
2.85
VCC = ± 5 V
2.80
−0.55
2.75
−0.6
−40
−20
60
0
20
40
80
TA − Free-Air Temperature − °C
2.70
−40
100
Figure 3. Input Offset Voltage vs Free-Air Temperature
0
20
40
60
80
TA − Free-Air Temperature − °C
100
Figure 4. Input Bias Current vs Free-Air Temperature
14
VOM − Maximum Output Voltage Swing − ± V
14
TA = 25°C
|VO | – Output Voltage Swing – ± V
−20
12
RL = 1 KΩ
10
RL = 150 Ω
8
6
4
2
5
13
7
9
11
± VCC – Supply Voltage – ± V
15
Figure 5. Output Voltage Swing vs Supply Voltage
VCC = ± 15 V
RL = 1 kΩ
13.5
13
VCC = ± 15 V
RL = 250 Ω
12.5
12
4.5
VCC = ± 5 V
RL = 1 kΩ
4
3.5
VCC = ± 5 V
RL = 150 Ω
3
2.5
−40
−20
60
80
0
20
40
TA − Free-Air Temperature − °C
100
Figure 6. Maximum Output Voltage Swing vs Free-Air
Temperature
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Typical Characteristics (continued)
11
110
Each Amplifier
VCC = ± 15 V
Source Current
100
10
I CC − Supply Current − mA
I O − Maximum Output Current − mA
RL = 20 Ω
90
VCC = ± 15 V
Sink Current
VCC = ± 5 V
Sink Current
80
VCC = ± 5 V
Source Current
70
50
−40
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
−20
100
100
Z O− Closed-Loop Output Impedance − Ω
TA = 25°C
13
11
9
7
5
3
5
7
9
11
13
± VCC − Supply Voltage − ± V
15
0°
60
−45°
Phase
40
−90°
20
−135°
0
−180°
Phase Response
Gain
−225°
10 M 100 M
1G
PSRR − Power-Supply Rejection Ratio − dB
80
1M
0.1
1 kΩ
VI
+
THS403x
1000
VO
Zo =
−1
VI
50 Ω
(
10 M
1M
)
100 M
500 M
THS4032 − VCC+
100
THS4031 − VCC+
THS4031 − VCC−
80
60
THS4032 − VCC−
40
20
VCC = ± 15 V and ± 5 V
0
10
100
f − Frequency − Hz
1k
10 k
100 k
1M
10 M
100 M
f − Frequency − Hz
Figure 11. Open-Loop Gain and Phase Response
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VO
1 kΩ
−
120
VCC = ± 15 V
RL = 150 Ω
100 k
1
Figure 10. Closed-Loop Output Impedance vs Frequency
45°
10 k
10
f − Frequency − Hz
100
1k
Gain = 1
RF = 1 kΩ
PI = + 3 dBm
0.01
100 k
Figure 9. Common-Mode Input Voltage vs Supply Voltage
12
0
20
60
80
40
TA − Free-Air Temperature − °C
Figure 8. Supply Current vs Free-Air Temperature
15
VIC− Common-Mode Input − ± V
VCC = ± 5 V
7
5
−40
100
Figure 7. Maximum Output Current vs Free-Air Temperature
Open-Loop Gain − dB
VCC = ± 10 V
8
6
60
−20
100
VCC = ± 15 V
9
Figure 12. Power-Supply Rejection Ratio vs Frequency
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Typical Characteristics (continued)
0
VCC = ± 5 V
100
−20
VCC = ± 15 V
80
60
1 kΩ
1 kΩ
40
VO
+
1 kΩ
1 kΩ
100
1k
−40
−50
Input = CH 2
Output = CH 1
−70
RL
150 Ω
10 k
100 k
Input = CH 1
Output = CH 2
−80
0
10
−30
−60
_
VI
20
VCC = ± 15 V
PI = 0 dBm
See Figure 3
−10
Crosstalk − dB
CMRR − Common-Mode Rejection Ratio − dB
120
1M
−90
100 k
10 M 100 M
1M
100 M
10 M
500 M
f − Frequency − Hz
f − Frequency − Hz
Figure 13. Common-Mode Rejection Ratio vs Frequency
Figure 14. THS4032 Crosstalk vs Frequency
−40
−60
THS4031 and THS4032
Third Harmonics
−70
THS4031
Second Harmonic
−80
VCC = ± 15 V and ± 5 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
VO(PP) = 2 V
THS4031
Second Harmonic
−50
Harmonic Distortion − dBc
−50
Harmonic Distortion − dBc
−40
VCC = ± 15 V and ± 5 V
Gain = 2
RF = 300 Ω
RL = 1 kΩ
VO(PP) = 2 V
THS4032
Second Harmonic
−90
−60
THS4032
Second Harmonic
−70
−80
−90
−100
−100
−110
100 k
−110
100 k
THS4031 and THS4032
Third Harmonics
10 M
1M
f − Frequency − Hz
Figure 15. Harmonic Distortion vs Frequency
Figure 16. Harmonic Distortion vs Frequency
−10
−50
THS4031 and THS4032
Third Harmonics
VCC = ± 15 V
Gain = 5
RF = 300 Ω
RL = 150 Ω
f = 1 MHz
−20
−60
−30
Harmonic Distortion − dBc
Harmonic Distortion − dBc
10 M
1M
f − Frequency − Hz
THS4032
Second Harmonic
−70
−80
THS4031
Second Harmonic
−90
VCC = ± 15 V
Gain = 5
RF = 300 Ω
RL = 1 kΩ
f = 1 MHz
−100
−40
−50
THS4032
Second Harmonic
−60
−70
−80
THS4031
Second Harmonic
−90
THS4031 and THS4032
Third Harmonics
−100
−110
−110
0
2
4
6
8
10 12 14 16 18
VO(PP) − Peak-to-Peak Output Voltage − V
20
Figure 17. Harmonic Distortion vs Peak-to-Peak Output
Voltage
0
2
4
6
8
10 12 14 16 18
VO(PP) − Peak-to-Peak Output Voltage − V
20
Figure 18. Harmonic Distortion vs Peak-to-Peak Output
Voltage
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Typical Characteristics (continued)
80
120
Gain = −1
RL = 150 Ω
t s − 0.1% Settling Time − ns
SR − Slew Rate − V/ µ s
Vcc = ± 15 V
Step = 20 V
100
90
80
Vcc = ± 5 V
Step = 4 V
70
60
0
20
40
60
80
TA − Free-Air Temperature − °C
40
VCC = ± 15 V
30
20
VCC = ±15 V,
RL = 150 W,
−1
3
RF = 100 W
RF = 50 W
−2
RF = 0 W
−3
−4
−5
2
1
VCC = +15 V,
RL = 1 kW,
Gain = 1,
RF = 0 W
−7
100 k
1M
10 M
100 M
VO = 0.4 V(PP)
VO = 0.8 V(PP)
−2
VO = 1.6 V(PP)
−3
−4
−6
100 k
500 M
1M
−1
3
RF = 200 W
VO(PP) = 200 mV,
Gain = 1
RF = 100 W
RF = 50 W
−2
RF = 0 W
−3
−4
−5
2
1
VCC = +15 V,
RL = 150 W,
Gain = 1,
RF = 0 W
500 M
VO = 0.1 V(PP)
0
−1
−2
VO = 0.2 V(PP)
−3
VO = 0.4 V(PP)
−4
−6
−5
−7
100 k
−6
100 k
VO = 0.8 V(PP)
VO = 1.6 V(PP)
1M
10 M
100 M
500 M
1M
Figure 23. Small Signal Frequency Response With Varying
Feedback Resistance
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10 M
100 M
500 M
f − Frequency − Hz
f − Frequency − Hz
14
100 M
Figure 22. Frequency Response With Varying Output
Voltage Swing
Output Amplitude (Large Signal) − dB
Output Amplitude − dB
VCC = ±15 V,
RL = 150 W,
10 M
f − Frequency − Hz
Figure 21. Small Signal Frequency Response With Varying
Feedback Resistance
0
VO = 0.2 V(PP)
0
−1
f − Frequency − Hz
1
VO = 0.1 V(PP)
−5
−6
2
5
Figure 20. 0.1% Settling Time vs Output Voltage Step Size
RF = 200 W
VO(PP) = 200 mV,
Gain = 1
4
2
3
VO − Output Voltage Step Size − V
1
100
Output Amplitude (Large Signal) − dB
Output Amplitude − dB
0
VCC = ± 5 V
50
0
−20
Figure 19. Slew Rate vs Free-Air temperature
1
60
10
50
−40
2
Gain = −1
RF = 430 Ω
70
110
Figure 24. Frequency Response With Varying Output
Voltage Swing
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Typical Characteristics (continued)
3
RL = 1 kW,
VO(PP) = 200 mV
Gain = 1
RF = 200 W
Output Amplitude (Large Signal) − dB
VCC = ±5 V,
RF = 100 W
RF = 50 W
RF = 0 W
VCC = 5 V,
RL = 1 kW,
Gain = 1,
RF = 0 W
2
1
VO = 0.1 V(PP)
0
−1
VO = 0.2 V(PP)
−2
VO = 0.4 V(PP)
−3
VO = 0.8 V(PP)
−4
−5
VO = 1.6 V(PP)
−6
100 k
1M
10 M
100 M
500 M
f − Frequency − Hz
Figure 25. Small Signal Frequency Response With Varying
Feedback Resistance
Figure 26. Frequency Response With Varying Output
Voltage Swing
3
VCC = ±5 V,
RF = 200 W
Output Amplitude (Large Signal) − dB
RL = 150 W,
VO(PP) = 200 mV
Gain = 1
RF = 100 W
RF = 50 W
RF = 0 W
2
1
VCC = 5 V,
RL = 150 W,
Gain = 1,
RF = 0 W
VO = 0.1 V(PP)
0
−1
VO = 0.2 V(PP)
−2
VO = 0.4 V(PP)
−3
VO = 0.8 V(PP)
−4
VO = 1.6 V(PP)
−5
−6
100 k
1M
10 M
100 M
500 M
f − Frequency − Hz
Figure 27. Small Signal Frequency Response With Varying
Feedback Resistance
Figure 28. Frequency Response With Varying Output
Voltage Swing
8
R F = 1 kW
Output Amplitude − dB
7
RF = 300 W
RF = 100 W
VCC = ±15 V
Gain = 2
RL = 150 W
VO(PP) = 0.4 V
RF = 1 kΩ
6
5
RF = 300 Ω
RF = 100 Ω
4
3
2
1
0
VCC = ± 5 V
Gain = 2
RL = 150 Ω
VO(PP) = 0.4 V
−1
100 k
1M
10 M
100 M
500 M
f − Frequency − Hz
Figure 29. Small-Signal Frequency Response With Varying
Feedback Resistance
Figure 30. Small-Signal Frequency Response With Varying
Feedback Resistance
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Typical Characteristics (continued)
2
2
1
RF = 1 kΩ
0
−1
Output Amplitude − dB
Output Amplitude − dB
1
RF = 360 Ω
RF = 100 Ω
−2
−3
−4
−5
−6
VCC = ± 15 V
Gain = −1
RL = 150 Ω
VO(PP) = 0.4 V
−7
100 k
−1
100 M
RF = 100 Ω
−3
−4
−6
10 M
RF = 360 Ω
−2
−5
1M
RF = 1 kΩ
0
VCC = ± 5 V
Gain = −1
RL = 150 Ω
VO(PP) = 0.4 V
−7
100 k
500 M
1M
100 M
500 M
f − Frequency − Hz
Figure 31. Small-Signal Frequency Response With Varying
Feedback Resistance
Figure 32. Small-Signal Frequency Response With Varying
Feedback Resistance
16
3
VCC = ± 15 V
VCC = ± 5 V
8
6
4
2
0
100 k
Gain = 5
RF = 3.9 kΩ
RL = 150 Ω
VO(PP) = 0.4 V
−3
VI = 0.25 V RMS
−6
−9
VI = 125 mV RMS
−12
−15
VI = 62.5 mV RMS
−18
−21
1M
100 M
10 M
−24
100 k
500 M
1M
10 M
100 M
500 M
f − Frequency − Hz
f − Frequency − Hz
Figure 33. Small-Signal Frequency Response
Figure 34. Output Amplitude vs Frequency
3
0
VO − Output Voltage Level − dBv
VO − Output Voltage Level − dBV
10
−3
−6
−3
VCC = 5 V
Gain = 2
RF = 300 W
RL = 150 W
VI = 0.5 V RMS
VI = 0.25 V RMS
−9
−12
VI = 125 mV RMS
−15
VI = 62.5 mV RMS
−18
−21
−24
100 k
VCC = ± 15 V
Gain = −1
RF = 430 Ω
RL = 150 Ω
VI = 0.5 V RMS
−6
VO − Output Voltage Level − dBV
Output Amplitude − dB
12
VCC = ± 15 V
Gain = 2
RF = 300 Ω
RL= 150 Ω
VI = 0.5 V RMS
0
14
16
10 M
f − Frequency − Hz
−9
VI = 0.25 V RMS
−12
−15
VI = 125 mV RMS
18
−21
VI = 62.5 mV RMS
−24
−27
1M
10 M
100 M
500 M
−30
100 k
1M
10 M
100 M
500 M
f − Frequency − Hz
f − Frequency − Hz
Figure 35. Output Amplitude vs Frequency
Figure 36. Output Amplitude vs Frequency
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Typical Characteristics (continued)
−3
−9
Gain = 2
RF = 680 Ω
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
−15
VI = 125 mV RMS
18
−21
VI = 62.5 mV RMS
−24
VCC = ± 5 V
0.15°
VI = 0.25 V RMS
−12
Differential Phase
VO − Output Voltage Level − dBV
−6
0.2°
VCC = ± 5 V
Gain = −1
RF = 430 Ω
RL = 150 Ω
VI = 0.5 V RMS
0.1°
VCC = ± 15 V
0.05°
−27
−30
100 k
1M
100 M
10 M
0°
500 M
1
2
3
Number of 150-Ω Loads
f − Frequency − Hz
Figure 37. Output Amplitude vs Frequency
Figure 38. Differential Phase vs Number of 150-Ω Loads
0.25°
0.025°
0.15°
Gain = 2
RF = 680 Ω
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
VCC = ± 5 V
Differential Gain − %
Gain = 2
RF = 680 Ω
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
0.2°
Differential Phase
4
VCC = ± 15 V
0.1°
0.02°
VCC = ± 5 V
VCC = ± 15 V
0.015°
0.05°
0°
0.01°
1
2
3
Number of 150-Ω Loads
4
Figure 39. Differential Phase vs Number of 150-Ω Loads
1
4
Figure 40. Differential Gain vs Number of 150-Ω Loads
0.6
0.03
Gain = 2
RF = 680 Ω
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
0.4
VO − Output Voltage − V
0.025
Differential Gain − %
3
2
Number of 150-Ω Loads
VCC = ± 5 V
0.02
VCC = ± 15 V
0.15
VCC = ± 5 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
See Figure 4
0.2
0
−0.2
−0.4
0.01
1
3
2
Number of 150-Ω Loads
4
−0.6
t - Time - 200 ns/div
Figure 41. Differential Gain vs Number of 150-Ω Loads
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Figure 42. 1-V Step Response
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Typical Characteristics (continued)
2.5
0.6
2
1.5
VO − Output Voltage − V
VO − Output Voltage − V
0.4
VCC = ± 15 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
See Figure 4
0.2
0
−0.2
1
0.5
0
−0.5
VCC = ± 5 V
Gain = −1
RF = 430 Ω
RL = 150 Ω
See Figure 5
−1
−1.5
−0.4
−2
−2.5
−0.6
t - Time - 200 ns/div
t - Time - 200 ns/div
Figure 43. 1-V Step Response
Figure 44. 4-V Step Response
15
VO − Output Voltage − V
10
5
RL = 1 kΩ
VCC = ± 15 V
Gain = 2
RF = 330 Ω
See Figure 4
Offset For Clarity
0
−5
RL = 150 Ω
−10
−15
t - Time - 200 ns/div
Figure 45. 20-V Step Response
18
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7 Parameter Measurement Information
330 Ω
330 Ω
330 Ω
_
VI1
330 Ω
_
VO1
+
CH1
VO2
150 Ω
50 Ω
+
VI2
CH2
150 Ω
50 Ω
Figure 46. THS4032 Crosstalk Test Circuit
Rg
Rf
_
VI
VO
+
RL
50 Ω
Figure 47. Step Response Test Circuit
Rg
Rf
VI
50 Ω
_
VO
+
RL
Figure 48. Step Response Test Circuit
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8 Detailed Description
8.1 Overview
The THS403x is a high-speed operational amplifier configured in a voltage feedback architecture. The family is
built using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors that
possess fTs of several GHz. This results in an exceptionally high-performance amplifier that features wide
bandwidth, high slew rate, fast settling time, and low distortion. Figure 49 shows a simplified schematic.
IN-
(7)
VCC+
(6)
OUT
(4)
VCC-
(2)
IN+ (3)
NULL (1)
NULL (8)
Figure 49. THS4031 Simplified Schematic
8.2 Functional Block Diagrams
Null
IN−
IN+
20
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2
3
1
−
8
6
OUT
+
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Functional Block Diagrams (continued)
VCC
2
1IN−
−
8
1
3
1IN+
2IN−
6
−
7
2IN+
5
1OUT
+
2OUT
+
4
−VCC
8.3 Feature Description
8.3.1 Noise Calculations and Noise Figure
Noise can cause errors on small signals. This is especially true when amplifying small signals. The noise model
for the THS403x (shown in Figure 50) includes all of the noise sources as follows:
• en = Amplifier internal voltage noise (nV/√Hz)
• IN+ = Noninverting current noise (pA/√Hz)
• IN– = Inverting current noise (pA/√Hz)
• eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
eRs
RS
en
Noiseless
+
_
eni
IN+
eno
eRf
RF
eRg
IN−
RG
Figure 50. Noise Model
The total equivalent input noise density (eni) is calculated by using Equation 1:
2
e ni
en
2
2
IN
u RS
IN u R F R G
4kTR s
4kT R F R G
where:
•
•
•
k = Boltzmann's constant = 1.380658 × 10–23
T = Temperature in degrees Kelvin (273+°C)
RF || RG = Parallel resistance of RF and RG
(1)
To calculate the equivalent output noise of the amplifier, multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV) in Equation 2.
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Feature Description (continued)
e no
§
e ni ¨ 1
¨
©
e ni A V
RF ·
¸ Noninverting Case
R G ¸¹
(2)
As the previous equations show, to keep noise at a minimum, use resistors with a small value. As the closedloop gain increases (by reducing RG), the input noise is reduced considerably because of the parallel resistance
term. As a result, the general conclusion is that the most dominant noise sources are the source resistor (RS)
and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares method, noise
sources smaller than 25% of the largest noise source can be effectively ignored. This advantage can simplify the
formula and noise calculations.
For more information on noise analysis, see the Noise Analysis for High-Speed Op Amps application note.
8.3.2 Optimizing Frequency Response
Internal frequency compensation of the THS403x was selected to provide very wide bandwidth performance and
still maintain a very low noise floor. To meet these performance requirements, the THS403x must have a
minimum gain of 2 (–1). Because everything is referred to the noninverting pin of an operational amplifier, the
noise gain in a G = –1 configuration is the same as a G = 2 configuration.
One of the keys to maintaining a smooth frequency response, and and as a result, a stable pulse response, is to
pay particular attention to the inverting pin. Any stray capacitance at this node causes peaking in the frequency
response (see Figure 51 and Figure 52). There are two techniques to minimize this effect. The first is to remove
any ground planes under the inverting pin of the amplifier, including the trace that connects to this terminal.
Additionally, the length of this trace must be minimized. The capacitance at this node causes a lag in the voltage
feedback due to the charging and discharging of the stray capacitance. If this lag becomes too long, the amplifier
is unable to correctly keep the noninverting pin voltage at the same potential as the voltage of the inverting pin.
Peaking and possible oscillations can occur if this happens.
10
Output Amplitude − dB
8
7
Ci− = 10 pF
3
2
Output Amplitude − dB
9
4
VCC = ± 15 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
VO(PP) = 0.4 V
6
No Ci−
(Stray C Only)
5
4
3
2
Ci−
300 Ω
300 Ω
VI
1M
VO
+
50 Ω
1
0
100 k
_
VCC = ± 15 V
Gain = −1
RF = 360 Ω
RL = 150 Ω
VO(PP) = 0.4 V
Ci−= 10 pF
1
0
No Ci−
(Stray C Only)
−1
−2
360 Ω
360 Ω
−3
VI
−4
56 W
Ci−
_
VO
+
150 Ω
150 Ω
−5
10 M
100 M
500 M
−6
100 k
1M
f − Frequency − Hz
10 M
100 M
500 M
f − Frequency − Hz
Figure 51. Output Amplitude vs Frequency
Figure 52. Output Amplitude vs Frequency
The second precaution to help maintain a smooth frequency response is to keep the feedback resistor (Rf) and
the gain resistor (Rg) values low. These two resistors are in parallel when looking at the AC small-signal
response. But, as Figure 21 through Figure 32 show, an insufficient value reduces the bandwidth of the amplifier.
Table 2 shows some recommended feedback resistors to use with the THS403x.
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Table 2. Recommended Feedback Resistors
GAIN
Rf FOR VCC = ±15 V AND ±5 V
1
50 Ω
2
300 Ω
–1
360 Ω
5
3.3 kΩ (low stray-c PCB only)
8.3.3 Driving a Capacitive Load
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS403x is internally compensated to maximize the bandwidth and slew-rate
performance. When the amplifier is compensated in this manner, capacitive loading directly on the output
decreases the phase margin of the device, which results in high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, TI recommends placing a resistor in series with the output of the amplifier,
as Figure 53 shows. A minimum value of 20 Ω should work well for most applications. For example, in 75-Ω
transmission systems, setting the series resistor value to 75 Ω isolates any capacitance loading and provides the
proper line impedance matching at the source end.
360 Ω
360 Ω
_
Input
20 Ω
Output
THS403x
+
CLOAD
Figure 53. Driving a Capacitive Load
8.3.4 Offset Voltage
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. Figure 54 shows a schematic and formula that can be used to calculate the output
offset voltage:
Figure 54. Output Offset Voltage Model
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8.3.5 General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting pin of the amplifier (see
Figure 55).
RG
RF
−
VO
+
VI
R1
C1
f
V
O +
V
I
ǒ
R
1)
R
F
G
Ǔǒ
–3dB
+
1
2pR1C1
Ǔ
1
1 ) sR1C1
Figure 55. Single-Pole Low-Pass Filter
If even more attenuation is required, a multiple-pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier must have a bandwidth that is eight to 10 times the filter frequency
bandwidth. Otherwise, phase shift of the amplifier can occur.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG =
RF
RG
–3dB
1
2pRC
+
(
RF
1
Q
2–
)
Figure 56. Two-Pole Low-Pass Sallen-Key Filter
8.4 Device Functional Modes
8.4.1 Offset Nulling
The THS403x has low input offset voltage for a high-speed amplifier. However, if additional correction is
required, the designer can use an offset nulling function provided on the THS4031. By placing a potentiometer
between pins 1 and 8 of the device and tying the wiper to the negative supply, the input offset can be adjusted.
This is shown in Figure 57.
VCC+
0.1 mF
3
7
+
THS4031
2
_
4
8
1 10 k Ω
0.1 mF
VCC −
Figure 57. Offset Nulling Schematic
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This application report is intended as a guide for using an analog multiplexer to multiplex several input signals to
a high-performance driver amplifier which subsequently drives a single high-resolution, high-speed SAR analogto-digital converter (ADC). This example uses the ADS8411 and the TS5A3159 or TS5A3359 as the ADC and
the multiplexer, respectively. This application uses the THS4031 as the operational amplifier.
9.2 Typical Application
As Figure 58 shows, the evaluation system consists of the ADC (ADS8411), a driving operational amplifier
(THS4031), the multiplexer (TS5A3159), an AC source, a DC source, and two driving operational amplifiers (two
THS4031s or a single THS4032) for the sources to make them a low-impedance source, a passive band-pass
filter after the AC source to filter the source noise and distortion.
50
±
OPA1
+
Band-Pass
Filter
50
±
OPA3
+
THS4031
4 Vpp
300 Ÿ
(R1)
20
(R2)
20
ADS8411
16-bit 2 MSPS
THS4031
50
TS5A3159
2V
±
OPA2
+
DC
THS4031
Figure 58. Evaluation Set Up
9.2.1 Design Requirements
Design a multiplexed digitizer system with the dynamic performance as Table 3 lists:
Table 3. Design Specifications
DEVICE SPEED
(MSPS)
INPUT FREQUENCY (kHz)
SNR (dB)
THD (dB)
CROSSTALK (dB)
2
20
> 84
< –90
< –110
2
100
> 84
< –90
< –96
9.2.2 Detailed Design Procedure
The ADS8411 is a 16-bit, 2-MSPS analog-to-digital converter (ADC) with a 4-V reference. The device includes a
16-bit capacitor-based SAR ADC with inherent sample and hold. It has a unipolar single-ended input. The device
offers a 16-bit parallel interface.
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The TS5A3159 is a single-pole, double-throw (SPDT) analog switch that is designed to operate from 1.65 V to
5.5 V. The device offers a low ON state resistance and an excellent ON resistance matching with the breakbefore-make feature to prevent signal distortion during the transfer of a signal from one channel to another. The
device has an excellent total harmonic distortion (THD) performance and consumes low power. The TS5A3359 is
a single-pole, triple-throw (SP3T) version of the same switch.
9.2.2.1 Selection of Multiplexer
Figure 59 shows an equivalent circuit diagram of one of the channels of a multiplexer. CS is the input
capacitance of the channel; CD is the output capacitance of the channel. RON is the resistance of the channel
when the channel is ON. CL and RL are the load capacitance and resistance, respectively. VIN is the input voltage
of the source. RS is the source resistance of the source. VOUT is the output voltage of the multiplexer.
Figure 59. Multiplexer Equivalent Circuit
To improve settling time, the values of RS, RON, CS, CD, and CL must be smaller, and the value of RL must be
large.
For TS5A3159:
• RS = 1 Ω
• CS = CD = 84 pF
Considering
• RS = 50 Ω
• CL = 5 pF
• RL = 10 kΩ
• TRC (time constant) = 8.65 ns
For a 16-bit system, at least 18-bit settling is required. For 18-bit settling, the time required is (18 × ln2) × TRC =
108 ns, which is better than 2 MSPS (500 ns). If the settling time is more than the conversion time of the ADC,
the output of the multiplexer does not settle to the required accuracy which results in harmonic distortion.
One more important parameter of a multiplexer is the ON-state resistance variation with voltage. This also affects
distortion because RON and RL act like a resistor divider circuit and any variation of RON with voltage affects the
output voltage.
9.2.2.2 Signal Source
The input signal source must be a low-noise, low-distortion source with low source resistance. As discussed in
the earlier section, RS must be low to improve settling time. If the source is not a low-noise and low-distortion
source, a passive band-pass filter can be added to improve the signal quality as shown in Figure 58.
9.2.2.3 Driving Amplifier
The driving operational amplifier (OPA3 in Figure 58) in this application must have good slew rate, bandwidth,
low noise, and distortion. The input of the operational amplifier can result in a maximum step of 4 V because of
MUX switching. As a result, even if the signal bandwidth is low, the driving amplifier must settle from 0 V to 4 V
(or 4 V to 0 V) within one ADC sampling frame. When selecting the operational amplifier, one must ensure that
the amplifier settles from 0 V to 4 V (or from 4 V to 0 V) within the ADC sampling time (in this case 500 ns). The
amplifier used for driving the ADC is the THS4031. The operational amplifiers (OPA1, OPA2 in Figure 58) used
before the MUX is for signal conditioning. These operational amplifiers must have low noise and distortion.
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9.2.2.4 Driving Amplifier Bandwidth Restriction
The restriction of bandwidth by an RC filter (after OPA3 in Figure 58) may result in better SNR and THD, but the
restriction makes the operational amplifier difficult to settle within the required accuracy. If the output does not
settle properly, some residual charge of the previous channel remains in the next sampling and appears as a
crosstalk. If the throughput of the ADC is reduced, allowing the output of the operational amplifier to settle
properly, the problem becomes smaller. Therefore, using a larger capacitor slows down the settling of the
operational amplifier output. Within the ADC sampling frame, the operational amplifier output does not settle to
the final level. Figure 60 and Figure 61 show SNR and crosstalk as a function of the filter capacitor.
Figure 62 shows input settling behavior with three different bandwidths. The value of the capacitor changes to
change the bandwidth. As the bandwidth increases, the settling time improves (see Equation 3).
1
Bandwidth @
2pR1C1
(3)
9.2.3 Application Curves
Figure 60. SNR vs Input Bandwidth
Figure 61. Crosstalk vs Input Bandwidth
Figure 62. Input Settings With Different Values of Capacitors
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10 Power Supply Recommendations
The THS4031 can operate off a single supply or with dual supplies if the input CM voltage range (CMIR) contains
the required headroom to either supply rail. Operating from a single supply can have numerous advantages. With
the negative supply at ground, the DC errors due to the –PSRR term are minimized. Supplies must be decoupled
with low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. TI
recommends using a ground plane. In most high-speed devices, removing the ground plane close to device
sensitive pins (such as the inputs) is advisable. An optional supply decoupling capacitor across the two power
supplies (for split-supply operation) improves second harmonic distortion performance.
11 Layout
11.1 Layout Guidelines
In order to achieve the levels of high-frequency performance of the THS403x, it is essential that proper printedcircuit board (PCB) high-frequency design techniques be followed. A general set of guidelines is shown below. In
addition, a THS403x evaluation board is available to use as a guide for layout or for evaluating the performance
of the device.
• Ground planes: TI highly recommends using a ground plane on the board to provide all components with a
low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane
can be removed to minimize the stray capacitance.
• Proper power-supply decoupling: Use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-μF ceramic capacitor must always be used on the supply terminal of every amplifier. In
addition, the 0.1-μF capacitor must be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer must strive
for distances of less than 0.1 inch between the device power pins and the ceramic capacitors.
• Sockets: TI does not recommend sockets for high-speed operational amplifiers. The additional lead
inductance in the socket pins often leads to stability problems. Surface-mount packages soldered directly to
the printed-circuit board is the best implementation.
• Short trace runs andcompact part placements: Optimum high-frequency performance is achieved when stray
series inductance is minimized. To realize this, the circuit layout must be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention must be paid to the inverting input of the
amplifier. The length must be kept as short as possible. This helps minimize stray capacitance at the input of
the amplifier.
• Surface-mount passive components: TI recommends using surface-mount passive components for highfrequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing stray
inductance and capacitance. If leaded components are used, TI recommends that the lead lengths are kept
as short as possible.
11.2 Layout Example
An evaluation board is available for the THS4031 and THS4032. This board is configured for very low parasitic
capacitance to realize the full performance of the amplifier. Figure 63 shows the a schematic of the evaluation
board. The circuitry is designed so that the amplifier can be used in an inverting or noninverting configuration.
For more information, see THS4031 EVM User's Guide or the THS4032 EVM User's Guide. To order the
evaluation board, contact your local TI sales office or distributor.
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Layout Example (continued)
VCC+
+
C3
0.1 µF
R4
301 Ω
IN +
C2
6.8 µF
NULL
R5
49.9 Ω
+
R3
49.9 Ω
OUT
THS4031
_
NULL
R2
301 Ω
+
C4
0.1 µF
C1
6.8 µF
IN −
VCC −
R4
49.9 Ω
Figure 63. THS4031 Evaluation Board
11.3 General PowerPAD™ Design Considerations
The THS403x is available in a thermally-enhanced DGN package, which is a member of the PowerPAD™ family
of packages. This package is constructed using a downset leadframe upon which the die is mounted [see
Figure 64(a) and Figure 64(b)]. This arrangement results in the leadframe exposed as a thermal pad on the
underside of the package [see Figure 64(c)]. Because this thermal pad has direct thermal contact with the die,
excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD™ package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can be soldered
to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be
conducted away from the package into a ground plane or other heat-dissipating device.
The PowerPAD™ package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the heretofore awkward mechanical methods of heat sinking.
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General PowerPAD™ Design Considerations (continued)
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
A.
Bottom View (c)
The thermal pad is electrically isolated from all pins in the package.
Figure 64. Views of Thermally-Enhanced DGN Package
Although there are many ways to properly heat sink this device, the following steps show the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 65. PowerPAD™ PCB Etch and Via Pattern
1. Prepare the PCB with a top-side etch pattern as shown in Figure 65. There must be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes must be 13 mils (0.3302 mm) in diameter. They
are kept small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias can be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS403xDGN device. These additional vias may be larger than the 13mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the THS403xDGN package must connect to the internal ground plane with a complete
connection around the entire circumference of the plated-through hole.
6. The top-side solder mask must leave the pins of the package and the thermal pad area with the five holes
exposed. The bottom-side solder mask must cover the five holes of the thermal pad area, which prevents
solder from pulling away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and to all the device pins.
8. With these preparatory steps in place, the THS403xDGN device is placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
The actual thermal performance achieved with the THS403xDGN in the PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches
(7.62 cm × 7.62 cm), then the expected thermal coefficient, RθJA, is approximately 58.4°C/W. For a given RθJA,
the maximum power dissipation is calculated by Equation 4:
PD
§ TMAX T A
¨
¨ R TJA
©
·
¸
¸
¹
where
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General PowerPAD™ Design Considerations (continued)
•
•
•
•
PD = Maximum power dissipation of THS403x device (watts)
TMAX = Absolute maximum operating junction temperature (125°C)
TA = Free-ambient air temperature (°C)
RθJA = RθJC + RθCA
– RθJC = Thermal coefficient from junction to case
– RθCA = Thermal coefficient from case to ambient air (°C/W)
(4)
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments technical brief PowerPAD™ Thermally-Enhanced Package. This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office (see PowerPAD™ Thermally-Enhanced Package when ordering).
The next thing to be considered is package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer must never forget about the quiescent heat generated within the device,
especially multiamplifier devices. Because these devices have linear output stages (Class A-B), most of the heat
dissipation is at low output voltages with high output currents. When using VCC = ±5 V, heat is generally not a
problem, even with SOIC packages. When using VCC = ±15 V, the SOIC package is severely limited in the
amount of heat the package dissipates. The other key factor is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device must always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, RθJA decreases and the heat dissipation capability increases. For the dual amplifier package (THS4032),
the sum of the RMS output currents and voltages must be used to choose the proper package.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For development support, see these related devices:
• THS4051 70-MHz High-Speed Amplifier
• THS4052 70-MHz High-Speed Amplifier
• THS4081 175-MHz Low Power High-Speed Amplifier
• THS4082 175-MHz Low Power High-Speed Amplifier
• ADS8411 16-Bit, 2 MSPS ADC With P8/P16 Parallel Output, Internal Clock and Internal Reference
• TS5A3159 1-Ω SPDT Analog Switch
• TS5A3359 1-Ω SP3T Analog Switch 5-V/3.3-V Single-Channel 3:1 Multiplexer/Demultiplexer
• THS4031 Single Low-Noise Pre-Amp EVM Module
• THS4032 Dual Low-Noise Pre-Amp EVM Module
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments,Noise Analysis for High-Speed Op Amps
• Texas Instruments,PowerPAD™ Thermally-Enhanced Package
• Texas Instruments,THS4031 EVM User's Guide
• Texas Instruments, THS4032 EVM User's Guide
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
THS4031
Click here
Click here
Click here
Click here
Click here
THS4032
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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THS4031, THS4032
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SLOS224I – JULY 1999 – REVISED MAY 2018
12.6 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1999–2018, Texas Instruments Incorporated
Product Folder Links: THS4031 THS4032
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33
PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THS4031CD
ACTIVE
SOIC
D
8
75
RoHS & Green
THS4031CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
ACM
THS4031CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
ACM
THS4031CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4031C
THS4031ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4031I
THS4031IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4031I
THS4031IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
ACN
THS4031IDGNG4
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
Level-1-260C-UNLIM
ACN
THS4031IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
ACN
THS4031IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4031I
THS4032CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4032C
THS4032CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
ABD
THS4032CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4032C
THS4032ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4032I
THS4032IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4032I
THS4032IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
ABG
THS4032IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
ABG
THS4032IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
Level-1-260C-UNLIM
-40 to 85
4032I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
0 to 70
4031C
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2021
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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