SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
7
3
6
4
5
1
8
2
7
3
6
4
5
VCC+
2OUT
2IN−
2IN+
NC − No internal connection
Cross-Section View Showing
PowerPAD Option (DGN)
VI
3
2
1
20 19
NC
NULL
THS4061
FK PACKAGE
(TOP VIEW)
description
NC
4
18 NC
IN−
5
17 VCC+
NC
6
16 NC
IN+
7
15 OUT
NC
8
14 NC
9
10 11 12 13
+
NC
The THS4061 and THS4062 are generalpurpose, single/dual, high-speed voltage feedback amplifiers ideal for a wide range of
applications including video, communication, and
imaging. The devices offer very good ac
performance with 180-MHz bandwidth, 400-V/µs
slew rate, and 40-ns settling time (0.1% ). The
THS4061/2 are stable at all gains for both
inverting and noninverting configurations. These
amplifiers have a high output drive capability of
115 mA and draw only 7.8 mA supply current per
channel. Excellent professional video results can
be obtained with the low differential gain/phase
errors of 0.02%/0.02° and wide 0.1 db flatness to
75 MHz. For applications requiring low distortion,
the THS4061/2 is ideally suited with total
harmonic distortion of −72 dBc at f = 1 MHz.
1OUT
1IN −
1IN +
−VCC
NC
D
2
NULL
VCC+
OUT
NC
NC
D
8
NULL
D
1
VCC−
NC
D
NULL
IN −
IN +
VCC−
THS4062
D AND DGN PACKAGE
(TOP VIEW)
NC
D
D
− 180 MHz Bandwidth (G = 1, −3 dB)
− 400 V/µs Slew Rate
− 40-ns Settling Time (0.1%)
High Output Drive, IO = 115 mA (typ)
Excellent Video Performance
− 75 MHz 0.1 dB Bandwidth (G = 1)
− 0.02% Differential Gain
− 0.02° Differential Phase
Very Low Distortion
− THD = −72 dBc at f = 1 MHz
Wide Range of Power Supplies
− VCC = ±5 V to ±15 V
Available in Standard SOIC, MSOP
PowerPAD, JG, or FK Package
Evaluation Module Available
THS4061
JG, D AND DGN PACKAGE
(TOP VIEW)
NC
D High Speed
75 Ω
THS4061
VO
75 Ω
_
2 kΩ
75 Ω
2 kΩ
LINE DRIVER (G = 2)
CAUTION: The THS4061 and THS4062 provide ESD protection circuitry. However, permanent damage can still occur if this
device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any
performance degradation or loss of functionality
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
Copyright 1998 − 2003, Texas Instruments Incorporated
!"#$ % &'!!( $ #% )'*+ &#$ ,#$(! ,'&$% & !" $ %)(& &#$ % )(! $.( $(!"% (/#% %$!'"( $%
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
RELATED DEVICES
DEVICE
DESCRIPTION
THS4011/2
THS4031/2
THS4061/2
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High Speed-Amplifiers
180-MHz High-Speed Amplifiers
AVAILABLE OPTIONS
PACKAGED DEVICES
NUMBER OF
CHANNELS
PLASTIC
SMALL
OUTLINE†
(D)
PLASTIC
MSOP†
(DGN)
CERAMIC
DIP
(JG)
CHIP
CARRIER
(FK)
0°C
0
C to
70°C
1
THS4061CD
THS4061CDGN
—
2
THS4062CD
THS4062CDGN
—
−40 C to
−40°C
85°C
1
THS4061ID
THS4061IDGN
2
THS4062ID
1
—
TA
−55°C to
125°C
MSOP
SYMBOL
EVALUATION
MODULES
—
TIABS
THS4061EVM
—
TIABM
THS4062EVM
—
—
TIABT
—
THS4062IDGN
—
—
TIABN
—
—
THS4061MJG
THS4061MFK
—
—
† The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4061CDGNR).
functional block diagram
Null
2
IN−
3
IN+
1
8
−
6
OUT
+
Figure 1. THS4061 − Single Channel
VCC
1IN−
2
8
−
1
1IN+
2IN−
3
6
−
7
2IN+
5
1OUT
+
2OUT
+
4
−VCC
Figure 2. THS4062 − Dual Channel
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC+ to VCC− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
Differential input voltage, VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Operating free-air temperature, TA: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, D and DGN package . . . . . . . . . . . . 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . . 300°C
Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70
70°C
C
POWER RATING
TA = 85
85°C
C
POWER RATING
TA = 125
125°C
C
POWER RATING
D
475 mW
385 mW
—
740 mW
6 mW/°C
DGN‡
2.14 W
17.1 mW/°C
1.37 W
1.11 W
—
JG
1057 mW
8.4 mW/°C
627 mW
546 mW
210 mW
FK
1375 mW
11 mW/°C
880 mW
715 mW
275 mW
‡ The DGN package incorporates a PowerPAD on the underside of the device. This acts as a heatsink and must be connected to a thermal dissipation
plane for proper power dissipation. Failure to do so can result in exceeding the maximum specified junction temperature, which could permanently
damage the device.
recommended operating conditions
MIN
Dual supply
Supply voltage, VCC+ and VCC−
Single supply
C-suffix
Operating free-air temperature, TA
NOM
MAX
±4.5
±16
9
32
0
70
I-suffix
−40
85
M-suffix
−55
125
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
°C
C
3
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
dynamic performance
THS4061C/I,
THS4062C/I
TEST CONDITIONS†
PARAMETER
MIN
Dynamic performance small-signal
bandwidth (−3 dB)
BW
Bandwidth for 0.1 dB flatness
SR
Slew rate
Settling time to 0.1%
ts
Settling time to 0.01%
VCC = ±5 V
VCC = ±15 V
Gain = 1
TYP
UNIT
MAX
180
MHz
50
Gain = −1
VCC = ±5 V
VCC = ±15 V
MHz
50
75
Gain = 1
VCC = ±5 V
VCC = ±15 V
MHz
20
400
Gain = −1
VCC = ±5 V
VCC = ±15 V,
5-V step (0 V to 5 V)
VCC = ±5 V,
VCC = ±15 V,
VO = −2.5 V to 2.5 V,
5-V step (0 V to 5 V)
VCC = ±5 V,
VO = −2.5 V to 2.5 V,
† Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix
V/ s
V/µs
350
40
Gain = −1
ns
40
140
Gain = −1
ns
150
noise/distortion performance
THS4061C/I,
THS4062C/I
TEST CONDITIONS†
PARAMETER
MIN
THD
Total harmonic distortion
f = 1 MHz
Vn
In
Input voltage noise
f = 10 kHz,
Input current noise
f = 10 kHz,
Differential gain error
Gain = 2,
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
Gain = 2,
NTSC, 40 IRE modulation
Channel-to-channel crosstalk
(THS4062 only)
VCC = ±5 V or ±15 V,
UNIT
MAX
−72
dBc
14.5
nV/√Hz
1.6
pA/√Hz
VCC = ±15 V
0.02
%
VCC = ±5 V
0.02
%
VCC = ±15 V
VCC = ±5 V
0.02°
NTSC, 40 IRE modulation
Differential phase error
TYP
0.06°
f = 1 MHz
65
dB
† Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix
dc performance
Input offset voltage
IIB
IOS
Offset drift
Input bias current
Input offset current
TYP
15
VO = ±10 V,
TA = 25°C
TA = full range
5
RL = 1 kΩ
VCC = ±5 V,
VO = ±2.5 V, RL = 1 kΩ
TA = 25°C
TA = full range
2.5
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
TA = full range
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
TA = full range
TA = full range
TA = full range
† Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix
POST OFFICE BOX 655303
V/mV
8
V/mV
2
8
mV
µV/°C
15
3
6
75
250
0.3
• DALLAS, TEXAS 75265
UNIT
MAX
4
2.5
Offset current drift
4
MIN
VCC = ±15 V,
Open loop gain
VOS
THS4061C/I,
THS4062C/I
TEST CONDITIONS†
PARAMETER
µA
nA
nA/°C
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued)
input characteristics
THS4061C/I,
THS4062C/I
TEST CONDITIONS†
PARAMETER
VICR
Common-mode input voltage range
VCC = ±15 V
VCC = ±5 V
CMRR
Common mode rejection ratio
VCC = ±15 V,
VCC = ±5 V,
RI
Input resistance
VICR = ±12 V
VICR = ±2.5 V
TA = full range
MIN
TYP
±13.8
±14.1
± 3.8
± 4.3
70
110
70
95
Ci
Input capacitance
† Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix
UNIT
MAX
V
dB
1
MΩ
2
pF
output characteristics
PARAMETER
VO
IO
Output voltage swing
Output current
THS4061C/I,
THS4062C/I
TEST CONDITIONS†
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
MIN
TYP
RL = 250 Ω
±11.5
±12.5
RL = 150 Ω
±3.2
±3.5
RL = 1 kΩ
±13
±13.5
±3.5
±3.7
80
115
50
75
RL = 20 Ω
VCC = ±5 V
VCC = ±15 V
ISC
Short-circuit current
RO
Output resistance
Open loop
† Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix
UNIT
MAX
V
V
mA
150
mA
12
Ω
power supply
THS4061C/I,
THS4062C/I
TEST CONDITIONS†
PARAMETER
MIN
Dual supply
VCC
Supply voltage operating range
ICC
Quiescent current (per amplifier)
VCC = ±15 V
VCC = ±5 V
TA = full range
PSRR
Power supply rejection ratio
VCC = ±5 V or ±15 V
TA = 25°C
TA = full range
Single supply
TYP
UNIT
MAX
±4.5
±16.5
9
33
70
68
7.8
10.5
7.3
10
V
mA
78
dB
† Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
dynamic performance
Unity-gain bandwidth
BW
SR
Closed loop,
Dynamic performance small-signal
bandwidth (−3 dB)
Bandwidth for 0.1 dB flatness
Slew rate
Settling time to 0.1%
ts
Settling time to 0.01%
THS4061M
TEST CONDITIONS†
PARAMETER
RL = 1 kΩ
VCC = ±15 V
VCC = ±15 V
VCC = ±5 V
Gain = 1
VCC = ±15 V
VCC = ±5 V
Gain = −1
VCC = ±15 V
VCC = ±5 V
Gain = 1
MIN
TYP
*140
180
MAX
UNIT
MHz
180
MHz
180
50
MHz
50
75
VCC = ±15 V
VCC = ±15 V,
RL = 1 kΩ
VCC = ±5 V,
VCC = ±15 V,
VO = −2.5 V to 2.5 V,
5-V step (0 V to 5 V)
VCC = ±5 V,
VO = −2.5 V to 2.5 V,
MHz
20
*400
5-V step (0 V to 5 V)
500
V/µs
40
Gain = −1
ns
40
140
Gain = −1
ns
150
† Full range = −55°C to 125°C for M suffix
*This parameter is not tested.
noise/distortion performance
THS4061M
TEST CONDITIONS†
PARAMETER
MIN
TYP
THD
Total harmonic distortion
f = 1 MHz
Vn
In
Input voltage noise
f = 10 kHz,
Input current noise
f = 10 kHz,
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
Gain = 2,
NTSC, 40 IRE Modulation
VCC = ±15 V
VCC = ±5 V
0.02
Differential gain error
Differential phase error
Gain = 2,
NTSC, 40 IRE Modulation
VCC = ±15 V
VCC = ±5 V
0.02°
MAX
UNIT
−72
dBc
14.5
nV/√Hz
1.6
pA/√Hz
%
0.02
0.06°
† Full range = −55°C to 125°C for M suffix
dc performance
VIO
IIB
IIO
Open loop gain
VCC = ±15 V,
VCC = ±5 V,
Input offset voltage
VCC = ±5 V or ±15 V
RL = 1 kΩ
Offset drift
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
RL = 1 kΩ
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
RL = 1 kΩ
Input bias current
Input offset current
Offset current drift
† Full range = −55°C to 125°C for M suffix
6
THS4061M
TEST CONDITIONS†
PARAMETER
VO = ±10 V, RL = 1 kΩ
VO = ±2.5 V, RL = 1 kΩ
POST OFFICE BOX 655303
RL = 1 kΩ
RL = 1 kΩ
• DALLAS, TEXAS 75265
TA = full range
MIN
TYP
5
9
2.5
6
MAX
UNIT
V/mV
TA = 25°C
TA = full range
2.5
TA = full range
TA = full range
15
3
6
µA
TA = full range
TA = full range
75
250
nA
0.3
8
mV
9
mV
µV/°C
nA/°C
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
(continued)
input characteristics
THS4061M
TEST CONDITIONS†
PARAMETER
VICR
Common-mode input voltage range
VCC = ±15 V
VCC = ±5 V
CMRR
Common mode rejection ratio
VCC = ±15 V,
VCC = ±5 V,
RI
Input resistance
VICR = ±12 V
VICR = ±2.5 V
MIN
TYP
±13.8
±14.1
± 3.8
± 4.3
70
86
80
90
Ci
Input capacitance
† Full range = −55°C to 125°C for M suffix
MAX
UNIT
V
dB
1
MΩ
2
pF
output characteristics
VO
IO
Output voltage swing
Output current
ISC
Short-circuit current
RO
Output resistance
† Full range = −55°C to 125°C for M suffix
THS4061M
TEST CONDITIONS†
PARAMETER
VCC = ±15 V
VCC = ±5 V
MIN
TYP
RL = 250 Ω
±12
±13.1
RL = 150 Ω
±3.2
±3.5
±13
±13.5
±3.5
±3.7
70
115
50
75
VCC = ±15 V
VCC = ±5 V
RL = 1 kΩ
VCC = ±15 V
VCC = ±5 V
RL = 20 Ω
VCC = ±15 V
Open loop
TA = 25°C
MAX
UNIT
V
V
mA
150
mA
12
Ω
power supply
THS4061M
TEST CONDITIONS†
PARAMETER
MIN
Dual supply
VCC
ICC
PSRR
Supply voltage operating range
Quiescent current
Power supply rejection ratio
Single supply
VCC = ±15 V
VCC = ±5 V
TA = 25°C
VCC = ±15 V
VCC = ±5 V
TA = full range
VCC = ±5 V or ±15 V
TA = 25°C
TA = full range
TYP
MAX
±4.5
±16.5
9
33
7.8
9
7.3
8.5
11
UNIT
V
mA
10.5
76
80
74
78
dB
† Full range = −55°C to 125°C for M suffix
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
FIGURE
IIB
VIO
8
Input bias current
vs Free-air temperature
3
Input offset voltage
vs Free-air temperature
4
Open-loop gain
vs Frequency
5
Phase
vs Frequency
5
Differential gain
vs Number of loads
Differential phase
vs Number of loads
Closed-loop gain
vs Frequency
10, 11
6, 8
7, 9
Output amplitude
vs Frequency
12, 13
CMRR
Common-mode rejection ratio
vs Frequency
14
vs Frequency
15
PSRR
Power supply rejection ratio
vs Free-air temperature
16
VO(PP)
ICC
Output voltage swing
vs Supply voltage
17
Supply current
vs Free-air temperature
18
Env
THD
Noise spectral density
vs Frequency
19
Total harmonic distortion
vs Frequency
20, 21
Crosstalk
vs Frequency
22, 23
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
4
0
VIO − Input Offset Voltage − mV
−0.5
3.5
3
2.5
VCC = ±5 V
−1
−1.5
VCC = ±15 V
−2
−2.5
−3
−20
0
20
40
60
80
−3.5
−40
100
−20
TA − Free-Air Temperature − °C
0
20
40
60
80
100
TA − Free-Air Temperature − °C
Figure 3
Figure 4
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
90
VCC = ±15 V
80
0°
VCC = ±5 V
70
60
−45°
Phase
50
40
−90°
Phase
2
−40
Open-Loop Gain − dB
I IB − Input Bias Current − µ A
VCC = ±15 V, ±5 V
30
−135°
20
10
0
1k
10k
100k
1M
10M
100M
−180°
1G
f − Frequency − Hz
Figure 5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.14%
0.7°
Gain = 2
RF = 680 Ω
40 IRE − NTSC
Worst Case ±100 IRE Ramp
0.12%
0.6
Differential Phase
Differential Gain
0.1%
0.08%
VCC = ±15
Gain
0.06%
VCC = ±5
Gain
0.04%
0.5°
VCC = ± 5
Phase
0.4°
VCC = ± 15
Phase
0.3°
0.2°
0.02%
0%
Gain = 2
RF = 680 Ω
40 IRE − NTSC
Worst Case ±100 IRE Ramp
0.1°
2
1
3
0°
4
1
2
Number of 150 Ω Loads
Figure 6
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.2%
1°
Gain = 2
RF = 680 Ω
40 IRE − PAL
Worst Case ±100 IRE Ramp
0.18%
0.16%
0.8°
VCC = ±15
Gain
0.12%
0.1%
VCC = ±5
Gain
0.08%
0.7°
0.6°
0.5°
0.4°
0.06%
0.3°
0.04%
0.2°
0.02%
0.1°
1
2
Gain = 2
RF = 680 Ω
40 IRE − PAL
Worst Case ±100 IRE Ramp
0.9°
Differential Phase
Differential Gain
0.14%
3
4
0°
VCC = ±5
Phase
VCC = ±15
Phase
1
Number of 150 Ω Loads
2
Figure 9
POST OFFICE BOX 655303
3
Number of 150 Ω Loads
Figure 8
10
4
Figure 7
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
0%
3
Number of 150 Ω Loads
• DALLAS, TEXAS 75265
4
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
CLOSED-LOOP GAIN
vs
FREQUENCY
2
CLOSED-LOOP GAIN
vs
FREQUENCY
5
VCC = ±15 V
0
−2
VCC = ±5 V
Closed-Loop Gain − dB
Closed-Loop Gain − dB
0
−4
−6
−8
−5
−10
−10
−12
−15
Gain = 1
RF = 270 Ω
RL = 150 Ω
−14
100k
1M
10M
100M
VCC = ±15 V, ±5 V
Gain = −1
RF = 510 Ω
RL = 150 Ω
−20
100k
1G
1M
10M
f − Frequency − Hz
Figure 10
OUTPUT AMPLITUDE
vs
FREQUENCY
4
RF = 510 Ω
RF = 1 kΩ
0
Output Amplitude − dB
Output Amplitude − dB
2
0
RF = 270 Ω
RF = 200 Ω
−2
−4
−6
−8
100k
1G
Figure 11
OUTPUT AMPLITUDE
vs
FREQUENCY
2
100M
f − Frequency − Hz
RF = 3 kΩ
−2
−4
−6
−8
Gain = 1
RL = 150 Ω
1M
10M
100M
1G
−10
100k
Gain = −1
RL = 150 Ω
f − Frequency − Hz
1M
10M
100M
1G
f − Frequency − Hz
Figure 12
Figure 13
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
−80
VCC = ±15 V, ±5 V
PSRR − Power Supply Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
120
100
80
60
40
20
0
10k
100k
1M
10M
−70
−60
−50
−40
−30
−20
−10
VCC = ±15 V, ±5 V
0
1k
100M
10k
f − Frequency − Hz
Figure 14
10M
100M
OUTPUT VOLTAGE SWING
vs
SUPPLY VOLTAGE
90
30
88
VO(PP) − Output Voltage Swing − V
PSRR − Power Supply Rejection Ratio − dB
1M
Figure 15
POWER SUPPLY REJECTION RATIO
vs
FREE-AIR TEMPERATURE
86
VCC = −15 V
84
82
80
VCC = 15 V
78
76
25
RL = 1 kΩ
20
RL = 150 Ω
15
10
5
74
72
−40
−20
0
20
40
60
80
100
0
±4
TA − Free-Air Temperature − °C
±6
±8
±10
Figure 17
POST OFFICE BOX 655303
±12
VCC − Supply Voltage − V
Figure 16
12
100k
f − Frequency − Hz
• DALLAS, TEXAS 75265
±14
±16
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
NOISE SPECTRAL DENSITY
vs
FREQUENCY
10
180
E nv − Noise Spectral Density − nV/ Hz
TA = 25°C
I CC − Supply Current − mA
9
VCC = ±15 V
8
VCC = ±5 V
7
6
5
4
−40
−20
0
20
40
60
80
160
140
120
100
80
60
40
20
0
10
100
100
TA − Free-Air Temperature − °C
Figure 18
100k
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
−40
−40
Gain = 2
VCC = ±15 V
RL = 150 Ω
THD − Total Harmonic Distortion − dB
THD − Total Harmonic Distortion − dB
10k
Figure 19
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
−50
1k
f − Frequency − Hz
−60
−70
2nd Harmonic
−80
3rd Harmonic
−90
−100
−110
100k
1M
10M
−50
Gain = 2
VCC = ±5 V
RL = 150 Ω
−60
−70
2nd Harmonic
−80
3rd Harmonic
−90
−100
−110
100k
f − Frequency − Hz
1M
10M
f − Frequency − Hz
Figure 20
Figure 21
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
0
0
−20
Crosstalk − dBc
−30
−10
−20
Crosstalk − dBc
−10
G = 2,
RF = 300 W,
RL = 100 W,
VO = 200 mVPP,
VS = +15 V
See Figure 24
−40
−50
CH B to A
−60
−70
−30
−40
−60
CH A to B
−70
CH A to B
−80
−90
−90
1M
10 M
100 M
CH B to A
−50
−80
−100
100 k
G = 2,
RF = 300 W,
RL = 100 W,
VO = 200 mVPP,
VS = +5 V
See Figure 24
1G
−100
100 k
1M
f − Frequency − Hz
Figure 22
Figure 23
300 W
300 W
−
THS4062
A
+
VIN
100 W
49.9 W
300 W
300 W
−
THS4062
B
+
50 W Load
Measured
49.9 W
49.9 W
Figure 24. Test Circuits
14
10 M
f − Frequency − Hz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100 M
1G
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
APPLICATION INFORMATION
theory of operation
The THS406x is a high speed, operational amplifier configured in a voltage feedback architecture. It is built using
a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing fTs of
several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew
rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 25.
(7) VCC +
(6) OUT
IN − (2)
IN + (3)
(4) VCC −
NULL (1)
NULL (8)
Figure 25. THS4061 Simplified Schematic
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
APPLICATION INFORMATION
offset nulling
The THS4061 has very low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided. By placing a potentiometer between terminals 1 and 8
and tying the wiper to the negative supply, the input offset can be adjusted. This is shown in
Figure 26.
VCC+
0.1 µF
+
THS4061
_
10 kΩ
0.1 µF
VCC −
Figure 26. Offset Nulling Schematic
optimizing unity gain response
Internal frequency compensation of the THS406x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 270 Ω should
be used as shown in Figure 27. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
Input
+
Output
THS406x
_
270 Ω
Figure 27. Noninverting, Unity Gain Schematic
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS406x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 28. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
510 Ω
510 Ω
Input
_
20 Ω
Output
THS406x
+
CLOAD
Figure 28. Driving a Capacitive Load
circuit layout considerations
In order to achieve the levels of high frequency performance of the THS406x, it is essential that proper
printed-circuit board high frequency design techniques be followed. A general set of guidelines is given below.
In addition, a THS406x evaluation board is available to use as a guide for layout or for evaluating the device
performance.
D Ground planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distances increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D Sockets − Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
D Short trace runs/compact part placements − Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance
at the input of the amplifier.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
APPLICATION INFORMATION
circuit layout considerations (continued)
D Surface-mount passive components − Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance
of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the
small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both
stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths
be kept as short as possible.
evaluation board
An evaluation board is available for the THS4061 (literature number SLOP226) and THS4062 (literaure number
SLOP235). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the evaluation board is shown in Figure 29. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. To order the
evaluation board contact your local TI sales office or distributor. For more detailed information, refer to the
THS4061 EVM User’s Manual (literature number SLOU038) or the THS4062 EVM User’s Manual (literature
number SLOU040)
VCC+
+
C3
0.1 µF
R4
1 kΩ
IN +
C2
6.8 µF
NULL
R5
49.9 Ω
+
R3
49.9 Ω
OUT
THS4061
_
NULL
R2
1 kΩ
+
C4
0.1 µF
C1
6.8 µF
IN −
R1
49.9 Ω
VCC −
Figure 29. THS4061 Evaluation Board Schematic
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9960101Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629960101Q2A
THS4061MFKB
5962-9960101QPA
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
9960101QPA
THS4061M
Samples
THS4061CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4061C
Samples
THS4061CDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4061C
Samples
THS4061CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ABS
Samples
THS4061CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ABS
Samples
THS4061CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4061C
Samples
THS4061ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4061I
Samples
THS4061IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4061I
Samples
THS4061IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT
Samples
THS4061IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4061I
Samples
THS4061MFKB
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629960101Q2A
THS4061MFKB
THS4061MJG
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
THS4061MJG
Samples
THS4061MJGB
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
9960101QPA
THS4061M
Samples
THS4062CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4062C
Samples
THS4062CDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4062C
Samples
THS4062CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ABM
Samples
THS4062CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4062C
Samples
Addendum-Page 1
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
THS4062ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4062I
Samples
THS4062IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABN
Samples
THS4062IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABN
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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