THS4150
THS4151
www.ti.com........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
HIGH-SPEED DIFFERENTIAL I/O AMPLIFIERS
FEATURES
1
• High Performance
– 150 MHz –3 dB Bandwidth (VCC = ±5 V)
– 650 V/µs Slew Rate (VCC = ±15 V)
– –89 dB Third Harmonic Distortion at 1 MHz
– –83 dB Total Harmonic Distortion at 1 MHz
– 7.6 nV/√Hz Input-Referred Noise
• Differential Input/Differential Output
– Balanced Outputs Reject Common-Mode
Noise
– Differential Reduced Second Harmonic
Distortion
• Wide Power-Supply Range
– VCC = 5 V Single-Supply to ±15 V Dual
Supply
• ICC(SD) = 1 mA (VCC = ±5) in Shutdown Mode
(THS4150)
23
VINVOCM
VCC+
VOUT+
1
8
2
7
3
6
4
5
DEVICE
DESCRIPTION
THS412x
100 MHz, 43 V/µs, 3.7 nV/√Hz
THS413x
150 MHz, 51 V/µs, 1.3 nV/√Hz
THS414x
160 MHz, 450 V/µs, 6.5 nV/√Hz
8
2
7
3
6
4
5
VIN+
NC
VCCVOUT-
THS4150
1
X
THS4151
1
-
SHUTDOWN
Typical A/D Application Circuit
VDD
5V
VOCM
+
−
AIN
−
+
AIN
AVDD
AVSS
DVDD
Vref
DIGITAL
OUTPUT
−5 V
THS4151
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
−40
THD − Total Harmonic Distortion − dB
RELATED DEVICES
1
NUMBER OF
CHANNELS
DESCRIPTION
The THS415x is made of a true fully-differential signal
path from input to output. This design leads to an
excellent common-mode noise rejection and
improved total harmonic distortion.
VIN+
VINPD
VOCM
VCCVCC+
VOUT- VOUT+
DEVICE
Single-Ended to Differential Conversion
Differential ADC Driver
Differential Antialiasing
Differential Transmitter and Receiver
Output Level Shifter
The THS415x is one in a family of fully differential
input/differential output devices fabricated using
Texas
Instruments'
state-of-the-art
BiComI
complementary bipolar process.
THS4151
D, DGN, DGK PACKAGES
(TOP VIEW)
HIGH-SPEED DIFFERENTIAL I/O FAMILY
VIN
KEY APPLICATIONS
•
•
•
•
•
THS4150
D, DGN, DGK PACKAGES
(TOP VIEW)
−50
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = 5 V to ±15 V
−60
−70
Single Input to
Differential Output
−80
−90
−100
100 k
Differential Input to
Differential Output
1M
10 M
f − Frequency − Hz
100 M
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2009, Texas Instruments Incorporated
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009........................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS (1)
PACKAGED DEVICES
TA
0°C to 70°C
–40°C to 85°C
(1)
MSOP PowerPAD™
SMALL OUTLINE(D)
EVALUATION
MODULES
MSOP
(DGN)
SYMBOL
(DGK)
SYMBOL
THS4150CD
THS4150CDGN
AQB
THS4150CDGK
ATT
THS4150EVM
THS4151CD
THS4151CDGN
AQD
THS4151CDGK
ATU
THS4151EVM
THS4150ID
THS4150IDGN
AQC
THS4150IDGK
AST
–
THS4151ID
THS4151IDGN
AQE
THS4151IDGK
ASU
–
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
UNIT
VCC- to
VCC+
Supply voltage
VI
Input voltage
IO
Output current (2)
VID
Differential input voltage
TJ
±16.5 V
±VCC
150 mA
See Dissipation Rating Table
Maximum junction temperature (3)
150°C
Maximum junction temperature, continuous operation, long term reliability (4)
TA
Operating free-air temperature
Tstg
Storage temperature
Lead temperature
(2)
(3)
(4)
(5)
2
125°C
C suffix
0°C to 70°C
I suffix
–40°C to 85°C
–65°C to 150°C
(5)
ESD ratings
(1)
±6 V
Continuous total power dissipation
HBM
2500 V
CDM
1500 V
MM
200 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The THS415x may incorporate a PowerPad™ on the underside of the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPad™ thermally enhanced package.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
See the MSL/Reflow Rating information provided with the material, or see TI's web site at www.ti.com for the latest information.
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THS4151
www.ti.com........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
DISSIPATION RATING TABLE
(1)
(2)
POWER RATING (2)
PACKAGE
θJA (1)
(°C/W)
θJC
(°C/W)
TA = 25°C
TA = 85°C
D
97.5
38.3
1.02 W
410 mW
DGN
58.4
4.7
1.71 W
685 mW
DGK
260
54.2
385 mW
154 mW
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of 125°C. This is the point where distortion
starts to substantially increase. Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and long term reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC+ to
VCC–
Supply voltage
TA
Operating free-air temperature
Dual supply
Single supply
C suffix
I suffix
TYP
MAX
±2.5
±15
5
30
0
70
–40
85
UNIT
V
°C
ELECTRICAL CHARACTERISTICS
At VCC = 15 V, RL = 800 Ω, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
VCC = 5
BW
Small-signal bandwidth (–3 dB)
VCC = ±5
150
Gain = 1,
Rf = 390 Ω
VCC = ±15
Small-signal bandwidth (–3 dB)
VCC = ±5
80
Gain = 2,
Rf = 750 Ω
VCC = ±15
Slew rate (1)
SR
VCC = ±15,
Settling time to 0.1%
ts
81
MHz
81
Gain = 1
Differential step voltage = 2 VPP,
Gain = 1
Settling time to 0.01%
MHz
150
VCC = 5
BW
150
650
53
247
V/µs
ns
DISTORTION PERFORMANCE
VCC = 5
THD
Total harmonic distortion
Differential input, differential output Gain = 1,
Rf = 390 Ω, RL = 800 Ω, VO= 2 VPP
VCC = ±5
VCC = ±15
f = 1 MHz
–85
f = 8 MHz
–66
f = 1 MHz
–83
f = 8 MHz
–65
f = 1 MHz
–84
f = 8 MHz
–65
f = 1 MHz
–87
dB
–95
dBc
Spurious free dynamic range (SFDR)
VO = 2 VPP,
Third intermodulation distortion
VO = 0.14 VRMS, Gain = 1,
f = 20 MHz
dB
NOISE PERFORMANCE
Vn
Input voltage noise
f > 10 kHz
7.6
nV/√Hz
In
Input current noise
f > 10 kHz
1.78
pA/√Hz
(1)
Slew rate is measured from an output level range of 25% to 75%.
Copyright © 2000–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4150 THS4151
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THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009........................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At VCC = 15 V, RL = 800 Ω, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
63
67
MAX
UNIT
DC PERFORMANCE
TA = 25°C
Open loop gain
TA = full range
TA = 25°C
Offset drift
TA = full range
IIB
Input bias current
IOS
Input offset current
1.1
TA = full range
Input offset voltage, referred to VOCM
dB
60
TA = 25°C
Input offset voltage
VOS
(2)
7
8.5
0.6
8
µV/°C
7
TA = full range
mV
4.3
15
250
1200
µA
nA
Offset drift
TA = full range
0.7
nA/°C
Shutdown delay to output
TA = full range
1.1
µs
–83
dB
VS– +1.5V
to
VS+ –1.5V
V
INPUT CHARACTERISTICS
CMRR
Common-mode rejection ratio
VICR
Common-mode input voltage range
rI
Input resistance
CI
Input capacitance, closed loop
ro
Output resistance
ro(SD)
Output resistance
TA = full range
–75
Measured into each input terminal
14.4
MΩ
3.9
pF
Open loop/single ended
0.4
Ω
Shutdown
636
Ω
OUTPUT CHARACTERISTICS
VCC = 5 V
Output voltage swing
VCC = ±5 V
VCC = ±15 V
VCC = 5 V
IO
Output current, RL = 7Ω
VCC = ±5 V
VCC = ±15 V
TA = 25°C
1.2 to 3.8
TA = full range
1.2 to 3.8
TA = 25°C
±3.7
TA = full range
±3.6
TA = 25°C
±11.6
TA = full range
0.9 to 4.1
±3.9
V
±12.7
±11
TA = 25°C
30
TA = full range
25
TA = 25°C
45
TA = full range
35
TA = 25°C
65
TA = full range
50
45
60
mA
85
POWER-SUPPLY
VCC
Single supply
Supply voltage range
Split supply
VCC = ±5 V
ICC
Quiescent current (per amplifier)
VCC = ±15 V
ICC(SD)
Quiescent current (shutdown) (THS4150) (3)
PSRR
Power-supply rejection ratio (dc)
(2)
(3)
4
4
30
33
±2
±15
±16.5
15.8
18.5
TA = 25°C
TA = full range
21
TA = 25°C
17.5
21
1
1.3
TA = full range
V
mA
23
TA = 25°C
TA = full range
1.5
TA = 25°C
70
TA = full range
65
90
mA
dB
The full range temperature is 0°C to 70°C for the C suffix, and –40°C to 85°C for the I suffix.
For detailed information on the behavior of the power-down circuit, see the Power-down mode description in the Principles of Operation
section of this data sheet.
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Product Folder Link(s): THS4150 THS4151
THS4150
THS4151
www.ti.com........................................................................................................................................................... SLOS321G – MAY 2000 – REVISED MARCH 2009
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Small-signal frequency response
1, 2
Large-signal frequency response
3
Settling time
SR
4
Slew rate
Total harmonic distortion
vs Temperature
5
vs Frequency
6
vs Output voltage
Harmonic distortion
7
vs Frequency
8–13
vs Output voltage
14–17
Third intermodulation distortion
vs Output voltage
18
Vn
Voltage noise
vs Frequency
19
In
Current noise
vs Frequency
20
VO
Output voltage
vs Single-ended load resistance
21
Power supply current shutdown
vs Supply voltage
22
Output current range
vs Supply voltage
23
VOS
Single-ended output offset voltage
vs Common-mode output voltage
24
CMRR
Common-mode rejection ratio
vs Frequency
25
z
Impedance of the VOCM terminal
vs Frequency
26
zo
Output impedance (powered up)
vs Frequency
27
zo
Output impedance (shutdown)
vs Frequency
28
PSRR
Power-supply rejection ratio
vs Frequency
29
TYPICAL CHARACTERISTICS
SMALL-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
1
50
VCC = ±5 V
VI = 22.5 mVRMS
G = 100
40
VCC = 5
0.5
VCC = ±5
0
20
G = 10
G=5
10
VCC = ±15
−0.5
G - Gain - dB
G − Gain − dB
30
G=2
G=1
−1
−1.5
−2
−2.5
0
−3
−10
−3.5
−20
100 k
1M
10 M
100 M
1G
Gain = 1
Rf = 390W
RL = 800W
VI = 22.5 mVRMS
−4
100 k
f − Frequency − Hz
Figure 1.
1M
10 M
100 M
1G
f - Frequency - Hz
Figure 2.
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THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009........................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
LARGE-SIGNAL FREQUENCY RESPONSE
SETTLING TIME
2.3
1
Rf = 390 Ω,
CF = 1 pF,
VCC = ±5 V,
VO = 4 Vpp,
Gain = 1
VCC = ±5
VCC = 5
0.5
2.2
VCC = ±15
−0.5
G − Gain − dB
VO − Output Voltage − V
0
−1
−1.5
−2
−2.5
Gain = 1
Rf = 390 Ω,
RL = 800 Ω,
VI = 0.2 VRMS
−3
−3.5
2.1
2
1.9
1.8
Settling to 1% = 17.2 ns
Settling to 0.1% = 53.3 ns
Settling to 0.01% = 247.5 ns
1.7
1.6
1.5
−4
100 k
1M
10 M
100 M
0
1G
50
f − Frequency − Hz
Figure 4.
SLEW RATE
vs
TEMPERATURE
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
THD − Total Harmonic Distortion − dB
SR − Slew Rate − V/ µ s
650
VCC = ±15 V, VO = 4 VPP
550
VCC = ±5 V, VO = 2 VPP
500
400
−40
VCC = ±5 V, VO = 4 VPP
−20
40
0
20
60
T − Temperature −°C
80
100
−50
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±5 V to ±15 V
−60
−70
Single Input to
Differential Output
−80
Differential Input to
Differential Output
−90
−100
100 k
1M
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10 M
100 M
f − Frequency − Hz
Figure 5.
6
300
−40
CL= 0,
CF = 1 pF
VCC = ±15 V, VO = 2 VPP
450
250
Figure 3.
700
600
100
150
200
ts − Settling Time − ns
Figure 6.
Copyright © 2000–2009, Texas Instruments Incorporated
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THS4151
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TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
THD − Total Harmonic Distortion − dB
VCC = ±5 to ±15
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
f = 1 MHz
Single Input to
Differential Output
−80
Differential Input to
Differential Output
−90
−100
0.2
1.2
2.2
3.2
VO − Output Voltage − V
4.2
Figure 7.
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
−40
−60
−70
3rd HD
−80
2nd HD
−90
−100
5th HD
4th HD
−110
−120
100 k
1M
Single Input to
Differential Output
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±5 V
−50
Harmonic Distortion − dB
Harmonic Distortion − dB
−50
−40
Single Input to
Differential Output
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±2.5 V
−60
5th HD
−70
−80
−90
3rd HD
2nd HD
−100
−110
10 M
100 M
−120
100 k
4th HD
1M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 8.
Figure 9.
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100 M
7
THS4150
THS4151
SLOS321G – MAY 2000 – REVISED MARCH 2009........................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
−40
−40
−60
−50
5th HD
−70
−80
2nd HD
−90
−100
−120
100 k
1M
10 M
2nd HD
−90
4th HD
−100
100 k
1M
10 M
f − Frequency − Hz
Figure 10.
Figure 11.
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
−40
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±5 V
Differential Input to
Differential Output
−80
−50
3rd HD
2nd HD
5th HD
−100
4th HD
−110
−120
100 k
8
3rd HD
−80
f − Frequency − Hz
−70
−90
−70
−120
10 k
100 M
Harmonic Distortion − dB
Harmonic Distortion − dB
−60
Differential Input to
Differential Output
−110
4th HD
−40
−50
−60
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±2.5 V
5th HD
3rd HD
−110
Harmonic Distortion − dB
Harmonic Distortion − dB
−50
Single Input to
Differential Output
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±15 V
1M
10 M
−60
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VO = 2 Vpp,
VCC = ±15 V
Differential Input to
Differential Output
−70
−80
−90
3rd HD
2nd HD
4th HD
−100
5th HD
−110
100 M
−120
10 k
100 k
1M
f − Frequency − Hz
f − Frequency − Hz
Figure 12.
Figure 13.
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10 M
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TYPICAL CHARACTERISTICS (continued)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
−70
Single Input to
Differential Output
Single Input to
Differential Output
3rd HD
−80
2nd HD
5th HD
−90
−100
4th HD
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VCC = ±5 V
f = 1 MHz
−110
−120
0
Harmonic Distortion − dB
Harmonic Distortion − dB
−80
2nd HD
−90
5th HD
−100
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VCC = ±15 V
f = 1 MHz
−110
2
3
4
5
0
1
3
4
Figure 14.
Figure 15.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
5
−70
Differential Input to
Differential Output
Differential Input to
Differential Output
3rd HD
3rd HD
−80
Harmonic Distortion − dB
−80
Harmonic Distortion − dB
2
VO − Output Voltage − V
−70
2nd HD
−90
5th HD
−100
−120
0
4th HD
−120
1
VO − Output Voltage − V
−110
3rd HD
4th HD
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VCC = ±5 V
f = 1 MHz
2nd HD
−90
5th HD
−100
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VCC = ±15 V
f = 1 MHz
−110
4th HD
−120
1
2
3
4
5
0
VO − Output Voltage − V
Figure 16.
1
2
3
4
5
VO − Output Voltage − V
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
THIRD INTERMODULATION DISTORTION
vs
OUTPUT VOLTAGE
VOLTAGE NOISE
vs
FREQUENCY
100
−80
Gain = 1,
Rf = 390 Ω,
RL = 800 Ω,
VCC = ±5 V,
f = 1 MHz
VCC = 5 V to ±15 V
Single Input to
Differential Output
V n − Voltage Noise − nV/ Hz
Third Intermodulation Distortion − dB
−70
−90
−100
−110
−12
10
1
−2
−7
3
8
10
100
VO − Output Voltage − V
1k
10 k
100 k
f − Frequency − Hz
Figure 18.
Figure 19.
CURRENT NOISE
vs
FREQUENCY
OUTPUT VOLTAGE
vs
SINGLE-ENDED LOAD RESISTANCE
15
100
VCC = 5 V to ±15 V
VCC = ±15 V
VOUT+
VO − Output Voltage − V
I n − Current Noise − pA/ Hz
10
10
VOUT+
5
0
VCC = ±5 V
VOUT−
VCC = − ±5 V
−5
−10
VOUT−
VCC = − ±15 V
1
10
100
1k
10 k
f − Frequency − Hz
100 k
−15
10
100
1k
10 k
RL − Single-Ended Load Resistance − Ω
Figure 20.
10
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100 k
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
POWER-SUPPLY CURRENT SHUTDOWN
vs
SUPPLY VOLTAGE
OUTPUT CURRENT RANGE
vs
SUPPLY VOLTAGE
100
TA = 25°C
2
1.5
1
0.5
TA = 25°C
80
70
TA = 125°C
60
TA = 85°C
50
40
30
20
10
0
0
0
2
4
6
8
10
12
VCC − Supply Voltage − ±V
14
16
1
2
3
4
5 6 7 8 9 10 11 12 13 14 15 16
VCC − Supply Voltage − V
Figure 22.
Figure 23.
SINGLE-ENDED OUTPUT OFFSET VOLTAGE
vs
COMMON-MODE OUTPUT VOLTAGE
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
100
0
VCC = 2.5 V
60
VCC = 5 V
20
−20
VCC = 15 V
−60
−100
−12
−7
−2
3
8
VOCM − Common-Mode Output Voltage − V
CMRR − Common Mode Rejection Ratio − dB
VOS − Single-Ended Output Offset Voltage − mV
TA = 40°C
90
I O − Output Current Range − mA
I CC − Power Supply Current Shutdown − mA
2.5
−10
VCC = 5 V to ±15 V,
VI = 0.25 VRMS
−20
−30
−40
−50
−60
−70
−80
−90
1M
Figure 24.
10 M
100 M
1G
f − Frequency − Hz
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
IMPEDANCE OF THE VOCM TERMINAL
vs
FREQUENCY
OUTPUT IMPEDANCE (POWERED UP)
vs
FREQUENCY
16000
100
VCC = ±5 V
14000
12000
Output Impedance − Ω
z − Impedance of the V OCM Terminal − Ω
VCC = 5 V to ±15 V
10000
8000
6000
10
1
4000
2000
0
100 k
1M
10 M
100 M
0.1
100 k
1G
1M
Figure 27.
OUTPUT IMPEDANCE (SHUTDOWN)
vs
FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs
FREQUENCY
1G
−10
PSRR − Power Supply Rejection Ratio − dB
VCC = ±5 V
Output Impedance (Shutdown) − Ω
100 M
Figure 26.
1000
Rf = R(g) = 500 Ω
100
10
100 k
1M
10 M
100 M
1G
VCC+ = 2.5 V, 5 V, 15 V
−20
−30
−40
−50
VCC− = 225 mVRMS + (-2.5 V) dc
= 225 mVRMS + (-5 V) dc
= 225 mVRMS + (-15 V) dc
−60
−70
100 k
1M
f − Frequency − Hz
Figure 28.
12
10 M
f − Frequency − Hz
f − Frequency − Hz
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10 M
100 M
f − Frequency − Hz
1G
Figure 29.
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APPLICATION INFORMATION
RESISTOR MATCHING
Resistor matching is important in fully differential amplifiers. The balance of the output on the reference voltage
depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion
will diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to
keep the performance optimized.
VOCM sets the dc level of the output signals. If no voltage is applied to the VOCM pin, it will be set to the midrail
voltage internally defined as:
ǒVCC)Ǔ ) ǒVCC–Ǔ
2
In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential
mode is the same as the input when gain is 1. VOCM has a high bandwidth capability up to the typical operating
range of the amplifier. For the prevention of noise going through the device, use a 0.1-µF capacitor on the VOCM
pin as a bypass capacitor. Figure 30 shows the simplified diagram of the THS415x.
VCC+
Output Buffer
VIN-
x1
VOUT+
C
VIN+
R
Vcm Error
Amplifier
+
_
C
x1
R
VOUT-
Output Buffer
VCC+
30 kΩ
VCC-
30 kΩ
VCCVOCM
Figure 30. THS415x Simplified Diagram
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DATA CONVERTERS
Data converters are one of the most popular applications for the fully differential amplifiers. The following
schematic shows a typical configuration of a fully differential amplifier attached to a differential ADC.
VDD
VCC
5V
VIN
+
-
AIN1
-
+
AIN2
VOCM
0.1 µF
AVDD
DVDD
AVSS
Vref
-5 V
VCC-
Figure 31. Fully Differential Amplifier Attached to a Differential ADC
Fully differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VCC/2. The
differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit.
If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the
amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input
terminal of the amplifier should not exceed the common-mode input voltage range.
VDD
VCC
5V
VIN
+
-
AIN1
-
+
AIN2
VOCM
0.1 µF
AVDD
DVDD
AVSS
Vref
Figure 32. Fully Differential Amplifier Using a Single-Supply
Some single-supply applications may require the input voltage to exceed the common-mode input voltage range.
In such cases, the following circuit configuration is suggested to bring the common-mode input voltage within the
specifications of the amplifier.
VCC
R(g)
VIN
VDD
Rf
RPU
VP
5V
VOUT
+
-
AIN1
-
+
AIN2
VOCM
VOUT
RPU
VCC
AVDD
DVDD
THS1206
0.1 µF
R(g)
VCC
AVSS
Vref
Rf
Figure 33. Circuit With Improved Common-Mode Input Voltage
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The following equation is used to calculate RPU:
V –V
P
CC
R
+
PU
1
1
ǒVIN – V PǓ RG ) V OUT – V P RF
ǒ
Ǔ
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS415x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device's phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 34. A minimum value of 20 Ω should work well for most applications. For
example, in 50-Ω transmission systems, setting the series resistor value to 20 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
390 Ω
20 Ω
Output
390 Ω
THS415x
20 Ω
390 Ω
Output
390 Ω
Figure 34. Driving a Capacitive Load
ACTIVE ANTIALIAS FILTERING
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass
filters can prevent the aliasing of the high frequency noise with the frequency of operation. Figure 35 presents a
method by which the noise may be filtered in the THS415x.
C1
R2
VCC
R4
+
R1
VIN-
-
VIN+
THS415x
+
C2
Vs
R1
C3
R3
+
VIN+
R(t)
VOCM
R3
THS1050
VINVOCM
C3
VIC
R4
VCC-
+
C1
R2
Figure 35. Antialias Filtering
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The transfer function for this filter circuit is:
ȡ
ȣ ȡ
Rt
ȣ
2R4
) Rt
K
ȧ
H (f) + ȧ
xȧ
d
ȧ f 2 1 jf
ȧ 1 ) j2πfR4RtC3ȧ
ǒ
Ǔ
2R4 ) Rt Ȥ
Ȣ– FSF x fc ) Q FSF x fc ) 1Ȥ Ȣ
FSF x fc +
Where K + R2
R1
Ǹ2 x R2R3C1C2
1
and Q +
R3C1 ) R2C1 ) KR3C1
2π Ǹ2 x R2R3C1C2
K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency-scaling factor, and Q is the
quality factor.
FSF +
ǸRe
2
) |Im|
2
and Q +
ǸRe
2
) |Im|
2
2Re
where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 =
C, and C2 = nC results in:
Ǹ2 x mn
1
FSF x fc +
and Q +
Ǹ
1 ) m(1 ) K)
2πRC 2 x mn
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select
C and calculate R for the desired fc.
PRINCIPLES OF OPERATION
THEORY OF OPERATION
The THS415x is a fully differential amplifier. Differential amplifiers are typically differential in/single out, whereas
fully differential amplifiers are differential in/differential out.
Differential Amplifier
Rf
R(g)
_
+
R(g)
Rf
THS415x
Fully differential Amplifier
VCC+
VINVIN+
_
+
+
_
VO+
VO-
VOCM
VCC-
Figure 36. Differential Amplifier Versus a Fully Differential Amplifier
To understand the THS415x fully differential amplifiers, the definition for the pinouts of the amplifier are provided.
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Input voltage definition
V
ID
Output voltage definition
V
Transfer function
V
+
ǒVI)Ǔ – ǒV I–Ǔ
ǒVO)Ǔ – ǒVO–Ǔ
OD
+
OD
+ V
Output common mode voltage V
V
OC
ID
x A
+ V
IC
V
ǒVI)Ǔ
+
)
ǒVI–Ǔ
2
+
OC
ǒVO)Ǔ ) ǒVO–Ǔ
2
ǒfǓ
OCM
Differential Structure Rejects
Coupled Noise at the Input
Differential Structure Rejects
Coupled Noise at the Output
VCC+
_
VIN-
VO+
+
VIN+
Differential Structure Rejects
Coupled Noise at the Power Supply
+
_
VO-
VOCM
VCC-
Figure 37. Definition of the Fully Differential Amplifier
The following schematics depict the differences between the operation of the THS415x, a fully differential
amplifier, in two different modes. Fully differential amplifiers can work with differential input or can be
implemented as single in/differential out.
Rf
R(g)
VIN−
VCC+
VO+
−+
Vs
+−
VIN+
VO−
VOCM
R(g)
VCC−
Rf
Note: For proper operation, maintain symmetry by setting
Rf1 = Rf2 = Rf and R(g)1 = R(g)2 = R(g) ⇒ A = Rf/R(g)
Figure 38. Amplifying Differential Signals
Rf
VIN-
R(g)
VCC+
VIN+
Vs
RECOMMENDED RESISTOR VALUES
- +
VO+
+-
VOVOCM
R(g)
GAIN
R(g) Ω
Rf Ω
1
2
5
10
390
374
402
402
390
750
2010
4020
VCCRf
Figure 39. Single In With Differential Out
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If each output is measured independently, each output is one-half of the input signal when the gain is 1. The
following equations express the transfer function for each output:
V
V
+ I) ) V
O)
OCM
2
The second output is equal and opposite in sign:
–VI)
V
+
) V
O–
OCM
2
VOCM will be set to midrails if it is not derived by any external power source.
Fully differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting
amplifier holds true for gain calculations. One advantage of fully differential amplifiers is that they offer twice as
much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input
signal of 1 VPP. If the output of the amplifier is 2 VPP, then it will not be practical to feed a 2-VPP signal into the
targeted ADC. Using a fully differential amplifier enables the user to break down the output into two 1-VPP signals
with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer has been
able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully differential amplifier. The
final result indicates twice as much dynamic range.
Figure 40 illustrates the increase in dynamic range. The gain factor should be considered in this scenario. The
THS415x fully differential amplifier offers an improved CMRR and PSRR due to its symmetrical input and output.
Furthermore, second harmonic distortion is improved. Second harmonics tend to cancel because of the
symmetrical output.
a
VOD= 1-0 = 1
VCC+
VINVIN+
+1
_
+
+
_
VOCM
VCC-
VO+
0
VO-
+1
0
VOD = 0-1 = -1
b
Figure 40. Fully Differential Amplifier With Two 1-VPP Signals
Similar to the standard inverting amplifier configuration, input impedance of a fully differential amplifier is selected
by the input resistor, R(g). If input impedance is a constraint in design, the designer may choose to implement the
differential amplifier as an instrumentation amplifier. This configuration improves the input impedance of the fully
differential amplifier. The following schematic depicts the general format of instrumentation amplifiers.
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The general transfer function for this circuit is:
V
R
OD
f 1 ) 2R2
+
V
–V
R
R1
IN1
IN2
(g)
ǒ
Ǔ
THS4012
R(g)
+
_
VIN1
Rf
R2
_
R1
THS415x
+
R2
_
+
VIN2
THS4012
R(g)
Rf
Figure 41. Fully Differential Instrumentation Amplifier
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the levels of high frequency performance of the THS415x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS415x evaluation board
is available to use as a guide for layout or for evaluating the device performance.
• Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
• Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
• Short trace runs/compact part placements—Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
• Surface-mount passive components—Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
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POWER-DOWN MODE
The power-down mode is used when power saving is required. The power-down terminal (PD) found on the
THS415x is an active low terminal. If it is left as a no-connect terminal, the device will always stay on due to an
internal 50 kΩ resistor to VCC. The threshold voltage for this terminal is approximately 1.4 V above VCC–. This
means that if the PD terminal is 1.4 V above VCC–, the device is active. If the PD terminal is less than 1.4 V
above VCC–, the device is off. For example, if VCC– = –5 V, then the device is on when PD reaches 3.6 V, (–5 V +
1.4 V = –3.6 V). By the same calculation, the device is off below –3.6 V. It is recommended to pull the terminal to
VCC– in order to turn the device off. Figure 42 shows the simplified version of the power-down circuit. While in the
power-down state, the amplifier goes into a high-impedance state. The amplifier output impedance is typically
greater than 1 MΩ in the power-down state.
VCC
50 kΩ
To Internal Bias
Circuitry Control
PD
VCC-
Figure 42. Simplified Power-Down Circuit
Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be very
low while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still
connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of
the amplifier. An example of the closed-loop output impedance is shown in Figure 43.
OUTPUT IMPEDANCE (SHUTDOWN)
vs
FREQUENCY
1000
Output Impedance (Shutdown) - Ω
VCC = ±5 V
Rf = R(g) = 500 Ω
100
10
100 k
1M
10 M
100 M
1G
f Frequency - Hz
Figure 43.
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GENERAL PowerPAD DESIGN
The THS415x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 44(a) and Figure 44(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 44(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
More complete details of the PowerPAD™ installation process and thermal management techniques can be
found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package (SLMA002). This
document can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The
document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when
ordering.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
A.
Bottom View (c)
The thermal pad is electrically isolated from all terminals in the package.
Figure 44. Views of Thermally Enhanced DGN Package
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (November, 2006) to Revision G .......................................................................................... Page
•
22
Corrected x-axis values in Figure 2 ....................................................................................................................................... 5
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
THS4150CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4150C
Samples
THS4150CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AQB
Samples
THS4150CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AQB
Samples
THS4150CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4150C
Samples
THS4150ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4150I
Samples
THS4150IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AQC
Samples
THS4150IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AQC
Samples
THS4151CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4151C
Samples
THS4151CDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ATU
Samples
THS4151CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AQD
Samples
THS4151ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4151I
Samples
THS4151IDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASU
Samples
THS4151IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AQE
Samples
THS4151IDGNG4
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AQE
Samples
THS4151IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AQE
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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