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THS4281DGKG4

THS4281DGKG4

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VSSOP-8_3X3MM

  • 描述:

    Voltage Feedback Amplifier 1 Circuit Rail-to-Rail 8-VSSOP

  • 数据手册
  • 价格&库存
THS4281DGKG4 数据手册
Sample & Buy Product Folder Support & Community Tools & Software Technical Documents THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 THS4281 Very Low-Power, High-Speed, Rail-to-Rail Input and Output Voltage-Feedback Operational Amplifier 1 Features • • 1 • • • • • • • • • 3 Description Fabricated using the BiCom-II process, the THS4281 is a low-power, rail-to-rail input and output, voltagefeedback operational amplifier designed to operate over a wide power-supply range of 2.7-V to 15-V single supply, and ±1.35-V to ±7.5-V dual supply. Consuming only 750 μA with a unity gain bandwidth of 90 MHz and a high 35-V/μs slew rate, the THS4281 allows portable or other power-sensitive applications to realize high performance with minimal power. To ensure long battery life in portable applications, the quiescent current is trimmed to be less than 900 μA at +25°C, and 1 mA from –40°C to +85°C. Very Low Quiescent Current: 750 μA (at 5 V) Rail-to-Rail Input and Output: – Common-Mode Input Voltage Extends 400 mV Beyond the Rails – Output Swings Within 150 mV From the Rails Wide –3-dB Bandwidth at 5 V: – 90 MHz at Gain = +1, 40 MHz at Gain = +2 High Slew Rate: 35 V/μs Fast Settling Time (2-V Step): – 78 ns to 0.1% – 150 ns to 0.01% Low Distortion at Gain = +2, VO = 2-VPP, 5 V: – –91 dBc at 100 kHz, –67 dBc at 1 MHz Input Offset Voltage: 2.5 mV (Max at +25°C) Output Current > 30 mA (10-Ω Load, 5 V) Low Voltage Noise of 12.5 nV/√Hz Supply Voltages: +2.7 V, 3 V, +5 V, ±5 V, +15 V Packages: SOT23, MSOP, and SOIC The THS4281 is a true single-supply amplifier with a specified common-mode input range of 400 mV beyond the rails. This allows for high-side current sensing applications without phase reversal concerns. Its output swings to within 40 mV from the rails with 10-kΩ loads, and 150 mV from the rails with 1-kΩ loads. The THS4281 has a good 0.1% settling time of 78 ns, and 0.01% settling time of 150 ns. The low THD of –87 dBc at 100 kHz, coupled with a maximum offset voltage of less than 2.5 mV, makes the THS4281 a good match for high-resolution ADCs sampling less than 2 MSPS. 2 Applications • • • • • Portable/Battery-Powered Applications High Channel Count Systems ADC Buffer Active Filters Current Sensing The THS4281 is offered in a space-saving SOT23-5 package, a small MSOP-8 package, and the industry standard SOIC-8 package. Device Information(1) PART NUMBER THS4281 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm SOT-23 (5) 2.90 mm × 1.60 mm VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. High-side, Low Power Current-Sensing system 470 pF V BAT 500 W I 2.5 kW RSENSE 0.2 W + 470 pF VBAT 100 W - 500 W Load V OUT = I RSENSE VBAT THS4281 10 nF +IN ADS8320 -IN 2.5 kW VBAT/2 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7 1 1 1 2 3 4 Absolute Maximum Ratings ..................................... 4 ESD Ratings ............................................................ 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics, VS = 3 V (VS+ = 3 V, VS– = GND) .......................................................................... 5 Electrical Characteristics, VS = 5 V (VS+ = 5 V, VS– = GND) .......................................................................... 7 Electrical Characteristics, VS = ±5 V......................... 9 Dissipation Ratings ................................................. 11 Typical Characteristics ............................................ 12 Detailed Description ............................................ 24 7.1 Overview ................................................................. 24 7.2 Feature Description................................................. 24 7.3 Device Functional Modes........................................ 25 8 Application and Implementation ........................ 26 8.1 Application Information............................................ 26 8.2 Typical Application ................................................. 27 9 Power Supply Recommendations...................... 29 9.1 Power-Supply Decoupling Techniques and Recommendations ................................................... 29 10 Layout................................................................... 29 10.1 Layout Guidelines ................................................. 29 10.2 Layout Examples................................................... 30 10.3 Thermal Considerations ........................................ 31 11 Device and Documentation Support ................. 33 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 33 33 33 33 33 12 Mechanical, Packaging, and Orderable Information ........................................................... 33 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (November 2009) to Revision B Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Removed the Packaging/Ordering Information table ............................................................................................................ 1 • Removed Design Tools section ............................................................................................................................................. 1 • Updated Thermal Values ....................................................................................................................................................... 1 • Removed the Applications Section Contents section .......................................................................................................... 24 • Removed the Bill of Materials section ................................................................................................................................. 24 Changes from Original (April 2004) to Revision A Page • Updated document format to current standards..................................................................................................................... 1 • Deleted Lead temperature specification from Absolute Maximum Ratings table................................................................... 4 • Revised Driving Capacitive Loads section ........................................................................................................................... 26 • Changed Board Layout section; revised statements in fourth recommendation about how to make connections to other wideband devices on the board .................................................................................................................................. 29 2 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 5 Pin Configuration and Functions D and DGK Packages 8-Pin SOIC Top View NC 1 8 NC IN− 2 7 VS+ IN+ 3 6 VOUT VS− 4 5 NC DBV Package 5-Pin SOT-23 Top View Note: VOUT 1 VS− 2 IN+ 3 5 VS+ 4 IN− NC Indicates there is no internal connection to these pins Pin Functions PIN I/O DESCRIPTION SOIC, VSSOP SOT-23 NC 1 — — IN- 2 4 I Negative input voltage pin IN+ 3 3 I Positive input voltage pin Vs- 4 2 I/O NC 5 — — Vout 6 1 O Output voltage pin Vs+ 7 5 I/O Postive supply input voltage pin NC 8 — — NAME Negative supply input voltage pin Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 3 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted). (1) MIN MAX UNIT 16.5 V ±VS ± 0.5 V Supply voltage, VS– to VS+ Input voltage, VI Differential input voltage, VID Output current, IO Continuous power dissipation (2) TJ Maximum junction temperature, continuous operation, long-term reliability (2) TJ Storage temperature, Tstg (2) V ±100 mA See Dissipation Ratings Table Maximum junction temperature, any condition, (1) ±2 +150 °C 125° °C 150 °C –65 The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. recommended operating conditions. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±3500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 Machine Model (MM) ±100 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Supply voltage, (VS+ and VS –) Dual supply Single supply MIN MAX ±1.35 ±8.25 2.7 16.5 UNIT V 6.4 Thermal Information THS4281 THERMAL METRIC (1) (2) DBV (SOT-23) D (SOIC) DGK (VSSOP) 5 PINS 8 PINS 8 PINS 154.4 126.6 UNIT RθJA Junction-to-ambient thermal resistance 192.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 115 69 77.7 °C/W RθJB Junction-to-board thermal resistance 31.4 64.7 112.8 °C/W ψJT Junction-to-top characterization parameter 14.7 20.5 14.6 °C/W ψJB Junction-to-board characterization parameter 31 64.3 111.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) (2) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. This data was taken using the JEDEC standard High-K test PCB. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 6.5 Electrical Characteristics, VS = 3 V (VS+ = 3 V, VS– = GND) At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ to 1.5 V, TA = 25°C unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE G = +1, VO = 100 mVPP, RF = 34 Ω 83 MHz G = +2, VO = 100 mVPP, RF = 1.65 kΩ 40 MHz G = +5, VO = 100 mVPP, RF = 1.65 kΩ 8 MHz G = +10, VO = 100 mVPP, RF = 1.65 kΩ 3.8 MHz 0.1-dB Flat Bandwidth G = +2, VO = 100 mVPP, RF = 1.65 kΩ 20 MHz Full-Power Bandwidth G = +2, VO = 2 VPP 8 MHz G = +1, VO = 2-V Step 26 V/μs G = –1, VO = 2-V Step 27 V/μs Settling time to 0.1% G = –1, VO = 1-V Step 80 ns Settling time to 0.01% G = –1, VO = 1-V Step 155 ns Rise/Fall Times G = +1, VO = 2-V Step 55 ns Small-Signal Bandwidth Slew Rate AC PERFORMANCE— HARMONIC DISTORTION Second Harmonic Distortion Third Harmonic Distortion THD + N G = +2, VO = 2 VPP, f = 1 MHz, RL = 1 kΩ –52 G = +2, VO = 2 VPP, f = 100 kHz, RL = 1 kΩ –52 G = +2, VO = 2 VPP, f = 1 MHz, RL = 1 kΩ –69 G = +2, VO = 2 VPP, f = 100 kHz, RL = 1 kΩ –71 G = +2, VO = 2 VPP, VO = 1 VPP, f = 10 kHz dBc dBc 0.003% G = +2, VO = 2 VPP, VO = 2 VPP, f = 10 kHz 0.03% Differential Gain (NTSC/PAL) G = +2, RL = 150 Ω 0.05/0.08 % Differential Phase (NTSC/PAL) G = +2, RL = 150 Ω 0.25/0.35 Input Voltage Noise f = 100 kHz 12.5 nA/√Hz Input Current Noise f = 100 kHz 1.5 pA/√Hz º DC PERFORMANCE Open-Loop Voltage Gain (AOL) 95 25°C Input Offset Voltage VCM = 1.5 V Average Offset Voltage Drift VCM = 1.5 V Input Bias Current VCM = 1.5 V 0.5 0°C to 70°C 3.5 –40°C to +85°C 3.5 0°C to 70°C ±7 –40°C to +85°C ±7 25°C Average Bias Current Drift VCM = 1.5 V Input Offset Current VCM = 1.5 V Average Offset Current Drift VCM = 1.5 V dB 2.5 0.5 1 –40°C to +85°C 1 ±2 –40°C to +85°C ±2 25°C 0.1 µV/°C 0.8 0°C to 70°C 0°C to 70°C mV µA nA/°C 0.4 0°C to 70°C 0.5 –40°C to +85°C 0.5 0°C to 70°C ±2 –40°C to +85°C ±2 μA nA/°C INPUT CHARACTERISTICS Common-Mode Input Range Common-Mode Rejection Ratio 25°C –0.3/3.3 0°C to 70°C –0.1/3.1 –40°C to +85°C –0.1/3.1 VCM = 0 V to 3 V Input Resistance Common-mode Input Capacitance Common-mode/Differential 25°C 75 0°C to 70°C 70 –40°C to +85°C 70 –0.4/3.4 V 92 dB 100 MΩ 0.8/1.2 pF Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 5 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Electrical Characteristics, VS = 3 V (VS+ = 3 V, VS– = GND) (continued) At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ to 1.5 V, TA = 25°C unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT CHARACTERISTICS RL = 10 kΩ Output Voltage Swing Output Current (Sourcing) Output Current (Sinking) Output Impedance 0.04/2.96 25°C RL = 1 kΩ RL = 10 Ω RL = 10 Ω 0.14/2.86 0°C to 70°C 0.2/2.8 –40°C to +85°C 0.2/2.8 25°C 18 0°C to 70°C 15 –40°C to +85°C 15 25°C 22 0°C to 70°C 19 –40°C to +85°C 19 V 0.1/2.9 V 23 mA 29 mA f = 1 MHz 1 25°C 3 Ω POWER SUPPLY Maximum Operating Voltage Minimum Operating Voltage 16.5 –40°C to +85°C 16.5 25°C 2.7 0°C to 70°C 2.7 –40°C to +85°C 2.7 25°C Maximum Quiescent Current V 0.75 0°C to 70°C Power-Supply Rejection (–PSRR) 6 0.9 0.98 0.6 0°C to 70°C 0.57 –40°C to +85°C 0.55 VS+ = 3.25 V to 2.75 V, VS– = 0 V VS+ = 3 V, VS– = 0 V to 0.65 V mA 1 25°C Power-Supply Rejection (+PSRR) V 3 –40°C to +85°C Minimum Quiescent Current 16.5 0°C to 70°C 25°C 70 0°C to 70°C 65 –40°C to +85°C 65 25°C 70 0°C to 70°C 65 –40°C to +85°C 65 Submit Documentation Feedback 0.75 mA 90 dB 90 dB Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 6.6 Electrical Characteristics, VS = 5 V (VS+ = 5 V, VS– = GND) At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ to 2.5 V, TA = 25°C unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE Small-Signal Bandwidth G = +1, VO = 100 mVPP, RF = 34 Ω 90 MHz G = +2, VO = 100 mVPP, RF = 2 kΩ 40 MHz G = +5, VO = 100 mVPP, RF = 2 kΩ 8 MHz G = +10, VO = 100 mVPP, RF = 2 kΩ 3.8 MHz 0.1-dB Flat Bandwidth G = +2, VO = 100 mVPP, RF = 2 kΩ 20 MHz Full-Power Bandwidth G = +2, VO = 2 VPP 9 MHz G = +1, VO = 2-V Step 31 V/μs G = –1, VO = 2-V Step 34 V/μs Settling Time to 0.1% G = –1, VO = 2-V Step 78 ns Settling Time to 0.01% G = –1, VO = 2-V Step 150 ns Rise/Fall Times G = +1, VO = 2-V Step 48 ns Slew Rate AC PERFORMANCE— HARMONIC DISTORTION Second Harmonic Distortion Third Harmonic Distortion THD + N Differential Gain (NTSC/PAL) Differential Phase (NTSC/PAL) G = +2, VO = 2 VPP, f = 1 MHz, RL = 1 kΩ –67 G = +2, VO = 2 VPP, f = 100 kHz, RL = 1 kΩ –92 G = +2, VO = 2 VPP, f = 1 MHz, RL = 1 kΩ dBc –76 G = +2, VO = 2 VPP, f = 100 kHz, RL = 1 kΩ –106 G = +2, VO = 2 VPP, VO = 2 VPP, f = 10 kHz 0.0009% G = +2, VO = 2 VPP, VO = 4 VPP, f = 10 kHz dBc 0.0005% 0.11/0.17% G = +2, RL = 150 Ω 0.11/0.14 º Input Voltage Noise f = 100 kHz 12.5 nV/√Hz Input Current Noise f = 100 kHz 1.5 pA/√Hz DC PERFORMANCE Open-Loop Voltage Gain (AOL) 25°C 85 0°C to 70°C 80 –40°C to +85°C 80 25°C Input Offset Voltage VCM = 2.5 V Average Offset Voltage Drift VCM = 2.5 V Input Bias Current VCM = 2.5 V 105 dB 2.5 3.5 –40°C to +85°C 3.5 0°C to 70°C ±7 –40°C to +85°C ±7 25°C 0.5 0°C to 70°C VCM = 2.5 V Input Offset Current VCM = 2.5 V Average Offset Current Drift VCM = 2.5 V mV µV/°C 0.8 1 –40°C to +85°C Average Bias Current Drift 0.5 0°C to 70°C µA 1 0°C to 70°C ±2 –40°C to +85°C ±2 25°C 0.1 nA/°C 0.4 0°C to 70°C 0.5 –40°C to +85°C 0.5 0°C to 70°C ±2 –40°C to +85°C ±2 µA nA/°C INPUT CHARACTERISTICS Common-Mode Input Range 25°C –0.4/5.4 0°C to 70°C –0.1/5.1 –40°C to +85°C –0.1/5.1 –0.3/5.3 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 V 7 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Electrical Characteristics, VS = 5 V (VS+ = 5 V, VS– = GND) (continued) At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ to 2.5 V, TA = 25°C unless otherwise noted. PARAMETER Common-Mode Rejection Ratio TEST CONDITIONS MIN TYP 25°C 85 100 0°C to 70°C 80 –40°C to +85°C 80 VCM = 0 V to 5 V Input Resistance Common-mode Input Capacitance Common-mode/Differential MAX UNIT dB 100 MΩ 0.8/1.2 pF 0.04/4.96 V OUTPUT CHARACTERISTICS RL = 10 kΩ Output Voltage Swing Output Current (Sourcing) Output Current (Sinking) 25°C RL = 1 kΩ RL = 10 Ω RL = 10 Ω 0.2/4.8 0°C to 70°C 0.25/4.75 –40°C to +85°C 0.25/4.75 25°C 24 0°C to 70°C 20 –40°C to +85°C 20 25°C 30 0°C to 70°C 25 –40°C to +85°C 25 25°C Output Impedance f = 1 MHz 0.15/4.85 V 33 mA 44 mA 1 Ω 0°C to 70°C –40°C to +85°C POWER SUPPLY 25°C Maximum Operating Voltage Minimum Operating Voltage 5 16.5 –40°C to +85°C 16.5 25°C 2.7 0°C to 70°C 2.7 –40°C to +85°C 2.7 25°C Maximum Quiescent Current V 0.75 0°C to 70°C Power-Supply Rejection (–PSRR) 8 0.9 0.98 mA 1.0 25°C Power-Supply Rejection (+PSRR) V 5 –40°C to +85°C Minimum Quiescent Current 16.5 0°C to 70°C 0.6 0°C to 70°C 0.57 –40°C to +85°C 0.55 VS+ = 5.5 V to 4.5 V, VS– = 0 V VS+ = 5 V, VS– = 0 V to 1.0 V 25°C 80 0°C to 70°C 75 –40°C to +85°C 75 25°C 80 0°C to 70°C 75 –40°C to +85°C 75 Submit Documentation Feedback 0.75 mA 100 dB 100 dB Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 6.7 Electrical Characteristics, VS = ±5 V At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE Small-Signal Bandwidth G = +1, VO = 100 mVPP, RF = 34 Ω 95 MHz G = +2, VO = 100 mVPP 40 MHz G = +5, VO = 100 mVPP 8 MHz G = +10, VO = 100 mVPP 3.8 MHz 0.1-dB Flat Bandwidth G = +2, VO = 100 mVPP 20 MHz Full-Power Bandwidth G = +1, VO = 2 VPP 9.5 MHz G = +1, VO = 2-V Step 35 V/μs G = –1, VO = 2-V Step 35 V/μs Settling Time to 0.1% G = –1, VO = 2-V Step 78 ns Settling Time to 0.01% G = –1, VO = 2-V Step 140 ns Rise/Fall Times G = +1, VO = 2-V Step 45 ns Slew Rate AC PERFORMANCE— HARMONIC DISTORTION Second Harmonic Distortion Third Harmonic Distortion G = +2, VO = 2 VPP, f = 1 MHz, RL = 1 kΩ –69 G = +2, VO = 2 VPP, f = 100 kHz, RL = 1 kΩ –76 G = +2, VO = 2 VPP, f = 1 MHz, RL = 1 kΩ –93 G = +2, VO = 2 VPP, f = 100 kHz, RL = 1 kΩ THD + N dBc dBc –107 G = +2, VO = 2 VPP, VO = 2 VPP, f = 10 kHz 0.0009 G = +2, VO = 2 VPP, VO = 4 VPP, f = 10 kHz 0.0003% G = +2, RL = 150 Ω 0.03/0.03 % Differential Gain (NTSC/PAL) Differential Phase (NTSC/PAL) 0.08/0.1 º Input Voltage Noise f = 100 kHz 12.5 nV/√Hz Input Current Noise f = 100 kHz 1.5 pA/√Hz DC PERFORMANCE Open-Loop Voltage Gain (AOL) 25°C 90 0°C to 70°C 85 –40°C to +85°C Input Offset Voltage Average Offset Voltage Drift VCM = 0 V Input Bias Current VCM = 0 V Average Bias Current Drift VCM = 0 V Input Offset Current VCM = 0 V Average Offset Current Drift VCM = 0 V dB 85 25°C VCM = 0 V 108 0.5 2.5 0°C to 70°C 3.5 –40°C to +85°C 3.5 0°C to 70°C ±7 –40°C to +85°C ±7 25°C 0.5 μV/°C 0.8 0°C to 70°C 1 –40°C to +85°C 1 0°C to 70°C ±2 –40°C to +85°C ±2 25°C 0.1 0.4 0.5 –40°C to +85°C 0.5 ±2 –40°C to +85°C ±2 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 μA nA/°C 0°C to 70°C 0°C to 70°C mV μA nA/°C 9 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Electrical Characteristics, VS = ±5 V (continued) At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX 25°C ±5.3 ±5.4 0°C to 70°C ±5.1 UNIT INPUT CHARACTERISTICS Common-Mode Input Range –40°C to +85°C Common-Mode Rejection Ratio VCM = –5 V to +5 V Input Resistance Common-mode Input Capacitance Common-mode/Differential V ±5.1 25°C 90 0°C to 70°C 85 –40°C to +85°C 85 107 dB 100 MΩ 0.8/1.2 pF ±4.93 V OUTPUT CHARACTERISTICS RL = 10 kΩ Output Voltage Swing Output Current (Sourcing) Output Current (Sinking) Output Impedance RL = 1 kΩ RL = 10 Ω RL = 10 Ω 25°C ±4.6 0°C to 70°C ±4.5 –40°C to +85°C ±4.5 25°C 35 0°C to 70°C 30 –40°C to +85°C 30 25°C 45 0°C to 70°C 40 –40°C to +85°C 40 f = 1 MHz ±4.8 V 48 mA 60 mA Ω 1 POWER SUPPLY Maximum Operating Voltage Minimum Operating Voltage Maximum Quiescent Current ±5 25°C 0°C to 70°C ±8.2 5 –40°C to +85°C ±8.2 5 25°C ±1.35 0°C to 70°C ±1.35 –40°C to +85°C ±1.35 25°C V 0.8 25°C 0.67 0°C to 70°C 0.62 10 0.8 mA 0.6 VS+ = 5.5 V to 4.5 V, VS– = 5.0 V 25°C VS+ = 5 V, VS– = –5.5 V to –4.5 V mA 1.05 –40°C to +85°C Power-Supply Rejection (–PSRR) 0.93 1.0 –40°C to +85°C Power-Supply Rejection (+PSRR) V ±5 0°C to 70°C Minimum Quiescent Current ±8.2 5 80 0°C to 70°C 75 –40°C to +85°C 75 25°C 80 0°C to 70°C 75 –40°C to +85°C 75 Submit Documentation Feedback 100 dB 100 dB Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 6.8 Dissipation Ratings PACKAGE (1) POWER RATING (1) TA < +25°C TA = +85°C DBV (5) 391 mW 156 mW D (8) 1.02 W 410 mW DGK (8) 553 mW 221 mW Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and long term reliability. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 11 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com 6.9 Typical Characteristics VS = 3 V Figure 1. Quiescent Current vs Supply Voltage Figure 2. Input Offset Voltage vs Common-mode Input Voltage VS = 15 V VS = ±5 V 12 VS = 5 V Figure 3. Input Offset Voltage vs Common-Mode Input Voltage Figure 4. Input Offset Voltage vs Common-Mode Input Voltage Figure 5. Positive Voltage Headroom vs Source Current Figure 6. Negative Voltage Headroom vs Sink Current Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 Typical Characteristics (continued) VS = 5 V VS = ±5 V Figure 7. Output Voltage vs Load Resistance Figure 8. Output Voltage vs Load Resistance 6 Gain = 1, RF = 34 W, RL = 1 kW, VO = 100 mVPP 5 Signal Gain − dB 4 3 VS = 15 V VS = 2.7 V VS = 5 V 2 VS = ±5 V 1 0 −1 −2 −3 −4 1 VS = 15 V) 10 100 f − Frequency − MHz Figure 9. Output Voltage vs Load Resistance Figure 10. Frequency Response 9 RF = 4 kW Signal Gain − dB 6 RF = 1.65 kW RF = 1 kW 3 0 VS = 2.7 V Gain = 2, RL = 1 kW, VO = 0.1 VPP −3 0.1 1 10 f − Frequency − MHz 100 VS = 3 V VS = 2.7 V Figure 11. Frequency Response Figure 12. Frequency Response Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 13 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics (continued) VS = ±5 V VS = 5 V Figure 14. Frequency Response Figure 13. Frequency Response VS = 2.7 V VS = 3 V VS = 5 V, ±5 V, 15 V Figure 16. 0.1-dB Frequency Response Figure 15. 0.1-dB Frequency Response 24 VS = 2.7 V, RF = 1.65 kW, RL = 1 kW, VO = 0.1 VPP G = 10 Signal Gain − dB 20 16 G=5 12 8 G=2 4 G = −1 0 −4 0.1 1 10 100 f − Frequency − MHz VS = 3 V VS = 2.7 V Figure 17. Frequency Response 14 Submit Documentation Feedback Figure 18. Frequency Response Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 Typical Characteristics (continued) VS = 5 V VS = ±5 V Figure 19. Frequency Response VS = 15 V Figure 20. Frequency Response VS = 2.7 V Figure 21. Frequency Response VS = 5 V Figure 22. Large-Signal Frequency Response VS = ±5 V Figure 23. Large-Signal Frequency Response Figure 24. Large-Signal Frequency Response Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 15 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics (continued) Figure 25. Open-Loop Gain vs Frequency Figure 26. Output Impedance vs Frequency Figure 27. Rejection Ratio vs Frequency Figure 28. Noise vs Frequency VS = 5 V VS = 2.7 V Figure 30. Slew Rate Figure 29. Slew Rate 16 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 Typical Characteristics (continued) VS = ±5 V VS = 15 V Figure 31. Slew Rate VS = ±1.35 V Figure 32. Slew Rate VS = ±1.35 V Figure 33. Settling Time Figure 34. Settling Time VS = ±2.5 V VS = ±2.5 V Figure 36. Settling Time Figure 35. Settling Time Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 17 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics (continued) VS = ±5 V VS = ±5 V Figure 38. Settling Time Figure 37. Settling Time Gain = +1 Gain = +1 Figure 39. Harmonic Distortion vs Frequency Gain = +2 VS = 3 V, 3.3 V Figure 41. Harmonic Distortion vs Frequency 18 Figure 40. Harmonic Distortion vs Frequency Figure 42. Harmonic Distortion vs Frequency Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 Typical Characteristics (continued) Gain = +2 Figure 43. Harmonic Distortion vs Frequency Figure 44. Harmonic Distortion vs Load Resistance VS = 3 V, ±5 V \ VS = 2.7 V, 5 V Figure 45. Harmonic Distortion vs Output Voltage VS = 3.3 V, 15 V Figure 46. Harmonic Distortion vs Output Voltage VS = 2.7 V Figure 47. Harmonic Distortion vs Output Voltage Figure 48. Total Harmonic Distortion + Noise vs Frequency Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 19 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics (continued) VS = 5 V VS = 3 V Figure 49. Total Harmonic Distortion + Noise vs Frequency Figure 50. Total Harmonic Distortion + Noise vs Frequency VS = 15 V VS = ±5 V Figure 51. Total Harmonic Distortion + Noise vs Frequency Figure 52. Total Harmonic Distortion + Noise vs Frequency f = 1 kHz f = 10 kHz Figure 53. Total Harmonic Distortion + Noise vs Output Voltage 20 Figure 54. Total Harmonic Distortion + Noise vs Output Voltage Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 Typical Characteristics (continued) 0.8 PAL 0.7 Differential Gain − % 0.6 0.5 NTSC 0.4 0.3 Gain = 2 RF= 2.5 kW VS = 5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.2 0.1 0 1 f = 100 kHz 2 3 Number of Loads − 150 W VS = 5 V Figure 55. Total Harmonic Distortion + Noise vs Output Voltage Figure 56. Differential Gain vs Number of Loads 2 1.6 1.8 1.4 PAL 1.6 ° Differential Gain − % Differential Phase − NTSC 1.4 1.2 1 0.8 0.6 Gain = 2 Rf = 2.5 kW VS = 5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.4 0.2 0 1 2 Number of Loads − 150 W PAL 1.2 1 0.8 NTSC 0.6 Gain = 2 RF= 2.5 kW VS = ±5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.4 0.2 0 3 1 2 3 Number of Loads − 150 W VS = ±5 V VS = 5 V Figure 57. Differential Phase vs Number of Loads Figure 58. Differential Gain vs Number of Loads 1.6 1.4 PAL Differential Phase − ° 1.2 1 NTSC 0.8 0.6 Gain = 2 Rf = 2.5 kW VS = ±5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.4 0.2 0 1 2 Number of Loads − 150 W 3 VS = ±5 V Figure 59. Differential Phase vs Number of Loads Figure 60. Input Offset Voltage vs Temperature Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 21 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics (continued) VS = 15 V VS = 5 V Figure 61. Input Bias and Offset Current vs Temperature Figure 62. Input Bias and Offset Current vs Temperature Figure 63. Small-Signal Transient Response Figure 64. Large-Signal Transient Response VS = 5 V VS = ±5 V Figure 65. Overdrive Recovery Time 22 Submit Documentation Feedback Figure 66. Overdrive Recovery Time Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 Typical Characteristics (continued) Figure 67. Overdrive Response Output Voltage vs Time Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 23 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com 7 Detailed Description 7.1 Overview 7.1.1 High-Speed Operational Amplifiers The THS4281 is a unity gain stable, rail-to-rail input and output, voltage-feedback operational amplifier designed to operate from a single 2.7-V to 16.5-V power supply. 7.2 Feature Description 7.2.1 Wideband, Noninverting Operation Figure 68 shows the noninverting gain configuration of 2 V/V used to demonstrate the typical performance curves. Voltage feedback amplifiers can use a wide range of resistors values to set their gain with minimal impact on frequency response. Larger-valued resistors decrease loading of the feedback network on the output of the amplifier, but may cause peaking and instability. For a gain of +2, feedback resistor values between 1 kΩ and 4 kΩ are recommended for most applications. However, as the gain increases, the use of even higher feedback resistors can be used to conserve power. This is due to the inherent nature of amplifiers becoming more stable as the gain increases, at the expense of bandwidth. Figure 73 and Figure 74 show the THS4281 using feedback resistors of 10 kΩ and 100 kΩ. Be cautioned that using such high values with high-speed amplifiers is not typically recommended, but under certain conditions, such as high gain and good high-speed printed circuit board (PCB) layout practices, such resistances can be used. +VS + 0.1 µF 6.8 µF 50-W Source + VI 49.9 W VO _ Rf 2.49 kW To Load 2.49 kW Rg 0.1 µF 6.8 µF + −VS Figure 68. Wideband, Noninverting Gain Configuration 7.2.2 Wideband, Inverting Operation Figure 69 shows a typical inverting configuration where the input and output impedances and noise gain from Figure 68 are retained with an inverting circuit gain of –1 V/V. 24 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 Feature Description (continued) +VS + 0.1 µF 6.8 µF + RT 1.24 kW CT 0.1 µF VO _ To Load 50-W Source Rg VI Rf 2.49 kW RM 51.1 W 2.49 kW 0.1 µF 6.8 µF + −VS Figure 69. Wideband, Inverting Gain Configuration In the inverting configuration, some key design considerations must be noted. One is that the gain resistor (Rg) becomes part of the signal channel input impedance. If the input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PCB trace, or other transmission line conductors), Rg may be set equal to the required termination value and Rf adjusted to give the desired gain. However, care must be taken when dealing with low inverting gains, as the resulting feedback resistor value can present a significant load to the amplifier output. For example, an inverting gain of 2, setting Rg to 49.9 Ω for input matching, eliminates the need for RM but requires a 100-Ω feedback resistor. The 100-Ω feedback resistor, in parallel with the external load, causes excessive loading on the amplifier output. To eliminate this excessive loading, it is preferable to increase both Rg and Rf values, as shown in Figure 69, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance is the parallel combination of Rg and RM. Another consideration in inverting amplifier design is setting the bias current cancellation resistor (RT) on the noninverting input. If the resistance is set equal to the total dc resistance presented to the device at the inverting terminal, the output dc error (due to the input bias currents) is reduced to the input offset current multiplied by RT. In Figure 69, the dc source impedance presented at the inverting terminal is 2.49 kΩ || (2.49 kΩ + 25.3 Ω) ≈ 1.24 kΩ. To reduce the additional high-frequency noise introduced by the resistor at the noninverting input, RT is bypassed with a 0.1-μF capacitor to ground (CT). 7.3 Device Functional Modes This device has no specific function modes. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 25 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Single-Supply Operation The THS4281 is designed to operate from a single 2.7-V to 16.5-V power supply. When operating from a single power supply, care must be taken to ensure the input signal and amplifier are biased appropriately to allow for the maximum output voltage swing and not violate VICR. The circuits shown in Figure 70 shows inverting and noninverting amplifiers configured for single-supply operation. +VS 50-W Source + VI RT 49.9 W VO _ To Load +VS Rf 2 Rg 2 kW 2 kW Power Supply Bypassing Not Shown For Simplicity +VS 2 Rf VS 2 kW 50-W Source Rg VI RT 51.1 W _ 2 kW +VS +VS 2 2 RT + VO To Load CT Figure 70. DC-Coupled Single Supply Operation 8.1.2 Driving Capacitive Loads One of the most demanding, and yet common, load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter, including additional external capacitance, which may be recommended to improve A/D linearity. A high-speed, high open-loop gain amplifier like the THS4281 can be susceptible to instability and peaking when a capacitive load is placed directly on the output. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the feedback path that decreases the phase margin. When the primary considerations are frequency response flatness, pulse response fidelity, or distortion, a simple and effective solution is to isolate the capacitive load from the feedback loop by inserting a small series isolation resistor (for example, R(ISO) = 100 Ω for CLOAD = 10 pF to R(ISO) = 10 Ω for CLOAD = 1000 pF) between the amplifier output and the capacitive load. 26 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 8.2 Typical Application 2 kW 2.05 kW 2 kW 270 pF 5V _ 649 VO 2.61 kW + VI 1.5 nF 1 nF RL 1 kW −5V 1.02 kW 2.1 kW VI 5V _ VO + 2.2 nF −5V Figure 71. Second-Order Sallen-Key 100-kHz Butterworth Filter, Gain = 2 V/V RL 1 kW Figure 72. Second-Order MFB 100-kHz Butterworth Filter, Gain = 2 V/V 8.2.1 Design Requirements Table 1 shows example design parameters and values for the typical application design example in Figure 71. Table 1. Design Parameters DESIGN PARAMETERS VALUE Supply voltage ±5 V Amplifier topology Voltage feedback Gain 2 V/V Filter requirement Second Order 100 KHz Sallen- Key Butterworth Filter Input/Output Requirements Rail to Rail 8.2.2 Detailed Design Procedure 8.2.2.1 Active Filtering With the THS4281 High-performance active filtering with the THS4281 is achievable due to the amplifier's good slew rate, wide bandwidth, and voltage-feedback architecture. Several options are available for high-pass, low-pass, bandpass, and bandstop filters of varying orders. Filters can be quite complex and time consuming to design. Several books and application reports are available to help design active filters. But, to help simplify the process and minimize the chance of miscalculations, Texas Instruments has developed a filter design program called FilterPro™. FilterPro is available for download at no cost from TI's web site (www.ti.com). The two most common low-pass filter circuits used are the Sallen-Key filter and the Multiple Feedback (MFB) – aka Rauch filter. FilterPro was used to determine a 2-pole Butterworth response filter with a corner (–3-dB) frequency of 100 kHz, which is shown in Figure 71 and Figure 72. One of the advantages of the MFB filter, a much better high-frequency rejection, is clearly shown in the response shown in Figure 75. This is due to the inherent R-C filter to ground being the first elements in the design of the MFB filter. The Sallen-Key design also has an R-C filter, but the capacitor connects directly to the output. At very high frequencies, where the amplifier's access loop gain is decreasing, the ability of the amplifier to reject high frequencies is severely reduced and allows the high-frequency signals to pass through the system. One other advantage of the MFB filter is the reduced sensitivity in component variation. This is important when using real-world components where capacitors can easily have ±10% variations. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 27 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com 8.2.3 Application Curves 24 24 RF = 100 kW RF = 1.65 kW and 10 kW 16 12 8 VS = 3 V Gain = 10, RL = 1 kW, VO = 0.1 VPP 4 1 RF = 2.5 kW and 10 kW 16 12 8 VS = ±5 V Gain = 10, RL = 1 kW, VO = 0.1 VPP 4 0 0.1 RF = 100 kW 20 Signal Gain − dB Signal Gain − dB 20 10 100 0 0.1 1 10 f − Frequency − MHz f − Frequency − MHz Figure 73. Signal Gain vs Frequency, VS = 3 V Figure 74. Signal Gain vs Frequency, VS = ±5 V 100 Figure 75. Second-Order 100-kHz Active Filter Response 28 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 9 Power Supply Recommendations 9.1 Power-Supply Decoupling Techniques and Recommendations Power-supply decoupling is a critical aspect of any high-performance amplifier design. Careful decoupling provides higher quality ac performance. The following guidelines ensure the highest level of performance. 1. Place decoupling capacitors as close to the power-supply inputs as possible, with the goal of minimizing the inductance. 2. Placement priority should put the smallest valued capacitors closest to the device. 3. Use of solid power and ground planes is recommended to reduce the inductance along power-supply return current paths (with the exception of the areas underneath the input and output pins as noted below). 4. A bulk decoupling capacitor is recommended (6.8 μF to 22 μF) within 1 inch, and a ceramic (0.1 μF) within 0.1 inch of the power input pins. NOTE The bulk capacitor may be shared by other operational amplifiers. 10 Layout 10.1 Layout Guidelines Achieving optimum performance with a high-frequency amplifier like the THS4281 requires careful attention to board layout parasitics and external component types. See the EVM layout figures (Figure 76 to Figure 79) in the Design Tools section. Recommendations that optimize performance include: 1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability and on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. 2. Minimize the distance (< 0.1 inch) from the power-supply pins to high-frequency, 0.1-μF decoupling capacitors. Avoid narrow power and ground traces to minimize inductance. The power-supply connections should always be decoupled as described above. 3. Careful selection and placement of external components preserves the high-frequency performance of the THS4281. Resistors should be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film, axial-lead resistors can also provide good high-frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Excessively high resistor values can create significant phase lag that can degrade performance. Keep resistor values as low as possible, consistent with load-driving considerations. It is suggested that a good starting point for design is to set the Rf to 2 kΩ for low-gain, noninverting applications. Doing this automatically keeps the resistor noise terms reasonable and minimizes the effect of parasitic capacitance. 4. Connections to other wideband devices on the board should be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Low parasitic capacitive loads (< 4 pF) may not need an R(ISO), because the THS4281 is nominally compensated to operate at unity gain (+1 V/V) with a 2-pF capacitive load. Higher capacitive loads without an R(ISO) are allowed as the signal gain increases. If a long trace is required, and the 6-dB signal loss intrinsic to a doubly terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A matching series resistor into the trace from the output of the THS4281 is used as well as a terminating shunt resistor at the input of the destination Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 29 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Layout Guidelines (continued) device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case, and use a series resistor (R(ISO) = 10 Ω to 100 Ω, as noted Driving Capacitive Loads) to isolate the capacitive load. If the input impedance of the destination device is low, there is signal attenuation due to the voltage divider formed by R(ISO) into the terminating impedance. A 50-Ω environment is normally not necessary onboard, and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots. 5. Socketing a high-speed part like the THS4281 is not recommended. The additional lead length and pinto-pin capacitance introduced by the socket can create a troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS4281 onto the board. 10.2 Layout Examples TOP Figure 76. THS4281EVM Layout (Top Layer and Silkscreen Layer) 30 Submit Documentation Feedback Layer 2 − GND Figure 77. THS4281EVM Board Layout Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 Layout Examples (continued) Layer 3 − GND Figure 78. THS4281EVM Board Layout BOTTOM Figure 79. THS4281EVM Board Layout 10.3 Thermal Considerations The THS4281 does not incorporate automatic thermal shutoff protection, so the designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute maximum junction temperature of +150°C is exceeded. For long-term dependability, the junction temperature should not exceed +125°C. The thermal characteristics of the device are dictated by the package and the PCB. Maximum power dissipation for a given package can be calculated using the following formula. PDmax = (Tmax - TA) / θJA where • • • • • • PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junciton temperature (ºC). TA is the ambient temperature (ºC). θJA = θJC + θCA θJC is the thermal coefficient from the silicon junctions to the case (ºC/W). θJA is the thermal coefficient from the case to ambient air (ºC/W). (1) Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 31 THS4281 SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 www.ti.com Thermal Considerations (continued) P D − Maximum Power Dissipation − W 1.8 1.6 8-pin SOIC (D) Package 1.4 8-pin MSOP (DGK) Package 1.2 1 0.8 0.6 0.4 0.2 0 −40 5-pin SOT23 (DBV) Package −20 0 20 40 60 80 TA − Free-Air Temperature − °C 100 ΘJA = 97.5°C/W for 8-Pin SOIC (D) ΘJA = 180.8°C/W for 8-Pin MSOP (DGK) ΘJA = 255.4°C/W for 5-Pin SOT−23 (DBV) TJ = 125°C, No Airflow Figure 80. Maximum Power Dissipation vs Ambient Temperature When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often maximum power dissipation is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS value can provide a reasonable analysis. 32 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 THS4281 www.ti.com SLOS432B – APRIL 2004 – REVISED OCTOBER 2015 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation, see the following: • PowerPAD Made Easy, application brief (SLMA004) • PowerPAD Thermally Enhanced Package, technical brief (SLMA002) • Active Low-Pass Filter Design, application report (SLOA049) • FilterPro MFB and Sallen-Key Low-Pass Filter Design Program, application report (SBFA001) 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks FilterPro, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: THS4281 33 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) THS4281D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4281 THS4281DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AON THS4281DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AON THS4281DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AON THS4281DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AOO THS4281DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AOO THS4281DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4281 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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