THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
Wideband Operational Amplifier
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
Wide Bandwidth: 3 GHz
High Slew Rate: 830 V/µs
Low Voltage Noise: 2.4 nV/√Hz
Single Supply: 5 V, 3 V
Quiescent Current: 18 mA
Active Filter
ADC Driver
Ultrasound
Gamma Camera
RF/Telecom
DESCRIPTION
The THS4304 is a wideband, voltage-feedback operational amplifier designed for use in high-speed analog
signal-processing chains operating with a single 5-V power supply. Developed in the BiCom3 silicon germanium
process technology, the THS4304 offers best-in-class performance using a single 5-V supply as opposed to
previous generations of operational amplifiers requiring ±5-V supplies.
The THS4304 is a traditional voltage-feedback topology that provides the following benefits: balanced inputs, low
offset voltage and offset current, low offset drift, high common mode and power supply rejection ratio.
The THS4304 is offered in 8-pin MSOP package (DGK), the 8-pin SOIC package (D), and the space-saving 5-pin
SOT-23 package (DBV).
DIFFERENTIAL ADC DRIVE
+5V
10 kΩ
90
V REF (= 2.5V)
RG
RF
0.1 µF
10 kΩ
Combined THS4304 and
ADS5500 SFDR
V REF
85
+5V
V IN
dB
+3.3 VA +3.3 VD
THS 4304
1: 1
100 Ω
V REF
From
50−Ω
source
49 .9 Ω
1nF
1k Ω
CM
+5V
A IN+
80
ADS 5500
1k Ω
A IN−
CM
D
G = 10 dB,
RF = 249 Ω,
RG = 115 Ω,
SNR = 69.6,
FS = 125 MSPS
A
THS 4304
100 Ω
1nF
CM
0.1 µF
75
10
20
30
40
50
f − Frequency − MHz
V REF
RG
RF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PINOUT DRAWING
TOP VIEW
DBV
VOUT
1
VS−
2
IN+
3
5
4
TOP VIEW
VS+
D and DGK
NC
1
8
NC
IN−
2
7
VS+
IN+
3
6
VOUT
VS−
4
5
VOUT
IN−
NOTE: NC indicates there is no internal connection to these pins.
PACKAGING / ORDERING INFORMATION
PACKAGED DEVICES
THS4304DBVT
THS4304DBVR
THS4304D
THS4304DR
THS4304DGK
THS4304DGKR
PACKAGE TYPE
PACKAGE MARKINGS
SOT-23-5
AKW
SOIC-8
—
MSOP-8
AKU
TRANSPORT MEDIA,
QUANTITY
Tape and Reel, 250
Tape and Reel, 3000
Rails, 75
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
DISSIPATION RATINGS
(1)
(2)
2
POWER RATING (2)
PACKAGE
θJC
(°C/W)
θJA
(°C/W) (1)
TA≤ 25°C
TA = 85°C
DBV (5)
55
255.4
391 mW
156 mW
D (8)
38.3
97.5
1.02 W
410 mW
DGK (8)
71.5
180.8
553 mW
221 mW
This data was taken using the JEDEC standard High-K test PCB.
Power rating determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal
management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term
reliability.
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VS
Supply voltage
VI
Input voltage
+6.0 V
IO
Output current
VID
Differential input voltage
±VS
150 mA
±2 V
Continuous power dissipation
TJ
Tstg
See Dissipation Rating Table
Maximum junction temperature, any condition (2)
150°C
Operating free-air temperature range, continuous operation, long-term reliability (2)
125°C
Storage temperature range
–65°C to 150°C
Lead temperature: 1,6 mm (1/16 inch) from case for 10 seconds
ESD Ratings
(1)
(2)
300°C
HBM
1600 V
CDM
1000 V
MM
100 V
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
Supply voltage, (VS+ and VS–)
Input common-mode voltage range
Dual supply
Single supply
MIN
MAX
±1.35
±2.5
2.7
5
VS–– 0.2
VS+ + 0.2
UNIT
V
V
3
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
Specifications: VS = 5 V: RF = 249 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
TYP
PARAMETER
CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
–40°C to
85°C
TEST
LEVEL (1)
UNITS
MIN/
MAX
GHz
Typ
C
AC PERFORMANCE
G = +1, VO = 100 mVpp
3
G = +2, VO = 100 mVpp
1
GHz
Typ
C
G = +5, VO = 100 mVpp
187
MHz
Typ
C
G = +10, VO = 100 mVpp
87
MHz
Typ
C
Gain Bandwidth Product
G >+10
870
MHz
Typ
C
0.1-dB Flat Bandwidth
G= +2, VO = 100 mVpp,
CF = 0.5 pF
300
MHz
Typ
Large-Signal Bandwidth
G = +2, VO = 2 VPP
240
MHz
Typ
C
G = +2, VO = 1-V Step
830
V/µs
Typ
C
G = +2, VO = 2-V Step
790
V/µs
Typ
C
Settling Time to 1%
G = –2, VO = 2-V Step
4.5
ns
Typ
C
Settling Time to 0.1%
G = –2, VO = 2-V Step
7.5
ns
Typ
C
Settling Time to 0.01%
G = –2, VO = 2-V Step
35
ns
Typ
C
Rise / Fall Times
G = +2, VO = 2-V Step
2.5
ns
Typ
C
RL= 100 Ω
–84
dBc
Typ
C
RL = 1 kΩ
–95
dBc
Typ
C
RL = 100 Ω
–100
dBc
Typ
C
RL = 1 kΩ
–100
dBc
Typ
C
–84
dBc
Typ
C
48
dBm
Typ
C
Small-Signal Bandwidth
Slew Rate
C
Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
Third-Order Intermodulation
Distortion (IMD3)
Third-Order Output Intercept
(OIP3)
G = +2,
VO = 2 VPP,
f = 10 MHz
G = +2, VO= 2-VPP envelope,
200-kHz tone spacing,
f = 20 MHz
Noise Figure
G = +2, f = 1 GHz
15
dB
Typ
C
Input Voltage Noise
f = 1 MHz
2.4
nV/√Hz
Typ
C
Input Current Noise
f = 1 MHz
2.1
pA/√Hz
Typ
C
VO = ± 0.8 V, VCM = 2.5 V
65
54
50
50
dB
Min
A
0.5
4
5
5
mV
Max
A
5
5
µV/°C
Typ
B
18
µA
Max
A
DC PERFORMANCE
Open-Loop Voltage Gain
(AOL)
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
VCM = 2.5 V
Input Offset Current
7
12
18
50
50
nA/°C
Typ
B
0.5
1
1.2
1.2
µA
Max
A
10
10
nA/°C
Typ
B
A
Input Offset Current Drift
INPUT CHARACTERISTICS
Common-Mode Input Range
Common-Mode Rejection
Ratio
Input Resistance
Input Capacitance
(1)
4
VO = ± 0.2 V, VCM = 2.5 V
Each input, referenced to GND
–0.2 to
5.2
0.2 to
4.8
0.4 to
4.6
0.4 to
4.6
V
Min
95
80
73
73
dB
Min
100
kΩ
Typ
C
1.5
pF
Typ
C
A
Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
THS4304
www.ti.com
SLOS436A – MARCH 2004 – REVISED JULY 2004
ELECTRICAL CHARACTERISTICS (continued)
Specifications: VS = 5 V: RF = 249 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
PARAMETER
CONDITIONS
TYP
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
–40°C to
85°C
1.1 to
3.9
1.2 to
3.8
1.3 to
3.7
1.3 to
3.7
1 to 4
1.1 to
3.9
1.2 to
3.8
1.2 to
3.8
140
100
57
92
65
40
TEST
LEVEL (1)
UNITS
MIN/
MAX
V
Min
A
57
mA
Min
A
40
mA
Min
A
Ω
Typ
A
OUTPUT CHARACTERISTICS
RL = 100 Ω
Output Voltage Swing
RL = 1 kΩ
Output Current (Sourcing)
RL = 10 Ω
Output Current (Sinking)
RL = 10 Ω
Output Impedance
f = 100 kHz
0.016
POWER SUPPLY
Maximum Operating Voltage
5
5.5
5.5
5.5
Minimum Operating Voltage
5
2.7
2.7
2.7
Maximum Quiescent Current
18
18.9
19.4
19.4
mA
Max
A
Minimum Quiescent Current
18
17.5
16.6
16.6
mA
Min
A
V
Max
Min
A
Power Supply Rejection
(+PSRR)
VS+ = 5.5 V to 4.5 V, VS– = 0 V
80
73
66
66
dB
Min
A
Power Supply Rejection
(-PSRR)
VS+ = 5 V, VS– = –0.5 V to +0.5
V
60
57
54
54
dB
Min
A
5
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
Specifications: VS = 3 V: RF = 249 Ω, RL = 499 Ω, and G = +2 unless otherwise noted
TYP
PARAMETER
CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
–40°C
to
85°C
UNITS
MIN/
MAX
TEST
LEVEL (1)
AC PERFORMANCE
Small-Signal Bandwidth
G = +1, VO = 100 mVpp
3
GHz
Typ
C
G = +2, VO = 100 mVpp
900
MHz
Typ
C
G = +5, VO = 100 mVpp
190
MHz
Typ
C
G = +10, VO = 100 mVpp
83
MHz
Typ
C
Gain Bandwidth Product
G >+10
830
MHz
Typ
C
Large-Signal Bandwidth
G = +2, VO = 1 VPP
450
MHz
Typ
C
G = +2, VO = 1-V Step
750
V/µs
Typ
C
Slew Rate
G = +2, VO = 1-V Step
675
V/µs
Typ
C
Settling Time to 1%
G = –2, VO = 0.5-V Step
4.5
ns
Typ
C
Settling Time to 0.1%
G = –2, VO = 0.5-V Step
20
ns
Typ
C
Rise / Fall Times
G = +2, VO = 0.5-V Step
1.5
ns
Typ
C
G = +2,
VO = 0.5 VPP,
f = 10 MHz
–92
dBc
Typ
C
–91
dBc
Typ
C
Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
RL = 499 Ω
Noise Figure
G = +2, f = 1 GHz
15
dB
Typ
C
Input Voltage Noise
f = 1 MHz
2.4
nV/√Hz
Typ
C
Input Current Noise
f = 1 MHz
2.1
pA/√Hz
Typ
C
VO = ± 0.5 V, VCM = 1.5 V
49
44
dB
Min
A
2
4
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
VCM = 1.5 V
Input Offset Current
7
0.4
12
1
Input Offset Current Drift
5
5
mV
Max
A
5
5
µV/°C
Typ
B
18
18
µA
Max
A
50
50
nA/°C
Typ
B
1.2
1.2
µA
Max
A
10
10
nA/°C
Typ
B
V
Min
A
INPUT CHARACTERISTICS
Common-Mode Input Range
Common-Mode Rejection Ratio
Input Resistance
Input Capacitance
(1)
6
VO = ± 0.09 V, VCM = 1.5 V
Each input, referenced to GND
–0.2
to 3.2
0.2 to
2.8
0.4 to
2.6
0.4 to
2.6
92
80
70
70
dB
Min
A
100
kΩ
Typ
C
1.5
pF
Typ
C
Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
ELECTRICAL CHARACTERISTICS (continued)
Specifications: VS = 3 V: RF = 249 Ω, RL = 499 Ω, and G = +2 unless otherwise noted
TYP
PARAMETER
CONDITIONS
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
–40°C
to
85°C
1.1 to
1.9
1.2 to
1.8
1.3 to
1.7
1.3 to
1.7
1 to 2
1.1 to
1.9
1.2 to
1.8
1.2 to
1.8
TEST
LEVEL (1)
UNITS
MIN/
MAX
V
Min
A
OUTPUT CHARACTERISTIC
RL = 100 Ω
Output Voltage Swing
RL = 1 kΩ
Output Current (Sourcing)
RL = 10 Ω
57
50
40
40
mA
Min
A
Output Current (Sinking)
RL = 10 Ω
57
45
35
35
mA
Min
A
Output Impedance
f = 100 kHz
Ω
Typ
A
0.016
POWER SUPPLY
Maximum Operating Voltage
3
5.5
5.5
5.5
Minimum Operating Voltage
3
2.7
2.7
2.7
Maximum Quiescent Current
17.2
17.9
18.4
18.4
mA
Max
A
Minimum Quiescent Current
V
Max
Min
A
17.2
16.5
15.6
15.6
mA
Min
A
Power Supply Rejection (+PSRR)
VS+ = 3.3 V to 2.7 V, VS– = 0 V
80
60
54
54
dB
Min
A
Power Supply Rejection (-PSRR)
VS+ = 5 V, VS– = –0.5 V to +0.5 V
60
55
52
52
dB
Min
A
7
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
5V
Frequency response
1–3, 5, 6
0.1-dB Flatness
4
Frequency response by package
7
S-Parameters
vs Frequency
8
2nd Harmonic distortion
vs Frequency
9, 11
3rd Harmonic distortion
vs Frequency
10, 12
2nd Harmonic distortion
vs Output voltage
13
3rd Harmonic distortion
vs Output voltage
14
IMD3
3rd Order intermodulation distortion
vs Frequency
15
OIP3
3rd Order output intercept point
vs Frequency
16
SR
Slew rate
vs Output voltage
17
Vn/In
Noise
vs Frequency
18
Noise figure
vs Frequency
19
Quiescent current
vs Supply voltage
20
Rejection ratio
vs Frequency
21
VO
Output voltage
vs Load resistance
22
VOS
Input offset voltage
vs Input common-mode voltage
23
IIB
Input bias and offset current
vs Case temperature
24
VOS
Input offset voltage
vs Case temperature
25
Open-loop gain
vs Frequency
26
Iq
VO
Small-signal transient response
27
VO
Large-signal transient response
28
VO
Settling time
29
VO
Overdrive recovery time
ZO
Output impedance
30
vs Frequency
31
3V
Frequency response
32–35
2nd Harmonic distortion
vs Frequency
36
3rd Harmonic distortion
vs Frequency
37
Harmonic Distortion
vs Output voltage
38
SR
Slew rate
vs Output voltage
39
VO
Settling time
VO
Output voltage
vs Load resistance
41
IIB
Input bias and offset current
vs Case temperature
42
VOS
Input offset voltage
vs Case temperature
43
VO
Large-signal transient response
VO
Overdrive recovery time
ZO
Output impedance
8
40
44
45
vs Frequency
46
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
TYPICAL CHARACTERISTICS (5 V)
FREQUENCY RESPONSE
8
3
7
2
VO = 200 mVPP
0
VO = 400 mVPP
−1
−2
10 M
6
5
CF = 0.5 pF
CF = 1 pF
3
100 M
1G
0
10 G
1M
10 M
f − Frequency − Hz
0.1-dB FLATNESS
Gain = 2,
RF = 249 Ω,
CF = 0.5 pF,
RL = 100 Ω,
VO = 100 mVPP,
VS = 5 V
90 MHz
18
16
300 MHz
6
5.9
5.8
10 G
10
100 M
1G
100 M
18
16
8
6
4
480 MHz
RF = 0 Ω
87 MHz
20
RF = 249 Ω,
RL = 100 Ω,
VO = 1 VPP,
VS = 5 V
1G
10 G
12
10
175 MHz
8
6
4
240 MHz
RF = 0 Ω
0
−2
560 MHz
290 MHz
−4
10 M
100 M
1G
RF = 249 Ω,
RL = 100 Ω,
VO = 2 VPP,
VS = 5 V
14
2
10 G
1M
f − Frequency − Hz
10 M
100 M
1G
10 G
f − Frequency − Hz
Figure 4.
Figure 5.
Figure 6.
FREQUENCY RESPONSE
BY PACKAGE
S-PARAMETERS
vs
FREQUENCY
2ND HARMONIC DISTORTION
vs
FREQUENCY
−40
10
8
SOIC
−20
Signal Gain − dB
7
6
MSOP
5
4
Gain = 2,
RF = 249 Ω,
RL = 100 Ω,
VO = 100 mVPP,
VS = 5 V
10 M
S22
−40
S11
100 M
f − Frequency − Hz
Figure 7.
1G
10 G
S12
−60
Gain = 2,
RF = 249 Ω,
RL = 100 Ω,
VO = 100 mVPP,
VS = 5 V
−80
0
1M
S21
0
2nd Harmonic Distortion − dBc
SOT-23
9
Signal Gain − dB
10 M
FREQUENCY RESPONSE
200 MHz
f − Frequency − Hz
1
1M
Figure 3.
12
0
−2
−4
1M
5.6
2
G = 1, RF = 0 Ω
f − Frequency − Hz
14
2
5.7
3
G=2
22
20
10 M
8
6
4
FREQUENCY RESPONSE
6.1
1M
G=5
2
0
−2
−4
100 k
22
Signal Gain − dB
Signal Gain − dB
1G
16
14
12
10
Figure 2.
6.4
6.2
100 M
RF = 249 Ω,
RL = 100 Ω,
VO = 100 mVPP
VS = 5 V
G = 10
f − Frequency − Hz
Figure 1.
6.3
1 GHz
4
1
3 GHz
1M
CF = 0 pF
2
VO = 800 mVPP
−3
−4
Gain = 2,
RF = 249 Ω,
RL = 100 Ω,
VO = 100 mVPP,
VS = 5 V
9
VO = 100 mVPP
4
1
FREQUENCY RESPONSE
24
22
20
18
Signal Gain − dB
Gain = 1,
RL = 100 Ω,
VS = 5 V
Signal Gain − dB
Signal Gain − dB
5
FREQUENCY RESPONSE
10
Signal Gain − dB
6
−100
1M
10 M
100 M
f − Frequency − Hz
Figure 8.
1G
−50
−60
Gain = 2
RF = 249 Ω
VO = 2 VPP
VS = 5 V
SOT-23 RL = 100 Ω
MSOP RL = 100 Ω
−70
−80
−90
−100
MSOP and SOT-23 RL = 499 to 1 k Ω
10 G
−110
1M
10 M
100 M
f − Frequency − Hz
Figure 9.
9
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
TYPICAL CHARACTERISTICS (5 V) (continued)
3RD HARMONIC DISTORTION
vs
FREQUENCY
2ND HARMONIC DISTORTION
vs
FREQUENCY
−70
MSOP and SOT-23
RL = 100 Ω to 1 kΩ
−80
−90
−100
−50
−60
SOT-23 RL = 100 Ω
−70
MSOP RL = 100 Ω
−80
−90
−100
10 M
1M
1M
−70
−80
10 M
f − Frequency − Hz
MSOP and SOT-23
RL = 100 Ω to 1 kΩ
−90
−100
−110
10 M
1M
100 M
100 M
f − Frequency − Hz
Figure 10.
Figure 11.
Figure 12.
2ND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
3RD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
3RD ORDER
INTERMODULATION DISTORTION
vs
FREQUENCY
−40
−30
−70
SOT-23 RL = 100 Ω
−90
SOT-23 RL = 499 Ω to 1 kΩ
−50
−60
0.5
1
1.5
2
2.5
VO − Output Voltage − VPP
−70
−80
SOT-23 RL = 100 Ω to 1 kΩ
−70
−80
−90
−90
−100
−100
0
3
VO = 2 VPP
envelope
−60
−110
−110
0.5
1
1.5
2
2.5
3
−110
VO = 1 VPP
envelope
10 M
VO − Output Voltage − VPP
100 M
f − Frequency − Hz
Figure 13.
Figure 14.
Figure 15.
3RD ORDER
OUTPUT INTERCEPT POINT
vs
FREQUENCY
SLEW RATE
vs
OUTPUT VOLTAGE
NOISE
vs
FREQUENCY
900
60
50
SR − Slew Rate − V/ µ s
800
40
30
Gain = 2,
RF = 249 Ω,
RL = 100 Ω,
VO = 2−VPP envelope,
200−kHz Spacing,
VS = 5 V
10
f − Frequency − Hz
Figure 16.
750
Rise
700
Fall
650
600
550
500
100
In
10
Vn
450
1
100 M
10 M
1000
Gain = 2,
RF = 249 Ω,
RL = 100 Ω,
VS = 5 V
850
Hz
0
−50
Gain = 2,
RF = 249 Ω,
RL = 100 Ω,
200 kHz Spacing,
VS = 5 V
−40
V n − Voltage Noise − nV/
−80
−40
IMD 3 − dBc
−60
−30
Gain = 2,
RF = 249 Ω,
RL = 100 Ω,
f = 10 MHz,
VS = 5 V
Hz
−50
3rd Harmonic Distortion − dBc
Gain = 2,
RF = 249 Ω,
RL = 100 Ω,
f = 10 MHz,
VS = 5 V
−100
OIP 3 − dBm
−60
−110
100 M
f − Frequency − Hz
Gain = 2,
RF = 249 Ω,
VO = 1 VPP,
VS = 5 V
−50
MSOP and SOT-23 RL = 499 Ω to 1 kΩ
−110
10
3rd Harmonic Distortion − dBc
−60
Gain = 2
RF = 249 Ω
VO = 1 VPP
VS = 5 V
I n − Current Noise − pA/
3rd Harmonic Distortion − dBc
−50
2nd Harmonic Distortion − dBc
Gain = 2,
RF = 249 Ω,
VO = 2 VPP,
VS = 5 V
−40
3rd Harmonic Distortion − dBc
−40
−40
−30
20
3RD HARMONIC DISTORTION
vs
FREQUENCY
400
0
0.5
1
1.5
2
VO − Output Voltage −VPP
Figure 17.
2.5
3
10
100
1k
10 k
100 k
f − Frequency − Hz
Figure 18.
1M
10 M
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
TYPICAL CHARACTERISTICS (5 V) (continued)
NOISE FIGURE
vs
FREQUENCY
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
14
12
10
8
6
Gain = 2,
RF = 249 Ω,
RG = 249 Ω,
RL = 100 Ω,
VS = 5 V
4
2
0
18
16
TA = 25°C
14
500 M
TA = −40°C
12
10
8
6
40
30
10
0
2.5
3.5
4.5
3
4
VS − Supply Voltage − V
5
10 k
100 k
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 19.
Figure 20.
Figure 21.
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
INPUT OFFSET VOLTAGE
vs
INPUT COMMON-MODE VOLTAGE
INPUT BIAS AND OFFSET
CURRENT
vs
CASE TEMPERATURE
5
9
3
VS = 5 V
2.5
2
1.5
8
I IB − Input Bias Current − µ A
3.5
VS = 5 V
4
3.5
3
2.5
2
1.5
260
240
6
220
IIB+
5
200
4
180
3
160
IOS
2
140
1
120
100
0
−40−30 −20−10 0 10 20 30 40 50 60 70 80 90
0
100
IIB−
7
1
0.5
1
280
VS = 5 V
1000
−1
RL − Load Resistance − Ω
0
1
2
3
4
5
6
Case Temperature − °C
VICR − Input Common-Mode Range − V
Figure 22.
Figure 23.
Figure 24.
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
OPEN-LOOP GAIN
vs
FREQUENCY
SMALL-SIGNAL
TRANSIENT RESPONSE
80
VS = 5 V
70
Open-Loop Gain − dB
60
400
300
200
100
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 25.
2.6
−20
Gain
2.5
50
−40
40
−60
30
Phase
−80
20
−100
10
−120
0
−140
−10
−160
−20
10 k
100 k 1 M
10 M
2.7
Input
0
Phase − °
500
2.8
20
VS = 5 V
100 M 1 G
f − Frequency − Hz
Figure 26.
−180
10 G
VO − Output Voltage − V
600
I
VOS − Input Offset Voltage − mV
4.5
10
PSRR−
50
20
2
4
VO − Output Voltage − V
60
2
f − Frequency − Hz
VOS − Input Offset Voltage − µ V
70
4
1G
PSRR+
80
0
10 M
VS = 5 V
CMRR
90
Rejection Ratio − dB
Noise Figure − dB
16
110
100
TA = 85°C
OS − Input Offset Current − nA
20
2.9
2.4
Output
2.8
2.3
2.7
2.6
Gain = 2
RL = 100 Ω
RF = 249 Ω
tr/tf = 300 ps
VS = 5 V
2.5
2.4
2.3
2.2
VI − Input Voltage − V
22
18
I q − Quiescent Current − mA
20
REJECTION RATIO
vs
FREQUENCY
0
10
20
30
40
50
60
t − Time − ns
Figure 27.
11
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
TYPICAL CHARACTERISTICS (5 V) (continued)
3.5
2
Output
1.5
3.5
3
Gain = 2
RL = 100 Ω
RF = 249 Ω
VS = 5 V
2.5
2
1.5
Input
4
3.5
VO − Output Voltage − V
VO − Output Voltage − V
2.5
3
Gain = 2
RL = 100 Ω
RF = 249 Ω
VS = 5 V
2.5
2
1.5
10
20
30
40
50
0
1
t − Time − ns
2
3
4
5
6
7
t − Time − ns
Figure 28.
Figure 29.
Z o − Output Impedance − Ω
10 k
Gain = 2,
RF = 249 Ω,
VS = 5 V
100
10
1
0.1
0.01
100 k
1M
10 M
f − Frequency − Hz
Figure 31.
12
3
2.75
3
2.5
2.5
Output
2
2.25
1.5
2
1.75
1.5
0
0.1
0.2
0.3
0.4
0.5
t − Time − µs
Figure 30.
OUTPUT IMPEDANCE
vs
FREQUENCY
1k
3.25
0.5
1
60
3.5
Gain = 2
RL = 100 Ω
RF = 249 Ω
VS = 5 V
1
1
0
3.5
4.5
4
V O− Output Voltage − V
3
VI − Input Voltage − V
Input
4
OVERDRIVE
RECOVERY TIME
SETTLING TIME
100 M
1G
0.6
0.7
VI − Input Voltage − V
LARGE-SIGNAL
TRANSIENT RESPONSE
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SLOS436A – MARCH 2004 – REVISED JULY 2004
TYPICAL CHARACTERISTICS (3 V)
FREQUENCY RESPONSE
FREQUENCY RESPONSE
10
8
VO = 200 mVPP
6
5
VO = 400 mVPP
4
−3dB 900 MHz
7
CF = 0.5 pF
6
5
4
CF = 1 pF
VO = 800 mVPP
2
2
1
1
0
10 M
0
100 M
1G
10 G
100 M
22
2nd Harmonic Distortion − dBc
RF = 249 Ω,
RL = 499 Ω,
VO = 1 VPP,
VS = 3 V
Gain = 2
RL = 499 Ω
RF = 249 Ω,
VO = 500 mVPP,
VS = 3 V
−60
−70
−80
−90
−100
−4
1M
10 M
100 M
1M
1G
10 M
f − Frequency − Hz
100 M
Gain = 2
RL = 499 Ω
RF = 249 Ω,
VO = 500 mVPP,
VS = 3 V
−60
−70
−80
−90
−100
1M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 35.
Figure 36.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
SLEW RATE
vs
OUTPUT VOLTAGE
−40
SETTLING TIME
1.75
Gain = 2,
RF = 249 Ω,
RL = 499 Ω,
VS = 3 V
850
−60
−70
−80
HD 2
800
Rise
V O− Output Voltage − V
Gain = 2
RL = 499 Ω
RF = 249 Ω,
f = 10 MHz,
VS = 3 V
750
Fall
700
650
600
550
500
−90
100 M
Figure 37.
900
SR − Slew Rate − V/µ s
−50
10 G
−50
−50
−3 dB 450 MHz
0
−2
1G
FREQUENCY RESPONSE
10
2
100 M
f − Frequency − Hz
3RD HARMONIC DISTORTION
vs
FREQUENCY
12
4
10 M
2ND HARMONIC DISTORTION
vs
FREQUENCY
−3 dB 90 MHz
6
1M
10 G
Figure 34.
14
8
G 1, RF 0Ω
Figure 33.
18
16
G2
Figure 32.
−3 dB 85 MHz
20
1G
G5
f − Frequency − Hz
f − Frequency − Hz
3rd Harmonic Distortion − dBc
10 M
RF = 249 Ω,
RL = 499 Ω,
VO = 100 mVPP,
VS = 3 V
G 10
8
6
4
2
0
−2
−4
3
3
Signal Gain − dB
CF = 0 pF
Signal Gain − dB
7
Gain = 2
RL = 499 Ω
RF = 249 Ω,
VO = 100 mVPP,
VS = 3 V
9
Signal Gain − dB
8
Signal Gain − dB
VO = 100 mVPP
Gain = 2
RL = 499 Ω
RF = 249 Ω,
VS = 3 V
9
Harmonic Distortion − dBc
FREQUENCY RESPONSE
24
22
20
18
16
14
12
10
10
1.65
Gain = 2
RL = 499 Ω
RF = 249 Ω
VS = 3 V
1.55
1.45
1.35
450
HD 3
−100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VO − Output Voltage − VPP
Figure 38.
1
400
0
0.1
0.2
0.3
0.4
VO − Output Voltage − VPP
Figure 39.
0.5
0.6
1.25
0
1
2
3
4
5
6
7
8
9
10
t − Time − ns
Figure 40.
13
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
TYPICAL CHARACTERISTICS (3 V) (continued)
INPUT BIAS AND
OFFSET CURRENT
vs
CASE TEMPERATURE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
9
I IB − Input Bias Current − µ A
1.75
1.5
1.25
1
100
IIB−
1000
580
5
560
IIB+
4
540
IOS
3
500
1
480
460
−20
0
3
1
VO − Output Voltage − V
Output
0.5
2.5
2
1.5
Gain = 2,
RF = 249 Ω,
RL = 499 Ω,
VS = 3 V
30
40
1.25
−40
−20
0
50
60
2
1.75
1.5
2
1.75
1.5
Input
1.25
1
Output
0.75
0.75
0.5
0.5
14
Figure 45.
80
10 k
1
1k
Gain = 2,
RF = 249 Ω,
VS = 3 V
100
10
1
0.1
0.01
100 k
1M
10 M
f − Frequency − Hz
Figure 44.
60
OUTPUT IMPEDANCE
vs
FREQUENCY
2.25
G = 2,
RL = 499 Ω,
RF = 249 Ω,
VS = 3 V
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
t − Time − µs
40
Figure 43.
1.25
1
20
TC − Case Temperature − °C
Z o − Output Impedance − Ω
1.5
20
1.5
1
80
2.25
V O − Output Voltage − V PP
2
V I − Input Voltage − V
Input
t − Time − ns
60
1.75
OVERDRIVE RECOVERY TIME
2.5
10
40
2
Figure 42.
LARGE-SIGNAL
TRANSIENT RESPONSE
0
20
2.25
TC − Case Temperature − °C
Figure 41.
0.5
520
2
RL − Load Resistance −
1
600
6
0
−40
0.5
10
7
I
0.75
VS = 3 V
620
VI − Input Voltage − VPP
VO − Output Voltage − V
2
2.5
640
VS = 3 V
8
VOS − Input Offset Voltage − mV
VS = 3 V
OS − Input Offset Current − nA
2.25
0
−10
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
Figure 46.
100 M
1G
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
APPLICATION INFORMATION
For many years, high-performance analog design has required the generation of split power supply voltages, like
±15 V, ±8 V, and more recently ±5 V, in order to realize the full performance of the amplifiers available. Modern
trends in high-performance analog are moving towards single-supply operation at 5 V, 3 V, and lower. This
reduces power supply cost due to less voltages being generated and conserves energy in low power
applications. It can also take a toll on available dynamic range, a valuable commodity in analog design, if the
available voltage swing of the signal must also be reduced.
Two key figures of merit for dynamic range are signal-to-noise ratio (SNR) and spurious free dynamic range
(SFDR).
SNR is simply the signal level divided by the noise:
Signal
SNR
Noise
and SFDR is the signal level divided by the highest spur:
Signal
SFDR
Spur
In an operational amplifier, reduced supply voltage typically results in reduced signal levels due to lower voltage
available to operate the transistors within the amplifier. When noise and distortion remain constant, the result is a
commensurate reduction in SNR and SFDR. To regain dynamic range, the process and the architecture used to
make the operational amplifier must have superior noise and distortion performance with lower power supply
overhead required for proper transistor operation.
The THS4304 BiCom3 operational amplifier is just such a device. It is able to provide 2-Vpp signal swing at its
output on a single 5-V supply with noise and distortion performance similar to the best 10-V operational
amplifiers on the market today
GENERAL APPLICATION
The THS4304 is a traditional voltage-feedback topology with wideband performance up to 3 GHz at unity gain.
Care must be taken to ensure that parasitic elements do not erode the phase margin.
Capacitance at the output and inverting input, and resistance and inductance in the feedback path, can cause
problems.
To reduce parasitic capacitance, the ground plane should be removed from under the part.
To reduce inductance in the feedback, the circuit traces should be kept as short and direct as possible. For best
performance in non-inverting unity gain (G=+1V/V), it is recommended to use a wide trace directly between the
output and inverting input.
For a gain of +2V/V, it is recommended to use a 249-Ω feedback resistor. With good layout, this should keep the
frequency response peaking to around 2 dB. This resistance is high enough to not load the output excessively,
and the part is capable of driving 100-Ω load with good performance. Higher-value resistors can be used, with
more peaking. For example, 499 Ω gives about 5 dB of peaking, and gives slightly better distortion performance
with 100-Ω load. Lower value feedback resistors can also be used to reduce peaking, but degrades the distortion
performance with heavy loads.
Power supply bypass capacitors are required for proper operation. The most critical are 0.1-µF ceramic
capacitors; these should be placed as close to the part as possible. Larger bulk capacitors can be shared with
other components in the same area as the operational amplifier.
HARMONIC DISTORTION
For best second harmonic (HD2), it is important to use a single-point ground between the power supply bypass
capacitors when using a split supply. It is also recommended to use a single ground or reference point for input
termination and gain-setting resistors (R8 and R11 in the non-inverting circuit). It is recommended to follow the
EVM layout closely in your application.
15
THS4304
www.ti.com
SLOS436A – MARCH 2004 – REVISED JULY 2004
APPLICATION INFORMATION (continued)
SOT-23 versus MSOP
With light loading of 500-Ω and higher resistance, the THS4304 shows HD2 that is not dependant of package.
With heavy output loading of 100 Ω, the THS4304 in SOT-23 package shows about 6 dB better HD2
performance versus the MSOP package.
EVALUATION MODULES
The THS4304 has two evaluation modules (EVMs) available. One is for the MSOP (DGK) package and the other
for the SOT-23 (DBV) package. These provide a convenient platform for evaluating the performance of the part
and building various different circuits. The full schematics, board layout, and bill of materials (as supplied) for the
boards are shown in the following illustrations.
−VS
−VS
VREF
R3
J3
GND GND
J4
+VS
J6
FB1
FB2
C5
C1
C2
GND
TP1
C3
R8
C8
−VS
R7
C6* +VS
R9
+VS
U1
C7
R10
THS4304
4
3
5
1
R2
C9
J2
2
R11
R1
R12*
−VS
VREF
*C6 − DGK EVM Only
*R12 − DBV EVM Only
Figure 47. EVM Full Schematic
16
+VS
R6
+VS
J1
J5
C4
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
APPLICATION INFORMATION (continued)
EVM BILL OF MATERIALS
THS4304 EVM (1)
Item
1
Description
SMD
Size
Reference
Designator
PCB
Quantity
Manufacturer's
Part Number
Distributor's
Part Number
FB1, FB2
2
(STEWARD)
HI1206N800R-00
(DIGI-KEY)
240-1010-1-ND
Bead, ferrite, 3-A, 80-Ω
1206
2
Capacitor, 3.3-µF, Ceramic
1206
C1, C2
2
(AVX) 1206YG335ZAT2A
(GARRETT)
1206YG335ZAT2A
3
Capacitor, 0.1-µF, Ceramic
0603
C4, C5
2
(AVX) 0603YC104KAT2A
(GARRETT)
0603YC104KAT2A
4
Open
0603
C3, C6 (2)
2
5
Open
0603
R1, R3, R6,
R9, R12 (3)
5
6
Resistor, 0-Ω, 1/10-W, 1%
0603
C7. C8, C9,
C10
4
(KOA) RK73Z1JTTD
(GARRETT)
RK73Z1JTTD
7
Resistor, 49.9-Ω, 1/10-W, 1%
0603
R2, R11
2
(KOA) RK73H1JLTD49R9F
(GARRETT)
RK73H1JLTD49R9F
8
Resistor, 249-Ω, 1/10-W, 1%
0603
R7, R8
2
(KOA) RK73H1JLTD2490F
(GARRETT)
RK73H1JLTD2490F
9
Jack, banana recepticle, 0.25-in. diameter hole
J3, J4, J5, J6
4
(HH SMITH) 101
(NEWARK) 35F865
10
Test point, black
11
Connector, edge, SMA PCB jack
12
Integrated Circuit, THS4304
13
TP1
1
(KEYSTONE) 5001
(DIGI-KEY) 5001K-ND
J1, J2
2
(JOHNSON) 142-0701-801
(NEWARK) 90F2624
U1
1
(TI) THS4304DGK, or
(TI) THS4304DBV
Standoff, 4-40 HEX, 0.625-in.
Length
4
(KEYSTONE) 1808
14
Screw, Phillips, 4-40, 0.250-in.
4
SHR-0440-016-SN
15
Board, printed-circuit
1
(TI) THS4304DGK ENG A, or
(TI) THS4304DBV ENG A
(1)
(2)
(3)
NEWARK) 89F1934
NOTE: All items are designated for both the DBV and DGK EVMs unless otherwise noted.
C6 used on DGK EVM only.
R12 used on DBV EVM only.
17
THS4304
SLOS436A – MARCH 2004 – REVISED JULY 2004
18
www.ti.com
Figure 48. THS4304DGK EVM Layout Top and L2
Figure 49. THS4304DGK EVM Layout Bottom and L3
Figure 50. THS4304DBV EVM Layout Top and L2
Figure 51. THS4304DBV EVM Layout Bottom and L3
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
NON-INVERTING GAIN WITH SPLIT SUPPLY
The following schematic shows how to configure the operational amplifier for non-inverting gain with split power
supply (± 2.5V). This is how the EVM is supplied from TI. This configuration is convenient for test purposes
because most signal generators and analyzer are designed to use ground-referenced signals by default. Note
the input and output provides 50-Ω termination.
−VS
−VS
C5
0.1 F
C8
R8
R7
0
249
249
GND
J3
GND
J4
+VS
J6
FB1
J5
FB2
C1
3.3 F
C2
3.3 F
+VS
C4
0.1 F
GND
TP1
+VS
J1
4
C7
R10
0
0
R11
49.9
U1
5
3
1
2 THS4304DBV
R2
C9
49.9
0
J2
−VS
Figure 52. Non-Inverting Gain with Split Power Supply
19
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
INVERTING GAIN WITH SPLIT POWER SUPPLY
The following schematic shows how to configure the operational amplifier for inverting gain of 1 (–1 V/V) with
split power supply (±2.5 V). Note the input and output provides 50-Ω termination for convenient interface to
common test equipment.
−VS
−VS
C5
0.1 F
R7
GND
J3
J4
C7
R9
0
221
J6
C1
3.3 F
GND
TP1
+VS
44
3
R1
124
−
+
5
22
11
THS4304DBV
R2
C9
49.9
0
J2
−VS
C8
0
Figure 53. Inverting Gain with Split Power Supply
20
J5
C2
3.3 F
U1
R11
61.9
+VS
FB2
FB1
249
J1
GND
+VS
C4
0.1 F
THS4304
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SLOS436A – MARCH 2004 – REVISED JULY 2004
NON-INVERTING SINGLE-SUPPLY OPERATION
The THS4304 EVM can easily be configured for single 5-V supply operation, as shown in the following
schematic, with no change in performance. This circuit passes dc signals at the input, so care must be taken to
reference (or bias) the input signal to mid-supply.
If dc operation is not required, the amplifier can be ac coupled by inserting a capacitor in series with the input
(C7) and output (C9).
VREF
R3
R6
10 k
10 k
+VS
−VS
GND
GND
J3
J4
J6
+VS
J5
+VS
FB2
NC
C8
R8
R7
0.1 F
249
249
C2
3.3 F
GND
C4
0.1 F
TP1
+VS
J1
C7
R10
0
0
44
33
−
+
R1
49.9
U1
55
22
11
THS4304DBV
R2
C9
49.9
0
J2
C5
VREF
Figure 54. Non-Inverting 5-V Single-Supply Amplifier
DIFFERENTIAL ADC DRIVE AMPLIFIER
The circuit shown in Figure 54 is adapted as shown in Figure 55 to provide a high-performance differential
amplifier drive circuit for use with high-performance ADCs, like the ADS5500 (14-bit 125-MSP ADC). For testing
purposes, the circuit uses a transformer to convert the signal from a single-ended source to differential. If the
input signal source in your application is differential and biased to mid-rail, no transformer is required.
The circuit employs two amplifiers to provide a differential signal path to the ADS5500. A resistor divider (two
10-kΩ resistors) is used to obtain a mid-supply reference voltage of 2.5 V (VREF) (the same as shown in the
single-supply circuit of Figure 54). Applying this voltage to the one side of RG and to the positive input of the
operational amplifier (via the center-tap of the transformer) sets the input and output common-mode voltage of
the operational amplifiers to mid-rail to optimize their performance. The ADS5500 requires an input
common-mode voltage of 1.5 V. Due to the mismatch in required common-mode voltage, the signal is ac coupled
from the amplifier output, via the two 1-nF capacitors, to the input of the ADC. The CM voltage of the ADS5500 is
used to bias the ADC input to the required voltage, via the 1-kΩ resistors. Note: 100-µA common-mode current is
drawn by the ADS5500 input stage (at 125 MSPS). This causes a 100-mV shift in the input common-mode
voltage, which does not impact the performance when driving the input to –1 dB of full scale. To offset this effect,
a voltage divider from the power supply can be used to derive the input common-mode voltage reference.
Because the operational amplifiers are configured as non-inverting, the inputs are high impedance. This is
particularly useful when interfacing to a high-impedance source. In this situation, the amplifiers provide
impedance matching and amplification of the signal.
The SFDR performance of the circuit is shown in the following graph (see Figure 56) and provides for full
performance from the ADS5500 to 40 MHz.
21
THS4304
www.ti.com
SLOS436A – MARCH 2004 – REVISED JULY 2004
The differential topology employed in this circuit provides for significant suppression of the 2nd-order harmonic
distortion of the amplifiers. This, along with the superior 3rd-order harmonic distortion performance of the
amplifiers, results in the SFDR performance of the circuit (at frequencies up to 40 MHz) being set by higher-order
harmonics generated by the sampling process of the ADS5500.
The amplifier circuit (with resistor divider for bias voltage generation) requires a total of 185 mW of power from a
single 5-V power supply.
+5 V
10 k
V REF (= 2 .5V )
RG
0.1 F
10 k
RF
V REF
+5V
+ 3 .3 VA +3 .3 VD
THS4304
1 :1
100
V IN
V REF
49 .9
From
50
source
1 nF
1k
CM
+5V
A IN+
ADS 5500
1k
A IN−
CM
THS4304
100
1 nF
CM
0. 1 F
V REF
RG
RF
Figure 55. Differential ADC Drive Amplifier Circuit
90
Combined THS4304 and
ADS5500 SFDR
dB
85
80
G = 10 dB,
−1 dBFS,
RF = 249 Ω,
RG = 115 Ω,
SNR = 69.6,
FS = 125 MSPS
75
10
20
30
40
50
f − Frequency − MHz
Figure 56. SFDR Performance versus Frequency – THS4304 Driving ADS5500
22
D
A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THS4304D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4304
THS4304DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AKW
THS4304DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AKW
THS4304DG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4304
THS4304DGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AKU
THS4304DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AKU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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