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THS4509RGTRG4

THS4509RGTRG4

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VFQFN16_4X4MM_EP

  • 描述:

    IC OPAMP DIFF 3GHZ 16QFN

  • 数据手册
  • 价格&库存
THS4509RGTRG4 数据手册
Sample & Buy Product Folder Support & Community Tools & Software Technical Documents THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 THS4509 Wideband, Low-Noise, Low-Distortion, Fully-Differential Amplifier 1 Features 3 Description • • • • • • • • • • • • • • The THS4509 device is a wideband, fully-differential op amp designed for 5-V data acquisition systems. It has a low noise at 1.9 nV/√Hz, and low harmonic distortion of –75 dBc HD2 and –80 dBc HD3 at 100 MHz with 2 VPP, G = 10 dB, and 1-kΩ load. Slew rate is high at 6600 V/μs, and with settling time of 2 ns to 1% (2-V step), it is ideal for pulsed applications. It is designed for a minimum gain of 6 dB, but is optimized for gains of 10 dB. 1 Fully-Differential Architecture Centered Input Common-Mode Range Output Common-Mode Control Minimum Gain of 2 V/V (6 dB) Bandwidth: 1900 MHz Slew Rate: 6600 V/μs 1% Settling Time: 2 ns HD2: –75 dBc at 100 MHz HD3: –80 dBc at 100 MHz OIP3: 37 dBm at 70 MHz Input Voltage Noise: 1.9 nV/√Hz (f > 10 MHz) Power-Supply Voltage: 3 V to 5 V Power-Supply Current: 37.7 mA Power-Down Current: 0.65 mA To allow for DC coupling to analog-to-digital converters (ADCs), its unique output common-mode control circuit maintains the output common-mode voltage within 3-mV offset (typical) from the set voltage, when set within 0.5-V of midsupply, with less than 4-mV differential offset voltage. The commonmode set point is set to midsupply by internal circuitry, which may be overdriven from an external source. The input and output are optimized for best performance with the common-mode voltages set to midsupply. Along with high performance at low power-supply voltage, this design makes it ideal for high-performance, single-supply 5-V data acquisition systems. The combined performance of the THS4509 in a gain of 10 dB driving the ADS5500 ADC, sampling at 125 MSPS, is 81-dBc SFDR and 69.1-dBc SNR with a –1 dBFS signal at 70 MHz. 2 Applications • • • • 5-V Data Acquisition Systems High Linearity ADC Amplifiers Wireless Communication Medical Imaging Test and Measurement The THS4509 is offered in a quad, leadless VQFN-16 package (RGT), and is characterized for operation over the full industrial temperature range from –40°C to +85°C. Device Information(1) PART NUMBER THS4509 PACKAGE VQFN (16) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Test Configuration Measured 3rd Order Intermodulation Spurious Signal Level 250 W -60 VIN Mini-Circuits ADT2-1T 50 W 1:1.4 +VS = 5 V Mini-Circuits ADT2-1T 10 nF 1:1.4 VOUT -70 + VCM 953 W THS4509 - -90 10 nF 50 W 0.1 mF -80 -100 VOUT VIN -110 250 W = 20 dB Copyright © 2016, Texas Instruments Incorporated -120 0 50 100 150 200 f - Frequency - MHz 250 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 1 1 1 2 4 4 5 Absolute Maximum Ratings ..................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics: VS+ – VS– = 5 V ............... 6 Electrical Characteristics: VS+ – VS– = 3 V ............... 8 Dissipation Ratings ................................................... 9 Typical Characteristics ............................................ 10 Detailed Description ............................................ 25 8.1 Overview ................................................................. 25 8.2 Functional Block Diagram ....................................... 25 8.3 Feature Description................................................. 25 8.4 Device Functional Modes........................................ 28 9 Application and Implementation ........................ 29 9.1 Application Information............................................ 29 9.2 Typical Applications ................................................ 29 10 Power Supply Recommendations ..................... 35 11 Layout................................................................... 36 11.1 Layout Guidelines ................................................. 36 11.2 Layout Example .................................................... 37 11.3 PowerPAD™ Design Considerations.................... 38 12 Device and Documentation Support ................. 40 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support...................................................... Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 40 40 40 40 40 40 40 13 Mechanical, Packaging, and Orderable Information ........................................................... 40 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (November 2009) to Revision I Page • Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1 • Deleted the Packaging/Ordering Information table, see POA at the end of the data sheet .................................................. 1 • Deleted the THS4509 EVM section to the Layout Example section ................................................................................... 37 Changes from Revision G (May 2008) to Revision H Page • Changed title of Typical Characteristics: VS+ – VS– = 5 V .................................................................................................... 10 • Deleted conditions from Typical Characteristics: VS+ – VS– = 5 V table of graphs............................................................... 10 • Changed title of Typical Characteristics: VS+ – VS– = 3 V .................................................................................................... 18 • Deleted conditions from Typical Characteristics: VS+ – VS– = 3 V table of graphs............................................................... 18 • Added y-axis to Figure 87..................................................................................................................................................... 33 • Added y-axis to Figure 90..................................................................................................................................................... 35 • Changed item 10 in Layout Recommendations section ....................................................................................................... 36 • Added the PowerPAD PCB Layout Considerations section................................................................................................. 36 • Moved Figure 92 and associated paragraph to PowerPAD PCB Layout Considerations section ....................................... 36 • Added the PowerPAD Design Considerations section......................................................................................................... 38 Changes from Revision F (October 2007) to Revision G Page • Updated document format ...................................................................................................................................................... 1 • Changed common-mode range column for THS4509 and THS4513 rows in the Related Products table ............................ 4 • Added footnote 1 to Absolute Maximum Ratings table .......................................................................................................... 5 • Added V (volts) to unit column of ESD ratings rows in Absolute Maximum Ratings table..................................................... 5 2 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 • Changed VS+ – VS– = 5 V Input specifications from 1.75 V typ (common-mode input range high) to 1.4 V typ; –1.75 V (common-mode input range low) to –1.4 V; 1.35 MΩ || 1.77 pF (differential input impedance) to 1.3 MΩ || 1.8 pF; 1.02 MΩ || 2.26 pF (common-mode input impedance) to 1.0 MΩ || 2.3 pF ........................................................................... 6 • Changed VS+ – VS– = 5 V Input specifications from 1.75 V typ (common-mode input range high) to 1.4 V typ; –1.75 V (common-mode input range low) to –1.4 V; 1.35 MΩ || 1.77 pF (differential input impedance) to 1.3 MΩ || 1.8 pF; 1.02 MΩ || 2.26 pF (common-mode input impedance) to 1.0 MΩ || 2.3 pF ........................................................................... 7 • Changed VS+ – VS– = 3 V Input specifications from 0.75 V typ (common-mode input range high) to 0.4 V typ; –0.75 V (common-mode input range low) to –0.4 V; 1.35 MΩ || 1.77 pF (differential input impedance) to 1.3 MΩ || 1.8 pF; 1.02 MΩ || 2.26 pF (common-mode input impedance) to 1.0 MΩ || 2.3 pF ........................................................................... 8 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 3 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com 5 Device Comparison Table (1) COMMON-MODE RANGE OF INPUT (1) DEVICE MIN. GAIN THS4508 6 dB –0.3 V to 2.3 V THS4509 6 dB 1.1 V to 3.9 V THS4511 0 dB –0.3 V to 2.3 V THS4513 0 dB 1.1 V to 3.9 V Assumes a 5-V single-ended power supply 6 Pin Configuration and Functions RGT Package 16-Pin VQFN Top View VS− 16 15 14 13 NC 1 12 PD VIN− 2 11 VIN+ VOUT+ 3 10 VOUT− CM 4 9 5 6 7 CM 8 VS+ Pin Functions PIN NAME NO. NC 1 VIN– VOUT+ TYPE DESCRIPTION N/A No internal connection 2 I Inverting amplifier input 3 O Noninverting amplifier output CM 4, 9 I Common-mode voltage input VS+ 5-8 P Positive amplifier power-supply input VOUT– 10 O Inverted amplifier output VIN+ 11 I Noninverting amplifier input PD 12 I Power-down; PD = logic low puts part into low power mode, PD = logic high or open for normal operation VS– 13, 14, 15, 16 P Negative amplifier power-supply input 4 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range, unless otherwise noted. (1) MIN VS– to VS+ Supply voltage VI Input voltage VID Differential input voltage IO Output current (2) MAX UNIT 6 V ±VS Continuous power dissipation 4 V 200 mA See Dissipation Ratings TJ Maximum junction temperature 150 °C TA Operating free-air temperature –40 85 °C Tstg Storage temperature –65 150 °C (1) (2) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The THS4509 incorporates a (QFN) exposed thermal pad on the underside of the chip. This pad acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the QFN thermally-enhanced package. 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500 Machine model ±100 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltage Ambient temperature NOM MAX UNIT 3 5 5.25 V –40 25 85 °C 7.4 Thermal Information THS4509 THERMAL METRIC (1) RGT (VQFN) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 49.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 66.9 °C/W RθJB Junction-to-board thermal resistance 23.7 °C/W ψJT Junction-to-top characterization parameter 1.7 °C/W ψJB Junction-to-board characterization parameter 23.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 5 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com 7.5 Electrical Characteristics: VS+ – VS– = 5 V Test conditions are at VS+ = +2.5 V, VS– = –2.5 V, G = 10 dB, CM = open, VO = 2 VPP, RF = 349 Ω, RL = 200-Ω differential, TA = +25°C, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. PARAMETER TEST CONDITIONS TEST LEVEL (1) MIN TYP MAX UNIT AC PERFORMANCE G = 6 dB, VO = 100 mVPP Small-signal bandwidth 2 GHz G = 10 dB, VO = 100 mVPP 1.9 GHz G = 14 dB, VO = 100 mVPP 600 MHz G = 20 dB, VO = 100 mVPP 275 MHz Gain-bandwidth product G = 20 dB Bandwidth for 0.1-dB flatness G = 10 dB, VO = 2 VPP Large-signal bandwidth G = 10 dB, VO = 2 VPP Slew rate (differential) Rise time 3 GHz 300 MHz 1.5 GHz 6600 V/μs 0.5 Fall time 2-V step 0.5 Settling time to 1% Settling time to 0.1% 2nd-order harmonic distortion 10 f = 10 MHz –104 f = 50 MHz –80 f = 100 MHz C –92 f = 100 MHz –81 200-kHz tone spacing, RL = 499 Ω 3rd-order intermodulation distortion 3rd-order output intercept point –108 f = 50 MHz 2nd-order intermodulation distortion 2nd-order output intercept point dBc –68 f = 10 MHz 3rd-order harmonic distortion ns 2 200-kHz tone spacing RL = 100 Ω, referenced to 50-Ω output fC = 70 MHz –78 fC = 140 MHz –64 fC = 70 MHz –95 fC = 140 MHz –78 fC = 70 MHz 78 fC = 140 MHz 58 fC = 70 MHz 43 fC = 140 MHz dBc dBc dBm 38 fC = 70 MHz 12.2 fC = 140 MHz 10.8 Noise figure 50-Ω system, 10 MHz 17.1 dB Input voltage noise f > 10 MHz 1.9 nV/√Hz Input current noise f > 10 MHz 2.2 pA/√Hz 1-dB compression point dBm DC PERFORMANCE Open-loop voltage gain (AOL) Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift (1) 6 C TA = +25°C TA = –40°C to +85°C TA = –40°C to +85°C TA = +25°C TA = –40°C to +85°C TA = –40°C to +85°C TA = +25°C TA = –40°C to +85°C TA = –40°C to +85°C A B A B A B 68 dB 1 4 1 5 2.6 mV μV/°C 8 15.5 8 18.5 20 μA nA/°C 1.6 3.6 1.6 7 4 mV μA nA/°C Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 Electrical Characteristics: VS+ – VS– = 5 V (continued) Test conditions are at VS+ = +2.5 V, VS– = –2.5 V, G = 10 dB, CM = open, VO = 2 VPP, RF = 349 Ω, RL = 200-Ω differential, TA = +25°C, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. PARAMETER TEST CONDITIONS TEST LEVEL (1) MIN TYP MAX UNIT INPUT Common-mode input range high 1.4 Common-mode input range low V B –1.4 Differential input impedance C 1.3 || 1.8 MΩ || pF Common-mode input impedance C 1.0 || 2.3 MΩ || pF Common-mode rejection ratio 90 dB OUTPUT Maximum output voltage high Each output with 100 Ω to midsupply Minimum output voltage low Differential output voltage swing TA = +25°C 1.2 1.4 TA = –40°C to +85°C 1.1 1.4 TA = +25°C A TA = –40°C to +85°C 4.8 TA = –40°C to +85°C Differential output current drive RL = 10 Ω Output balance error VO = 100 mV, f = 1 MHz Closed-loop output impedance f = 1 MHz V –1.4 –1.2 –1.4 –1.1 V 5.6 V 4.4 96 mA –49 dB 0.3 Ω Small-signal bandwidth 700 MHz Slew rate 110 V/μs 1 V/V 5 mV ±40 μA C OUTPUT COMMON-MODE VOLTAGE CONTROL Gain Output common-mode offset from CM input CM input bias current 1.25 V < CM < 3.5 V 1.25 V < CM < 3.5 V C CM input voltage high 1.5 CM input voltage low –1.5 CM input impedance 23 || 1 CM default voltage V kΩ || pF 0 V POWER SUPPLY Specified operating voltage Maximum quiescent current Minimum quiescent current C 3 TA = +25°C TA = –40°C to +85°C TA = +25°C A TA = –40°C to +85°C Power-supply rejection (±PSRR) C 5 5.25 37.7 40.9 37.7 41.9 34.5 37.7 33.5 37.7 V mA mA 90 dB > 2.1 + VS– V < 0.7 + VS– V POWER-DOWN - Referenced to VS– Enable voltage threshold Assured on above 2.1 V + VS– C Disable voltage threshold Power-down quiescent current Input bias current Assured off below 0.7 V + VS– TA = +25°C TA = –40°C to +85°C A PD = VS– 0.65 0.9 0.65 1 mA 100 Input impedance Turnon time delay Measured to output on Turnoff time delay Measured to output off C 50 || 2 μA kΩ || pF 55 ns 10 μs Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 7 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com 7.6 Electrical Characteristics: VS+ – VS– = 3 V Test conditions at VS+ = +1.5 V, VS– = –1.5 V, G = 10 dB, CM = open, VO = 1 VPP, RF = 349 Ω, RL = 200-Ω differential, TA = +25°C, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. PARAMETER TEST CONDITIONS TEST LEVEL (1) MIN TYP MAX UNIT AC PERFORMANCE Small-signal bandwidth G = 6 dB, VO = 100 mVPP 1.9 G = 10 dB, VO = 100 mVPP 1.6 GHz G = 14 dB, VO = 100 mVPP 625 MHz G = 20 dB, VO = 100 mVPP 260 MHz Gain-bandwidth product G = 20 dB Bandwidth for 0.1-dB flatness G = 10 dB, VO = 1 VPP Large-signal bandwidth G = 10 dB, VO = 1 VPP GHz 3 GHz 400 MHz 1.5 GHz Slew rate (differential) 3500 V/μs Rise time 0.25 Fall time 2-V step 0.25 Settling time to 1% 1 Settling time to 0.1% 2nd-order harmonic distortion 10 f = 10 MHz –107 f = 50 MHz –83 f = 100 MHz dBc –60 f = 10 MHz 3rd-order harmonic distortion ns C –87 f = 50 MHz –65 f = 100 MHz –54 2nd-order intermodulation distortion 200-kHz tone spacing, RL = 499 Ω 3rd-order intermodulation distortion 2nd-order output intercept point 200-kHz tone spacing RL = 100 Ω 3rd-order output intercept point fC = 70 MHz –77 fC = 140 MHz –54 fC = 70 MHz –77 fC = 140 MHz –62 fC = 70 MHz 72 fC = 140 MHz 52 fC = 70 MHz 38.5 fC = 140 MHz dBc dBc dBm 30 fC = 70 MHz 2.2 fC = 140 MHz 0.25 Noise figure 50 Ω system, 10 MHz 17.1 dB Input voltage noise f > 10 MHz 1.9 nV/√Hz Input current noise f > 10 MHz 2.2 pA/√Hz 1-dB compression point dBm DC PERFORMANCE Open-loop voltage gain (AOL) Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift (1) 8 TA = +25°C TA = –40°C to +85°C TA = +25°C 68 dB 1 mV 2.6 C μV/°C 6 μA TA = –40°C to +85°C 20 nA/°C TA = +25°C 1.6 TA = –40°C to +85°C 4 μA nA/°C Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 Electrical Characteristics: VS+ – VS– = 3 V (continued) Test conditions at VS+ = +1.5 V, VS– = –1.5 V, G = 10 dB, CM = open, VO = 1 VPP, RF = 349 Ω, RL = 200-Ω differential, TA = +25°C, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. PARAMETER TEST CONDITIONS TEST LEVEL (1) MIN TYP MAX UNIT INPUT Common-mode input range high 0.4 Common-mode input range low V B –0.4 Differential input impedance C 1.3 || 1.8 MΩ || pF Common-mode input impedance C 1.0 || 2.3 MΩ || pF Common-mode rejection ratio 80 dB OUTPUT Maximum output voltage high Minimum output voltage low Each output with 100 Ω to midsupply TA = +25°C 0.45 V TA = +25°C –0.45 V Differential output voltage swing C 1.8 V 50 mA Differential output current drive RL = 10 Ω Output balance error VO = 100 mV, f = 1 MHz –49 dB Closed-loop output impedance f = 1 MHz 0.3 Ω 570 MHz 60 V/μs 1 V/V 4 mV ±40 μA OUTPUT COMMON-MODE VOLTAGE CONTROL Small-signal bandwidth Slew rate Gain Output common-mode offset from CM input CM input bias current 1.25 V < CM < 3.5 V C 1.25 V < CM < 3.5 V CM input voltage high 1.5 CM input voltage low –1.5 CM input impedance 20 || 1 CM default voltage V kΩ || pF 0 V POWER SUPPLY Specified operating voltage Quiescent current TA = +25°C Power-supply rejection (±PSRR) C 3 A 34.8 mA V C 70 dB V POWER-DOWN Referenced to VS– Enable voltage threshold Assured on above 2.1 V + VS– > 2.1 + VS– Disable voltage threshold Assured off below 0.7 V + VS– < 0.7 + VS- Power-down quiescent current Input bias current V 0.46 C PD = VS– mA 65 Input impedance μA 50 || 2 kΩ || pF Turnon time delay Measured to output on 100 ns Turnoff time delay Measured to output off 10 μs 7.7 Dissipation Ratings POWER RATING PACKAGE θJC θJA TA ≤ +25°C TA = +85°C RGT (16) 2.4°C/W 39.5°C/W 2.3 W 225 mW Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 9 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com 7.8 Typical Characteristics 7.8.1 Typical Characteristics: VS+ – VS– = 5 V Test conditions at VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 VPP, RF = 349 Ω, RL = 200-Ω differential, G = 10 dB, singleended input, and input and output referenced to midrail, unless otherwise noted. Table 1. Table of Graphs FIGURE Small-Signal Frequency Response Figure 1 Large-Signal Frequency Response Harmonic Distortion Intermodulation Distortion Output Intercept Point Figure 2 HD2, G = 6 dB, VOD = 2 VPP vs Frequency Figure 3 HD3, G = 6 dB, VOD = 2 VPP vs Frequency Figure 4 HD2, G = 10 dB, VOD = 2 VPP vs Frequency Figure 5 HD3, G = 10 dB, VOD = 2 VPP vs Frequency Figure 6 HD2, G = 14 dB, VOD = 2 VPP vs Frequency Figure 7 HD3, G = 14 dB, VOD = 2 VPP vs Frequency Figure 8 HD2, G = 10 dB vs Output Voltage Figure 9 HD3, G = 10 dB vs Output Voltage Figure 10 HD2, G = 10 dB vs Common-Mode Input Voltage Figure 11 HD3, G = 10 dB vs Common-Mode Input Voltage Figure 12 IMD2, G = 6 dB, VOD = 2 VPP vs Frequency Figure 13 IMD3, G = 6 dB, VOD = 2 VPP vs Frequency Figure 14 IMD2, G = 10 dB, VOD = 2 VPP vs Frequency Figure 15 IMD3, G = 10 dB, VOD = 2 VPP vs Frequency Figure 16 IMD2, G = 14 dB, VOD = 2 VPP vs Frequency Figure 17 IMD3, G = 14 dB, VOD = 2 VPP vs Frequency Figure 18 OIP2 vs Frequency Figure 19 OIP3 vs Frequency Figure 20 0.1-dB Flatness Figure 21 S-Parameters vs Frequency Figure 22 Transition Rate vs Output Voltage Figure 23 Transient Response Figure 24 Settling Time Figure 25 Rejection Ratio vs Frequency Figure 26 Output Impedance vs Frequency Figure 27 Overdrive Recovery Output Voltage Swing Figure 28 vs Load Resistance Figure 29 Turnoff Time Figure 30 Turnon Time Figure 31 Input Offset Voltage vs Input Common-Mode Voltage Figure 32 Open-Loop Gain vs Frequency Figure 33 Input-Referred Noise vs Frequency Figure 34 Noise Figure vs Frequency Figure 35 Quiescent Current vs Supply Voltage Figure 36 Power-Supply Current vs Supply Voltage in Power-Down Mode Figure 37 Output Balance Error vs Frequency Figure 38 CM Input Impedance vs Frequency Figure 39 CM Small-Signal Frequency Response Figure 40 CM Input Bias Current vs CM Input Voltage Figure 41 Differential Output Offset Voltage vs CM Input Voltage Figure 42 10 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 Typical Characteristics: VS+ – VS– = 5 V (continued) Table 1. Table of Graphs (continued) FIGURE Output Common-Mode Offset vs CM Input Voltage 22 22 Large Signal Gain − dB 16 G = 14 dB 14 12 G = 10 dB 10 8 G = 6 dB 6 18 16 G = 14 dB 14 12 G = 10 dB 10 8 G = 6 dB 6 4 4 2 2 0 0 0.1 0.1 1 10 100 1000 f - Frequency - MHz 10000 Figure 1. Small-Signal Frequency Response 10 100 f − Frequency − MHz 1 1000 10000 Figure 2. Large-Signal Frequency Response −60 −60 G = 6 dB, VOD = 2 VPP −70 3rd Order Harmonic Distortion − dBc 2nd Order Harmonic Distortion − dBc VOD = 2 VPP 20 G = 20 dB 18 Small Signal Gain - dB G = 20 dB VOD = 100 mVPP 20 RL = 100 W −80 −90 RL = 200 W −100 RL = 1 kW −110 RL = 500 W −120 G = 6 dB, VOD = 2 VPP −70 −80 RL = 100 W −90 RL = 1 kW −100 RL = 500 W −110 RL = 200 W −120 10 100 f − Frequency − MHz 1 1000 1 Figure 3. HD2 vs Frequency 10 100 f − Frequency − MHz 1000 Figure 4. HD3 vs Frequency −60 −60 G = 10 dB, VOD = 2 VPP −70 3rd Order Harmonic Distortion − dBc 2nd Order Harmonic Distortion − dBc Figure 43 RL = 200 W −80 RL = 100 W −90 −100 RL = 1 kW −110 RL = 500 W −120 G = 10 dB, VOD = 2 VPP −70 −80 RL = 500 W −90 RL = 1 kW −100 RL = 100 W −110 RL = 200 W −120 1 10 100 f − Frequency − MHz 1000 1 Figure 5. HD2 vs Frequency 10 100 f − Frequency − MHz 1000 Figure 6. HD3 vs Frequency Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 11 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com −60 G = 14 dB, VOD = 2 VPP −70 3rd Order Harmonic Distortion − dBc 2nd Order Harmonic Distortion − dBc −60 RL = 100 W −80 RL = 200 W RL = 500 W −90 −100 −110 RL = 1 kW G = 14 dB, VOD = 2 VPP −70 −80 RL = 100 W −90 RL = 1 kW −100 RL = 200 W −110 RL = 500 W −120 −120 10 100 f − Frequency − MHz 1 1000 1 1000 10 100 f − Frequency − MHz Figure 7. HD2 vs Frequency Figure 8. HD3 vs Frequency -60 -60 3nd Order Harmonic Distortion - dBc 2nd-Order Harmonic Distortion - dBc f = 64 MHz -70 f = 64 MHz -80 f = 32 MHz -90 f = 16 MHz -100 f = 8 MHz -110 -70 f = 32 MHz -80 f = 8 MHz -90 -100 -110 f = 16 MHz -120 -120 0 1 2 VOD - VPP 4 3 0 3 4 Figure 10. HD3 vs Output Voltage 0 -20 VCM = -1 V to 1 V VOD = 2 VPP G = 10 dB RL = 200 W -20 3rd Order Harmonic Distortion − dBc 2nd Order Harmonic Distortion − dBc 2 VOD - VPP Figure 9. HD2 vs Output Voltage -40 150 MHz -60 100 MHz 64 MHz -80 32 MHz -100 16 MHz 4 MHz 1 MHz -120 VCM = -1 V to 1 V VOD = 2 VPP G = 10 dB RL = 200 W -30 -40 -50 -60 150 MHz -70 100 MHz -80 64 MHz -90 32 MHz -100 16 MHz -110 1 MHz 4 MHz -120 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 VIC − Common-Mode Output Voltage − V 1 Figure 11. HD2 vs Common-Mode Output Voltage 12 1 -1 0.2 0.4 0.6 -0.8 -0.6 -0.4 -0.2 0 VIC − Common-Mode Output Voltage − V 0.8 1 Figure 12. HD3 vs Common-Mode Output Voltage Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 -60 Gain = 6 dB, VOD = 2 VPP Envelope -40 IMD3 - Intermodulation Distortion - dBc IMD2 - Intermodulation Distortion - dBc -30 RL = 200 W RL = 100 W -50 -60 -70 RL = 500 W -80 RL = 1 kW -90 -100 0 50 100 150 200 Gain = 6 dB, VOD = 2 VPP Envelope -65 RL = 200 W -70 RL = 1 kW -75 -80 -85 -90 -95 RL = 500 W -100 f - Frequency - MHz 0 Figure 13. IMD2 vs Frequency RL = 200 W -50 RL = 100 W -60 -70 RL = 500 W -80 RL = 1 kW -90 50 100 150 f - Frequency - MHz Gain = 10 dB, VOD = 2 VPP Envelope -65 RL = 100 W -75 -80 -85 RL = 1 kW -90 RL = 500 W -95 200 0 50 100 F - Frequency - MHz 150 200 Figure 16. IMD3 vs Frequency Figure 15. IMD2 vs Frequency −30 −60 Gain = 14 dB, VCO = 2 VPP Envelope −40 −50 IMD 3 − Intermodulation Distortion − dBc IMD 2− Intermodulation Distortion − dBc 200 RL = 200 W -70 -100 -100 0 100 150 f - Frequency - MHz -60 Gain = 10 dB, VOD = 2 VPP Envelope -40 50 Figure 14. IMD3 vs Frequency IMD 3 − Intermodulation Distortion - dBc IMD2 - Intermodulation Distortion - dBc -30 RL = 100 W RL = 200 W RL = 100 W −60 −70 RL = 500 W −80 RL = 1 kW −90 RL = 100 W Gain = 14 dB VOD = 2 VPP Envelope −65 −70 RL = 200 W −75 −80 −85 −90 RL = 1 kW −95 RL = 500 W −100 0 50 100 150 f − Frequency − MHz 200 −100 0 Figure 17. IMD2 vs Frequency 50 100 150 f − Frequency − MHz 200 Figure 18. IMD3 vs Frequency Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 13 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com 45 Gain = 6 dB 85 OIP − Output Intercept Point − dBm 3 OIP 2 − Output Intercept Point − dBm 90 Gain = 14 dB 80 75 70 65 Gain = 10 dB 60 55 50 45 40 0 50 100 150 f − Frequency − MHz Gain = 6 dB 43 41 39 Gain = 10 dB 37 35 33 31 Gain = 14 dB 29 27 25 200 0 50 Figure 19. OIP2 vs Frequency 100 150 f − Frequency − MHz 200 250 Figure 20. OIP3 vs Frequency 10.2 0 S21 VOD = 2VPP -10 S-Parameters - dB Signal Gain − dB 10.1 10 -20 S11 -30 -40 S22 -50 9.9 -60 S12 -70 9.8 1 0.1 1 10 100 f − Frequency − MHz 1000 Figure 22. S-Parameters vs Frequency 1.5 7000 V OD − Differential Output V oltage − V 8000 Transition Rate - V/ms 100 f - Frequency - MHz Figure 21. 0.1-dB Flatness Rise 6000 Fall 5000 4000 3000 2000 1000 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1 0.5 0 VOD = 2 Vstep −0.5 −1 −1.5 VOD - Differential Output Voltage - VSTEP Figure 23. Transition Rate vs Output Voltage 14 10 1000 Submit Documentation Feedback t − Time − 500 ps/div Figure 24. Transient Response Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 5 100 VOD = 2 Vstep 90 PSRR− 3 80 Rejection Ratio −dB 1 0 −1 60 40 30 −3 20 −4 10 0 0.01 −5 t − Time − 500 ps/div 1 10 f − Frequency − MHz Figure 25. Settling Time Figure 26. Rejection Ratio vs Frequency 0.1 100 5 V OD− Differential Output Voltage − V 100 Z o − Output Impedance − Ω CMRR 50 −2 10 1 0.1 0.1 1 10 100 f − Frequency− MHz 0.8 3 2 Input 0.4 1 0.2 0 0 −1 −0.2 −2 −0.4 −3 −0.6 −4 −0.8 −1 t − Time − 200 ns/div Figure 28. Overdrive Recovery 2 VOD − Differential Ouput Voltage − V 7 6 5 4 3 2 1 5 1.6 Output 1.2 0.8 100 1000 4 3 PD 2 0.4 1 0 0 0 10 0.6 Output −5 1000 1000 1 4 Figure 27. Output Impedance vs Frequency VOD - Differential Output Voltage - V PSRR+ 70 Input V oltage − V 2 RL - Load Resistance - W Power Down Input − V Percent of Final Value − % 4 t − Time − 2 ms/div Figure 29. Output Voltage Swing vs Load Resistance Figure 30. Turnoff Time Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 15 THS4509 www.ti.com 5 1.6 4 PD 1.2 3 0.8 2 Output 0.4 1 0 0 40 V IO − Input Offset V oltage − mV 2 Power Down Input − V VOD − Differential Output V oltage − V SLOS454I – JANUARY 2005 – REVISED JULY 2016 30 25 20 15 10 5 0 −5 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 Input Common-Mode Voltage − V t − Time − 50 ns/div Figure 31. Turnon Time 10 -20 Gain -50 Phase -80 40 -110 30 -140 20 -170 10 -200 I n − Current Noise − pA/ Hz 80 50 100 In 10 Vn -230 0 100 1 10 k 1M 100 M 1 10 G 10 100 f − Frequency − Hz 1k 10 k 100 k f − Frequency − Hz 1M 10 M Figure 34. Input-Referred Noise vs Frequency Figure 33. Open-Loop Gain and Phase vs Frequency 20 40 19 Gain = 6 dB 18 TA = 25°C 50 - W System I Q − Quiescent Current − mA NF − Noise Figure − dB 2.5 1000 Vn − Voltage Noise − nV/ Hz 40 Open Loop Phase − degrees 90 60 2 Figure 32. Input Offset Voltage vs Input Common-Mode Voltage 70 Open Loop Gain − dB 35 17 Gain = 10 dB 16 15 Gain = 14 dB 14 13 Gain = 20 dB 12 TA = -40°C 35 ±1.35 V TA = 85°C 30 11 25 10 0 50 100 150 f − Frequency − MHz 200 Figure 35. Noise Figure vs Frequency 16 1 1.5 2 VS - Supply Voltage - V 2.5 Figure 36. Quiescent Current vs Supply Voltage Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 800 10 TA = 85°C 0 Output Balance Error − dB Power Supply Current − µ A 700 TA = 25°C 600 500 400 TA = −40°C 300 200 −10 −20 −30 −40 −50 100 0 0 0.5 1 1.5 VS − Supply Voltage − V 2 −60 0.1 2.5 1000 10 100 f − Frequency − MHz 1 Figure 38. Output Balance Error vs Frequency Figure 37. Power-Supply Current vs Supply Voltage in Power-Down Mode 100 1 100 mVPP 0 CM Input Impedance − k Ω -1 10 CM Gain − dB -2 1 -3 -4 -5 -6 -7 0.1 -8 -9 0.01 0.1 1 10 100 f − Frequency − MHz -10 0.1 1000 100 1000 Figure 40. CM Small-Signal Frequency Response 5 Differential Output Offset Voltage − mV 300 CM Input Bias Current − µ A 10 f − Frequency − MHz Figure 39. CM Input Impedance vs Frequency 200 100 0 −100 −200 −300 −2.5 1 −2 −1.5 −1 −0.5 0 0.5 1 CM Input Voltage − V 1.5 2 2.5 4 3 2 1 0 −1 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 CM Input Voltage − V Figure 41. CM Input Bias Current vs CM Input Voltage Figure 42. Differential Output Offset Voltage vs CM Input Voltage Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 17 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com 50 Output Common−Mode Offset − mV 40 30 20 10 0 −10 −20 −30 −40 −50 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 CM Input Voltage − V Figure 43. Output Common-Mode Offset vs CM Input Voltage 7.8.2 Typical Characteristics: VS+ – VS– = 3 V Test conditions at VS+ = +1.5 V, VS– = –1.5 V, CM = open, VOD = 1 VPP, RF = 349 Ω, RL = 200-Ω differential, G = 10 dB, single-ended input, and input and output referenced to midrail, unless otherwise noted. Table 2. Table of Graphs FIGURE Small-Signal Frequency Response Figure 44 Large-Signal Frequency Response Harmonic Distortion Intermodulation Distortion Output Intercept Point Figure 45 HD2, G = 6 dB, VOD = 1 VPP vs Frequency Figure 46 HD3, G = 6 dB, VOD = 1 VPP vs Frequency Figure 47 HD2, G = 10 dB, VOD = 1 VPP vs Frequency Figure 48 HD3, G = 10 dB, VOD = 1 VPP vs Frequency Figure 49 HD2, G = 14 dB, VOD = 1 VPP vs Frequency Figure 50 HD3, G = 14 dB, VOD = 1 VPP vs Frequency Figure 51 IMD2, G = 6 dB, VOD = 1 VPP vs Frequency Figure 52 IMD3, G = 6 dB, VOD = 1 VPP vs Frequency Figure 53 IMD2, G = 10 dB, VOD = 1 VPP vs Frequency Figure 54 IMD3, G = 10 dB, VOD = 1 VPP vs Frequency Figure 55 IMD2, G = 14 dB, VOD = 1 VPP vs Frequency Figure 56 IMD3, G = 14 dB, VOD = 1 VPP vs Frequency Figure 57 OIP2 vs Frequency Figure 58 OIP3 vs Frequency Figure 59 0.1 dB Flatness Figure 60 S-Parameters vs Frequency Figure 61 Transition Rate vs Output Voltage Figure 62 Transient Response Figure 63 Settling Time Figure 64 Output Voltage Swing vs Load Resistance Figure 65 Rejection Ratio vs Frequency Figure 66 Overdrive Recovery Output Impedance Figure 67 vs Frequency Turnoff Time Figure 68 Figure 69 Turnon Time Figure 70 Output Balance Error vs Frequency Figure 71 Noise Figure vs Frequency Figure 72 CM Input Impedance vs Frequency Figure 73 18 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 Typical Characteristics: VS+ – VS– = 3 V (continued) Table 2. Table of Graphs (continued) FIGURE Differential Output Offset Voltage vs CM Input Voltage Figure 74 Output Common-Mode Offset vs CM Input Voltage Figure 75 22 22 VOD = 100 mVPP 20 VOD = 1 VPP 20 G = 20 dB G = 20 dB 18 16 Large Signal Gain − dB Small Signal Gain − dB 18 G = 14 dB 14 12 G = 10 dB 10 8 G = 6 dB 6 4 16 G = 14 dB 14 12 G = 10 dB 10 8 G = 6 dB 6 4 2 2 0 0 0.1 1 10 100 f - Frequency - MHz 1000 10000 0.1 Figure 44. Small-Signal Frequency Response 10 100 f− Frequency − MHz 1 1000 10000 Figure 45. Large-Signal Frequency Response G = 6 dB, VOD = 1 VPP -50 3rd Order Harmonic Distortion − dBc 2nd Order Harmonic Distortion - dBc -40 -60 -70 -80 RL = 100 W -90 RL = 200 W RL = 1 kW -100 -110 -120 G = 6 dB, VOD = 1 VPP −40 −50 −60 RL = 100 W −70 RL = 200 W −80 −90 RL = 1 kW RL = 500 W RL = 500 W −100 1 10 100 f - Frequency - MHz −40 3rd Order Harmonic Distortion − dBc 2nd Order Harmonic Distortion − dBc −40 G = 10 dB, VOD = 1 VPP −60 −70 −80 R L = 200 Ω −90 −100 −110 −120 1 1000 Figure 47. HD3 vs Frequency Figure 46. HD2 vs Frequency −50 10 100 f − Frequency − MHz 1 1000 R L = 1 kΩ R L = 500 Ω G = 10 dB, COD = 1 VPP −50 −60 −70 RL = 1 kW −80 RL = 500 W −90 RL = 200 W −100 10 100 f − Frequency − MHz 1000 1 100 10 f − Frequency − MHz 1000 Figure 49. HD3 vs Frequency Figure 48. HD2 vs Frequency Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 19 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com −40 G = 14 dB, VOD = 1 VPP −50 3rd Order Harmonic Distortion − dBc 2nd Order Harmonic Distortion − dBc −40 −60 R L = 100 Ω −70 −80 R L = 200 Ω −90 −100 R L = 500 Ω −110 R L= 1 kΩ −120 10 1 100 −60 RL = 100 W −70 RL = 200 W −80 RL = 500 W −90 RL = 1 kW −100 1000 f − Frequency − MHz 10 100 f − Frequency − MHz Figure 50. HD2 vs Frequency Figure 51. HD3 vs Frequency 1 −40 IMD3 − Intermodulation Distortion − dBc Gain = 6 dB, VOD = 1 VPP RL = 500 W RL = 1 kW −50 −60 RL = 100 W −70 RL = 200 W −80 −90 −100 0 Gain = 6 dB, VOD = 1 VPP Envelope −40 RL = 100 W −50 −60 RL = 1 kW RL = 500 W −70 −80 −90 RL = 200 W −100 50 100 f − Frequency − MHz 150 200 0 50 Figure 52. IMD2 vs Frequency −40 RL = 500 W IMD3 - IntermodulationDistortion - dBc IMD − Intermodulation Distortion − dBc 2 -30 Gain = 10 dB, VOD = 1 VPP Envelope −50 −60 RL = 1 kW RL = 100 W −70 RL = 200 W −80 100 150 f − Frequency − MHz 200 Figure 53. IMD3 vs Frequency −30 −90 −100 Gain = 10 dB, VOD = 1 VPP Envelope -40 -50 RL = 100 W -60 RL = 500 W -70 RL = 1 kW -80 -90 RL = 200 W -100 0 50 100 f − Frequency − MHz 150 200 05 0 100 150 f - Frequency - MHz 200 Figure 55. IMD3 vs Frequency Figure 54. IMD2 vs Frequency 20 1000 −30 −30 IMD2 − Intermodulation Distortion − dBc G = 14 dB, VOD = 1 VPP −50 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 −30 Gain = 14 dB, VOD = 1 VPP Envelope −40 IMD3 − Intermodulation Distortion − dBc IMD 2 − Intermodulation Distortion − dBc −30 RL = 500 W −50 −60 RL = 1 kW RL = 100 W −70 RL = 200 W −80 −90 Gain = 14 dB, VOD = 1 VPP Envelope −40 RL = 100 W −50 −60 RL = 500 W −70 RL = 1 kW −80 RL = 200 W −90 −100 −100 0 50 100 150 f − Frequency − MHz 200 0 50 Figure 56. IMD2 vs Frequency 200 Figure 57. IMD3 vs Frequency 80 45 OIP3 − Output Intercept Point − dBm Gain = 6 dB OIP2 − Output Intercept Point − dBm 100 150 f − Frequency − MHz 75 70 65 60 Gain = 10 dB 55 50 Gain = 14 dB 45 40 35 Gain = 6 dB 40 Gain = 10 dB 35 30 25 Gain = 14 dB 20 15 30 0 50 150 100 f − Frequency − MHz 0 200 Figure 58. OIP2, dBm vs Frequency 50 150 100 f − Frequency − MHz 250 200 Figure 59. OIP3, dBm vs Frequency 10.2 0 VOD = 1 VPP S21 -10 -20 S-Parameters - dB Signal Gain − dB 10.1 10 S11 -30 -40 S22 -50 9.9 -60 S12 9.8 0.1 -70 1 10 100 f − Frequency − MHz 1000 10000 1 Figure 60. 0.1-dB Flatness 10 100 f = Frequency - MHz 1000 Figure 61. S-Parameters vs Frequency Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 21 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com 4000 VOD − Differential Output Voltage - V 0.6 Rising 3000 2500 Falling 2000 1500 1000 500 0 0.2 1.4 1 1.2 0.4 0.6 0.8 VOD − Differential Output Voltage - VSTEP 0 0.5 0.4 0.3 VOD = 1 Vstep 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 −0.6 t − Time − 500 ps/div Figure 63. Transient Response Figure 62. Transition Rate vs Output Voltage 5 2.5 Percent of Final Voltage - V 4 VOD - Differential Output Voltage - V VOD = 1 Vstep 3 2 1 0 −1 −2 −3 −4 2 1.5 1 0.5 0 −5 100 RL - Load Resistance - W 0 t − Time − 500 ps/div Figure 64. Settling Time Figure 65. Output Voltage Swing vs Load Resistance 3 90 V OD − Differential Output Voltage - V PSRR− 80 CMRR Rejection Ratio −dB 70 60 PSRR+ 50 40 0.6 2.5 2 Input 0.4 1.5 1 0.5 0.2 Output 0 0 −0.5 30 −0.2 −1 −1.5 20 10 0 0.01 0.1 1 10 100 f − Frequency − MHz 1000 −0.4 −2 −2.5 −3 −0.6 t − Time − 200 ns/div Figure 66. Rejection Ratio vs Frequency 22 1000 Input Voltage - V SR − Transition Rate − V/ µ s 3500 Submit Documentation Feedback Figure 67. Overdrive Recovery Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 3 1 10 1 2.5 0.8 Output 1.5 0.4 PD 0.5 0 0.1 1 10 f − Frequency− MHz 0 1000 100 t – Time – 2 ms/div Figure 69. Turnoff Time Figure 68. Output Impedance vs Frequency 10 3 0 PD 0.8 2 1.5 0.6 Output Power Down Input − V 2.5 1 Output Balance Error − dB 1.2 VOD - Differential Output Voltage - V 1 0.2 0.1 −10 −20 −30 0.4 1 0.2 0.5 −50 0 −60 0.1 0 −40 1 t − Time − 50 ns/div Figure 70. Turnon Time 10 100 f − Frequency − MHz 1000 Figure 71. Output Balance Error vs Frequency 20 100 19 50 - W System Gain = 6 dB CM Input Impedance − k Ω 18 NF − Noise Figure − dB 2 0.6 Power Down Input − V VOD − Differential Ouput Voltage - V Z o − Output Impedance − Ω 100 17 Gain = 10 dB 16 15 Gain = 14 dB 14 13 12 10 1 0.1 Gain = 20 dB 11 10 0 50 100 150 f − Frequency − MHz 200 Figure 72. Noise Figure vs Frequency 0.01 0.1 1 100 10 f − Frequency − MHz 1000 Figure 73. CM Input Impedance vs Frequency Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 23 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com 50 Output Common−Mode Offset − mV Differential Output Offset V oltage − mV 5 4 3 2 1 0 −1 −1.5 −1 −0.5 0 0.5 CM Input Voltage − V 1 1.5 Figure 74. Differential Output Offset Voltage vs CM Input Voltage 24 40 30 20 10 0 −10 −20 −30 −40 −50 −1.5 −1 −0.5 0 0.5 CM Input Voltage - V 1 1.5 Figure 75. Output Common-Mode Offset vs CM Input Voltage Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 8 Detailed Description 8.1 Overview The THS4509 is a fully differential amplifier with integrated common-mode control designed to provide low distortion amplification to wide bandwidth differential signals. The common-mode feedback circuit sets the output common-mode voltage independent of the input common mode, as well as forcing the V+ and V − outputs to be equal in magnitude and opposite in phase, even when only one of the inputs is driven as in single to differential conversion. 8.2 Functional Block Diagram V+ +OUT -IN ± 10 k High-Aol + Differential I/O Amplifier ± +IN 10 k + -OUT V+ 50 k ± Vcm Error Amplifier + EN Vcm Buffer 50 k V± Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Test Circuits The THS4509 is tested with the following test circuits built on the evaluation module (EVM). For simplicity, power-supply decoupling is not shown—see Layout for recommendations. Depending on the test conditions, component values are changed per Table 3 and Table 4, or as otherwise noted. The signal generators used are AC-coupled, 50-Ω sources, and a 0.22-μF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the alternate input to balance the circuit. A split power supply is used to ease the interface to common test equipment, but the amplifier can be operated single-supply as described in Typical Applications with no impact on performance. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 25 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com Feature Description (continued) Table 3. Gain Component Values GAIN RF RG RIT 6 dB 348 Ω 165 Ω 61.9 Ω 10 dB 348 Ω 100 Ω 69.8 Ω 14 dB 348 Ω 56.2 Ω 88.7 Ω 20 dB 348 Ω 16.5 Ω 287 Ω Note the gain setting includes 50-Ω source impedance. Components are chosen to achieve gain and 50-Ω input termination. Table 4. Load Component Values RL RO ROT ATTEN. 100 Ω 25 Ω Open 6 dB 200 Ω 86.6 Ω 69.8 Ω 16.8 dB 499 Ω 237 Ω 56.2 Ω 25.5 dB 1k Ω 487 Ω 52.3 Ω 31.8 dB Note the total load includes 50-Ω termination by the test equipment. Components are chosen to achieve load and 50-Ω line termination through a 1:1 transformer. Due to the voltage divider on the output formed by the load component values, the amplifier output is attenuated. The column Atten in Table 4 shows the attenuation expected from the resistor divider. When using a transformer at the output as shown in Figure 77, the signal sees slightly more loss, and these numbers are approximate. 8.3.1.1 Frequency Response The circuit shown in Figure 76 is used to measure the frequency response of the circuit. From 50 Ω Source VIN RG RF VS+ R IT 49.9 Ω RG 0.22 µF THS4509 CM R IT VS− 49.9 Ω 49.9 Ω 100 Ω Output Measured Here With High Impedance Differential Probe Open 0.22 µF RF Copyright © 2016, Texas Instruments Incorporated Figure 76. Frequency Response Test Circuit A network analyzer is used as the signal source and as the measurement device. The output impedance of the network analyzer is 50 Ω. RIT and RG are chosen to impedance match to 50 Ω, and to maintain the proper gain. To balance the amplifier, a 0.22-μF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the alternate input. The output is probed using a high-impedance differential probe across the 100-Ω resistor. The gain is referred to the amplifier output by adding back the 6-dB loss due to the voltage divider on the output. 8.3.1.2 Distortion and 1-dB Compression The circuit shown in Figure 77 is used to measure harmonic distortion, intermodulation distortion, and 1-db compression point of the amplifier. 26 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 Feature Description (continued) From 50 Ω Source VIN RF RG VS+ RIT RO RG 0.22 µF THS 4509 CM RIT VS− 49.9 Ω RO 1:1 VOUT ROT To 50 Ω Test Equipment Open 0.22 µF RF Copyright © 2016, Texas Instruments Incorporated Figure 77. Distortion Test Circuit A signal generator is used as the signal source and the output is measured with a spectrum analyzer. The output impedance of the signal generator is 50 Ω. RIT and RG are chosen to impedance-match to 50 Ω, and to maintain the proper gain. To balance the amplifier, a 0.22-μF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the alternate input. A low-pass filter is inserted in series with the input to reduce harmonics generated at the signal source. The level of the fundamental is measured, then a high-pass filter is inserted at the output to reduce the fundamental so that it does not generate distortion in the input of the spectrum analyzer. The transformer used in the output to convert the signal from differential to single-ended is an ADT1-1WT. It limits the frequency response of the circuit so that measurements cannot be made below approximately 1 MHz. The 1-dB compression point is measured with a spectrum analyzer with 50-Ω double termination or 100-Ω termination; see Table 4. The input power is increased until the output is 1 dB lower than expected. The number reported in the table data is the power delivered to the spectrum analyzer input. Add 3 dB to refer to the amplifier output. 8.3.1.3 S-Parameter, Slew Rate, Transient Response, Settling Time, Output Impedance, Overdrive, Output Voltage, Turnon, and Turnoff Time The circuit shown in Figure 78 is used to measure s-parameters, slew rate, transient response, settling time, output impedance, overdrive recovery, output voltage swing, turnon, and turnoff times of the amplifier. For output impedance, the signal is injected at VOUT with VIN left open and the drop across the 49.9-Ω resistor is used to calculate the impedance seen looking into the amplifier output. Because S21 is measured single-ended at the load with 50-Ω double termination, add 12 dB to refer to the amplifier output as a differential signal. From V IN 50 Ω Source RF RG VS+ R IT 49.9 Ω VOUT+ RG THS 4509 49.9 Ω VOUT− 0.22 µF 49.9 Ω CM R IT VS− To 50 Ω Test Equipment Open 0.22 µF RF Copyright © 2016, Texas Instruments Incorporated Figure 78. S-Parameter, SR, Transient Response, Settling Time, ZO, Overdrive Recovery, VOUT Swing, Turnon, and Turnoff Test Circuit Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 27 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com Feature Description (continued) 8.3.1.4 CM Input The circuit shown in Figure 79 is used to measure the frequency response and input impedance of the CM input. Frequency response is measured single-ended at VOUT+ or VOUT– with the input injected at VIN, RCM = 0 Ω, and RCMT = 49.9 Ω. The input impedance is measured with RCM = 49.9 Ω with RCMT = open, and calculated by measuring the voltage drop across RCM to determine the input current. RG 0.22 mF RF VS+ RIT 49.9 W 49.9 W VOUT– RG 0.22 mF THS4509 49.9 W VOUT+ CM RIT RCM VIN VS– 49.9 W To 50-W Test Equipment RCMT RF From 50-W source Copyright © 2016, Texas Instruments Incorporated Figure 79. CM Input Test Circuit 8.3.1.5 CMRR and PSRR The circuit shown in Figure 80 is used to measure the CMRR and PSRR of VS+ and VS–. The input is switched appropriately to match the test being performed. 348 Ω VS+ PSRR+ From VIN 50 Ω CMRR Source VS+ 49.9 Ω 100 Ω 100 Ω THS4509 69.8 Ω VS− PSRR− VS− CM 49.9 Ω 100 Ω Open 0.22 µF Output Measured Here With High Impedance Differential Probe 348 Ω Copyright © 2016, Texas Instruments Incorporated Figure 80. CMRR and PSRR Test Circuit 8.4 Device Functional Modes The THS4509 has one main functional mode with two variants. The amplifier functions as either a differential to differential or a single-ended to differential amplifier. In either of these modes the amplifier output operating point (common-mode voltage) is set independently by the CM pin. The THS4509 also features a power-down state for reduced power consumption when the amplifier is not required to be operational. 28 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The THS4509 is a fully-configurable, differential operational amplifier. The closed-loop gain is set by external resistors. Many performance metrics are set by the matching of these external resistors, so 0.1% or better tolerance resistors are recommended. The amplifier output common-mode voltage is set by the CM pin. From the CM pin to the amplifier outputs there is a fixed gain of 1 V/V so that the amplifier output voltage is identical to the voltage applied to the CM pin. This pin must be driven by a low impedance reference and must also be bypassed to ground using a 0.1-µF ceramic, low ESR resistor. The ideal common-mode voltage is equal to the voltage that is midway between the positive and negative supply voltages. The THS4509 can be operated from either single or split power supplies with a range of 3 V to 5 V of total supply voltage. When selecting a power supply voltage, make sure to provide adequate margin for input and output voltage levels. In many cases, split supplies are the best option. It is not necessary to have power supply voltages symmetrical around ground. For example, –1 V and +4 V is a valid power supply configuration. 9.2 Typical Applications The following circuits show application information for the THS4509. For simplicity, power-supply decoupling capacitors are not shown in these diagrams. See the Layout section for recommendations. For more detail on the use and operation of fully-differential op amps refer to the application report, Fully-Differential Amplifiers (SLOA054). 9.2.1 Differential Input to Differential Output Amplifier The THS4509 is a fully-differential op amp, and can be used to amplify differential input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 81 (CM input not shown). The gain of the circuit is set by RF divided by RG. Depending on the source and load, input and output termination can be accomplished by adding RIT and RO. RF Differential Input Differential Output VS+ RG V IN+ + – VOUT– THS4509 VIN– RG – + VOUT+ VS– RF Copyright © 2016, Texas Instruments Incorporated Figure 81. Differential Input to Differential-Output Amplifier 9.2.1.1 Design Requirements The following sections detail how to determine if your design meets these requirements. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 29 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com Typical Applications (continued) The main design requirements for the THS4509 are the input common mode, the output swing voltage. Other design requirements are signal linearity and accuracy. With flexible supply voltage ranges and externally configurable resistors the THS4509 can be configured to meet many design requirements. Table 5 lists the design parameters of this example. Table 5. Design Parameters PARAMETER EXAMPLE VALUE Gain 6 dB Output swing 2 Vpp Harmonic distortion >75 dBc Load resistance 100 Ω 9.2.1.2 Detailed Design Procedure The first parameter is gain. Gain is set by external resistors as shown in Table 3. With a gain of 6 dB, the appropriate resistor values are 348 Ω for RF and 165 Ω for RG and 61.9 Ω for the termination resistor. These resistor values are for a 50-Ω source. The desired output swing of 2 Vpp and distortion of –75 dBc means that a supply voltage of 5 V is required. Further design details are covered in this section. 9.2.1.2.1 Input Common-Mode Voltage Range The input common-mode voltage of a fully-differential op amp is the voltage at the + and – input pins of the op amp. It is important to not violate the input common-mode voltage range (VICR) of the op amp. Assuming the op amp is in linear operation the voltage across the input pins is only a few millivolts at most. So finding the voltage at one input pin determines the input common-mode voltage of the op amp. Treating the negative input as a summing node, the voltage is given by Equation 1: ö ö æ æ RG RF ÷ ÷ + ç VIN- ´ VIC = çç VOUT + ´ ÷ ç R G + R F ÷ø R G + RF ø è è (1) To determine the VICR of the op amp, the voltage at the negative input is evaluated at the extremes of VOUT+. As the gain of the op amp increases, the input common-mode voltage becomes closer and closer to the input common-mode voltage of the source. 9.2.1.2.2 Setting the Output Common-Mode Voltage The output common-mode voltage is set by the voltage at the CM pin(s). The internal common-mode control circuit maintains the output common-mode voltage within 3-mV offset (typical) from the set voltage, when set within 0.5 V of midsupply, with less than 4-mV differential offset voltage. If left unconnected, the common-mode set point is set to midsupply by internal circuitry, which may be overdriven from an external source. Figure 82 is representative of the CM input. The internal CM circuit has about 700 MHz of –3-dB bandwidth, which is required for best performance, but it is intended to be a DC bias input pin. Bypass capacitors are recommended on this pin to reduce noise at the output. The external current required to overdrive the internal resistor divider is given by Equation 2: IEXT = 2VCM - (VS + - VS - ) 50 kW where • 30 VCM is the voltage applied to the CM pin Submit Documentation Feedback (2) Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 VS+ 50 kW I EXT to internal CM circuit CM 50 kW V S– Figure 82. CM Input Circuit 9.2.1.2.3 Single-Supply Operation (3 V to 5 V) To facilitate testing with common lab equipment, the THS4509 EVM allows split-supply operation, and the characterization data presented in this data sheet were taken with split-supply power inputs. The device can easily be used with a single-supply power input without degrading the performance. Figure 83, Figure 84, and Figure 85 show DC and AC-coupled single-supply circuits with single-ended inputs. These configurations all allow the input and output common-mode voltage to be set to midsupply allowing for optimum performance. The information presented here can also be applied to differential input sources. In Figure 83, the source is referenced to the same voltage as the CM pin (VCM). VCM is set by the internal circuit to midsupply. RT along with the input impedance of the amplifier circuit provides input termination, which is also referenced to VCM. NOTE RS and RT are added to the alternate input from the signal input to balance the amplifier. Alternately, one resistor can be used equal to the combined value RG+ RS || RT on this input. This is also true of the circuits shown in Figure 84 and Figure 85. RG RS VS+ RT VSignal RF RO VCM VBias= VCM RG RS RT THS4509 RO VOUTVOUT+ CM VS– VCM VCM VCM RF Copyright © 2016, Texas Instruments Incorporated Figure 83. THS4509 DC-Coupled Single-Supply With Input Biased to VCM In Figure 84 the source is referenced to ground and so is the input termination resistor. RPU is added to the circuit to avoid violating the VICR of the op amp. The proper value of resistor to add can be calculated from Equation 3: R PU = (VIC - VS+ ) æ 1 VCM çç è RF æ 1 ö 1 ÷÷ - VIC çç + è R IN R F ø ö ÷÷ ø (3) Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 31 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com V S+ R PU RS RF RG RT V Signal V S+ V S+ RO V OUT- R PU THS 4509 RG RO V OUT+ RS V S- RT CM RF Copyright © 2016, Texas Instruments Incorporated Figure 84. THS4509 DC-Coupled Single-Supply With RPU Used to Set VIC VIC is the desired input common-mode voltage, VCM = CM, and RIN = RG+ RS || RT. To set to midsupply, make the value of RPU = RG+ RS || RT. Table 6 is a modification of Table 3 to add the proper values with RPU assuming a 50-Ω source impedance and setting the input and output common-mode voltage to midsupply. Table 6. RPU Values for Various Gains GAIN RF RG RIT RPU 6 dB 348 Ω 169 Ω 64.9 Ω 200 Ω 10 dB 348 Ω 102 Ω 78.7 Ω 133 Ω 14 dB 348 Ω 61.9 Ω 115 Ω 97.6 Ω 20 dB 348 Ω 40.2 Ω 221 Ω 80.6 Ω There are two drawbacks to this configuration. One is that it requires additional current from the power supply. Using the values shown for a gain of 10 dB requires 37 mA more current with 5-V supply, and 22-mA more current with 3-V supply. The other drawback is that this configuration also increases the noise gain of the circuit. In the 10-dB gain case, noise gain increases by a factor of 1.5. Figure 85 shows AC coupling to the source. Using capacitors in series with the termination resistors allows the amplifier to self-bias both input and output to midsupply. C RS V Signal RG RT RF V S+= 3V to 5V RO C V OUTRG THS 4509 RO V OUT+ RS RT C C CM V S- RF Figure 85. THS4509 AC-Coupled Single-Supply 32 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 9.2.1.2.4 THS4509 and ADS5500 Combined Performance The THS4509 is designed to be a high-performance drive amplifier for high-performance data converters like the ADS5500 14-bit 125-MSPS ADC. Figure 86 shows a circuit combining the two devices, and Figure 87 shows the combined SNR and SFDR performance versus frequency with –1-dBFS input signal level sampling at 125 MSPS. The THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5500. The 100-Ω resistors and 2.7-pF capacitor between the THS4509 outputs and ADS5500 inputs along with the input capacitance of the ADS5500 limit the bandwidth of the signal to 115 MHz (–3 dB). For testing, a signal generator is used for the signal source. The generator is an ac-coupled 50-Ω source. A band-pass filter is inserted in series with the input to reduce harmonics and noise from the signal source. Input termination is accomplished through the 69.8-Ω resistor and 0.22-μF capacitor to ground in conjunction with the input impedance of the amplifier circuit. A 0.22-μF capacitor and 49.9-Ω resistor is inserted to ground across the 69.8-Ω resistor and 0.22-μF capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. Refer to Table 6 for component values to set proper 50-Ω termination for other common gains. A split power supply of +4 V and –1 V is used to set the input and output common-mode voltages to approximately midsupply while setting the input common-mode of the ADS5500 to the recommended +1.55 V. This configuration maintains maximum headroom on the internal transistors of the THS4509 to insure optimum performance. VIN From 50-W source 348 W 100 W 4V 69.3 W 0.22 mF THS 4509 100 W 49.9 W 14 -bit, 125 MSPS 100 W A IN + ADS5500 A IN - CM 100 W2.7 pF CM 69.8 W 49.9 W -1 V 0.22 mF 0.22 mF 348 W 0.1 mF 0.1 mF Copyright © 2016, Texas Instruments Incorporated SFDR (dBc), SNR (dBFS) Figure 86. THS4509 and ADS5500 Circuit 90 SFDR (dBc) 85 80 SNR (dBFS) 75 70 65 10 20 30 40 50 60 70 80 Input Frequency - MHz 90 100 110 Figure 87. THS4509 and ADS5500 SFDR and SNR Performance vs Frequency Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 33 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com Figure 88 shows the two-tone FFT of the THS4509 and ADS5500 circuit with 65-MHz and 70-MHz input frequencies. The SFDR is 90 dBc. Figure 88. THS4509 and ADS5500 2-Tone FFT With 65-MHz and 70-MHz Inputs 9.2.1.2.5 THS4509 and ADS5424 Combined Performance Figure 89 shows the THS4509 driving the ADS5424 ADC, and Figure 90 shows the combined SNR and SFDR performance versus frequency with –1-dBFS input signal level and sampling at 80 MSPS. As before, the THS4509 amplifier provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5424. Input termination and circuit testing is the same as described above for the THS4509 and ADS5500 circuit. The 225-Ω resistors and 2.7-pF capacitor between the THS4509 outputs and ADS5424 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 100MHz (–3 dB). Because the ADS5424 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a single power-supply input with VS+ = 5 V and VS– = 0 V (ground). From 50-W source V IN 348 W 100 W 69 .8 W 5V 225 W 0.22 mF 100 49 .9 W 0.22 mF 69 .8 W THS4509 225 W 2 .7 pF CM 0.22 mF 348 W 14-bit, 105 MSPS A IN+ ADS 5424 A IN– VBG 49.9 W 0.1 mF 0.1 mF Copyright © 2016, Texas Instruments Incorporated Figure 89. THS4509 and ADS5424 Circuit 34 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 9.2.1.3 Application Curve SFDR (dBc), SNR (dBFS) 95 90 SFDR (dBc) 85 80 75 SNR (dBFS) 70 10 20 30 40 50 Input Frequency - MHz 60 70 Figure 90. THS4509 and ADS5424 SFDR and SNR Performance vs Frequency 9.2.2 Single-Ended Input to Differential Output Amplifier The THS4509 can be used to amplify and convert single-ended input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 91 (CM input not shown). The gain of the circuit is again set by RF divided by RG. Single-Ended Input RF RG VS Differential Output + RG – VOUT– THS 4509 – + VOUT+ VS RF Copyright © 2016, Texas Instruments Incorporated Figure 91. Single-Ended Input to Differential Output Amplifier 10 Power Supply Recommendations The THS4509 can accommodate supply voltages from 3 V to 5 V, either single supply or split supply. Unless the application calls for AC coupling and a very small signal the 5-V supply option must be chosen. In many cases, split supplies are necessary because it is important to have the output common-mode voltage set very close to the midsupply voltage. For example, when driving an ADC with an input common-mode voltage of 1 V the ideal power supply voltage would be +3.5 V and –1.5 V. Power supply decoupling capacitors must be placed within 2 mm of the amplifier power supply pins. These capacitors must be very low ESR and must have a self resonant frequency above 200 mHz. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 35 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com 11 Layout 11.1 Layout Guidelines It is recommended to follow the layout of the external components near the amplifier, ground plane construction, and power routing of the EVM as closely as possible. 11.1.1 General Guidelines 1. Signal routing should be direct and as short as possible into and out of the op amp circuit. 2. The feedback path should be short and direct; avoid vias. 3. Ground or power planes should be removed from directly under the amplifier input and output pins. 4. An output resistor is recommended on each output, as near to the output pin as possible. 5. Two 10-μF and two 0.1-μF power-supply decoupling capacitors must be placed as near to the power-supply pins as possible. 6. Two 0.1-μF capacitors must be placed between the CM input pins and ground. This configuration limits noise coupled into the pins. One each must be placed to ground near pin 4 and pin 9. 7. TI recommends splitting the ground panel on layer 2 (L2) as shown below and to use a solid ground on layer 3 (L3). A single-point connection must be used between each split section on L2 and L3. 8. A single-point connection to ground on L2 is recommended for the input termination resistors R1 and R2. This configuration must be applied to the input gain resistors if termination is not used. 9. The THS4509 recommended PCB footprint is shown in Figure 92. 11.1.2 PowerPAD PCB Layout Considerations Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach: 1. Prepare the PCB with a top side etch pattern as shown in Figure 92. There must be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. The holes must be 13 mils (0.013 in, 0.33 mm) in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. They help dissipate the heat generated by the IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered, so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This resistance makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the IC PowerPAD package should make the connection to the internal ground plane, with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask must leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This configuration prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This process results in a part that is properly installed. 36 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 Layout Guidelines (continued) 0.144 0.049 0.012 Pin 1 0.0095 0.015 0.144 0.0195 0.0705 0.010 vias 0.032 0.030 0.0245 Top View Figure 92. PowerPAD PCB Etch and Via Pattern The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer must never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class AB), most of the heat dissipation is at low output voltages with high output currents. The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability increases. For a single package, the sum of the RMS output currents and voltages must be used to choose the proper package. 11.2 Layout Example Figure 93 is the THS4509 EVAL1 EVM schematic; layers 1 through 4 of the PCB are shown Figure 94. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 37 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com GND VS− J4 VS+ J5 J6 VEE 0.1 µF TP1 C9 0.1 µF C10 VCC 10 µF C4 10 µF J1 C15 R12 49.9 Ω PD 2 3 VO+ − + R4 4 VO− PwrPad 10 R7 86.6 Ω R8 86.6 Ω 9 R2 69.8 Ω 15 13 14 16 VEE R6 J3 T1 R11 69.8 Ω 6 C8 open 5 4 C1 open 1 3 XFMR_ADT1−1WT Vocm 100 Ω R10 open C14 0.1 µF C7 open C2 open J7 348 Ω TP3 TP2 C13 R9 open 7 U1 11 0.22 µF J2 12 0.1 µF C12 VCC VCC 8 6 100 Ω 0.1 µF C5 J8 348 Ω 5 10 µF C3 R5 R1 69.8 Ω R3 10 µF C6 VEE C11 0.1 µF Figure 93. THS4509 EVAL1 EVM Schematic Figure 94. THS4509 EVAL1 EVM Layer 1 Through Layer 4 11.3 PowerPAD™ Design Considerations The THS4509 is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe on which the die is mounted (see Figure 95a and Figure 95b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package (see Figure 95c). Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. 38 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 THS4509 www.ti.com SLOS454I – JANUARY 2005 – REVISED JULY 2016 PowerPAD™ Design Considerations (continued) NOTE The THS4509 has no electrical connection between the PowerPAD and circuitry on the die. Connecting the PowerPAD to any potential voltage between VS+ and VS– is acceptable. It is most important that it be connected for maximum heat dissipation. The PowerPAD package allows both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface-mount with the previously awkward mechanical methods of heatsinking. DIE Side View (a) DIE End View (b) Bottom View (c) Figure 95. Views of Thermally-Enhanced Package Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 39 THS4509 SLOS454I – JANUARY 2005 – REVISED JULY 2016 www.ti.com 12 Device and Documentation Support 12.1 Device Support For THS4509 device support, see the following: • ADS5500 • ADS5424 • THS4509EVM Evaluation Module 12.2 Documentation Support 12.2.1 Related Documentation For related documentation, see the following: Fully-Differential Amplifiers (SLOA054) 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 40 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: THS4509 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) THS4509RGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 4509 THS4509RGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 4509 THS4509RGTTG4 ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 4509 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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