THS4513EVM

THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 WIDEBAND, LOW-NOISE, LOW-DISTORTION, FULLY-DIFFERENTIAL AMPLIFIER Check for Samples: THS4513 FEATURES DESCRIPTION • • • • • • • • • • • • • • The THS4513 is a wideband, fully-differential op amp designed for 3.3-V to 5-V data acquisition systems. It has very low noise at 2.2 nV/√Hz, and extremely low harmonic distortion of –75 dBc HD2 and –86 dBc HD3 at 70 MHz with 2-VPP output, G = 0 dB, and 200-Ω load. Slew rate is very high at 5100 V/μs and with settling time of 2.9 ns to 1% (2-V step), it is ideal for pulsed applications. It is designed for a minimum gain of 0 dB. 23 • Fully-Differential Architecture Centered Input Common-Mode Range Minimum Gain of 1 V/V (0 dB) Bandwidth: 1600 MHz Slew Rate: 5100 V/μs 1% Settling Time: 2.9 ns HD2: –75 dBc at 70 MHz HD3: –86 dBc at 70 MHz OIP2: 77 dBm at 70 MHz OIP3: 42 dBm at 70 MHz Input Voltage Noise: 2.2 nV/√Hz (f > 10 MHz) Noise Figure: 19.8 dB Output Common-Mode Control Power Supply: – Voltage: 3 V (±1.5 V) to 5 V (±2.5 V) – Current: 37.7 mA Power-Down Capability: 0.65 mA APPLICATIONS • • • • 5-V Data Acquisition Systems, High Linearity ADC Amplifier Wireless Communication Medical Imaging Test and Measurement To allow for dc-coupling to analog-to-digital converters (ADCs), its unique output common-mode control circuit maintains the output common-mode voltage within 5-mV offset (typ) from the set voltage, when set within 0.5 V of midsupply, with less than 4mV differential offset voltage. The common-mode set point is set to midsupply by internal circuitry, which may be overdriven from an external source. The input and output are optimized for best performance with their common-mode voltages set to midsupply. Along with high performance at low power-supply voltage, this design makes it ideal for extremely high-performance, single-supply 5-V data acquisition systems. The THS4513 is offered in a quad, leadless QFN-16 package (RGT), and is characterized for operation over the full industrial temperature range from –40°C to +85°C. 60 MHz Low-Pass Filter 6.8 pF VIN RELATED PRODUCTS 50-W SingleEnded AC-Coupled Source 340 W 56.2 W DEVICE MIN. GAIN THS4508 6 dB –0.3 V to 2.3 V THS4509 6 dB 1.1 V to 3.9 V THS4511 0 dB –0.3 V to 2.3 V THS4513 0 dB 1.1 V to 3.9 V To 50-W Test Equipment 25 W 0.22 mF 340 W COMMON-MODE RANGE OF INPUT(1) 348 W 2.5 V THS4513 1:1 VOUT 25 W Low-Pass Filter Response 50 W 0.22 mF 56.2 W 0.22 mF CM -2.5 V 0 0.1 mF -2 0.1 mF -4 348 W -6 -8 6.8 pF Gain (dB) 1 -10 -12 -14 -16 -18 -20 -22 -24 1. Assumes a 5-V single-ended power supply. -26 0.1 1 10 100 f - Frequency (MHz) 1000 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGING/ORDERING INFORMATION (1) PACKAGED DEVICES TEMPERATURE QUAD QFN (2) (3) (RGT-16) THS4513RGTT –40°C to +85°C (1) (2) (3) SYMBOL — THS4513RGTR For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. This package is available taped and reeled. The R suffix standard quantity is 3000. The T suffix standard quantity is 250. The exposed thermal pad is electrically isolated from all other pins. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. UNIT VS– to VS+ Supply voltage 6V VI Input voltage ±VS VID Differential input voltage IO Output current 4V (2) 200 mA Continuous power dissipation See Dissipation Ratings Table TJ Maximum junction temperature TA Operating free-air temperature range –40°C to +85°C TSTG Storage temperature range –65°C to +150°C ESD ratings (1) (2) +150°C HBM 2000 V CDM 1500 V MM 100 V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The THS4513 incorporates a (QFN) exposed thermal pad on the underside of the chip. This pad acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the QFN thermally-enhanced package. DISSIPATION RATINGS TABLE 2 PACKAGE θJC θJA RGT (16) 2.4°C/W 39.5°C/W Submit Documentation Feedback POWER RATING TA ≤ +25°C TA = +85°C 2.3 W 225 mW Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 ELECTRICAL CHARACTERISTICS: VS+ – VS– = 5 V Test conditions at VS+ = 2.5 V, VS– = –2.5 V, G = 0 dB, CM = open, VO = 2 VPP, RF = 348 Ω, RL = 200-Ω differential, TA = +25°C, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE Small-signal bandwidth Gain-bandwidth product Bandwidth for 0-dB flatness Large-signal bandwidth G = 0 dB, VO = 100 mVPP 1.6 GHz G = 6 dB, VO = 100 mVPP 1.4 GHz G = 6 dB 2.8 GHz G = 0 dB, VO = 2 VPP 150 G = 6 dB, VO = 2 VPP 700 G = 0 dB, VO = 2 VPP Slew rate (differential) Rise time fall time 3rd-order intermodulation distortion 16 f = 10 MHz –110 f = 50 MHz –80 f = 100 MHz –66 f = 10 MHz –108 f = 50 MHz –94 dBc dBc C –81 VO = 2 VPP envelope, 200-kHz tone spacing, RL = 100 Ω 2nd-order output intercept point 200-kHz tone spacing RL = 100 Ω 3rd-order output intercept point 1-dB compression point ns 2.9 f = 100 MHz 2nd-order intermodulation distortion GHz V/μs 0.5 Settling time to 0.1% 3rd-order harmonic distortion 1.4 5100 0.5 2-V step Settling time to 1% 2nd-order harmonic distortion MHz fC = 70 MHz –78 fC = 140 MHz –55 fC = 70 MHz –88 fC = 140 MHz –72 fC = 70 MHz 77 fC = 140 MHz 53 fC = 70 MHz 42 fC = 140 MHz dBc dBm 34 fC = 70 MHz 12.2 fC = 140 MHz 10.8 Noise figure 50-Ω system, 10 MHz, G = 6 dB 19.8 dB Input voltage noise f > 10 MHz 2.2 nV/√Hz Input current noise f > 10 MHz 1.7 pA/√Hz dBm DC PERFORMANCE Open-loop voltage gain (AOL) Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift (1) 63 dB TA = +25°C 1 4 mV TA = –40°C to +85°C 1 5 mV TA = –40°C to +85°C 2.6 TA = +25°C 8 15.5 TA = –40°C to +85°C 8 18.5 TA = –40°C to +85°C 20 TA = +25°C 1.6 3.6 TA = –40°C to +85°C 1.6 7 TA = –40°C to +85°C 4 C A μV/°C B μA A nA/°C B μA A nA/°C B Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 3 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued) Test conditions at VS+ = 2.5 V, VS– = –2.5 V, G = 0 dB, CM = open, VO = 2 VPP, RF = 348 Ω, RL = 200-Ω differential, TA = +25°C, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) INPUT Common-mode input range high 1.4 Common-mode input range low –1.4 Common-mode rejection ratio V 90 Differential input impedance 1.3 || 1.8 Common-mode input impedance 1.0 || 2.3 B dB MΩ || pF C OUTPUT Maximum output voltage high Each output with 100 Ω to midsupply Minimum output voltage low Differential output voltage swing TA = +25°C 1.2 1.4 TA = –40°C to +85°C 1.1 1.4 V TA = +25°C –1.4 –1.2 TA = –40°C to +85°C –1.4 –1.1 V TA = +25°C 4.8 5.6 TA = –40°C to +85°C 4.4 5.6 V 96 mA A V Differential output current drive RL = 10 Ω Output balance error VO = 100 mV, f = 1 MHz –52 dB Closed-loop output impedance f = 1 MHz 0.3 Ω Small-signal bandwidth 250 MHz Slew rate 110 V/μs 1 V/V C OUTPUT COMMON-MODE VOLTAGE CONTROL Gain Output common-mode offset from CM input –1 V < CM < 1 V 5 mV CM input bias current –1 V < CM < 1 V ±40 μA CM input voltage range –1.5 to 1.5 CM input impedance V 23 || 1 CM default voltage C kΩ || pF 0 V POWER SUPPLY Specified operating voltage Maximum quiescent current Minimum quiescent current 5 5.5 TA = +25°C 3 37.7 40.9 TA = –40°C to +85°C 37.7 41.9 TA = +25°C 34.5 37.7 TA = –40°C to +85°C 33.5 37.7 Power-supply rejection (±PSRR) V C mA A mA 90 dB C POWER-DOWN Enable voltage threshold Referenced to VS–, assured on above 2.1 V + VS– > 2.1 + VS– V Disable voltage threshold Assured off below 0.7 V + VS– < 0.7 + VS– V Power-down quiescent current Input bias current TA = +25°C 0.65 0.9 TA = –40°C to +85°C 0.65 1 PD = VS– 100 Input impedance 50 || 2 mA Measured to output on 55 ns Turn-off time delay Measured to output off 10 μs Submit Documentation Feedback A μA kΩ || pF Turn-on time delay 4 C C Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 ELECTRICAL CHARACTERISTICS: VS+ – VS– = 3 V Test conditions at VS+ = 1.5 V, VS– = –1.5 V, G = 0 dB, CM = open, VO = 1 VPP, RF = 348 Ω, RL = 200-Ω differential, TA = +25°C, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. PARAMETER TEST CONDITIONS TYP UNIT G = 0 dB, VO = 100 mVPP 1.6 GHz G = 6 dB, VO = 100 mVPP 1.3 GHz G = 6 dB 2.6 GHz G = 0 dB, VO = 1 VPP 135 G = 6 dB, VO = 1 VPP 450 TEST LEVEL (1) AC PERFORMANCE Small-signal bandwidth Gain-bandwidth product Bandwidth for 0-dB Flatness Large-signal bandwidth G = 10 dB, VO = 1 VPP Slew rate (differential) Rise time MHz 1.4 GHz 2700 V/μs 0.25 Fall time 1-V step 0.25 Settling time to 1% 2.9 Settling time to 0.1% 2nd-order harmonic distortion 3rd-order harmonic distortion 2nd-order intermodulation distortion 3rd-order intermodulation distortion 16 f = 10 MHz –116 f = 50 MHz –86 f = 100 MHz –60 f = 10 MHz –83 f = 50 MHz –61 f = 100 MHz –49 VO = 1 VPP 200-kHz tone spacing, RL = 100 Ω 2nd-order output intercept point 200-kHz tone spacing RL = 100 Ω 3rd-order output intercept point 1-dB compression point ns fC = 70 MHz –78 fC = 140 MHz –55 fC = 70 MHz –82 fC = 140 MHz –65 fC = 70 MHz 70.2 fC = 140 MHz 47 fC = 70 MHz 32.7 fC = 140 MHz 24.7 fC = 70 MHz 3 fC = 140 MHz 2 dBc dBc dBc C dBm dBm Noise figure 50-Ω system, 10 MHz, G = 6 dB 19.8 dB Input voltage noise f > 10 MHz 3.3 nV/√Hz Input current noise f > 10 MHz 1.7 pA/√Hz DC PERFORMANCE Open-loop voltage gain (AOL) Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift TA = +25°C TA = –40°C to +85°C 68 dB 1 mV 2.6 μV/°C 6 μA TA = –40°C to +85°C 20 nA/°C TA = +25°C 1.6 TA = +25°C TA = –40°C to +85°C 4 μA nA/°C INPUT Common-mode input range high 0.4 Common-mode input range low –0.4 Common-mode rejection ratio 90 Differential input impedance 1.3 || 1.8 Common-mode input impedance 1.0 || 2.3 (1) V dB MΩ || pF Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 5 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS: VS+ – VS– = 3 V (continued) Test conditions at VS+ = 1.5 V, VS– = –1.5 V, G = 0 dB, CM = open, VO = 1 VPP, RF = 348 Ω, RL = 200-Ω differential, TA = +25°C, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. PARAMETER TEST CONDITIONS TYP UNIT 0.45 V –0.45 V TEST LEVEL (1) OUTPUT Maximum output voltage high Minimum output voltage low Each output with 100 Ω to midsupply Differential output voltage swing 1.8 V 50 mA Differential output current drive RL = 10 Ω Output balance error VO = 100 mV, f = 1 MHz –54 dB Closed-loop output Impedance f = 1 MHz 0.3 Ω 150 MHz 60 V/μs 1 V/V 4 mV ±40 μA –1.5 to 1.5 V OUTPUT COMMON-MODE VOLTAGE CONTROL Small-signal bandwidth Slew rate Gain Output common-mode offset from CM input –0.5 V < CM < 0.5 V CM input bias current –0.5 V < CM < 0.5 V CM input voltage range CM input impedance 20 || 1 CM default voltage 0 C kΩ || pF V POWER SUPPLY Quiescent current Power-supply rejection (±PSRR) 34.8 mA 80 dB V POWER-DOWN Enable voltage threshold Referenced to VS–, assured on above 2.1 V + VS– > 2.1 Disable voltage threshold Assured off below 0.7 V + VS– < 0.7 V 0.46 mA Power-down quiescent current Input bias current PD = VS– Input impedance 65 50 || 2 μA kΩ || pF Turn-on time delay Measured to output on 100 ns Turn-off time delay Measured to output off 10 μs 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 DEVICE INFORMATION TOP VIEW RGT Package THS4513 VS− 16 15 14 13 NC 1 12 PD VIN− 2 11 VIN+ VOUT+ 3 10 VOUT− CM 4 9 5 6 7 CM 8 VS+ TERMINAL FUNCTIONS TERMINAL (RGT PACKAGE) NO. DESCRIPTION NAME 1 NC No internal connection 2 VIN– Inverting amplifier input 3 VOUT+ Noninverting amplifier output 4, 9 CM Common-mode voltage input 5-8 VS+ Positive amplifier power-supply input 10 VOUT– Inverted amplifier output 11 VIN+ Noninverting amplifier input 12 PD Power-down; PD = logic low puts part into low-power mode, PD = logic high or open for normal operation 13-16 VS– Negative amplifier power-supply input Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 7 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V Small-Signal Frequency Response G = 0 dB, VOD = 100 mVPP Figure 1 G = 6 dB, VOD = 100 mVPP Figure 2 Large-Signal Frequency Response G = 0 dB, VOD = 2 VPP Figure 3 G = 6 dB, VOD = 2 VPP Figure 4 HD2, G = 0 dB, VOD = 2 VPP vs Frequency Figure 5 HD3, G = 0 dB, VOD = 2 VPP vs Frequency Figure 6 HD2, G = 6 dB, VOD = 2 VPP vs Frequency Figure 7 HD3, G = 6 dB, VOD = 2 VPP vs Frequency Figure 8 HD2, G = 0 dB vs Output Voltage Figure 9 HD3, G = 0 dB vs Output Voltage Figure 10 HD2, G = 0 dB vs CM Output Voltage Figure 11 HD3, G = 0 dB vs CM Output Voltage Figure 12 IMD2, G = 0 dB vs Frequency Figure 13 IMD3, G = 0 dB vs Frequency Figure 14 OIP2 vs Frequency Figure 15 OIP3 vs Frequency Figure 16 S-Parameters vs Frequency Figure 17 Transition Rate vs Output Voltage Figure 18 Harmonic Distortion Intermodulation Distortion Output Intercept Point Transient Response Figure 19 Settling Time Figure 20 Rejection Ratio vs Frequency Figure 21 Output Impedance vs Frequency Figure 22 Overdrive Recovery Output Voltage Swing Figure 23 vs Load Resistance Figure 24 Turn-Off Time Figure 25 Turn-On Time Figure 26 Input Offset Voltage vs Input Common-Mode Voltage Figure 27 Open-Loop Gain vs Frequency Figure 28 Input-Referred Noise vs Frequency Figure 29 Noise Figure vs Frequency Figure 30 Quiescent Current vs Supply Voltage Figure 31 Power-Supply Current vs Supply Voltage in Power-Down Mode Figure 32 Output Balance Error vs Frequency Figure 33 CM Input Impedance vs Frequency Figure 34 CM Small-Signal Frequency Response Figure 35 CM Input Bias Current vs CM Input Voltage Figure 36 Differential Output Offset Voltage vs CM Input Voltage Figure 37 Output Common-Mode Offset vs CM Input Voltage Figure 38 8 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V Test conditions at VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE 6 5 RL = 1K W RL = 500 W 4 Small Signal Gain - dB SMALL-SIGNAL FREQUENCY RESPONSE 7 G = 0 dB VOD =100 mVpp 6 RL = 200 W Small Signal Gain - dB 7 3 2 1 0 -1 RL = 100 W -2 -3 -4 G = 6 dB VOD = 100 mVpp 5 RL = 1K W RL = 500 W 4 RL = 200 W 3 RL = 100 W 2 1 -5 -6 10 100 1000 0 1000 10 100 f- Frequency -MHz Figure 1. LARGE-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 8 7 RL = 1K W RL = 500 W Large Signal Gain - dB Small Signal Gain - dB 3 10000 Figure 2. 6 G = 0 dB 5 V = 2 Vpp OD 4 1000 f- Frequency -MHz 2 1 RL = 200 W 0 -1 RL = 100 W -2 -3 6 5 G = 6 dB VOD = 2 Vpp RL = 1K W RL = 500 W 4 RL = 200 W RL = 100 W 3 2 -4 1 -5 -6 10 100 1000 0 10 10000 f - Frequency - MHz 100 Figure 3. 10000 Figure 4. HD2 vs FREQUENCY HD3 vs FREQUENCY -60 -70 G = 0 dB VOD = 2 Vpp -70 RL = 200 W RL = 500 W -80 RL = 1K W RL = 100 W -90 -100 -110 -120 -130 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc 1000 f- Frequency -MHz G = 0 dB VOD = 2 Vpp -80 -90 RL = 100 W -100 RL = 200 W -110 RL = 500 W RL = 1K W -120 1 10 100 f - Frequency - MHz 1000 1 Figure 5. 10 100 f - Frequency - MHz 1000 Figure 6. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 9 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued) Test conditions at VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. HD2 vs FREQUENCY HD3 vs FREQUENCY -70 G = 6 dB VOD = 2 Vpp -60 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc -50 -70 RL = 200 W -80 RL = 500 W RL = 100 W -90 RL = 1K W -100 -110 -120 10 100 f - Frequency - MHz 1 1000 G = 6 dB VOD = 2 Vpp -80 RL = 1K W -90 RL = 100 W -100 RL = 200 W -110 RL = 500 W -120 10 1 Figure 7. HD2 vs OUTPUT VOLTAGE 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc f = 100 MHz -60 f = 64 MHz -70 -80 f = 32 MHz -90 f = 8 MHz -100 f=16MHz -110 HD3 vs OUTPUT VOLTAGE -40 f = 150 MHz G = 0 dB -50 VOD = 2 Vpp f = 150 MHz G = 0 dB -50 VOD = 2 VPP f = 100 MHz -60 f = 64 MHz -70 -80 f = 32 MHz -90 f = 8 MHz -100 f = 16 MHz -110 -120 0 1 2 3 VOD - Output Voltage- Vpp 4 0 5 1 2 HD3 vs OUTPUT COMMON-MODE VOLTAGE 0 G = 0 dB VOD = 2 VPP RL = 200 W 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc HD2 vs OUTPUT COMMON-MODE VOLTAGE 150 MHz 100 MHz -40 64 MHz -60 -80 -100 -120 16 MHz 4 MHz 1 MHz G = 0 dB VOD = 2 VPP RL = 200 W -20 150 MHz -40 100 MHz -60 64 MHz -80 4 MHz -100 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 16 MHz 1 MHz -120 -140 -1 5 4 Figure 10. 0 -20 3 VOD - Output Voltage- VPP Figure 9. -1 VCM - Output Common-Mode Voltage - V Figure 11. 10 1000 Figure 8. -40 -120 100 f - Frequency - MHz -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 VCM - Output Common-Mode Voltage - V Figure 12. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued) Test conditions at VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. IMD2 vs FREQUENCY IMD3 vs FREQUENCY -60 VOD = 2 Vpp Envelope 200 kHz Tone Spacing -40 -50 IMD3 - Intermodulation Distortion - dBc IMD2 - Intermodulation Distortion - dBc -30 RL = 1k W -60 RL = 200 W -70 -80 RL = 100 W -90 -100 0 50 100 150 VOD = 2 Vpp Envelope 200 kHz Tone Spacing -70 RL = 1K W -90 RL = 200 W -100 -110 200 RL = 100 W -80 0 50 f - Frequency - MHz 100 f - Frequency - MHz Figure 13. 75 65 55 50 OIP3 - Output Intercept Point - dBm OIP2 - Output Intercept Point - dBm OIP3 vs FREQUENCY VOD = 2 Vpp Envelope 200 kHz Tone Spacing RL = 100 W 85 VOD = 2 Vpp Envelope 200 kHz Tone Spacing RL = 100 W 45 40 35 30 45 0 50 100 150 200 0 50 100 f - Frequency - MHz f - Frequency - MHz Figure 15. Figure 16. S-PARAMETERS vs FREQUENCY 150 200 TRANSITION RATE vs OUTPUT VOLTAGE 6000 20 RL = 200 W 10 0 5000 Transition Rate - V/ms S21 -10 s-Parameter - dB 200 Figure 14. OIP2 vs FREQUENCY 95 150 -20 -30 S22 S11 -40 -50 -60 S12 -70 Falling Rising 4000 3000 2000 1000 -80 -90 0 0.1 1 10 100 f - Frequency - MHz 1000 0 0.5 1 1.5 2 2.5 3 VOD - Output Voltage - VPP Figure 17. Figure 18. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 11 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued) Test conditions at VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. SETTLING TIME 5 VOD = 2 Vpp RL = 200 W 4 3 2 Percent of Final Value VOD - Differential Output Voltage - V TRANSIENT RESPONSE 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1 -1.25 -1.5 -1.75 -2 RL = 200 W VOD = 2 Vpp 1 0 -1 -2 -3 -4 -5 0 250 ps / div 1 3 2 4 5 6 t - Time t - Time - ns Figure 19. Figure 20. REJECTION RATIO vs FREQUENCY 7 8 9 10 OUTPUT IMPEDANCE vs FREQUENCY 100 100 RL = 200 W 90 Zo - Output Impedance - W PSRR70 60 PSRR+ 50 40 0.1 1 10 100 0.1 1000 Figure 21. Figure 22. 3 2.0 7 1.5 6 1.0 Output 1 0.5 0 0.0 -1 -0.5 -2 -1.0 -3 -1.5 0.4 0.6 t - Time - ms 0.8 -2.0 1.0 Input Voltage - V VOD - Differential Output Voltage - V Input 100 1000 OUTPUT VOLTAGE SWING vs LOAD RESISTANCE RL = 200 W VS = 5 V -4 5 4 3 2 1 0 0 Figure 23. 12 10 f - Frequency- MHz OVERDRIVE RECOVERY 0.2 1 f - Frequency - MHz 4 0 1 0.1 30 0.01 2 10 VOD - Differential Output Voltage - V Rejection Ratio - dB CMRR 80 500 1000 1500 RL- Load Resistance - W 2000 Figure 24. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued) Test conditions at VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. TURN-OFF TIME TURN-ON TIME 1.2 3 PD 2 0.4 1 PD 1.2 0.8 0 2 4 6 8 10 t − Time − µs 1 0 50 Figure 25. 100 150 t − Time − ns 200 Figure 26. INPUT OFFSET VOLTAGE vs INPUT COMMON-MODE VOLTAGE V IO − Input Offset V oltage − mV 0 250 0 14 12 2 Output 0.4 0 0 3 OPEN-LOOP GAIN vs FREQUENCY 40 80 60 35 70 30 60 0 Gain 30 -30 Open-loop Gain - dB 50 25 20 15 10 5 0 −5 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 Input Common-Mode Voltage − V 2 2.5 -60 40 Phase 30 -90 20 -120 10 -150 0 -180 -10 -210 -20 RL = 200 W VS = 5 V -30 10K 100K -240 1M 10M 100M f - Frequency - Hz Figure 27. 1G Phase 0.8 4 1.6 Power Down Input − V 4 Output VOD − Differential Output V oltage − V 1.6 5 2 5 Power Down Input − V VOD − Differential Ouput Voltage − V 2 -270 10G Figure 28. INPUT-REFERRED NOISE vs FREQUENCY NOISE FIGURE vs FREQUENCY 23 1000 NF - Noise Figure - dB Vn - Voltage Noise - nV/rt(Hz) In - Current Noise - pA/rt(Hz) 50-W System G = 6 dB 100 In Vn 10 22 21 20 19 18 1 10 100 1000 10000 100000 1M 10 M 0 f - Frequency - Hz 20 40 60 80 100 120 140 160 180 200 f - Frequency -MHz Figure 29. Figure 30. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 13 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued) Test conditions at VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE QUIESCENT CURRENT vs SUPPLY VOLTAGE 40 PDIQ - Powerdown Quiescent Current - mA 1000 IQ - Quiescent Current - mA TA = 25°C 35 30 25 20 1 1.5 2 TA = 25°C 900 800 700 600 500 400 300 200 100 0 2.5 0 0.5 ±VS - Supply Voltage- V 1 Figure 31. 2 2.5 Figure 32. OUTPUT BALANCE ERROR RESPONSE vs FREQUENCY CM INPUT IMPEDANCE vs FREQUENCY 100 -20 CM Input Impedance − k Ω RL = 200 W VOD = 500 mVpp -25 -30 Balance Error - dB 1.5 ±VS - Supply Voltage- V -35 -40 -45 -50 10 1 0.1 -55 0.01 0.1 -60 0.1 1 10 f- Frequency -MHz 100 1000 1 10 100 f − Frequency − MHz 1000 Figure 33. Figure 34. CM SMALL-SIGNAL FREQUENCY RESPONSE CM INPUT BIAS CURRENT vs CM INPUT VOLTAGE 150 2 100 CM Input Bias Current - mA 1 CM Gain - dB 0 -1 -2 -3 50 0 -50 -100 -150 -200 -4 0.1 -250 1 10 100 1000 -3 Figure 35. 14 -2 -1 0 1 2 3 CM INPUT VOLTAGE - V f - Frequency- MHz Figure 36. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued) Test conditions at VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. DIFFERENTIAL OUTPUT OFFSET VOLTAGE vs CM INPUT COMMON-MODE VOLTAGE OUTPUT COMMON-MODE OFFSET vs CM INPUT VOLTAGE 50 40 3.0 CM Output Offset Voltage -mV Differential Output Offset Voltage - mV 4.0 2.0 1.0 0.0 -1.0 30 20 10 0 -10 -20 -30 -40 -2.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 CM Input Common-Mode Voltage - V 2.0 2.5 -50 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 CM Input Common-Mode Voltage - V Figure 37. Figure 38. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 15 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS: VS+ – VS– = 3 V Small-Signal Frequency Response Large-Signal Frequency Response G = 0 dB, VOD = 100 mVPP Figure 39 G = 6 dB, VOD = 100 mVPP Figure 40 G = 0 dB, VOD = 1 VPP Figure 41 G = 6 dB, VOD = 1 VPP Figure 42 HD2, G = 0 dB, VOD = 1 VPP vs Frequency Figure 43 HD3, G = 0 dB, VOD = 1 VPP vs Frequency Figure 44 HD2, G = 6 dB, VOD = 1 VPP vs Frequency Figure 45 HD3, G = 6 dB, VOD = 1 VPP vs Frequency Figure 46 HD2, G = 0 dB vs Output Voltage Figure 47 HD3, G = 0 dB vs Output Voltage Figure 48 HD2, G = 0 dB vs CM Output Voltage Figure 49 HD3, G = 0 dB vs CM Output Voltage Figure 50 IMD2, G = 0 dB vs Frequency Figure 51 IMD3, G = 0 dB vs Frequency Figure 52 OIP2 vs Frequency Figure 53 OIP3 vs Frequency Figure 54 S-Parameters vs Frequency Figure 55 Transition Rate vs Output Voltage Figure 56 Harmonic Distortion Intermodulation Distortion Output Intercept Point Transient Response Figure 57 Settling Time Figure 58 Output Voltage Swing vs Load Resistance Figure 59 Rejection Ratio vs Frequency Figure 60 Overdrive Recovery Output Impedance Figure 61 vs Frequency Figure 62 Turn-Off Time Figure 63 Turn-On Time Figure 64 Output Balance Error vs Frequency Figure 65 Noise Figure vs Frequency Figure 66 CM Small-Signal Frequency Response Figure 67 CM Input Impedance vs Frequency Figure 68 Differential Output Offset Voltage vs CM Input Voltage Figure 69 Output Common-Mode Offset vs CM Input Voltage Figure 70 16 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS: VS+ – VS– = 3 V Test conditions at VS+ = +1.5 V, VS– = –1.5V, CM = open, VOD = 1 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE 5 4 3 2 6 5 RL = 100 W Signal Gain - dB Signal Gain - dB SMALL-SIGNAL FREQUENCY RESPONSE 7 RL = 1K W RL = 500 W RL = 200 W Gain = 0 dB VOD = 100 mVpp 1 0 -1 -2 Gain = 6dB VO = 100 mVpp RL = 1K W RL = 500 W 4 RL = 200 W 3 RL = 100 W 2 -3 -4 1 -5 -6 0.1 0 1 10 100 1000 10 10000 100 1000 f- Frequency -MHz f- Frequency -MHz Figure 39. Figure 40. LARGE-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 5 8 Gain = 0 dB VO = 1 VPP 4 RL = 1 kW RL = 500 W RL = 200 W 3 6 2 1 0 -1 Gain = 6 dB VOD = 1 VPP 7 Signal Gain - dB Signal Gain - dB 10000 RL = 100 W -2 -3 RL = 1 kW RL = 500 W 5 4 RL = 100 W RL = 200 W 3 2 -4 1 -5 0 10 -6 0.1 1 10 100 1000 10000 100 Figure 41. 10000 Figure 42. HD2 vs FREQUENCY HD3 vs FREQUENCY -40 -40 Gain = 0 dB VOD = 1 VPP -50 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc 1000 f - Frequency - MHz f- Frequency - MHz RL = 1 kW -60 -70 -80 RL = 200 W RL = 100 W -90 RL = 500 W -100 -110 Gain = 0 dB, VOD = 1 VPP -50 -60 RL = 500 W -70 RL = 100 W -80 RL = 1 kW -90 RL = 200 W -100 -120 1 10 100 1000 1 10 100 f - Frequency - MHz f - Frequency - MHz Figure 43. Figure 44. 1000 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 17 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS: VS+ – VS– = 3 V (continued) Test conditions at VS+ = +1.5 V, VS– = –1.5V, CM = open, VOD = 1 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. HD2 vs FREQUENCY HD3 vs FREQUENCY -40 Gain = 6 dB, VOD = 1 VPP -50 -60 RL = 1 kW 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc -40 RL = 200 W -70 -80 -90 RL =100 W -100 RL = 500 W -110 -120 1 10 100 Gain = 6 dB, VOD = 1 VPP -50 -60 RL = 500 W -70 RL = 100 W -80 -90 RL = 200W -100 1 1000 Figure 46. HD2 vs OUTPUT VOLTAGE HD3 vs OUTPUT VOLTAGE -20 -20 f = 150 MHz Gain = 0 dB, RL = 200 W -30 -40 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc 1000 f - Frequency - MHz Figure 45. f = 100 MHz -50 f = 64 MHz -60 -70 -80 -90 f = 32 MHz -100 -110 f = 8 MHz f = 16 MHz -120 Gain = 0 dB, RL = 200 W -30 f = 150 MHz -40 f = 100 MHz -50 f = 64 MHz -60 f = 32 MHz -70 f = 16 MHz -80 f = 8 MHz -90 -100 -110 0 0.5 1 1.5 2 2.5 0 0.5 VOD - Output Voltage - VPP 1 1.5 2 2.5 VOD - Output Voltage - VPP Figure 47. Figure 48. HD2 vs OUTPUT COMMON-MODE VOLTAGE HD3 vs OUTPUT COMMON-MODE VOLTAGE 0 0 3rd Order Harmonic Distortion - dBc f=150MHZ f=100MHZ 2nd Order Harmonic Distortion - dBc 100 10 f - Frequency - MHz -20 -40 -60 f=64MHZ -80 f=32MHZ -100 f=1MHZ -120 f=8MHZ -140 -10 f = 100 MHz f = 150 MHz -20 -30 -40 -50 f = 64 MHz -60 f = 32 MHz -70 -80 f = 8 MHz f = 1 MHz -90 -100 -1 18 RL = 1 kW -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 V CM - Output Common-mode Voltage - V V CM - Output Common-mode Voltage - V Figure 49. Figure 50. Submit Documentation Feedback 1 Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS: VS+ – VS– = 3 V (continued) Test conditions at VS+ = +1.5 V, VS– = –1.5V, CM = open, VOD = 1 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. IMD2 vs FREQUENCY IMD3 vs FREQUENCY -55 VOD = 1 VPP Envelope 200 kHz Tone Spacing -40 IMD3 - Intermodulation Distortion - dBc IMD2 - Intermodulation Distortion - dBc -35 -45 -50 RL = 1 kW -55 RL = 100 W -60 -65 RL = 200 W -70 -75 -80 -85 -90 0 50 100 150 VOD = 1 VPP Envelope 200 kHz Tone Spacing -60 -65 -70 -75 RL = 100 W -80 -85 RL = 200 W -90 RL = 1 kW -95 -100 200 0 50 f - Frequency - MHz Figure 51. 150 200 Figure 52. OIP2 vs FREQUENCY OIP3 vs FREQUENCY 45 85 VOD = 1 VPP Envelope 200 kHz Tone Spacing RL = 100 W 80 75 OIP3 - Output Intercept Point - dBm OIP2 - Output Intercept Point - dBm 100 f - Frequency - MHz 70 65 60 55 50 45 40 35 VOD = 1 VPP Envelope 200 kHz Tone 40 35 30 25 20 0 50 100 200 150 0 50 100 f - Frequency - MHz f - Frequency - MHz Figure 53. Figure 54. S-PARAMETERS vs FREQUENCY 150 200 TRANSITION RATE vs OUTPUT VOLTAGE 20 3000 RL = 200 W 10 0 2500 S21 Falling s-Parameter - dB -10 Rising 2000 -20 S22 -30 1500 S11 -40 -50 1000 S12 -60 -70 500 -80 -90 0.1 0 1 10 100 1000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 f - Frequency - MHz VOD - Differential Output Voltage - VPP Figure 55. Figure 56. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 19 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS: VS+ – VS– = 3 V (continued) Test conditions at VS+ = +1.5 V, VS– = –1.5V, CM = open, VOD = 1 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. SETTLING TIME 5 0.75 4 Percent of Final Value - % VOD - Differential Output Voltage - V TRANSIENT RESPONSE 1 0.5 0.25 RL = 200 W VOD = 1 VPP 0 -0.25 -0.5 -0.75 -1 VOD = 1 VPP 3 2 1 0 -1 -2 -3 -4 250 ps / div -5 t - Time 0 1 2 3 4 5 6 7 8 9 10 t - Time - ns Figure 57. Figure 58. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE REJECTION RATIO vs FREQUENCY 2.5 100 CMRR 90 2 Rejection Ratio - dB VOD - Differential Output Voltage - V RL = 200 W 1.5 1 80 PSRR70 PSRR+ 60 50 0.5 40 0 0 500 30 0.01 2000 1000 1500 RL - Load Resistance - W 1 10 100 1000 f - Frequency - MHz Figure 59. Figure 60. OVERDRIVE RECOVERY OUTPUT IMPEDANCE vs FREQUENCY 100 1.5 1.0 Input ZO - Output Impedance - W RL = 150 W G = 0 dB VO - Output Voltage - V Input Voltage - V 0.1 0.5 0 Output -0.5 10 1 -1.0 0.1 -1.5 0 0.2 0.4 0.6 0.8 1 0.1 t - Time - ms Figure 61. 20 1 10 f - Frequency- MHz 100 1000 Figure 62. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS: VS+ – VS– = 3 V (continued) Test conditions at VS+ = +1.5 V, VS– = –1.5V, CM = open, VOD = 1 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. TURN-OFF TIME TURN-ON TIME 1.5 0.4 PD 1 0.2 0.5 0 2 4 6 8 10 12 PD 0.8 2 1.5 0.6 Output 0.4 1 0.2 0.5 0 250 0 0 0 2.5 1 0 14 Power Down Input − V 2 VOD − Differential Ouput Voltage - V Output 0.6 Power Down Input − V VOD − Differential Ouput Voltage - V 2.5 0.8 3 1.2 3 1 50 100 150 200 t − Time − ns t - Time - ms Figure 63. Figure 64. OUTPUT BALANCE ERROR vs FREQUENCY NOISE FIGURE vs FREQUENCY 23 -20 RL = 200 W VOD = 500 mVPP -25 50-W System G = 6 dB NF - Noise Figure - dB Balance Error - dB 22 -30 -35 -40 -45 -50 21 20 19 -55 18 -60 0.1 1 10 100 1000 0 20 40 60 80 100 120 140 f - Frequency - MHz f - Frequency - MHz Figure 65. Figure 66. CM SMALL-SIGNAL FREQUENCY RESPONSE 160 180 200 CM INPUT IMPEDANCE vs FREQUENCY 100 2 CM Input Impedance − k Ω VOCM - Gain - dB 1 0 -1 -2 10 1 0.1 -3 -4 0.1 1 10 100 1000 0.01 0.1 f - Frequency - MHz Figure 67. 1 100 10 f − Frequency − MHz 1000 Figure 68. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 21 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS: VS+ – VS– = 3 V (continued) Test conditions at VS+ = +1.5 V, VS– = –1.5V, CM = open, VOD = 1 VPP, RF = 348 Ω, RL = 200-Ω differential, G = 0 dB, singleended input, and input and output referenced to midsupply, unless otherwise noted. DIFFERENTIAL OUTPUT OFFSET VOLTAGE vs CM INPUT VOLTAGE OUTPUT COMMON-MODE OFFSET vs CM INPUT VOLTAGE 50 Output Common−Mode Offset − mV Differential Output Offset V oltage − mV 5 4 3 2 1 0 −1 −1.5 −1 −0.5 0 0.5 CM Input Voltage − V 1 1.5 40 30 20 10 0 −10 −20 −30 −40 −50 −1.5 Figure 69. 22 −1 −0.5 0 0.5 CM Input Voltage - V 1 1.5 Figure 70. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 TEST CIRCUITS The THS4513 is tested with the following test circuits built on the evaluation module (EVM). For simplicity, power-supply decoupling is not shown—see Layout Recommendations in the Applications section for recommendations. Depending on the test conditions, component values are changed per the following tables, or as otherwise noted. The signal generators used are ac-coupled, 50-Ω sources and a 0.22-μF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the alternate input to balance the circuit. A split power supply is used to ease the interface to common test equipment, but the amplifier can be operated single-supply as described in the applications section with no impact on performance. The output is probed using a high-impedance differential probe across the 100-Ω resistor. The gain is referred to the amplifier output by adding back the 6-dB loss due to the voltage divider on the output. From 50 Ω Source VIN RG R IT RF VS+ 49.9 Ω RG 0.22 µF THS4513 49.9 Ω CM R IT Output Measured Here With High Impedance Differential Probe Open 0.22 µF VS− 49.9 Ω 100 Ω RF Figure 71. Frequency Response Test Circuit Table 1. Gain Component Values GAIN RF RG RIT 0 dB 348 Ω 340 Ω 56.2 Ω 6 dB 348 Ω 165 Ω 61.9 Ω Note the gain setting includes 50-Ω source impedance. Components are chosen to achieve gain and 50-Ω input termination. Table 2. Load Component Values RL RO ROT Atten. 100 Ω 25 Ω Open 6 dB 200 Ω 86.6 Ω 69.8 Ω 16.8 dB 499 Ω 237 Ω 56.2 Ω 25.5 dB 1k Ω 487 Ω 52.3 Ω 31.8 dB Note the total load includes 50-Ω termination by the test equipment. Components are chosen to achieve load and 50-Ω line termination through a 1:1 transformer. Due to the voltage divider on the output formed by the load component values, the amplifier output is attenuated. The column Atten in Table 2 shows the attenuation expected from the resistor divider. When using a transformer at the output as shown in Figure 72, the signal will see slightly more loss, and these numbers will be approximate. Distortion and 1-dB Compression The circuit shown in Figure 72 is used to measure harmonic distortion, intermodulation distortion, and 1db compression point of the amplifier. A signal generator is used as the signal source and the output is measured with a spectrum analyzer. The output impedance of the signal generator is 50 Ω. RIT and RG are chosen to impedance-match to 50 Ω, and to maintain the proper gain. To balance the amplifier, a 0.22-μF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the alternate input. A low-pass filter is inserted in series with the input to reduce harmonics generated at the signal source. The level of the fundamental is measured, then a high-pass filter is inserted at the output to reduce the fundamental so that it does not generate distortion in the input of the spectrum analyzer. The transformer used in the output to convert the signal from differential to single-ended is an ADT11WT. It limits the frequency response of the circuit so that measurements cannot be made below approximately 1 MHz. From 50 Ω Source VIN RF RG RIT VS+ RO Frequency Response The circuit shown in Figure 71 is used to measure the frequency response of the circuit. A network analyzer is used as the signal source and as the measurement device. The output impedance of the network analyzer is 50 Ω. RIT and RG are chosen to impedance match to 50 Ω, and to maintain the proper gain. To balance the amplifier, a 0.22-μF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the alternate input. RG 0.22 µF THS 4513 CM RIT VS− 49.9 Ω RO 1:1 VOUT ROT To 50 Ω Test Equipment Open 0.22 µF RF Figure 72. Distortion Test Circuit Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 23 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com The 1-dB compression point is measured with a spectrum analyzer with 50-Ω double termination or 100-Ω termination; see Table 2. The input power is increased until the output is 1 dB lower than expected. The number reported in the table data is the power delivered to the spectrum analyzer input. Add 3 dB to refer to the amplifier output. S-Parameter, Slew Rate, Transient Response, Settling Time, Output Impedance, Overdrive, Output Voltage, and Turn-On/Off Time CM Input The circuit shown in Figure 74 is used to measure the frequency response and input impedance of the CM input. Frequency response is measured single-ended at VOUT+ or VOUT– with the input injected at VIN, RCM = 0 Ω and RCMT = 49.9 Ω. The input impedance is measured with RCM = 49.9 Ω with RCMT = open, and calculated by measuring the voltage drop across RCM to determine the input current. RF RG The circuit shown in Figure 73 is used to measure sparameters, slew rate, transient response, settling time, output impedance, overdrive recovery, output voltage swing, and turn-on/turn-off times of the amplifier. For output impedance, the signal is injected at VOUT with VIN left open and the drop across the 49.9-Ω resistor is used to calculate the impedance seen looking into the amplifier output. Because S21 is measured single-ended at the load with 50-Ω double termination, add 12 dB to refer to the amplifier’s output as a differential signal. From V IN 50 Ω Source R IT VS+ 49.9 Ω VOUT+ RG THS 4513 49.9 Ω VOUT− 0.22 µF CM R IT 49.9 Ω VS− RIT VS+ 49.9 W 49.9 W VOUT– RG 0.22 mF THS4513 49.9 W VOUT+ CM RIT RCM VIN VS– 49.9 W To 50-W Test Equipment RCMT RF From 50-W source Figure 74. CM Input Test Circuit CMRR and PSRR RF RG 0.22 mF To 50 Ω Test Equipment The circuit shown in Figure 75 is used to measure the CMRR and PSRR of VS+ and VS–. The input is switched appropriately to match the test being performed. Open 0.22 µF 348 Ω VS+ RF Figure 73. S-Parameter, SR, Transient Response, Settling Time, ZO, Overdrive Recovery, VOUT Swing, and Turn-On/Off Test Circuit PSRR+ From VIN 50 Ω CMRR Source PSRR− VS− VS+ 49.9 Ω 100 Ω 100 Ω THS4513 CM 69.8 Ω VS− 49.9 Ω 100 Ω Open 0.22 µF Output Measured Here With High Impedance Differential Probe 348 Ω Figure 75. CMRR and PSRR Test Circuit 24 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 APPLICATION INFORMATION Amplifier APPLICATIONS The following circuits show application information for the THS4513. For simplicity, power-supply decoupling capacitors are not shown in these diagrams. Please see the THS4513 EVM section for recommendations. For more detail on the use and operation of fully-differential op amps refer to the application report, Fully-Differential Amplifiers (SLOA054). The THS4513 can be used to amplify and convert single-ended input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 77 (CM input not shown). The gain of the circuit is again set by RF divided by RG. Single-Ended Input RG RF VS Differential Output Differential Input to Differential Output Amplifier + The THS4513 is a fully-differential op amp, and can be used to amplify differential input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 76 (CM input not shown). The gain of the circuit is set by RF divided by RG. – VOUT– THS 4513 RG – + VOUT+ VS RF RF Differential Input RG V IN+ Differential Output VS+ Input Common-Mode Voltage Range + – VOUT– THS4513 VIN– RG Figure 77. Single-Ended Input to Differential Output Amplifier – + VOUT+ VS– RF Figure 76. Differential Input to Differential Output Amplifier Depending on the source and load, input and output termination can be accomplished by adding RIT and RO. Single-Ended Input to Differential Output The input common-model voltage of a fully differential op amp is the voltage at the '+' and '–' input pins of the op amp. It is important to not violate the input common-mode voltage range (VICR) of the op amp. Assuming the op amp is in linear operation the voltage across the input pins is only a few millivolts at most. So finding the voltage at one input pin will determine the input common-mode voltage of the op amp. Treating the negative input as a summing node, the voltage is given by Equation 1: ö ö æ æ RG RF ÷ ÷ + ç VIN- ´ VIC = çç VOUT + ´ ÷ ç R G + R F ÷ø R G + RF ø è è (1) To determine the VICR of the op amp, the voltage at the negative input is evaluated at the extremes of VOUT+. As the gain of the op amp increases, the input common-mode voltage becomes closer and closer to the input common-mode voltage of the source. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 25 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com Setting the Output Common-Mode Voltage The output common-mode voltage is set by the voltage at the CM pin(s). The internal common-mode control circuit maintains the output common-mode voltage within 3-mV offset (typ) from the set voltage, when set within 0.5 V of midsupply, with less than 4mV differential offset voltage. If left unconnected, the common-mode set point is set to midsupply by internal circuitry, which may be over-driven from an external source. Figure 78 is representative of the CM input. The internal CM circuit has about 700 MHz of –3-dB bandwidth, which is required for best performance, but it is intended to be a dc bias input pin. Bypass capacitors are recommended on this pin to reduce noise at the output. The external current required to overdrive the internal resistor divider is given by Equation 2: IEXT 2VCM - (VS + - VS - ) = 50 kW In Figure 79, the signal source is referenced to a voltage derived from the CM pin via a unity-gain wideband buffer such as the BUF602. VCM is set to midsupply by THS4513 internal circuitry. RT along with the input impedance of the amplifier provides input termination, which is also referenced to VCM. Note that RS and RT are added to the alternate input from the signal input to balance the amplifier. Alternately, one resistor can be used equal to the combined value RG+ RS || RT on this input. This technique is also true of the circuits shown in Figure 80 and Figure 81. RS RG RF VS+ RT VSIGNAL RO + VBIAS = VCM - VCM THS4513 RG VOUT+ (2) CM RS where VCM is the voltage applied to the CM pin. RT VS- G=1 VCM VCM to internal CM circuit I EXT VCM Wideband Buffer RF VS+ 50 kW VOUT- RO Figure 79. THS4513 DC-Coupled Single-Supply with Input Biased to VCM CM In Figure 80, the source is referenced to ground and so is the input termination resistor. RPU is added to the circuit to avoid violating the VICR of the op amp. The proper value of resistor to add can be calculated from Equation 3: 50 kW V S– R PU = Figure 78. CM Input Circuit Single-Supply Operation (3 V to 5 V) To facilitate testing with common lab equipment, the THS4513 EVM allows split-supply operation, and the characterization data presented in this data sheet were taken with split-supply power inputs. The device can easily be used with a single-supply power input without degrading the performance. Figure 79, Figure 80, and Figure 81 show dc and ac-coupled single-supply circuits with single-ended inputs. These configurations all allow the input and output commonmode voltage to be set to midsupply allowing for optimum performance. The information presented here can also be applied to differential input sources. (VIC - VS+ ) æ 1 VCM çç è RF æ 1 ö 1 ÷÷ - VIC çç + è R IN R F ø ö ÷÷ ø (3) V S+ R PU RS RF RG V Signal RT V S+ V S+ RO V OUT- R PU RG THS 4513 RO V OUT+ RS RT V S- CM RF Figure 80. THS4513 DC-Coupled Single-Supply with RPU Used to Set VIC 26 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 VIC is the desired input common-mode voltage, VCM = CM, and RIN = RG+ RS || RT. To set to midsupply, make the value of RPU = RG+ RS || RT. Table 3 is a modification of Table 1 to add the proper values with RPU assuming a 50-Ω source impedance and setting the input and output common-mode voltage to midsupply. There are two drawbacks to this configuration. One is that it requires additional current from the power supply. Using the values shown for a gain of 0 dB requires 14 mA more current with 5-V supply, and 8.2 mA more current with 3-V supply. The other drawback is that this configuration also increases the noise gain of the circuit. In the 10-dB gain case, noise gain increases by a factor of 1.5. driving 50-Ω test equipment. The circuit as shown has an overall gain of –6 dB due to the voltage divider on the device output, and has a roll-off frequency of approximately 60 MHz. The measured gain versus frequency response of the overall circuit is shown in Figure 83. The low-frequency roll-off is due to losses in the output transformer at those frequencies. 6.8 pF VIN 50-W SingleEnded AC-Coupled Source 340 W 56.2 W 50 W RF RG RIT RPU 0 dB 348 Ω 340 Ω 56.2 Ω 365 Ω 6 dB 348 Ω 168 Ω 64.9 Ω 200 Ω RG THS4513 1:1 VOUT 25 W CM 56.2 W 0.22 mF 0.1 mF 0.22 mF 0.1 mF 348 W Figure 81 shows ac-coupling to the source. Using capacitors in series with the termination resistors allows the amplifier to self-bias both input and output to midsupply. C 25 W -2.5 V Gain RS To 50-W Test Equipment 2.5 V 0.22 mF 340 W Table 3. RPU Values for Various Gains 348 W 6.8 pF Figure 82. 60-MHz Low-Pass Filter 0 RF -2 RT -4 V S+= 3V to 5V -6 RO C THS4513 RO V OUT+ RS C RT C -8 V OUTRG CM V S- Gain (dB) V SIGNAL -10 -12 -14 -16 -18 RF -20 -22 -24 Figure 81. THS4513 AC-Coupled Single-Supply -26 0.1 Low-Pass Filter One application for the THS4513 is as a unity-gain buffer with low-pass filtering. Figure 82 shows a circuit that is driven by an ac-coupled 50-Ω source. A 1:1 transformer converts the differential output of the THS4513 into a single-ended output capable of 1 10 100 f - Frequency (MHz) 1000 Figure 83. Low-Pass Filter Measured Frequency Response Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 27 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com THS4513 and ADS5500 Combined Performance The THS4513 is designed to be a high-performance drive amplifier for high-performance data converters like the ADS5500 14-bit 125-MSPS ADC. Figure 84 shows a circuit combining the two devices. The THS4513 amplifier circuit provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5500. The 100-Ω resistors and 2.7-pF capacitor between the THS4513 outputs and ADS5500 inputs along with the input capacitance of the ADS5500 limit the bandwidth of the signal to 115 MHz (–3 dB). For testing, a signal generator is used for the signal source. The generator is an ac-coupled 50-Ω source. A band-pass filter is inserted in series with the input to reduce harmonics and noise from the signal source. Input termination is accomplished via the 69.8-Ω resistor and 0.22-μF capacitor to ground in conjunction with the input impedance of the amplifier circuit. A 0.22-μF capacitor and 49.9-Ω resistor is inserted to ground across the 69.8-Ω resistor and 0.22-μF capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. Refer to Table 3 for component values to set proper 50-Ω termination for other common gains. A split power supply of +4 V and –1 V is used to set the input and output common-mode voltages to approximately midsupply while setting the input common-mode of the ADS5500 to the recommended +1.55 V. This configuration maintains maximum headroom on the internal transistors of the THS4513 to ensure optimum performance. VIN From 50-W source 4V 100 W 0.22 mF 340 W 49.9 W THS 4513 100 W2.7 pF CM 56.2 . W 14 -bit, 125 MSPS A IN + ADS5500 A IN - CM 49.9 W -1 V 0.22 mF Figure 85. THS4513 and ADS5500 2-Tone FFT with 65-MHz and 70-MHz Inputs THS4513 and ADS5424 Combined Performance Figure 86 shows the THS4513 driving the ADS5424 ADC. As before, the THS4513 amplifier provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5424. Input termination and circuit testing is the same as described above for the THS4513 and ADS5500 circuit. 348 W 340 W 56.2 W Figure 85 shows the two-tone FFT of the THS4513 and ADS5500 circuit with 65 MHz and 70 MHz input frequencies. The SFDR is 90 dBc. 0.22 mF 348 W 0.1 mF 0.1 mF Figure 84. THS4513 and ADS5500 Circuit The 225-Ω resistors and 2.7-pF capacitor between the THS4513 outputs and ADS5424 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 100 MHz (–3 dB). Since the ADS5424 recommended input commonmode voltage is 2.4 V, the THS4513 is operated from a single power-supply input with VS+ = 5 V and VS– = 0 V (ground). From 50-W source V IN 348 W 340 W 56.2 W 5V 225 W 0.22 mF 340 49 .9 W 0.22 mF 56.2 W THS4513 225 W 2 .7 pF CM 0.22 mF 348 W 14-bit, 105 MSPS A IN+ ADS 5424 A IN– VBG 49.9 W 0.1 mF 0.1 mF Figure 86. THS4513 and ADS5424 Circuit 28 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 Layout Recommendations It is recommended to follow the layout of the external components near the amplifier, ground plane construction, and power routing of the EVM as closely as possible. General guidelines are: 1. Signal routing should be direct and as short as possible into and out of the op amp circuit. 2. The feedback path should be short and direct; avoid vias. 3. Ground or power planes should be removed from directly under the amplifier input and output pins. 4. An output resistor is recommended on each output, as near to the output pin as possible. 5. Two 10-μF and two 0.1-μF power-supply decoupling capacitors should be placed as near to the power-supply pins as possible. 6. Two 0.1-μF capacitors should be placed between the CM input pins and ground. This configuration limits noise coupled into the pins. One each should be placed to ground near pin 4 and pin 9. 7. It is recommended to split the ground panel on layer 2 (L2) as shown below and to use a solid ground on layer 3 (L3). A single-point connection should be used between each split section on L2 and L3. 8. A single-point connection to ground on L2 is recommended for the input termination resistors R1 and R2. This configuration should be applied to the input gain resistors if termination is not used. 9. The recommended printed circuit board (PCB) footprint for the THS4513 is shown in the Land Pattern of Figure 88. as a thermal pad on the underside of the package (see Figure 87c). Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. Note that the THS4513 has no electrical connection between the PowerPAD and circuitry on the die. Connecting the PowerPAD to any potential voltage between VS+ and VS– is acceptable. It is most important that it be connected for maximum heat dissipation. The PowerPAD package allows both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface-mount with the previously awkward mechanical methods of heatsinking. DIE Side View (a) DIE End View (b) Bottom View (c) Figure 87. Views of Thermally-Enhanced Package PowerPAD™ DESIGN CONSIDERATIONS The THS4513 is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe on which the die is mounted (see Figure 87a and Figure 87b). This arrangement results in the lead frame being exposed Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 29 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com PowerPAD PCB LAYOUT CONSIDERATIONS Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. 0.144 0.049 0.012 Pin 1 0.0095 0.015 0.144 0.0195 0.0705 0.010 vias 0.032 0.030 0.0245 Top View Figure 88. PowerPAD PCB Etch and Via Pattern 1. Prepare the PCB with a top side etch pattern as shown in Figure 88. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. The holes should be 13 mils (0.013 in, 0.33 mm) in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. They help dissipate the heat generated by the IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered, so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is 30 useful for slowing the heat transfer during soldering operations. This resistance makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the IC PowerPAD package should make the connection to the internal ground plane, with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This configuration prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This process results in a part that is properly installed. The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class AB), most of the heat dissipation is at low output voltages with high output currents. The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability increases. For a single package, the sum of the RMS output currents and voltages should be used to choose the proper package. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 THS4513 EVM Figure 89 is the THS4513 EVAL1 EVM schematic; layers 1 through 4 of the PCB are shown Figure 91, and Table 4 is the bill of materials for the EVM as supplied from TI. GND VS− J4 VS+ J5 J6 VEE 0.1 µF TP1 C9 C10 0.1 µF VCC 10 µF C4 10 µF C15 R12 49.9 Ω 0.22 µF J2 12 2 3 VO+ − U1 11 + R4 340 Ω R2 56.2 Ω TP2 C14 0.1 µF VO− PwrPad 10 4 R7 86.6 Ω R8 15 13 14 16 VEE R6 J3 T1 R11 69.8 Ω 6 C1 open 1 C8 open 5 4 86.6 Ω Vocm 9 C13 R9 open 7 PD 340 Ω 0.1 µF C12 VCC VCC 8 6 5 0.1 µF C5 J8 348 Ω R1 56.2 Ω R3 10 µF C3 R5 J1 10 µF C6 3 XFMR_ADT1−1WT R10 open C7 open C2 open J7 348 Ω TP3 VEE C11 0.1 µF Figure 89. THS4513 EVAL1 EVM Schematic Figure 90. Figure 91. THS4513 EVAL1 EVM Layer 1 through Layer 4 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 31 THS4513 SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 www.ti.com Table 4. THS4513 EVAL1 EVM Bill of Materials ITEM 32 DESCRIPTION SMD SIZE REFERENCE DESIGNATOR PCB QTY MANUFACTURER PART NUMBER 1 CAP, 10.0 μF, Ceramic, X5R, 6.3 V 0805 C3, C4, C5, C6 4 (AVX) 08056D106KAT2A 2 CAP, 0.1 μF, Ceramic, X5R, 10 V 0402 C9, C10, C11, C12, C13, C14 6 (AVX) 0402ZD104KAT2A 3 CAP, 0.22 μF, Ceramic, X5R, 6.3 V 0402 C15 1 (AVX) 04026D224KAT2A 4 OPEN 0402 C1, C2, C7, C8 4 5 OPEN 0402 R9, R10 2 6 Resistor, 49.9 Ω, 1/16 W, 1% 0402 R12 1 (KOA) RK73H1ETTP49R9F 7 Resistor, 56.2 Ω, 1/16 W, 1% 0402 R1, R2 2 (KOA) RK73H1ETTP56R2F 8 Resistor, 69.8 Ω, 1/16 W, 1% 0402 R11 1 (KOA) RK73H1ETTP69R8F 9 Resistor, 86.6 Ω, 1/16 W, 1% 0402 R7, R8 2 (KOA) RK73H1ETTP86R6F 10 Resistor, 340 Ω, 1/16 W, 1% 0402 R3, R4 2 (KOA) RK73H1ETTP3400F 11 Resistor, 348 Ω, 1/16 W, 1% 0402 R5, R6 2 (KOA) RK73H1ETTP3480F 12 Transformer, RF T1 1 (MINI-CIRCUITS) ADT1-1WT 13 Jack, banana receptance, 0.25" diameter hole J4, J5, J6 3 (HH SMITH) 101 14 OPEN J1, J7, J8 3 15 Connector, edge, SMA PCB Jack J2, J3 2 (JOHNSON) 142-0701-801 16 Test point, Red TP1, TP2, TP3 3 (KEYSTONE) 5000 17 IC, THS4513 U1 1 (TI) THS4513RGT 18 Standoff, 4-40 HEX, 0.625" length 4 (KEYSTONE) 1808 19 SCREW, PHILLIPS, 4-40, 0.250" 4 SHR-0440-016-SN 20 Printed circuit board 1 (TI) EDGE# 6475514 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 THS4513 www.ti.com SLOS472E – AUGUST 2005 – REVISED JANUARY 2013 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (September 2009) to Revision E • Page Changed RG and RIT values in Table 1 .............................................................................................................................. 23 Changes from Revision C (May 2008) to Revision D Page • Changed title of Typical Characteristics: VS+ – VS– = 5 V ..................................................................................................... 8 • Deleted conditions from Typical Characteristics: VS+ – VS– = 5 V table of graphs ............................................................... 8 • Changed title of Typical Characteristics: VS+ – VS– = 3 V ................................................................................................... 16 • Deleted conditions from Typical Characteristics: VS+ – VS– = 3 V table of graphs ............................................................. 16 • Changed item 9 of the Layout Recommendations ............................................................................................................. 29 • Added the PowerPAD Design Considerations section ....................................................................................................... 29 • Added the PowerPAD PCB Layout Considerations section ............................................................................................... 30 • Moved Figure 88 and associated sentence to beginning of PowerPAD PCB Layout Considerations section .................. 30 Changes from Revision B (November 2006) to Revision C Page • Updated document format .................................................................................................................................................... 1 • Added Related Products table .............................................................................................................................................. 1 • Added footnote 1 to Absolute Maximum Ratings table ........................................................................................................ 2 • Added V (volts) to unit column of ESD ratings rows in Absolute Maximum Ratings table ................................................... 2 • Changed VS+ – VS– = 5 V Input specifications from 1.75 V typ (common-mode input range high) to 1.4 V typ; –1.75 V (common-mode input range low) to –1.4 V; 1.67 MΩ || 1.32 pF (differential input impedance) to 1.3 MΩ || 1.8 pF; 1.2 MΩ || 1.45 pF (common-mode input impedance) to 1.0 MΩ || 2.3 pF ............................................................................ 3 • Added V (volts) to unit column of second differential output voltage swing row in Output section of VS+ – VS– = 5 V specifications ........................................................................................................................................................................ 3 • Changed VS+ – VS– = 3 V Input specifications from 0.75 V typ (common-mode input range high) to 0.4 V typ; –0.75 V (common-mode input range low) to –0.4 V ....................................................................................................................... 5 • Added 1.3 MΩ || 1.8 pF (differential input impedance); 1.0 MΩ || 2.3 pF (common-mode input impedance) to VS+ – VS– = 3 V Input specifications ............................................................................................................................................... 5 • Changed y-axis of Figure 11 to match rest of curves ......................................................................................................... 10 • Changed y-axis of Figure 12 to match rest of curves ......................................................................................................... 10 • Added 1.0 at end of x-axis in Figure 23 .............................................................................................................................. 12 • Changed last number in x-axis of Figure 46 from 100 to 1000 .......................................................................................... 17 • Changed last number in y-axis of Figure 53 from 90 to 35 ................................................................................................ 19 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: THS4513 33 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) THS4513RGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 4513 THS4513RGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 4513 THS4513RGTTG4 ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 4513 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of