THS4561IDGKT

THS4561 THS4561 ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 www.ti.com.cn THS4561 低功耗、高电源电压范围、60MHz、全差分放大器 1 特性 • • • • • • • 带宽：60MHz (G = 1V/V) 压摆率：230V/µs 增益带宽积：68MHz 电压噪声： – 1/f 电压噪声拐角频率：8Hz – 宽带噪声 (≥ 500Hz)：4nV/√Hz 输入失调电压：±250µV（最大值） – 温漂：±4µV/°C（最大值） 电源工作范围：2.85V 至 12.6V 电源电流：775µA 负轨输入 (NRI) 轨至轨输出 (RRO) 超低的谐波失真： – HD2：–117dBc（2VPP、100kHz 时） – HD3：–124dBc（2VPP、100kHz 时） 0.01% 稳定时间（2V 阶跃）：90ns 2 应用 • • • • • • • 16 位至 20 位、差分 SAR 和 Δ-Σ 驱动器 差分有源滤波器 高输出摆幅 PCM 音频 DAC 输出 医疗超声波 电池测试仪 功率分析仪 THS4551 的低功耗替代器件 VS+ + ± VS± +5 V + ± ±5 V 3.57 k 909 20 357 VS+ G = 10 V/V PD 10 nF 50-kHz MFB Butterworth Output Driver FDA 150 pF VS± 20 10 nF 357 THS4561 具有所需的负电源轨输入，可用于将直流耦 合、以接地为中心的源信号连接到单电源差分输入 ADC。低直流误差和温漂项可满足新兴的高速和高分 辨率逐次逼近寄存器 (SAR) 和 Δ-Σ ADC 输入要求。 2.85V 至 12.6V 电源电压范围、灵活的输出共模设置 以及电源余量低等特性，有助于符合多种 ADC 输入和 数模转换器 (DAC) 输出的要求。 THS4561 器 件 的 额 定 工 作 温 度 范 围 是 – 40°C 至 +125°C。 器件信息 909 330 pF 3.57 k 增益为 10V/V 且具有 50kHz 二阶 MFB 滤波器的 PCM 音频 DAC 输出 封装(1) 器件型号 THS4561 (1) THS4561 Using ±5 VS 330 pF PCM Audio DAC Output THS4561 全差分放大器 (FDA) 可在单端源至差分输出 之间提供一个简单接口，从而满足精密模数转换器 (ADC) 的需求。THS4561 具有 8Hz 的超低 1/f 电压噪 声拐角频率和 130dB 的低总谐波失真 (THD)，同时仅 消耗 775µA 的静态电流，非常适用于功率敏感的数据 采集 (DAQ) 系统，该系统需要使用放大器和 ADC 组 合来改善信噪比 (SNR) 及无杂散动态范围 (SFDR)，从 而提供高性能。 Harmonic Distortion (dBc) • • • • 3 说明 封装尺寸（标称值） VSSOP (8) 3.00mm × 3.00mm WQFN (10) 2.00mm x 2.00mm VQFN (16) 3.00mm × 3.00mm 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 10k HD2, VO = 2 VPP HD3, VO = 2 VPP HD2, VO = 8 VPP HD3, VO = 8 VPP HD2, VO = 10 VPP HD3, VO = 10 VPP 100k 1M Frequency (Hz) 10M D007 谐波失真与频率间的关系 本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。 Product Folder Links: THS4561 English Data Sheet: SBOS874 1 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 Table of Contents 1 特性................................................................................... 1 2 应用................................................................................... 1 3 说明................................................................................... 1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings ....................................... 5 7.2 ESD Ratings .............................................................. 5 7.3 Recommended Operating Conditions ........................5 7.4 Thermal Information ...................................................5 7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V .............................................................................. 7 7.6 Typical Characteristics: (VS+) – (VS–) = 12 V..........11 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V........... 14 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V........... 17 7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range..................................................... 18 8 Parameter Measurement Information.......................... 22 8.1 Example Characterization Circuits............................22 8.2 Output Interface Circuit for DC-Coupled Differential Testing.......................................................24 8.3 Output Common-Mode Measurements.....................24 8.4 Differential Amplifier Noise Measurements...............25 8.5 Balanced Split-Supply Versus Single-Supply Characterization.......................................................... 25 8.6 Simulated Characterization Curves.......................... 25 8.7 Terminology and Application Assumptions............... 26 9 Detailed Description......................................................27 9.1 Overview................................................................... 27 9.2 Functional Block Diagram......................................... 27 9.3 Feature Description...................................................28 9.4 Device Functional Modes..........................................28 10 Application and Implementation................................ 31 10.1 Application Information........................................... 31 10.2 Typical Application.................................................. 36 11 Power Supply Recommendations..............................37 12 Layout...........................................................................38 12.1 Layout Guidelines................................................... 38 12.2 Layout Examples.................................................... 38 13 Device and Documentation Support..........................40 13.1 接收文档更新通知................................................... 40 13.2 支持资源..................................................................40 13.3 Trademarks............................................................. 40 13.4 静电放电警告.......................................................... 40 13.5 术语表..................................................................... 40 14 Mechanical, Packaging, and Orderable Information.................................................................... 40 4 Revision History Changes from Revision C (December 2020) to Revision D (February 2021) Page • Changed the status of the RGT package from preview to production ............................................................... 4 Changes from Revision B (August 2020) to Revision C (December 2020) • • • • • • • • • • Page 将特性 部分的压摆率从 315V/µs 更改为 230V/µs...............................................................................................1 更新了特性 部分中的“增益为 10V/V 且具有二阶 MFB 滤波器的 PCM 音频 DAC 输出”.................................1 为 THS4561 器件发布了 WQFN (10) 封装......................................................................................................... 1 Changed the status of the RUN package from preview to production ...............................................................4 Seperated slew rate specification into rising and falling specifications lines...................................................... 5 Changed the VOCM small-signal bandwidth test condition from 100 mVPP to 10 mVPP and the typical value from 23 MHz to 22 MHz .....................................................................................................................................5 Changed the VOCM large-signal bandwidth typical value from 10 MHz to 1.9 MHz .........................................5 Changed the maximum VOCM drift specification from 300 µV/°C .................................................................... 5 Updated the Common-Mode Voltage, Small-Signal and Large-Signal Response (VOCM Pin Driven) figure in the Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range section ............................................18 Updated the MFB Filter Driving an ADC Application figure in the Typical Application section ........................ 36 Changes from Revision A (December 2019) to Revision B (August 2020) Page • 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1 • Added the VQFN-10 and VQFN-16 Package Outlines.....................................................................................40 Changes from Revision * (August 2017) to Revision A (December 2019) Page • 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 5 Device Comparison Table DEVICE BW, G = 1 (MHz) IQ, 5 V (mA) INPUT NOISE (nV/√ Hz) THD (dBc) 2 VPP AT 10 kHz RAIL-TO-RAIL DUAL VERSIONS THS4561 60 0.78 4 –130 Negative in and out — THS4551 150 1.37 3.3 –138 Negative in and out THS4552 THS4521 145 1.14 5.6 –120 Negative in and out THS4522 THS4531A 36 0.25 10 –118 Negative in and out THS4532 THS4541 620 10.1 2.2 –140 Negative in and out — Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 3 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 6 Pin Configuration and Functions VS+ IN- 8 1 10 IN+ VOCM 2 7 PD VS+ 3 6 VS- OUT+ 4 5 OUT- OUT– 1 9 OUT+ NC 2 8 NC PD 3 7 VOCM IN+ 4 6 IN– 5 图 6-1. DGK Package 8-Pin VSSOP Top View VS– VS– VS– VS– VS– 图 6-2. RUN Package 10-Pin WQFN Top View 16 15 14 13 IN+ 2 11 OUT– IN– 3 10 OUT+ FB+ 4 9 VOCM 5 6 7 8 VS+ PD VS+ 12 VS+ 1 VS+ FB– 图 6-3. RGT Package 16-Pin VQFN With Exposed Thermal Pad Top View 表 6-1. Pin Functions PIN DESCRIPTION RUN RGT(1) FB– — — 1 O Inverting (negative) output feedback FB+ — — 4 O Noninverting (positive) output feedback IN– 1 6 3 I Inverting (negative) amplifier input IN+ 8 4 2 I Noninverting (positive) amplifier input NC — 2, 8 — — No internal connection OUT– 5 1 11 O Inverting (negative) amplifier output OUT+ 4 9 10 O Noninverting (positive) amplifier output PD 7 3 12 I Power down. PD = logic low = power off mode; PD = logic high = normal operation. VOCM 2 7 9 I Common-mode voltage input VS– 6 5 13, 14, 15, 16 P Negative power-supply input VS+ 3 10 5, 6, 7, 8 P Positive power-supply input (1) (2) 4 TYPE(2) DGK NAME Solder the exposed RGT package thermal pad to a heat-spreading power or ground plane. This pad is electrically isolated from the die, but must be connected to a power or ground plane and not floated. I = input, O = output, P = power. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX Total supply voltage, VS = (VS+ – VS–) Supply turn-on/off dV/dT(2) Voltage Input, output, power down and common-mode pin voltage range Current Temperature (1) (2) (3) UNIT 13.5 V ±0.35 V/µs (VS+) + 0.5 (VS–) – 0.5 V Differential input voltage ±1 V Continuous input current ±10 mA Continuous output current(3) ±20 mA Junction temperature, TJ 150 °C Operating free-air temperature, TA –40 125 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These stress-only ratings do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Staying below this specification ensures that the edge-triggered ESD absorption devices across the supply pins remains off. Long-term continuous output current for electromigration limits. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±3500 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VS Total supply voltage 2.85 TA Operating free-air temperature –40 NOM 25 MAX UNIT 12.6 V 125 °C 7.4 Thermal Information THS4561 THERMAL METRIC(1) DGK (VSSOP) RUN (WQFN) RGT (VQFN) 8 PINS 10 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 183.1 134.6 55.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 70.3 83.6 64.5 °C/W RθJB Junction-to-board thermal resistance 104.9 67.7 30.5 °C/W ΨJT Junction-to-top characterization parameter 10.8 7.2 3.5 °C/W ΨJB Junction-to-board characterization parameter 103.2 67.5 30.5 °C/W Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 5 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.4 Thermal Information (continued) THS4561 THERMAL RθJC(bot) (1) 6 METRIC(1) Junction-to-case (bottom) thermal resistance DGK (VSSOP) RUN (WQFN) RGT (VQFN) 8 PINS 10 PINS 16 PINS N/A N/A 15.6 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V at TA ≈ 25°C, VOCM(1) = midsupply, differential output (VO) = VOUT+ – VOUT– = 2 VPP, RF = 1.5 kΩ, RL = 1 kΩ, 50-Ω input match, differential closed-loop gain (G) = 1 V/V, single-ended input (SE-in), differential output (diff-out), and input and output referenced to midsupply for AC-coupled tests (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE VS = 5 V, VO = 200 mVPP, 2-dB peaking SSBW Small-signal bandwidth VS = 5 V, VO = 200 mVPP 60 G = 2 V/V 45 G = 5 V/V 12.5 G = 10 V/V 6.3 MHz GBWP Gain-bandwidth product VO = 200 mVPP, G = 20 V/V, RF = 10 kΩ 68 MHz LSBW Large-signal bandwidth VO = 4 VPP 20 MHz Bandwidth for 0.1-dB flatness SR HD2 Slew rate (20% – 80%) VS = 5 V, VO = 2-V step 5 MHz Rising 325 V/µs V/µs Falling 230 VS = 12 V 5% VS = 5 V 11% Overshoot and undershoot VO = 2-V step, input tr = 10 ns 0.1% settling time VO = 2-V step, input tr = 10 ns 0.01% settling time Rise and fall time (10% – 90%) Second-order harmonic distortion VS = 5 V, f = 100 kHz 40 ns VO = 2-V step, input tr = 10 ns 90 ns VO = 100-mV step, input tr = 2 ns 5.7 ns –117 Vo = 8 VPP –110 Vo = 2 VPP –124 Vo = 8 VPP –106 dBc HD3 Third-order harmonic distortion en Input differential voltage noise in Input current noise, each input f ≥ 50 kHz 0.35 pA/√Hz Overdrive recovery time VS = 5 V, G = 2 V/V, 2x output overdrive, dc-coupled 210 ns Closed-loop output impedance f = 100 kHz (differential) 0.06 Ω dB ZOUT VS = 5 V, f = 100 kHz Vo = 2 VPP f ≥ 500 Hz 4 nV/√Hz 1/f corner 8 Hz DC PERFORMANCE AOL Open-loop voltage gain Vo = ±2 V 104 115 VOS Input offset voltage TA = 25°C –250 ±50 250 Input offset voltage drift TA = 0°C to 85°C, TA = –40°C to 125°C –4 ±0.5 4 Input bias current(3) TA = 25°C 370 600 Input bias current drift TA = –40°C to 125°C 4.1 8 nA/°C Input offset current(4) TA = 25°C –20 ±2 20 nA Input offset current drift TA = –40°C to 125°C –200 ±40 200 pA/°C VICML Common-mode input low TA = –40°C to 125°C, 3-dB AOL degradation from midsupply VOCM AOL VS– – 0.1 VS– V VICMH Common-mode input high 3-dB AOL degradation from midsupply VOCM AOL CMRR Common-mode rejection ratio IB+, IB– IOS µV µV/°C nA INPUT TA = 25°C VS+ – 1.2 VS+ – 1.1 TA = –40°C to VS+ – 1.35 125°C VS+ – 1.2 Midsupply inputs Midsupply inputs, TA = –40°C to 125°C 95 110 108 V dB Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 7 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V (continued) at TA ≈ 25°C, VOCM(1) = midsupply, differential output (VO) = VOUT+ – VOUT– = 2 VPP, RF = 1.5 kΩ, RL = 1 kΩ, 50-Ω input match, differential closed-loop gain (G) = 1 V/V, single-ended input (SE-in), differential output (diff-out), and input and output referenced to midsupply for AC-coupled tests (unless otherwise noted) PARAMETER Differential input impedance 8 TEST CONDITIONS Inputs at midsupply Submit Document Feedback MIN TYP 150 || 2.4 MAX UNIT kΩ || pF Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V (continued) at TA ≈ 25°C, VOCM(1) = midsupply, differential output (VO) = VOUT+ – VOUT– = 2 VPP, RF = 1.5 kΩ, RL = 1 kΩ, 50-Ω input match, differential closed-loop gain (G) = 1 V/V, single-ended input (SE-in), differential output (diff-out), and input and output referenced to midsupply for AC-coupled tests (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT Output voltage range low VS = 5 V VS– + 0.13 VS– + 0.25 VS = 5 V, TA = –40°C to 125°C VS– + 0.15 VS = 5 V, RL = 10 kΩ VS– + 0.07 VS = 12 V VS = 5 V Output voltage range high VS = 5 V, TA = –40°C to 125°C Linear output current V VS– + 0.4 VS+ – 0.25 VS+ – 0.16 VS+ – 0.3 VS+ – 0.18 VS = 5 V, RL = 10 kΩ VS = 12 V Continuous output current VS– + 0.26 VS– + 0.3 V VS+ – 0.09 VS+ – 0.35 VS+ – 0.2 ±31 VO = ±3.6 V, VOCM offset < 15 mV ±27 TA = –40°C to +125°C, VO = ±2.25 V, VOCM offset < 15 mV ±17 VS = 5 V, VO = ±2.7 V,, AOL > 80 dB ±20 ±22 VS = 12 V, VO = ±4.6 V, AOL > 80 dB ±22 ±27 VS = 12 V, TA = –40°C to +125°C, VO = ±3.1 V, AOL > 80 dB ±15 mA mA OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL(1) Small-signal bandwidth VOCM = 10 mVPP 22 MHz Large-signal bandwidth VOCM = 1 VPP 1.9 MHz Slew rate(2) (20% – 80%) VOCM = 0.5-V step 4 V/µs DC output balance VOCM fixed midsupply, VOCM/VO (VO = ±1 V) 86 dB Output balance VOCM fixed midsupply, VOCM/VO (–3-dB from dc) 800 Hz Gain VOCM = 0 V Input bias current 0.997 1 1.003 V/V –0.5 –0.1 0.5 µA +PSR to VOCM VOCM = midsupply 72 78 dB –PSR to VOCM VOCM = midsupply 70 76 dB Input impedance 200 || 1.5 Default VOCM offset Relative to midsupply, VOCM pin floating Default VOCM offset voltage drift TA = –40℃ to 125℃ VOCM offset voltage VOCM offset voltage drift VOCM range low VOCM range high kΩ || pF –40 8 40 mV 120 200 600 µV/℃ VOCM driven to midsupply –3.5 0.25 3.5 mV TA = –40°C to 125°C –15 3 15 µV/°C VS– + 0.45 VS– + 0.5 TA = 25°C, < ±4-mV shift from midsupply offset V TA = –40°C to 125°C, < ±4-mV shift from midsupply offset VS– + 0.6 TA = 25°C, < ±4-mV shift from midsupply offset VS+ – 1.2 TA = –40°C to 125°C, < ±5-mV shift from midsupply offset VS+ – 1.3 VS+ – 1.1 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 9 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V (continued) at TA ≈ 25°C, VOCM(1) = midsupply, differential output (VO) = VOUT+ – VOUT– = 2 VPP, RF = 1.5 kΩ, RL = 1 kΩ, 50-Ω input match, differential closed-loop gain (G) = 1 V/V, single-ended input (SE-in), differential output (diff-out), and input and output referenced to midsupply for AC-coupled tests (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 12.6 V POWER SUPPLY Specified operating voltage IQ Quiescent current PSRR 2.85 VS = 2.85 V, no load, TA = 25°C 710 760 810 VS = 5 V, no load, TA = 25°C 725 775 825 VS = 5 V, no load, TA = –40°C to 125°C 700 VS = 12 V, no load, TA = 25°C 770 VS = 12 V, no load, TA = –40°C to 125°C 740 Quiescent current drift No load, TA = –40°C to 125°C Power-supply rejection ratio Either supply to input VOS 900 825 µA 880 1000 0.7 92 1.3 110 µA/°C dB POWER DOWN VEN Enable voltage threshold PD = VEN, guaranteed on above VS+ – 1.2 VS+ – 0.5 V VDIS Disable voltage threshold PD = VDIS, guaranteed off below VS+ – 1.7 VS+ – 1.8 V PD pin bias current PD = VS+ – 0.5 V (amplifier enabled) 1.2 3.5 µA PD pin bias current PD = VS– (amplifier disabled) Peak PD pull-down bias current Switch amplifier on to off Power-down quiescent current No load Turnon time delay Time from PD = high to VO = 90% of final value 600 ns Turnoff time delay Time from PD = low to VO = 10% of original value 1.5 µs –3 –1.9 µA 175 µA 3 15 (1) (2) (3) VOCM refers to the voltage at VOCM pin. VOCM = [(VOUT+ + VOUT–)/2] refers to the average output voltage. Average of the rising and falling slew rate. Current out of the node is considered positive. (4) IOS = IB+ – IB–. 10 Submit Document Feedback 40 µA Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.6 Typical Characteristics: (VS+) – (VS–) = 12 V 3 3 0 0 Normalized Gain (dB) -3 -6 -9 -12 100k G = 0.5 V/V G = 1 V/V G = 2 V/V G = 5 V/V G = 10 V/V 1M -3 -6 VO = 0.2 VPP VO = 2 VPP VO = 4 VPP VO = 8 VPP VO = 10 VPP -9 10M Frequency (Hz) -12 100k 100M 1M D001 VO = 200 mVPP, see 图 8-1 and 表 10-1 for resistor values 0 0 Normalized Gain (dB) Normalized Gain (dB) 3 -3 -6 VOCM = 1 V VOCM = 3 V VOCM = 6 V VOCM = 7.5 V VOCM = 9 V 1M -3 -6 -12 100k 100M Input Differential Voltage Noise, e n (nV/—Hz) Normalized Gain (dB) G = 5 V/V G = 10 V/V 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 100k D004 100 10 en in 10 1 1 1 1M Frequency (Hz) 100M 图 7-4. Small-Signal Frequency Response vs RL 0.5 0.3 10M Frequency (Hz) VO = 200 mVPP, see 图 8-1 with load resistance (RL) adjusted 图 7-3. Small-Signal Frequency Response vs VOCM 0.4 1M D003 VO = 200 mVPP , see 图 8-1 with VOCM adjusted G = 0.5 V/V G = 1 V/V G = 2 V/V RL = 150 : RL = 500 : RL = 1 k: RL = 2 k: RL = 10 k: -9 10M Frequency (Hz) D002 图 7-2. Frequency Response vs VO 3 -12 100k 100M See 图 8-1 图 7-1. Small-Signal Frequency Response vs Gain -9 10M Frequency (Hz) 10 10M D072 100 1k Frequency (Hz) 10k Input Current Noise, i n (pA/—Hz) Normalized Gain (dB) at TA ≈ 25°C, VOCM pin = midsupply, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. 0.1 100k D050 1/f corners: en = 8 Hz, in = 700 Hz VO = 200 mVPP 图 7-6. Input Noise Density vs Frequency 图 7-5. Gain Flatness vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 11 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.6 Typical Characteristics: (VS+) – (VS–) = 12 V (continued) at TA ≈ 25°C, VOCM pin = midsupply, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. -60 HD2, VO = 2 VPP HD3, VO = 2 VPP HD2, VO = 8 VPP HD3, VO = 8 VPP HD2, VO = 10 VPP HD3, VO = 10 VPP -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 10k -80 HD2, 100 kHz HD3, 100 kHz HD2, 1 MHz HD3, 1 MHz -90 -100 -110 -120 -130 100k 1M Frequency (Hz) 2 10M 10 Output Voltage (VPP) D007 图 7-7. Harmonic Distortion vs Frequency -40 HD2, 100 kHz HD3, 100 kHz HD2, 1 MHz HD3, 1 MHz -70 -80 -90 -100 -110 -120 -130 1k Load Resistance, RL (:) 10k 1 图 7-10. Harmonic Distortion vs Gain -20 Intermodulation Distortion (dBc) -10 -80 -85 HD2, 100 kHz HD3, 100 kHz HD2, 1 MHz HD3, 1 MHz -95 -100 -105 D010 VO = 5 VPP, see 表 10-1 for gain setting -75 -90 10 Gain, G (V/V) D009 图 7-9. Harmonic Distortion vs RL Harmonic Distortion (dBc) HD2, 1 MHz HD3, 1 MHz -60 VO = 5 VPP with RL adjusted -110 -115 -120 Max IMD2 Max IMD3 -30 -40 -50 -60 -70 -80 -90 -125 -130 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Common-Mode Voltage, VOCM (V) VO = 5 VPP with VOCM adjusted -100 2.5 3 1M Frequency (Hz) D011 10M D012 VO = 2 VPP per tone, ±50-kHz tone spacing 图 7-11. Harmonic Distortion vs VOCM 12 HD2, 100 kHz HD3, 100 kHz -50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 100 D008 图 7-8. Harmonic Distortion vs VO 图 7-12. Intermodulation Distortion (IMD2 and IMD3) vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.6 Typical Characteristics: (VS+) – (VS–) = 12 V (continued) 1.8 6 1.4 5 4 1 Each Output Voltage (V) Output Voltage, VO (V) at TA ≈ 25°C, VOCM pin = midsupply, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. 0.6 0.2 -0.2 -0.6 -1 3 2 OUT+, TA = 40qC OUT+, TA = 25qC OUT+, TA = 85qC OUT+, TA = 125qC OUT , TA = 40qC OUT , TA = 25qC OUT , TA = 85qC OUT , TA = 125qC 1 0 -1 -2 -3 -4 -1.4 SE-in, diff-out Diff-in, diff-out -5 -1.8 -6 Time, 15 ns per division D015 VO = 2-V step, SE-in, diff-out: rising SR = 350 V/µs, falling SR = 200 V/µs, diff-in, diff-out: rising SR = 285 V/µs, falling SR = 285 V/µs 图 7-13. Large-Signal Step Response 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Output Current (mA) D065 VS = 12 V, VOCM at midsupply, average of 30 units 图 7-14. ±Maximum Output Voltage vs Output Current and Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 13 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. 6 3 0 Normalized Gain (dB) 0 -3 -6 -9 -12 100k G = 0.5 V/V G = 1 V/V G = 2 V/V G = 5 V/V G = 10 V/V 1M -3 -6 VO = 0.2 VPP VO = 1 VPP VO = 2 VPP VO = 4 VPP VO = 8 VPP -9 10M Frequency (Hz) -12 100k 100M 1M D019 3 0 0 Normalized Gain (dB) Normalized Gain (dB) 3 -3 -6 VOCM = 1 V VOCM = 2 V VOCM = 2.5 V VOCM = 3 V VOCM = 3.5 V 1M -3 -6 -12 100k 100M Input Differential Voltage Noise, e n (nV/—Hz) Normalized Gain (dB) G = 5 V/V G = 10 V/V 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 100k D022 100 10 en in 10 1 1 1 1M Frequency (Hz) 100M 图 7-18. Small-Signal Frequency Response vs RL 0.5 0.3 10M Frequency (Hz) VO = 200 mVPP, see 图 8-1 with RL adjusted 图 7-17. Small-Signal Frequency Response vs VOCM G = 0.5 V/V G = 1 V/V G = 2 V/V 1M D021 VO = 200 mVPP, see 图 8-1 with VOCM adjusted 0.4 RL = 150 : RL = 500 : RL = 1 k: RL = 2 k: RL = 10 k: -9 10M Frequency (Hz) D020 图 7-16. Frequency Response vs VO 图 7-15. Small-Signal Frequency Response vs Gain -12 100k 100M See 图 8-1 VO = 200 mVPP, see 图 8-1 and 表 10-1 for resistor values -9 10M Frequency (Hz) 10 10M D073 100 1k Frequency (Hz) 10k Input Current Noise, i n (pA/—Hz) Normalized Gain (dB) 3 0.1 100k D070 1/f corners: en = 8 Hz, in = 700 Hz VO = 200 mVPP 图 7-20. Input Noise Density vs Frequency 图 7-19. Gain Flatness vs Frequency 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued) -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 10k HD2, VO = 2 VPP HD3, VO = 2 VPP HD2, VO = 8 VPP HD3, VO = 8 VPP Harmonic Distortion (dBc) Harmonic Distortion (dBc) at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. 100k 1M Frequency (Hz) -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 10M HD2, 100 kHz HD3, 100 kHz HD2, 1 MHz HD3, 1 MHz 2 10 Output Voltage (VPP) D025 图 7-21. Harmonic Distortion vs Frequency -50 -70 -75 -60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -80 -85 -90 -95 HD2, 100 kHz HD3, 100 kHz HD3, 1 MHz HD2, 1 MHz -100 -105 -110 -115 -120 -70 -80 -90 -100 -110 -120 -125 -130 100 10k 图 7-24. Harmonic Distortion vs Gain -10 -20 Intermodulation Distortion (dBc) Harmonic Distortion (dBc) D028 VO = 5 VPP, see 表 10-1 for gain setting -80 -85 -90 HD2, 100 kHz HD3, 100 kHz HD2, 1 MHz HD3, 1 MHz -110 -115 Max IMD2 Max IMD3 -30 -40 -50 -60 -70 -80 -90 -120 -125 -1 10 Gain, G (V/V) -75 -105 HD2, 1 MHz HD3, 1 MHz 1 D027 图 7-23. Harmonic Distortion vs RL -100 HD2, 100 kHz HD3, 100 kHz -130 1k Load Resistance, RL (:) VO = 5 VPP with RL adjusted -95 D026 图 7-22. Harmonic Distortion vs VO -100 -0.75 -0.5 -0.25 0 0.25 0.5 Common-Mode Voltage, VOCM (V) 0.75 1 1M Frequency (Hz) D029 VO = 5 VPP with VOCM adjusted 10M D030 VO = 2 VPP per tone, ±50-kHz tone spacing 图 7-25. Harmonic Distortion vs VOCM 图 7-26. Intermodulation Distortion (IMD2 and IMD3) vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 15 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. 2.5 1.4 2 1 1.5 Each Output Voltage (V) Output Voltage, VO (V) 1.8 0.6 0.2 -0.2 -0.6 -1 -1.4 SE-in, diff-out 1 OUT+, TA = 40qC OUT+, TA = 25qC OUT+, TA = 85qC OUT+, TA = 125qC OUT , TA = 40qC OUT , TA = 25qC OUT , TA = 85qC OUT , TA = 125qC 0.5 0 -0.5 -1 -1.5 -2 Diff-in, diff-out -2.5 -5 -1.8 Time, 15 ns per division 0 D033 VO = 2-V step, SE-in, diff-out: rising SR = 325 V/µs, falling SR = 230 V/µs, diff-in, diff-out: rising SR = 305 V/µs, falling SR = 310 V/µs 5 10 15 20 25 30 35 40 45 50 55 60 65 Output Current (mA) D075 VS = 5 V, VOCM at midsupply, average of 30 units 图 7-28. ±Maximum Output Voltage vs Output Current and Temperature 图 7-27. Large-Signal Step Response 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. 6 3 0 Normalized Gain (dB) 0 -3 -6 G = 0.5 V/V G = 1 V/V G = 2 V/V G = 5 V/V G = 10 V/V -9 -12 100k -3 -6 -9 1M 10M Frequency (Hz) VO = 0.2 VPP VO = 1 VPP VO = 2 VPP -12 100k 100M 1M D037 VO = 200 mVPP, see 图 8-1 and 表 10-1 for resistor values 0 -3 -6 RL = 150 : RL = 500 : RL = 1 k: RL = 2 k: RL = 10 k: -9 -12 100k 1M 10M Frequency (Hz) 100 100M 10 en in 10 1 1 1 10 D039 10k 0.1 100k D071 图 7-32. Input Noise Density vs Frequency 图 7-31. Small-Signal Frequency Response vs RL -60 HD2, VO = 1 VPP HD3, VO = 1 VPP HD2, VO = 2 VPP HD3, VO = 2 VPP HD2, 100 kHz HD3, 100 kHz HD2, 1 MHz HD3, 1 MHz -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 100 1k Frequency (Hz) 1/f corners: en = 9 Hz, in = 700 Hz VO = 200 mVPP, see 图 8-1 with RL adjusted -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 10k D038 图 7-30. Frequency Response vs VO Input Differential Voltage Noise, e n (nV/—Hz) Normalized Gain (dB) 3 100M See 图 8-1 图 7-29. Small-Signal Frequency Response vs Gain 6 10M Frequency (Hz) Input Current Noise, i n (pA/—Hz) Normalized Gain (dB) 3 -80 -90 -100 -110 -120 -130 100k 1M Frequency (Hz) 10M -140 100 D041 1k Load Resistance, RL (:) D042 G = 1 V/V, VO = 4 VPP, with RL adjusted G = 1 V/V 图 7-33. Harmonic Distortion vs Frequency 图 7-34. Harmonic Distortion vs RL Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 17 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input, differential output, and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. 500 250 VS = 5 V VS = 12 V 225 400 200 20 15 17.5 10 12.5 图 7-36. Input Offset Current (IOS) 图 7-35. Input Offset Voltage (VOS) 250 20 200 15 Input Offset Current, I OS (nA) Input Offset Voltage, V OS (PV) 5 1000 DGK units at each VS 1000 DGK units at each VS 150 100 50 0 -50 -100 -150 10 5 0 -5 -10 -15 -200 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 110 125 -20 -40 D061 VS = 12 V, 5 V, and 3 V, delta from 25°C VOS, 30 DGK units for each VS 图 7-37. Input Offset Voltage vs Temperature 18 D059 Input Offset Current (nA) Input Offset Voltage (PV) -250 -40 7.5 -20 D059 0 0 2.5 50 0 -250 -225 -200 -175 -150 -125 -100 -75 -50 -25 0 25 50 75 100 125 150 175 200 225 250 100 25 -5 150 50 -2.5 75 250 -10 100 300 -7.5 125 350 -15 150 -12.5 175 -17.5 # of units in each bin 200 # of units in each bin VS = 5 V VS = 12 V 450 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 110 125 D062 VS = 12 V and 5 V, delta from 25°C IOS, 50 DGK units for each VS 图 7-38. Input Offset Current vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input, differential output, and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. 30 12 VS = 3 V VS = 5 V VS = 12 V 11 10 24 # of units in each bin 9 8 7 6 5 4 3 21 18 15 12 9 65 -90 50 -120 35 -150 20 -180 5 -210 -240 -270 1M 10M Frequency (Hz) 200 175 150 125 75 100 50 0 100 100M D103 100 1k 10k 100k 1M Frequency (Hz) 10M 100M 1G Simulated Simulated 图 7-41. Main Amplifier Differential Open-Loop Gain and Phase vs Frequency 图 7-42. Open-Loop Output Impedance vs Frequency 100 80 VS = 3 V VS = 5 V VS = 12 V 60 Output Voltage, VO (mV) Closed-Loop Output Impedance, ZOUT (:) 25 1000 10 10 -300 100k -25 10000 Differential Output Impedance (:) -60 Phase (q) Gain (dB) 80 -40 10k -50 图 7-40. Input Offset Current Drift Histogram 图 7-39. Input Offset Voltage Drift Histogram -25 -75 –40°C to +125°C endpoint drift, 50 DGK units for each VS –40°C to +125°C endpoint drift, 30 DGK units for each VS Gain, no load Gain, 100-: load Phase, no load Phase, 100-: load D064 Input Offset Current Drift (pA/°C) Input Offset Voltage Drift (PV/°C) -10 -100 D063 -125 -200 4 3 3.5 2 2.5 1 1.5 0 0.5 -1 -0.5 -2 -1.5 -3 -2.5 0 -4 3 0 -3.5 1 -150 6 2 -175 # of units in each bin VS = 5 V VS = 12 V 27 10 1 0.1 40 20 0 -20 -40 -60 -80 VS = 12 V 0.01 VS = 5 V VS = 3 V -100 40k 100k 1M Frequency (Hz) 10M 60M Time, 20 ns per division D049 . D013 VO = 100-mV step, tr (10% - 90%) = 5.7 ns 图 7-43. Closed-Loop Output Impedance vs Frequency 图 7-44. Small-Signal Step Response Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 19 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input, differential output, and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. Voltage (V) 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 VO PD Time, 500 ns per division 12 .7 5 13 .5 0 11 .5 0 10 .2 5 9. 00 7. 75 6. 50 5. 25 IS+, TA = 40qC IS+, TA = 25qC IS+, TA = 85qC IS+, TA = 125qC 4. 00 2. 75 Quiescent Current, IQ (PA) 1000 975 950 925 900 875 850 825 800 775 750 725 700 675 D066 D068 Supply Voltage, VS (V) 5 MHz, 2-VPP input, G = 1 V/V, see 图 8-1 Average of 30 units 图 7-46. PD Turnon and Turnoff Waveform 图 7-45. Quiescent Current vs VS 6 VOCM Voltage Noise (nV/—Hz) 5000 3 Gain (dB) 0 -3 VS = 12 V, VO = 10 mVPP VS = 5 V, VO = 10 mVPP VS = 3 V, VO = 10 mVPP VS = 5 V, VO = 0.1 VPP VS = 12 V, VO = 1 VPP VS = 5 V, VO = 1 VPP -6 -9 -12 100k 1M Frequency (Hz) 1000 100 10 100 10M . 1k 1M 10M D057 图 7-48. Output Common-Mode (VOCM) Noise vs Frequency 0.6 70 60 50 40 30 20 10 0 -10 -20 -30 -40 -50 -60 -70 0.5 0.4 0.3 Voltage (V) 0.2 0.1 0 -0.1 -0.2 -0.3 VS = 3 V VS = 5 V VS = 12 V VS = 3 V VS = 5 V VS = 12 V -0.4 -0.5 -0.6 0 Time, 100 ns per division 200 D056 400 600 800 1000 Time (ns) 1200 1400 1600 D074 VOCM pin driven, 1-V VOCM step VOCM pin driven, 0.1-V VOCM step 图 7-49. Common-Mode Voltage Small-Signal Step Response 20 10k 100k Frequency (Hz) The VOCM pin is either driven to midsupply by low-impedance source or allowed to float and default to midsupply 图 7-47. Common-Mode Voltage, Small-Signal and Large-Signal Response (VOCM Pin Driven) Voltage (mV) VS = 3 V, VOCM floating VS = 3 V, VOCM driven VS = 5 V, VOCM floating VS = 5 V, VOCM driven VS = 12 V, VOCM floating VS = 12 V, VOCM driven 图 7-50. Common-Mode Voltage Large-Signal Step Response Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range (continued) 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 10 150 Small-Signal Large-Signal, VO = 2 VPP CMRR PSRR+ PSRR 140 130 CMRR and PSRR (dB) Output Balance (dB) at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, singleended input, differential output, and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted); see 图 8-1 for a gain of 1-V/V test circuit. 120 110 100 90 80 70 60 50 40 100 1k 10k 100k Frequency (Hz) 1M 10M 30 1k D051 Simulated 10k 100k 1M Frequency (Hz) 10M 100M D053 Simulated 图 7-51. Output Balance vs Frequency 图 7-52. CMRR and PSRR vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 21 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 8 Parameter Measurement Information 8.1 Example Characterization Circuits The THS4561 offers the advantages of a fully differential amplifier (FDA) design with the trimmed input offset voltage and low drift of a precision op amp. The FDA is a flexible device where the main aim is to provide a purely differential output signal centered on a user-configurable common-mode voltage usually matched to the input common-mode voltage required by an analog-to-digital converter (ADC) following the FDA stage. The primary options revolve around the choices of single-ended or differential inputs, AC-coupled or DC-coupled signal paths, gain targets, and resistor value selections. The characterization circuits described in this section focus on single-ended input to differential output designs as the more challenging application requirement. Differential sources are supported and are simple to implement and analyze. The characterization circuits are typically operated with a single-ended, matched, 50-Ω, input termination to a differential output at the FDA output pins because most lab equipment is single-ended. The FDA differential output is then translated back to single-ended through a variety of baluns (or transformers) depending on the test and frequency range. DC-coupled step response testing uses two 50-Ω scope inputs with trace math to measure the differential output. Single-supply operation is most common in end equipment designs. However, using split balanced supplies allows simple ground referenced testing without adding further blocking capacitors in the signal path beyond those capacitors already within the test equipment. The starting point for any singleended input to differential output measurements (such as any of the frequency response curves) is shown in 图 8-1. 50- Input Match, Gain of 1 V/V from RT, Single-Ended Source to Differential Output THS4561 Wideband, Fully Differential Amplifier RF1 1.5 k RO1 487 VS+ RG1 1.5 k Network Analyzer, 50- Source Impedance ADTL1-4-75+ ± N1 + RT1 52.3 VOCM FDA RG2 1.5 k Termination RS1 50 RT2 52.3 VO ± + 50- 31.8-dB Insertion Loss from VOPP to a 50- Load PD VS± VS+ RF2 1.5 k RO2 487 RM 52.3 N2 50Single-Ended Source Network Analyzer, 50- Load 1-k Differential Load 图 8-1. Single-Ended Source to a Differential Gain of a 1-V/V Test Circuit Most characterization plots fix the RF (RF1 = RF2) value at 1.5 kΩ, as shown in 图 8-1. This element value is flexible in application, but 1.5 kΩ provides a good compromise for the parasitic issues linked to this value, specifically: • Added output loading: The FDA functions similarly to an inverting op amp design with feedback resistors appearing as an added load across the outputs (the approximate total differential load in 图 8-1 is 1.5 kΩ || 1 kΩ = 857 Ω). The 1.5-kΩ value reduces the power dissipated in the feedback networks. • Noise contributions resulting from resistor values. These contributions are both the 4kTRF terms and the current noise times the RF term referred to the output (see 节 10.1.3). • Parasitic feedback pole at the input summing nodes. This pole is created by the feedback resistor (RF) value and the 2.4-pF differential input capacitance (as well as any board layout parasitic) and introduces a zero in the noise gain, which decreases the phase margin in most situations. This effect must be managed for best frequency response flatness or step response overshoot. 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 The frequency domain characterization curves start with the circuit and component selections of 图 8-1. Some of the features in this test circuit include: • The elements on the non-signal input side match the signal input resistors. This feature closely matches the divider networks on each side of the FDA. The three resistors (RG2, RT2, and RS1) on the non-signal input side can be replaced by a single resistor to ground using a standard value of 1.5 kΩ with some loss in gain balancing between the two sides. • Translating from a 1-kΩ differential load to a 50-Ω environment introduces considerable insertion loss in the measurements (–31.8 dB in 图 8-1). The measurement path insertion loss normalizes when reporting the frequency response curves to show the gain response to the FDA output pins. • In the pass band for the output balun, the 50-Ω load of the network analyzer reflects in parallel with the 52.3Ω shunt termination, RM. These elements combine to show a differential 1-kΩ load at the output pins of the THS4561. The source impedance presented to the balun is a differential 50-Ω source. 图 8-2 and 图 8-3 show the TINA-TI™ model (available as a TINA-TI™ simulation file) and resulting response flatness for this relatively low-frequency balun providing 0.1-dB flatness through 100 MHz. ADTL1-4-75 Model 198.94µ R1 25 L1 + ± + VG1 R2 25 R3 50 L2 VM1 L1 Inductance: 198.94 µH L2 Inductance: 198.94 µH Mutual Inductance: 198.92972 µH 图 8-2. Output Measurement Balun Simulation Circuit in TINA-TI™ 10 8 -6.02 6 -6.03 4 -6.04 2 -6.05 0 -6.06 -2 -6.07 -4 -6.08 -6.09 -6.1 1k Phase (deg) Gain (dB) -6 -6.01 -6 Gain (dB) Phase (deg) 10k -8 100k 1M Frequency (Hz) 10M -10 100M D061 图 8-3. Output Measurement Balun Flatness Test Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 23 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 Starting from the test circuit of 图 8-1, various elements are modified to show the effect of these elements over a range of design targets, specifically: • The gain setting is changed by adjusting the two RT and the RG resistors to provide a 50-Ω input match and setting the feedback resistors to 1.5 kΩ. • Resistive and capacitive output load testing. Changing to lower resistive loads is accomplished by adding parallel resistors across the output pins in 图 8-1. Changing to capacitive loads adds series output resistors to a differential capacitance before the 1-kΩ sense path of 图 8-1. • Power-supply settings. Most often, balanced bipolar supplies are used; a 12-V tests use ±6-V supplies, 5-V tests use ±2.5-V supplies, and 3-V tests use ±1.5-V supplies with the VOCM input control grounded. • The disable control pin (PD) is tied to the positive supply (VS+) for any active channel test. 8.2 Output Interface Circuit for DC-Coupled Differential Testing The pulse response plots are measured using the output circuit of 图 8-4. The two sides of this circuit present a 500-Ω load to ground (for a differential 1-kΩ load) with a 50-Ω source to the two scope inputs. Trace math function of the scope combines the two sides to generate the step response plots of 图 7-13, 图 7-27, and 图 7-44. Use balanced bipolar supplies for this test so that the THS4561 outputs deliver a ground-centered differential swing. This setup produces no DC load currents using the circuit of 图 8-4. RO1 475 RM1 56.2 THS4561 Output 50Scope Input RM1 56.2 RO2 475 50Scope Input 图 8-4. Output Interface for DC-Coupled Differential Outputs 8.3 Output Common-Mode Measurements The circuit of 图 8-5 is a typical setup for common-mode measurements. THS4561 Wideband, Fully Differential Amplifier RG1 1.5 k RF1 1.5 k VS+ Signal Source 100 RS 49.9 VOCM Input RT 49.9 ± FDA + + RG2 1.5 k 50Measurement Equipment VOCM ± PD 100 VS± VS+ RF2 1.5 k 图 8-5. Output Common-Mode Measurements In 图 8-5, the differential path is terminated back to ground with the two 1.5-kΩ input resistors and the VOCM control input is driven from a 50-Ω matched source for the frequency response and step response curves of 图 7-47, 图 7-49, and 图 7-50. The outputs are summed to a center point (to obtain the average, or common-mode output, VOCM) through two 100-Ω resistors. These 100-Ω resistors form an equivalent 50-Ω source to the common-mode output for measurements. 图 7-48 illustrates the common-mode output noise measurements with 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 a ground on the VOCM input pin or with the VOCM input pin floating. The higher noise in 图 7-48 for a floated input can be reduced by including a capacitor to ground at the VOCM control input pin. 8.4 Differential Amplifier Noise Measurements To extract the input-referred noise terms from the total output noise, a measurement of the differential output noise is required under two external conditions to emphasize the different noise terms. A high-gain, low resistor value condition is used to emphasize the differential input voltage noise and a higher RF at low gains is used to emphasize the two input current noise terms. The differential output noise must be converted to single-ended with added gain before being measured by a spectrum analyzer. At low frequencies, a zero 1/f noise, high-gain, differential to single-ended instrumentation amplifier (such as the INA188) is used. At higher frequencies, a differential to single-ended balun is used to drive into a high-gain, low-noise, op amp (such as the LMH6629). In this case, the THS4561 outputs drive 25-Ω resistors into a 1:1 balun where the balun output is terminated single-endedly at the LMH6629 input with 50 Ω. This termination provides a modest 6-dB insertion loss for the THS4561 differential output noise that is then followed by a 40-dB gain setting in the very wideband LMH6629. 8.5 Balanced Split-Supply Versus Single-Supply Characterization Although most end applications use a single-supply implementation, most characterizations are done on a bipolar balanced supply. Using a bipolar balanced supply keeps the I/O common-mode inputs near midsupply and provides the most output swing with no DC bias currents for level shifting. These characterizations include the frequency response, harmonic distortion, and noise plots. The time domain plots are in some cases done through single-supply characterization to obtain the correct movement of the input common-mode voltage. 8.6 Simulated Characterization Curves In some cases, a characteristic curve can only be generated through simulation. A good example of this scenario is the output balance plot of 图 7-51. This plot shows the best-case output balance (output differential signal versus output common-mode signal) using exact matching of the external resistors in simulation using a singleended input to differential output configuration. The actual output balance is set by resistor mismatch at low frequencies but intersects and follows the high-frequency portion of 图 7-51 at higher frequencies. The remaining simulated plots include: • AOL gain and phase; see 图 7-41. • CMRR and PSRR vs frequency; see 图 7-52. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 25 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 8.7 Terminology and Application Assumptions There are common terms that are unique to this device. This section identifies and explains these terms. • Fully differential amplifier (FDA). This term is restricted to devices offering what is similar to a differential inverting op amp design element that requires an input resistor (not a high-impedance input) and includes a second internal control loop that sets the output average voltage (VOCM) to a default or set point. This second common-mode control loop interacts with the differential loop in certain configurations. • The desired output signal at the two output pins is a differential signal that swings symmetrically around a common-mode voltage, VOCM, which is the average voltage of the two outputs. • Single-ended to differential. Generally the output is always used differentially in an FDA; however, the source signal can be either a single-ended or a differential source. For an FDA operating in single-ended to differential, the input is applied only to one of the two inputs via input resistors. • The common-mode control loop has limited bandwidth from the input VOCM pin to the common-mode output voltage. The internal loop bandwidth beyond the input VOCM buffer is a much wider bandwidth than the reported VOCM bandwidth, but is not directly discernable. A very wide bandwidth in the internal VOCM loop is required to perform an effective and low-distortion single-ended to differential conversion. Several features in the application of the THS4561 are not explicitly stated, but are necessary for correct operation. These features are: • Although often not stated, the disable pin ( PD) is tied to the positive supply when an enabled channel is desired. • Virtually all ac characterization equipment expects a 50-Ω termination from the 50-Ω source and a 50-Ω, single-ended source impedance from the device outputs to the 50-Ω sensing termination. This condition is achieved in all characterizations (often with some insertion loss) but is not necessary for most applications. Matching impedance is most often required when transmitting over longer distances. Tight layouts from a source, through the THS4561, and to an ADC input do not require doubly-terminated lines or filter designs. The only exception is if the source requires a defined termination impedance for correct operation (for example, mixer outputs). • The amplifier signal path is flexible for use as single-supply or split-supply operation. Most applications are intended to be single supply, but any split-supply design can be used as long as the total supply voltage across the TH4561 is less than 12.6 V and the required input, output, and common-mode pin headrooms to each supply are taken into account. When left open, the VOCM pin defaults to near midsupply for any combination of split or single supplies used. • External element values are normally assumed to be accurate and matched. In an FDA, this assumption translates to equal feedback resistor values and a matched impedance from each input summing junction to either a signal source or a DC bias reference on each side of the inputs. Unbalancing these values introduces non-idealities in the signal path. For the signal path, imbalanced resistor ratios on the two sides creates a common-mode to differential conversion. Furthermore, mismatched RF values and feedback ratios create additional differential output error terms from any common-mode DC or AC signal or noise terms. Using standard 1% resistor values is a typical approach and generally leads to some nominal feedback ratio mismatch. Modestly mismatched resistors or ratios do not by themselves degrade harmonic distortion. Where there is a meaningful common-mode noise or distortion in the input signal, that gets converted to differential via an element or ratio mismatch. For the best DC precision, use 0.1% accuracy resistors that are readily available in E96 values. 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 9 Detailed Description 9.1 Overview The THS4561 is a fully differential amplifier featuring an extremely flexible supply voltage range of 2.85 V to 12.6 V, which makes this device an excellent choice for driving differential ADCs and buffering DAC outputs. This device features a low-power mode with a unique active-pullup resistor (not a conventional pullup resistor) that improves EMI reliability of the shutdown pin when left floating. This pin draws very little bias current when enabled, but increases the bias current as it nears the threshold point of shutdown. The increased current prevents the pin from unintentionally turning the device off in the presence of EMI on the disable pin. Similar to other fully differential amplifiers, the THS4561 also includes an output common-mode control pin that can be used to independently set the output common mode to match that of an ADC or other load circuit. 9.2 Functional Block Diagram VS+ 8.5 (RGT Package) FB+ OUT+ IN± ± 6k High-AOL + Differential I/O Amplifier ± 2.4 pF IN+ 6k + OUT± VS+ (RGT Package) FB± 400 k 8.5 VS± ± VCM Error Amplifier + PD VOCM CMOS Buffer 400 k VS± Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 27 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 9.3 Feature Description In addition to the core differential I/O voltage feedback gain block, there are two 6-kΩ resistors internally across the outputs to sense the average voltage at the outputs. These resistors feed the average voltage back into a VCM error amplifier where the voltage is compared to either a default voltage divider across the supplies or an externally set VOCM target voltage. When the amplifier is disabled, the default midsupply bias string is disabled to save power. To achieve the very-low noise at the low power provided by the THS4561, the input stage transistors are relatively large, thus resulting in a higher differential input capacitance (2.4 pF in 节 9.2). When using the 16-pin WQFN package and the internal feedback traces to the input side of the package, include the nominal trace impedance of 8.5 Ω in the design. These elements are not included in the TINA-TI™ model and must be added externally to a design intending to use the RGT package. 9.4 Device Functional Modes The wideband FDA requires external resistors for correct signal-path operation. When configured for the desired input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin asserted to a voltage greater than (VS+) – 0.5 V, or turned off by asserting PD low (1.8 V below the positive supply). Disabling the amplifier shuts off the quiescent current and stops correct amplifier operation. The signal path is still present for the source signal through the external resistors, which provides poor signal isolation from the input to output in power-down mode. Internal protection diodes remain present across the input pins in both operating and shutdown mode. Large input signals during disable can turn on the input differential protection diodes, thus producing a load current in the supply even in power-down. The VOCM control pin sets the output average voltage. The VOCM defaults to an internal midsupply value if left open. Driving this high-impedance input with a voltage reference within the valid range sets a target for the internal VCM error amplifier. If floated to obtain a default midsupply reference for VOCM, an external decoupling capacitor is recommended to be added on the VOCM pin to reduce the otherwise high output noise for the internal high-impedance bias (see 图 7-48). 9.4.1 Power-Down Mode The power down ( PD) pin must be asserted to the desired voltage for proper power-down mode operation. A physical internal pullup resistor is not provided on the PD pin so that if the pin is floated, the device defaults to an ON state. Tie the PD pin to the positive supply voltage for applications that simply require the device to power on when the supplies are present. For single-supply operation, a minimum of 0.5 V within the positive supply is required for operation. The disable operation is referenced from the positive supply. For an OFF state condition, the disable control pin must be 1.8 V below the positive supply. The THS4561 has a unique power-down circuit that requires overcoming the specified peak PD pulldown current when the PD voltage is pulled low. When this current threshold is overcome, the PD current drops to a very small value. The benefit of the circuit is that the device stays disabled without having to use an active pullup resistor that wastes crucial power to keep the amplifier disabled in power-sensitive applications. 9.4.2 Single-Ended Source to Differential Output Mode One of the most useful features supported by the FDA device is an easy conversion from a single-ended input to a differential output centered on a user-controlled, common-mode level. Although the output side is relatively straightforward, the device input pins move in a common-mode manner with the input signal. The common-mode voltage at the input pins, which moves with the input signal, increases the apparent input impedance to be greater than the RG value. The input active impedance issue applies to both AC-coupled and DC-coupled designs, and requires somewhat more complex solutions for the resistors to account for this active impedance, as discussed in 节 10.1.2. 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 9.4.2.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions When the signal path can be AC-coupled, the DC biasing for the THS4561 becomes a relatively simple task. In all designs, start by defining the output common-mode voltage. The AC-coupling requirement can be separated for the input and output sides of an FDA design. The input can be AC-coupled and the output DC-coupled, or the output can be AC-coupled and the input DC-coupled, or both can be AC-coupled. One situation where the output can be DC-coupled (for an AC-coupled input), is when driving directly into an ADC where the VOCM control voltage uses the ADC common-mode reference to directly bias the FDA output common-mode voltage to the required ADC input common-mode voltage. In any case, the design starts by setting the desired VOCM. When an AC-coupled path follows the output pins, the best linearity is achieved by operating VOCM at midsupply, which can be easily delivered by floating the VOCM pin. The VOCM voltage must be within the linear range for the common-mode loop, as specified in the headroom specifications. If the output path is also AC-coupled, simply letting the VOCM control pin float is usually preferred in order to obtain a midsupply default VOCM bias with minimal elements. To limit noise, place a 0.1-µF decoupling capacitor on the VOCM control pin to ground. After V OCM is defined, check the target output voltage swing to make certain that the VOCM plus the positive and negative output swing on each side does not clip into the supplies. If the desired peak-to-peak output differential swing is defined as VOPP, divide by 4 to obtain the ±VP (peak voltage) swing around VOCM at each of the two output pins (each pin operates 180° out of phase with the other). Check that VOCM ±VP does not exceed the absolute supply rails for the rail-to-rail output (RRO) device. Common-mode current does not flow from the common-mode output voltage set by the VOCM pin towards the device input pins side, because both the source and balancing resistor on the non-signal input side are DC blocked. The AC-coupled input path sets the input pin common-mode voltage equal to the output common-mode voltage. If the VOCM voltage is within the headroom requirement, then the input pins are also in range for the AC-coupled input configuration. This headroom requirement functions similarly for when the VOCM voltage approaches the negative supply. The input pin voltages move in a common-mode manner with the input signal. Confirm that the VOCM voltage plus the input VPP common-mode swing also stays in the VICM specification range for the input pins. 9.4.2.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions The output considerations remain the same as for the AC-coupled design. Again, the input can be DC-coupled when the output is ac coupled. A DC-coupled input with an AC-coupled output can have some advantages to move the input VICM down by adjusting the VOCM down if the source is ground referenced. When the source is DC-coupled into the THS4561 (see 图 10-3), both sides of the input circuit must be DC-coupled to retain differential balance. Normally, the non-signal input side has an RG element biased to whatever the source midrange is expected to be, provided that this midscale reference gives a balanced differential swing around VOCM at the outputs. Often, RG2 is simply grounded for DC-coupled, bipolar-input applications. This configuration provides a balanced differential output if the source swings around ground. If the source swings from ground to some positive voltage, grounding RG2 gives a unipolar output differential swing from both outputs at VOCM (when the input is at ground) to one polarity of the swing. Biasing RG2 to an expected midpoint for the input signal creates a differential output swing around VOCM. One significant consideration for a DC-coupled input is that VOCM sets up a common-mode bias current from the output back through RF and RG to the source on both sides of the feedback. Without input balancing networks, the source must sink or source this dc current. After the input signal range and biasing on the other R G element is set, check that the voltage divider from VOCM to VIN through RF and RG (and possibly RS) establishes an input VICM at the device input pins that is within the specification range. If the average source is at ground, the negative rail input stage for the THS4561 is in range for applications using a single positive supply and a positive output VOCM setting because this dc common-mode current lifts the average FDA input summing junctions above ground to a positive voltage (the average of the V+ and V– input pin voltages on the FDA). TINA-TI™ simulations of the intended circuit offer a good check for input and output pin voltage swings. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 29 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 9.4.3 Differential Input to a Differential Output Mode In many ways, this method is a much simpler way to operate the FDA from a design equations perspective. Again, assuming that the two sides of the circuit are balanced with equal RF and RG elements, the differential input impedance is now just the sum of the two RG elements to a differential inverting summing junction. In these designs, the input common-mode voltage at the summing junctions does not move with the signal but must be dc biased in the design range for the input pins and must take into account the voltage headroom required to each supply. Slightly different considerations apply to AC-coupled or DC-coupled differential input to differential output designs, as described in the following sections. 9.4.3.1 AC-Coupled, Differential-Input to Differential-Output Design Issues The most common way to use the THS4561 with an AC-coupled differential source is to simply couple the input into the RG resistors through the blocking capacitors. 图 9-1 shows a typical blocking capacitor approach to a differential input. An optional input differential termination resistor (RM) is included in this design. The RM element allows the input RG resistors to be scaled up and still delivers lower differential input impedance to the source. In this example, the RG elements sum to show a 1-kΩ differential impedance and the RM element combines in parallel to provide a net 500-Ω ac differential impedance to the source. Again, the design ideally proceeds by selecting the RF element values, then the RG to set the differential gain, and then an RM element (if needed) to achieve a target input impedance. Alternatively, the RM element can be eliminated, with the 2 × RG elements set to the desired input impedance and RF set to obtain the differential gain (equal to RF / RG). THS4561 Wideband, Fully Differential Amplifier Differential I/O with AC-Coupled Input VS+ + ± 10 nF 5V ± VS+ RG1 499 ± VS± + RF1 1.5 k VOCM 0V VIN RM 1k 1 µF + FDA + RG2 499 RL 1k PD VS± 10 nF VO ± VS+ RF2 1.5 k 图 9-1. Example AC-Coupled Differential Input Design The DC biasing for an AC-coupled differential input design is very simple. The output VOCM is set by the VOCM input control voltage and, because there is no DC current path for the output common-mode voltage (as long as RM is only differential and not split and connected to ground for instance), the VOCM DC bias also sets the common-mode operating points for the input pins. For a purely differential input, the voltages on the input pins remain fixed at the output VOCM setting and do not move with the input signal (unlike the single-ended input configurations where the input pin common-mode voltages do move with the input signal). 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 10 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 10.1 Application Information Most applications for the THS4561 strive to deliver the best dynamic range in a design that delivers the desired signal processing along with adequate phase margin for the amplifier itself. The following sections detail some of the design issues with analysis and guidelines for improved performance. 10.1.1 Differential Open-Loop Gain and Output Impedance -60 65 -90 50 -120 35 -150 20 -180 5 -210 -10 -25 -40 10k 10000 -240 Gain, no load Gain, 100-: load Phase, no load Phase, 100-: load -270 -300 100k 1M 10M Frequency (Hz) 100M D103 图 10-1. No-Load and 100-Ω Loaded AOL Gain and Phase Differential Output Impedance (:) 80 Phase (q) Gain (dB) The most important elements to the closed-loop performance are the open-loop gain and open-loop output impedance. 图 10-1 shows the simulated differential open-loop gain and phase from the differential inputs to the differential outputs with no load and with a 100-Ω load. Operating with no load removes any effect introduced by the open-loop output impedance to a finite load. 图 10-2 shows the simulated differential open-loop output impedance. 1000 100 10 10 100 1k 10k 100k 1M Frequency (Hz) 10M 100M 1G 图 10-2. Differential Open-Loop Output Impedance This open-loop output impedance combines with the load to shift the apparent open-loop gain and phase to the output pins when the load changes. The rail-to-rail output stage shows a very high impedance at low frequencies that reduces with frequency to a lower midrange value and then peaks again at higher frequencies. The maximum value at low frequencies is set by the common-mode sensing resistors to be a 6-kΩ dc value (see 节 9.2.) This high impedance at a low frequency is significantly reduced in closed-loop operation by the loop gain, as shown in the closed-loop output impedance of 图 7-43. 图 10-1 compares the no load AOL gain to the AOL gain driving a 100-Ω load that shows the effect of the output impedance. The heavier loads pull the AOL gain down faster to lower crossovers with more phase shift at the lower frequencies. The much faster phase rolloff for the 100-Ω differential load explains the greater peaked response illustrated in 图 7-4 and 图 7-18 when the load decreases. This same effect happens for the RC loads common with converter interface designs. Use the TINA-TI™ model to verify loop phase margin in any design. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 31 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 10.1.2 Setting Resistor Values Versus Gain The THS4561 offers considerable flexibility in the configuration and selection of resistor values. The design starts with the selection of the feedback resistor value. The 1.5-kΩ feedback resistor value used for the characterization curves is a good compromise between power, noise, and phase margin considerations. With the feedback resistor values selected (and set equal on each side) the input resistors are set to obtain the desired gain with input impedance also set with these input resistors. Differential I/O designs provide an input impedance that is the sum of the two input resistors. Single-ended input to differential output designs present a more complicated input impedance. Most characteristic curves implement the single-ended to differential design as the more challenging requirement over differential-to-differential I/O. For single-ended, matched, input impedance designs, 表 10-1 illustrates the suggested standard resistors set to approximately a 1.5-kΩ feedback. This table assumes a 50-Ω source and a 50-Ω input match and uses a single resistor on the non-signal input side for gain matching. Better matching is possible using the same three resistors on the non-signal input side as on the input side. 图 10-3 shows the element values and naming convention for the gain of 1-V/V configuration where the gain is defined from the matched input at RT to the differential output. THS4561 Wideband, Fully Differential Amplifier 50- Input Match, Gain of 1 V/V from RT, Single-Ended Source to Differential Output 50Source Impedance RF1 1.5 k VS+ RG1 1.5 k RS1 50 ± + RT 52.3 VOCM FDA + RG2 1.52 k RL 1k VO ± PD VS± VS+ RF2 1.5 k 图 10-3. Single-Ended to Differential Gain of 1 V/V with Input Matching Using Standard Resistor Values Starting from a target feedback resistor value, the desired input matching impedance, and the target gain (AV), the required input RT value is given by solving the quadratic of 方程式 1. RT 2 RS § · 2RS ¨ 2RF A V2 ¸ 2 © ¹ RT 2RF 2 A V RS A V (4 A V ) 2RF 2 2RFRS2 A V AV RS A V (4 0 AV ) (1) When this value is derived, the required input side gain resistor is given by 方程式 2 and then the single value for RG2 on the non-signal input side is given by 方程式 3: 2 RG1 RF AV 1 RS RS RT (2) RF AV RS 1 RT 2 RG2 32 (3) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 Using these expressions to generate a swept gain table of values results in 表 10-1, where the best standard 1% resistor values are shown to minimize input impedance and gain error to target. 表 10-1. Swept Gain 50-Ω Input Match with RF = 1.5-kΩ (±1 Standard Values) GAIN (V/V) RF RG1 RT RG2 ZIN AV 0.1 1500 15000 49.9 15000 49.74 0.09973 1 1500 1500 51.1 1500 49.82 0.994 2 1500 750 52.3 768 49.98 1.978 5 1500 287 54.9 316 49.6 5.014 10 1500 137 61.9 165 50.4 10.08 Where an input impedance match is not required, simply set the input resistor to obtain the desired gain without an additional resistor to ground (remove RT in 图 10-3). This scenario is common when coming from the output of another single-ended op amp (such as the OPA810 or OPA192). This single-ended to differential stage shows a higher input impedance than the physical RG as given by the expression for ZA (active input impedance) shown as 方程式 4. ZA RG1 § ¨1 © RG1 ·§ RF · ¸¨ 1 ¸ RG2 ¹© RG1 ¹ RF 2 RG2 (4) Using 方程式 4 for the gain of 1 V/V with all resistors equal to 1.5-kΩ shows an input impedance of 2 kΩ. The increased input impedance comes from the common-mode input voltage at the amplifier pins moving in the same direction as the input signal. The common-mode input voltage must move to create the current in the nonsignal input RG resistor to produce the inverted output. The current flow into the signal-side input resistor is impeded because the common-mode input voltage moves with the input signal, thus increasing the apparent input impedance in the signal input path. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 33 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 10.1.3 Noise Analysis The first step in the output noise analysis is to reduce the application circuit to the simplest form with equal feedback and gain setting elements to ground. 图 10-4 shows the simplest analysis circuit with the FDA and resistor noise terms to be considered. enRg2 enRf2 RF RG r r In+2 + eno2 ± In±2 eni2 enRg2 enRf2 RG RF r r 图 10-4. FDA Noise Analysis Circuit The noise powers are shown in 图 10-4 for each term. When the RF and RG terms are matched on each side, the total differential output noise is the root sum squared (RSS) of these separate terms. Using NG ≡ 1 + RF / RG, the total output noise is given by 方程式 5. Each resistor noise term is a 4kT × R power (4kT = 1.6E-20J at 290K). eo eniNG 2 2 iNRF 2 2 4kTRFNG (5) The first term is simply the differential input spot noise times the noise gain, the second term is the input current noise terms times the feedback resistor (and because there are two uncorrelated current noise terms, the power is two times one of them), and the last term is the output noise resulting from both the RF and RG resistors, at again twice the value for the output noise power of each side added together. Running a wide sweep of gains when holding RF close to 1.5 kΩ and setting the input up for a 50-Ω match gives the standard values and resulting noise listed in 表 10-2. When the gain increases, the input-referred noise approaches only the gain of the FDA input voltage noise term at 5 nV/√ Hz. 表 10-2. Swept Gain of the Output- and Input-Referred Spot Noise Calculations 34 GAIN (V/V) RF RG1 RT RG2 ZIN AV 0.1 1500 15000 49.9 15000 49.74 0.09973 9.15 91.53 1 1500 1500 51.1 1500 49.82 0.994 14.03 14.03 2 1500 750 52.3 768 49.98 1.978 18.99 9.49 5 1500 287 54.9 316 49.6 5.014 33.20 6.64 10 1500 137 61.9 165 50.4 10.08 55.05 5.51 Submit Document Feedback eO (nV/√ Hz) eI (nV/√ Hz) Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 10.1.4 Factors Influencing Harmonic Distortion As illustrated in the swept frequency harmonic distortion plots (图 7-7 and 图 7-21), the THS4561 provides extremely low distortion at lower frequencies. In general, an FDA output harmonic distortion mainly relates to the open-loop linearity in the output stage corrected by the loop gain at the fundamental frequency. When the total load impedance decreases, including the effect of the feedback resistor elements in parallel for loading purposes, the output stage open-loop linearity degrades, thus increasing the harmonic distortion; see 图 7-9 and 图 7-23. When the output voltage swings increase, very fine scale open-loop output stage nonlinearities increase that also degrade the harmonic distortion; see 图 7-8 and 图 7-22. Conversely, decreasing the target output voltage swings drops the distortion terms rapidly. 图 7-8 and 图 7-22 illustrate the effect of going up to a 10-VPP and 8-VPP differential output, respectively, that is more common with SAR converters. Increasing the noise gain functions to decrease the loop gain resulting in the increasing harmonic distortion terms; see 图 7-10 and 图 7-24. One advantage of capacitive compensation that is typical in attenuator designs is that the noise gain is shaped up with frequency to achieve a crossover at an acceptable phase margin at higher frequencies. This technique holds the loop gain high at frequencies lower than the noise gain zero, thus improving distortion at lower frequencies. The THS4561 does an exceptional job of converting from single-ended inputs to differential outputs with very low harmonic distortions. External resistors of 1% tolerance are used in characterization with good results. Unbalancing the feedback divider ratios does not degrade distortion directly. However, imbalanced feedback ratios convert common-mode inputs to a differential mode at the outputs that can result in increased output errors. 10.1.5 Input Overdrive Performance 图 10-5 and 图 10-6 show a 2-V and a 2X output overdrive triangular waveform, respectively, for the THS4561. When the output maximum swing is reached at approximately the supply values, increasing input voltage beyond this condition turns on the internal protection diodes across the two input pins. The internal protection diodes are two diodes in series in both polarities. This feature clamps the maximum differential voltage across the inputs to approximately 1.5 V when the output is limited at the supplies but the input exceeds the available range. The input resistors on both sides limit the current flow in the internal diodes under these conditions. 10 15 Input Output 12 Input Output 7.5 9 5 3 Voltage (V) Voltage (V) 6 0 -3 -6 2.5 0 -2.5 -9 -5 -12 -7.5 -15 -10 Time, 500 ns per division Time, 500 ns per division D016 VS = 12 V, Single-ended to differential gain of 2, 2-V output overdrive, overdrive recovery = 250 ns 图 10-5. Overdrive Recovery Performance D034 VS = 5 V, Single-ended to differential gain of 2, 2x input overdrive, overdrive recovery = 210 ns 图 10-6. Overdrive Recovery Performance Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 35 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 10.2 Typical Application One common application for the THS4561 is to take a single-ended, high VPP voltage swing (from a high-voltage precision amplifier such as the OPA810 or OPA192) and deliver that swing to precision SAR ADC as a singleended to differential conversion with output common-mode control and implement an active 2nd-order multiple feedback (MFB) filter design. Designing for a 16-VPP maximum input down to an 8-VPP differential swing requires a gain of 0.5 V/V. Targeting a 170-kHz Butterworth response with the RC elements tilted towards low noise gives the example design of 图 10-7. The VCM control is set to half of a 4.096-V reference, which is typical for 5-V differential SAR applications. With the high voltage capabilities of the THS4561, the design can be easily adopted for 20-VPP input swing to the FDA for a full 10-VPP swing into 5-V differential SAR ADC by simply using wider power supplies for the THS4561 to allow for increased output swing headroom with minimal performance degradation. THS4561 Wideband, Fully Differential Amplifier RF1 1.5 k OPA810 or OPA192 Output VS+ 5V + ± 3.01 k VS± 0V RG1 931 470 pF To ADC VIN ± 680 pF 100 fF VOCM FDA + 2.2 nF ± + VOCM 2.048 V 10 VS+ + ± 100 pF 20 PD VS± VS+ + To ADC 10 20 ± 3.01 k RG2 931 RF2 1.5 k 8-VPP Differential SAR ADC Input 100 pF 470 pF 图 10-7. MFB Filter Driving an ADC Application: Example 170-kHz Butterworth Response 10.2.1 Design Requirements The requirements for this application are: • • • • • Single-ended to differential conversion Attenuation by 0.5-V/V gain Active filter set to a Butterworth, 170-kHz response shape Output RC elements set by SAR input requirements (not part of the filter design) Filter element resistors and capacitors are set to limit added noise over the THS4561 and noise peaking 10.2.2 Detailed Design Procedure The design proceeds using the techniques and tools suggested in the Design Methodology for MFB Filters in ADC Interface Applications application note. The process includes: Scale the resistor values to not meaningfully contribute to the output noise produced by the THS4561 by itself Select the RC ratios to hit the filter targets when reducing the noise gain peaking within the filter design Set the output resistor to 10 Ω into a 2.2-nF differential capacitor Add 100-pF common-mode capacitors to the load capacitor to improve common noise filtering Inside the loop, add 20-Ω output resistors after the filter feedback capacitor to increase the isolation to the load capacitor • Include a place for a differential input capacitor (illustrated as 100 fF in 图 10-7) • • • • • 36 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 10.2.3 Application Curves 145 100k 1M Frequency (Hz) 140 10 130 7.5 125 5 120 2.5 D101 图 10-8. Gain Plot for a 170-kHz Butterworth Filter 12.5 135 115 1k 10M 15 SNR Total Noise 10k 100k Frequency (Hz) 1M Total Noise (PV) 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 10k Signal-to-Noise Ratio, SNR (dB) Gain (dB) 图 10-8 and 图 10-9 show the gain response and the noise results of the circuit shown in 图 10-7. 图 10-7 shows a place for a differential input capacitor (shown as 100 fF) but is not used for the simulation results shown in this section. Results in 图 10-8 illustrate a flat Butterworth filter response at the output nodes going to the ADC. Obtaining the SNR to the ADC input pins, and assuming an 8-VPP full scale (2.83 VRMS), gives the result of 图 10-9. The 116-dB SNR and 13-µVRMS total noise shown in 图 10-9 does not limit the performance for any SAR application. 0 10M D102 图 10-9. Signal-to-Noise Ratio and Total Noise Plot 11 Power Supply Recommendations The THS4561 is principally intended to operate with a nominal single-supply voltage of 3 V to 12 V. Supply voltage tolerances are supported with the specified operating range of 2.85 V (10% low on a 3-V nominal supply) and 12.6 V (5% high on a 12-V nominal supply). Supply decoupling is required, as described in 节 8.7. Split (or bipolar) supplies can be used with the THS4561, as long as the total value across the device remains less than that specified in 节 7.3. Using a negative supply to deliver a true swing to ground output when driving SAR ADCs can be desired. Although the THS4561 quotes a rail-to-rail output, linear operation requires approximately 200-mV headroom to the supply rails. One easy option for extending the linear output swing to ground is to provide the small negative supply voltage required using the LM7705 fixed –230-mV, negative-supply generator. This low-cost, fixed, negative-supply generator can accept a 3-V to 5-V positive supply and provides a fixed –230-mV supply for the negative power supply. Using the LM7705 provides an effective solution, as discussed in the Extending Rail-toRail Output Range for Fully Differential Amplifiers to Include True Zero Volts reference guide. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 37 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 12 Layout 12.1 Layout Guidelines 12.1.1 Board Layout Recommendations Similar to all high-speed devices, best system performance is achieved with close attention to board layout. The provides a good example of high-frequency layout techniques as a reference. This EVM includes numerous extra elements and features for characterization purposes that may not apply to some applications. General high-speed signal path layout suggestions include: • Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs; however, both ground and power planes must be opened up around the capacitive sensitive input and output device pins. When the signal goes to a resistor, parasitic capacitance becomes more of a band-limiting issue and less of a stability issue. • Good high-frequency decoupling capacitors (0.1 µF) are required to a ground plane at the device power pins. Additional higher-value capacitors (2.2 µF) are also required but can be placed further from the device power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply decoupling capacitors that offer a much higher self-resonance frequency over standard capacitors. • Differential signal routing over any appreciable distance must use microstrip layout techniques with matched impedance traces. • The input summing junctions are very sensitive to parasitic capacitance. Any RG elements must connect into the summing junction with minimal trace length to the device pin side of the resistor. The other side of the RG elements can have more trace length if needed to the source or to GND. 12.2 Layout Examples RG± RF+ VIN RT± VS+ CBYP RO+ ± + VOCM FDA CL ± + PD RO± VS+ CBYP VS± RG+ RS+ RT+ RF± 图 12-1. Representative Schematic for the Layout in 38 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 RS+ VIN RT+ IN± IN+ PD 7 3 VS+ VS± 6 RO+ OUT+ OUT± CL RF± VOCM RF+ 2 4 Vias to connect supply pins to CBYP. Place CBYP capacitors on the other side of the PCB as close to the vias as possible. 8 Place the feedback resistors, RF±, gain resistors, RG±, and the isolation resistors, RO±, as close to the device pins as possible to minimize parasitics 5 RO± 1 RG+ Remove GND and Power plane under output and inverting pins to minimize stray PCB capacitance RG± RT± Ground and power plane exist on inner layers. Ground and power plane removed from inner layers. Ground fill on outer layers also removed. 图 12-2. Layout Recommendations Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 39 THS4561 www.ti.com.cn ZHCSGR2D – AUGUST 2017 – REVISED FEBRUARY 2021 13 Device and Documentation Support 13.1 接收文档更新通知 要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更 改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。 13.2 支持资源 TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解 答或提出自己的问题可获得所需的快速设计帮助。 链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。 13.3 Trademarks TI E2E™ is a trademark of Texas Instruments. 所有商标均为其各自所有者的财产。 13.4 静电放电警告 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理 和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参 数更改都可能会导致器件与其发布的规格不相符。 13.5 术语表 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 40 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4561 PACKAGE OPTION ADDENDUM www.ti.com 22-May-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) THS4561IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 4561 Samples THS4561IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 4561 Samples THS4561IRGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TH4561 Samples THS4561IRUNR ACTIVE QFN RUN 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 4561 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of