THS6002CDWPR

    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 D ADSL Differential Line Driver and Receiver D Driver Features D D D D D DWP PACKAGE (TOP VIEW) − 140 MHz Bandwidth (−3dB) With 25-Ω Load − 315 MHz Bandwidth (−3dB) With 100-Ω Load − 1000 V/µs Slew Rate, G = 2 − 400 mA Output Current Minimum Into 25-Ω Load − −72 dB 3rd Order Harmonic Distortion at f = 1 MHz, 25-Ω Load, and 20 VO(PP) Receiver Features − 330 MHz Bandwidth (−3dB) − 900 V/µs Slew Rate at G = 2 − −76 dB 3rd Order Harmonic Distortion at f = 1 MHz, 150-Ω Load, and 20 VO(PP) Wide Supply Range ± 4.5 V to ±16 V Available in the PowerPAD Package Improved Replacement for AD816 or EL1501 Evaluation Module Available VCC − D1 OUT VCC+ D1 IN+ D1 IN− R1 IN− R1 IN+ VCC+ R1 OUT VCC − 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC − D2 OUT VCC+ D2 IN+ D2 IN− R2 IN− R2 IN+ VCC+ R2 OUT VCC − Cross Section View Showing PowerPAD description The THS6002 contains two high-current, high-speed drivers and two high-speed receivers. These drivers and receivers can be configured differentially for driving and receiving signals over low-impedance lines. The THS6002 is ideally suited for asymmetrical digital subscriber line (ADSL) applications where it supports the high-peak voltage and current requirements of that application. Both the drivers and the receivers are current feedback amplifiers designed for the high slew rates necessary to support low total harmonic distortion (THD) in ADSL applications. Separate power supply connections for each driver are provided to minimize crosstalk. HIGH-SPEED xDSL LINE DRIVER/RECEIVER FAMILY DEVICE THS6002 THS6012 THS6022 THS6062 THS7002 DRIVER RECEIVER • • • • • • 5V • ±5 V ±15 V BW (MHz) SR (V/µs) THD f = 1 MHz (dB) IO (mA) Vn (nV/√Hz) • • • • • • • • • • 140 1000 −62 500 1.7 140 1300 −65 500 1.7 210 1900 −66 250 1.7 100 100 −72 90 1.6 70 100 −84 25 2.0 CAUTION: The THS6002 provides ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. Copyright  1999, Texas Instruments Incorporated 
 
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           SLOS202E− JANUARY 1998− REVISED MARCH 2007 description (continued) The THS6002 is packaged in the patented PowerPAD package. This package provides outstanding thermal characteristics in a small footprint package, which is fully compatible with automated surface mount assembly procedures. The exposed thermal pad on the underside of the package is in direct contact with the die. By simply soldering the pad to the PWB copper and using other thermal outlets, the heat is conducted away from the junction. AVAILABLE OPTIONS PACKAGED DEVICE TA PowerPAD PLASTIC SMALL OUTLINE† (DWP) EVALUATION MODULE 0°C to 70°C THS6002CDWP THS6002EVM −40°C to 85°C THS6002IDWP † The DWP packages are available taped and reeled. Add an R suffix to the device type (i.e., THS6002CDWPR) absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC+ to VCC− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V Input voltage, VI (driver and receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VCC Output current, IO (driver) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mA Output current, IO (receiver) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Differential input voltage, VID (driver and receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Continuous total power dissipation at (or below) TA = 25°C (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 W Operating free air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 125°C Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The THS6002 incorporates a PowerPad on the underside of the chip. This acts as a heatsink and must be connected to a thermal dissipation plane for proper power dissipation. Failure to do so can result in exceeding the maximum junction temperature, which could permanently damage the device. See the Thermal Information section of this document for more information about PowerPad technology. recommended operating conditions MIN Supply voltage, VCC+ and VCC − Operating free-air temperature, TA 2 TYP MAX ± 4.5 ± 16 Single supply 9 32 C suffix 0 70 −40 85 Split supply I suffix POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V °C 
    
          SLOS202E− JANUARY 1998− REVISED MARCH 2007 functional block diagram Driver 1 3 V + CC D1 IN+ 4 + 2 D1 IN− 5 1 Driver 2 D2 IN+ 17 18 D2 IN− 8 VCC+ D2 OUT _ 20 VCC+ VCC− + 19 16 D1 OUT _ Receiver 1 + 7 VCC− R1 IN+ R1 OUT 9 _ 6 R1 IN− VCC− 10 VCC+ 13 Receiver 2 + R2 OUT 14 R2 IN+ 12 _ 15 R2 IN− VCC− 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 DRIVER electrical characteristics, VCC = ±15 V, RL = 25 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted) TEST CONDITIONS† PARAMETER Split supply VCC Power supply operating range Single supply Single ended VO Common-mode input voltage range VCC = ± 5 V VCC = ± 15 V VIO Input offset voltage VCC = ± 5 V or ± 15 V Input offset voltage drift VCC = ± 5 V or ± 15 V, Differential input offset voltage VCC = ± 5 V or ± 15 V Differential input offset voltage drift VCC = ± 5 V or ± 15 V, Input bias current Positive VCC = ± 5 V or ± 15 V 12.5 to −12.2 VCC = ± 5 V 6 to −5.6 6.4 to −6 VCC = ± 15 V 23.6 to −23 25 to −24.4 IOS Short-circuit output current (see Note 2) ± 3.6 ± 3.7 ± 13.4 ± 13.5 TA = 25°C TA = full range 2 TA = full range TA = 25°C TA = full range TA = full range 4 TA = full range TA = full range RL = 5 Ω Differential common-mode rejection ratio µV/°C 8 mV µV/°C µA µA µA 500 400 500 800 VCC = ± 5 V or ± 15 V, 10 11 mA mA 1.5 VCC = ± 15 V Common-mode rejection ratio 9 12 1.5 mV 4 12 VCC = ± 5 V Open loop transresistance 5 10 TA = 25°C RL = 25 Ω V 5 3 V V 20 1.5 UNIT V 7 TA = 25°C VCC = ± 5 V, VCC = ± 15 V, Output current (see Note 2) CMRR VCC = ± 15 V 11.8 to −11.5 TA = full range Differential IO 33 TA = 25°C Negative IIB ±16.5 9 3.2 to −3 RL = 50 Ω MAX ±4.5 3 to −2.8 RL = 25 Ω VICR TYP VCC = ± 5 V Output voltage swing Differential MIN 5 62 TA = full range MΩ 70 100 dB Crosstalk Driver to driver VI = 200 mV, f = 1 MHz −62 dB † Full range is 0°C to 70°C for the THS6002C and − 40°C to 85°C for the THS6002I. NOTE 2: A heat sink is required to keep the junction temperature below absolute maximum when an output is heavily loaded or shorted. See absolute maximum ratings and Thermal Information section. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 DRIVER electrical characteristics, VCC = ±15 V, RL = 25 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted) (continued) TEST CONDITIONS† PARAMETER VCC = ± 5 V PSRR Power supply rejection ratio VCC = ± 15 V MIN TYP TA = 25°C −68 −74 TA = full range −65 TA = 25°C TA = full range −64 MAX UNIT dB −72 dB −62 CI Differential input capacitance 1.4 pF RI Input resistance 300 kΩ RO Output resistance ICC Open loop Ω 13 VCC = ± 5 V TA = 25°C TA = full range 8.5 VCC = ± 15 V TA = 25°C TA = full range 11.5 Quiescent current 10 12 13 mA 15 † Full range is 0°C to 70°C for the THS6002C and − 40°C to 85°C for the THS6002I. operating characteristics, VCC = ±15 V, RL = 25 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted) PARAMETER SR Differential slew rate ts Settling time to 0.1% TEST CONDITIONS VO = 20 V(PP), 0 V to 10 V Step, MIN UNIT G=2 70 ns −62 dBc 1.7 nV/√Hz THD Total harmonic distortion Vn Input voltage noise VCC = ± 5 V or ± 15 V, G = 2, f = 10 kHz, Single-ended In Input noise current VCC = ± 5 V or ± 15 V, G=2 f = 10 kHz, VI = 200 mV, RF = 680 Ω G = 1, VCC = ± 5 V VCC = ± 15 V VI = 200 mV, RF = 620 Ω G = 2, VI = 200 mV, RF = 820 Ω, Negative (IN−) MAX 1000 VO(PP) = 20 V,RF = 4 kΩ, G = 5, Positive (IN+) TYP G=2 f = 1 MHz V/µs 11.5 16 pA/√Hz 90 110 MHz 110 140 MHz VCC = ± 15 V 120 MHz G = 1, RL = 100 Ω VCC = ± 15 V 315 MHz VI = 200 mV, RF = 560 Ω, G = 2, RL = 100 Ω VCC = ± 15 V 265 MHz VI = 200 mV, RF = 680 Ω G = 1, VCC = ± 5 V VCC = ± 15 V 30 Bandwidth for 0.1 dB flatness Full power bandwidth (see Note 3) VO = 20 V(PP) Differential gain error NTSC, 40 IRE VCC = ± 5 V VCC = ± 15 V 0.04% AD G = 2, RL = 150 Ω, φD G = 2, RL = 150 Ω, NTSC, 40 IRE VCC = ± 5 V 0.07° Differential phase error VCC = ± 15 V 0.08° Small-signal bandwidth (−3 dB) BW 40 16 MHz MHz 0.05% NOTE 3: Full power bandwidth = slew rate/2πVpeak POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 RECEIVER electrical characteristics, VCC = ±15 V, RL = 150 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted) TEST CONDITIONS† PARAMETER Power supply operating range VO Output voltage swing VICR Common-mode input voltage range Single ended ± 16.5 9 33 VCC = ± 5 V VCC = ± 15 V ±3 ± 3.3 ± 12.4 ± 12.8 ± 3.6 ± 3.7 ± 13.4 ± 13.5 VCC = ± 5 V VCC = ± 15 V VCC = ± 5 V or ± 15 V Input offset voltage Differential Single ended Input offset voltage drift IIB Input bias current Differential VCC = ± 5 V or ± 15 V Negative VCC = ± 5 V or ± 15 , Positive VCC = ± 5 V or ± 15 V Differential VCC = ± 5 V or ± 15 V IO Output current (see Note 2) IOS Short-circuit output current (see Note 2) Common-mode rejection ratio Crosstalk (receiver to receiver) PSRR 1 TA = 25°C TA = full range 1.5 Differential V 4 4 mV 5 10 TA = 25°C 2 TA = full range µV/°C V/°C 8 10 TA = 25°C 3.5 TA = full range 9 11 TA = 25°C 1.5 TA = full range µA 8 10 RL = 25 Ω 95 80 85 110 mA mA 1.5 5 60 VCC = ± 5 V or ± 15 V, TA = full range VI = 200 mV, f = 1 MHz VCC = ± 5 V TA = 25°C TA = full range −66 VCC = ± 15 V TA = 25°C TA = full range −65 Power supply rejection ratio V V 20 RL = 150 Ω UNIT 6 VCC = ± 15 V Single ended CMRR VCC = ± 5 V VCC = ± 15 V RL = 25 Ω TA = 25°C TA = full range VCC = ±5 V Open loop transresistance MAX ± 4.5 Single ended VIO TYP Single supply Split supply VCC MIN MΩ 70 100 −67 dB dB −74 −63 −72 dB −62 RI Input resistance 300 kΩ CI Differential input capacitance 1.4 pF RO Output resistance Open loop 10 Ω † Full range is 0°C to 70°C for the THS6002C and − 40°C to 85°C for the THS6002I. NOTE 2: A heat sink is required to keep junction temperature below absolute maximum when an output is heavily loaded or shorted. See absolute maximum ratings and Thermal Information section. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 RECEIVER electrical characteristics, VCC = ±15 V, RL = 150 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted) (continued) TEST CONDITIONS† PARAMETER ICC MIN TYP MAX 5.5 VCC = ± 5 V TA = 25°C TA = full range 4.2 VCC = ± 15 V TA = 25°C TA = full range 5 Quiescent current UNIT 7.5 7 mA 9 † Full range is 0°C to 70°C for the THS6002C and − 40°C to 85°C for the THS6002I. operating characteristics, VCC = ±15 V, RL = 150 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted) PARAMETER SR Differential slew rate ts Settling time to 0.1% TEST CONDITIONS MIN TYP G=2 900 V/µs G=2 50 ns RF = 510 Ω, f =1 MHz −68 dBc 1.7 nV/√Hz THD Total harmonic distortion Vn Input voltage noise VCC = ± 5 V or ± 15 V G=2 f = 10 kHz, In Input current noise VCC = ± 5 V or ± 15 V, G=2 f = 10 kHz, VI = 200 mV, RF = 560 Ω G = 1, VCC = ± 5 V VCC = ± 15 V VI = 200 mV, RF = 430 Ω G = 2, VCC = ± 15 V 285 VI = 200 mV, RF = 560 Ω G = 1, VCC = ± 5 V VCC = ± 15 V 20 Bandwidth for 0.1 dB flatness Full power bandwidth (see Note 3) VO = 20 V(PP) Differential gain error G = 2, NTSC VCC = ± 5 V VCC = ± 15 V 0.09% AD 40 IRE, RL = 150 Ω, φD 40 IRE, RL = 150 Ω, G = 2, NTSC VCC = ± 5 V VCC = ± 15 V 0.13° Differential phase error Negative (IN−) Small-signal bandwidth (−3 dB) BW UNIT VO = 10 V(PP), 10 V Step, VO(PP) = 20 V, G = 5, Positive (IN+) MAX 11.5 16 270 300 300 330 25 14 pA/√Hz MHz MHz MHz MHz 0.1% 0.16° NOTE 3: Full power bandwidth = slew rate/2πVpeak POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION 1 kΩ 1 kΩ 1 kΩ − Driver 1 − VO + VI 1 kΩ VO 25 Ω 50 Ω Driver 2 + 25 Ω VI 50 Ω Figure 1. Driver Input-to-Output Crosstalk Test Circuit 1 kΩ 1 kΩ Receiver 1 VI 1 kΩ − − VO + VO 150 Ω 50 Ω + 150 Ω 1 kΩ Receiver 2 VI 50 Ω Figure 2. Receiver Input-to-Output Crosstalk Test Circuit RG RF 15 V Driver VI 50 Ω − VO + −15 V RL 25 Ω Figure 3. Driver Test Circuit, Gain = 1 + (RF/RG) RG RF 15 V VI Receiver 50 Ω − VO + −15 V RL 150 Ω Figure 4. Receiver Test Circuit, Gain = 1 + (RF/RG) 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Supply current Driver and Receiver vs Supply voltage 5 Input voltage noise Driver and Receiver vs Frequency 6 Input current noise Driver and Receiver vs Frequency 6 Closed-loop output impedance Driver and Receiver vs Frequency 7 Driver vs Supply voltage 8 Receiver vs Supply voltage 31 Driver vs Load resistance 9 Peak-to-peak output voltage swing Peak-to-peak output voltage VIO Input offset voltage IIB Input bias current CMMR Common-mode rejection ratio Input-to-output crosstalk PSSR ICC Receiver vs Load resistance 32 Driver vs Free-air temperature 10 Receiver vs Free-air temperature 33 Driver vs Free-air temperature 11 Receiver vs Free-air temperature 34 Driver vs Free-air temperature 12 Receiver vs Free-air temperature 35 Driver vs Frequency 13 Receiver vs Frequency 36 Driver-to-receiver crosstalk vs Frequency 14 Receiver-to-driver crosstalk vs Frequency 37 Driver vs Free-air temperature 15 Receiver vs Free-air temperature 38 Driver vs Free-air temperature 16 Power supply rejection ratio Supply current Normalized frequency response Receiver vs Free-air temperature Driver vs Frequency 39 17, 18 Receiver vs Frequency 40, 41 Normalized output response Driver vs Frequency 19 − 22 Single-ended output distortion Driver vs Output voltage Output distortion Receiver vs Output voltage Small and large signal frequency response Receiver Driver Differential gain Receiver Driver Differential phase Receiver Output step response 23 42 43, 44 DC input offset voltage 24, 25 Number of 150-Ω loads 26, 27 DC input offset voltage 45, 46 Number of 150-Ω loads 47, 48 DC input offset voltage 24, 25 Number of 150-Ω loads 26, 27 DC input offset voltage 45, 46 Number of 150-Ω loads 47, 48 Driver 28 − 30 Receiver 49 − 51 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS DRIVER AND RECEIVER DRIVER AND RECEIVER SUPPLY CURRENT vs SUPPLY VOLTAGE INPUT VOLTAGE AND CURRENT NOISE vs FREQUENCY 12 100 100 11 I CC − Supply Current − mA Vn − Voltage Noise − nV/ Hz Driver 10 9 8 7 6 5 Receiver 4 3 10 In+ Noise TA = 25°C RF = 1 kΩ Gain = +1 2 1 0 In− Noise 5 6 7 Vn Noise 8 9 10 11 12 13 14 1 10 15 100 ± VCC − Supply Voltage − V 1k f − Frequency − Hz Figure 5 Figure 6 DRIVER AND RECEIVER CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY Closed-Loop Output Impedance − Ω 200 100 10 VCC = ±15 V RF = 1 kΩ Gain = 2 TA = 25°C VI(PP) = 1 V Receiver 1 Driver 0.1 1 kΩ − + 0.01 VO 1 kΩ 1 kΩ 50 Ω VI THS6002 1000 VI Zo = −1 VO ( 0.001 100k 1M 10M f − Frequency − Hz 100M Figure 7 10 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ) 500M 10k 1 100k I n − Current Noise − pA/ Hz VCC = ±15 V TA = 25°C 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 DRIVER DRIVER PEAK-TO-PEAK OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE PEAK-TO-PEAK OUTPUT VOLTAGE vs LOAD RESISTANCE 15 15 VO(PP) − Peak-to-Peak Output Voltage − V VO(PP) − Peak-to-Peak Output Voltage Swing − V TYPICAL CHARACTERISTICS 10 5 0 −5 TA = 25°C RF = 1 kΩ RL = 25 Ω Gain = 1 −10 −15 5 6 7 8 9 10 11 12 13 14 VCC = ±15 V 10 VCC = ±5 V 5 TA = 25°C RF = 1 kΩ Gain = 1 0 VCC = ±5 V −5 −10 VCC = ±15 V −15 10 15 100 Figure 8 Figure 9 DRIVER DRIVER INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE 2 5 VCC = ±15 V IIB+ G=1 RF = 1 kΩ
   G=1 RF = 1 kΩ 4 I IB − Input Bias Current − µ A VIO − Input Offset Voltage − mV 1 1000 RL − Load Resistance − Ω VCC − Supply Voltage − V VCC = ±5 V 0 −1 −2 VCC = ±15 V −3 VCC = ±5 V IIB+ 3 2 VCC = ±5 V IIB− 1 −4 −5 −40 −20 0 20 40 60 80 100 0 −40 −20 TA − Free-Air Temperature − °C 0 20 VCC = ±15 V IIB− 40 60 80 100 TA − Free-Air Temperature − °C Figure 10 Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 DRIVER DRIVER COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE INPUT-TO-OUTPUT CROSSTALK vs FREQUENCY 0 80 −10 Input-to-Output Crosstalk − dB CMRR − Common-Mode Rejection Ratio − dB TYPICAL CHARACTERISTICS 75 VCC = ±15 V 70 VCC = ±5 V 1 kΩ 65 1 kΩ − + VI 1 kΩ 60 −40 −20 VO −30 −40 Driver 1 = Output Driver 2 = Input −50 −60 −70 Driver 1 = Input Driver 2 = Output −80 1 kΩ 0 −20 VCC = ±15 V RF = 1 kΩ RL = 25 Ω Gain = 2 VI = 200 mV See Figure 1 20 40 60 −90 100k 80 1M TA − Free-Air Temperature − °C Figure 12 10M f − Frequency − Hz 100M 500M Figure 13 DRIVER DRIVER-TO-RECEIVER CROSSTALK vs FREQUENCY Driver-to-Receiver Crosstalk − dB −10 −20 95 VCC = ±15 V RF = 1 kΩ Gain = 2 VI = 200 mV See Figures 1 and 2 PSRR − Power Supply Rejection Ratio − dB 0 POWER SUPPLY REJECTION RATIO vs FREE-AIR TEMPERATURE −30 −40 Receiver 2 = Output Driver 2 = Input Receiver 1 = Output Driver 1 = Input −50 −60 Receiver 1 = Output Driver 2 = Input −70 −80 −90 100k Receiver 2 = Output Driver 1 = Input 1M 10M f − Frequency − Hz 100M 500M G=1 RF = 1 kΩ 90 85 VCC = 15 V 80 VCC = 5 V 75 VCC = −5 V VCC = −15 V 70 65 −40 −20 Figure 14 12 0 20 Figure 15 POST OFFICE BOX 655303 40 60 TA − Free-Air Temperature − °C • DALLAS, TEXAS 75265 80 100 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS DRIVER DRIVER SUPPLY CURRENT vs FREE-AIR TEMPERATURE NORMALIZED FREQUENCY RESPONSE vs FREQUENCY 2 13 Normalized Frequency Response − dB VCC = ±15 V I CC − Supply Current − mA 12 VCC = ±5 V 10 8 6 4 2 0 −1 −20 0 20 40 60 80 RF = 750 Ω −3 RF = 1 kΩ −4 −5 −6 −8 100 100 RF = 510 Ω −2 −7 0 −40 RF = 300 Ω 1 VCC = ±15 V VI = 200 mV RL = 25 Ω Gain = 1 TA = 25°C 1M TA − Free-Air Temperature − °C Figure 16 DRIVER NORMALIZED OUTPUT RESPONSE vs FREQUENCY RL = 200 Ω 0 Normalized Output Response − dB Normalized Frequency Response − dB 1 RF = 360 Ω 0 −1 −2 −3 RF = 470 Ω −4 −5 RF = 620 Ω −6 −9 500M Figure 17 DRIVER 1 −8 100M NORMALIZED FREQUENCY RESPONSE vs FREQUENCY 2 −7 10M f − Frequency − Hz VCC = ±15 V Vin = 200 mV RL = 25 Ω Gain = 2 TA = 25°C −10 100K 1M −2 100M 500M RL = 100 Ω −3 RL = 50 Ω −4 RL = 25 Ω −5 −6 −7 −8 RF = 1 kΩ 10M −1 VCC = ±15 V RF = 1 kΩ Gain = 1 VI = 200 mV −9 100k f − Frequency − Hz Figure 18 1M 10M f − Frequency − Hz 100M 500M Figure 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 DRIVER DRIVER NORMALIZED OUTPUT RESPONSE vs FREQUENCY NORMALIZED OUTPUT RESPONSE vs FREQUENCY 1 3 0 2 Normalized Output Response − dB Normalized Output Response − dB TYPICAL CHARACTERISTICS −1 −2 −3 −4 RL = 25 Ω −5 RL = 200 Ω RL = 100 Ω −6 −7 −8 RL = 50 Ω VCC = ±15 V RF = 1 kΩ Gain = 2 VI = 200 mV −9 100k RF = 620 Ω RF = 820 Ω 1 0 −1 RF = 1 kΩ −2 −3 −4 VCC = ±15 V RL = 100 Ω Gain = 1 VI = 200 mV −5 −6 1M 10M f − Frequency − Hz 100M −7 100k 500M 1M Figure 20 DRIVER DRIVER NORMALIZED OUTPUT RESPONSE vs FREQUENCY SINGLE-ENDED OUTPUT DISTORTION vs OUTPUT VOLTAGE 0 RF = 430 Ω 1 0 −1 −2 RF = 620 Ω −3 RF = 1 kΩ VCC = ±15 V RL = 100 Ω Gain = 2 VI = 200 mV −6 100k −20 −30 −40 −50 2nd Harmonic −60 −70 3rd Harmonic −80 −90 1M 10M f − Frequency − Hz 100M 500M 0 Figure 22 14 500M VCC = ±15 V RF = 4 kΩ RL = 25 Ω f = 1 MHz Gain = 5 −10 Single-Ended Output Distortion − dB Normalized Output Response − dB 2 −5 100M Figure 21 3 −4 10M f − Frequency − Hz 5 10 15 VO(PP) − Output Voltage − V Figure 23 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 20 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS DRIVER DIFFERENTIAL GAIN AND PHASE vs DC INPUT OFFSET VOLTAGE Differential Gain − % 0.04 0.10 VCC = ±15 V RL = 150 Ω RF = 1 kΩ f = 3.58 MHz Gain = 2 40 IRE Modulation Gain 0.08 Phase 0.03 0.06 0.02 0.04 0.01 0.02 0 −0.7 −0.5 −0.3 −0.1 0.1 0.3 0.5 Differential Phase − ° 0.05 0 0.7 DC Input Offset Voltage − V Figure 24 DRIVER DIFFERENTIAL GAIN AND PHASE vs DC INPUT OFFSET VOLTAGE Differential Gain − % 0.04 0.10 VCC = ±5 V RL = 150 Ω RF = 1 kΩ f = 3.58 MHz Gain = 2 40 IRE Modulation 0.08 0.03 0.06 Gain 0.04 0.02 Differential Phase − ° 0.05 Phase 0.02 0.01 0 −0.7 −0.5 −0.3 −0.1 0.1 0.3 0.5 0 0.7 DC Input Offset Voltage − V Figure 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS DRIVER DIFFERENTIAL GAIN AND PHASE vs NUMBER OF 150-Ω LOADS 0.12 Differential Gain − % 0.25 VCC = ±15 V RF = 1 kΩ Gain = 2 f = 3.58 MHz 40 IRE Modulation 100 IRE Ramp 0.20 0.09 0.15 Phase 0.10 0.06 Differential Phase − ° 0.15 Gain 0.05 0.03 0 0 1 2 3 4 5 6 7 8 Number of 150-Ω Loads Figure 26 DRIVER DIFFERENTIAL GAIN AND PHASE vs NUMBER OF 150-Ω LOADS 0.12 Differential Gain − % 0.25 VCC = ±5 V RF = 1 kΩ Gain = 2 f = 3.58 MHz 40 IRE Modulation 100 IRE Ramp 0.20 0.09 0.15 0.10 0.06 Gain 0.05 0.03 Phase 0 0 1 2 3 4 5 6 7 Number of 150-Ω Loads Figure 27 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8 Differential Phase − ° 0.15 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS DRIVER OUTPUT 10 V STEP RESPONSE 8 300 6 200 4 VO − Output Voltage − V 400 100 0 −100 VCC = ±15 V Gain = 2 RL = 25 Ω RF = 1 kΩ tr/tf= 300 ps See Figure 3 −200 −300 2 0 −2 VCC = ±15 V Gain = 2 RL = 25 Ω RF = 1 kΩ tr/tf= 5 ns See Figure 3 −4 −6 −8 −400 0 50 0 100 150 200 250 300 350 400 450 500 50 100 150 200 250 300 350 400 450 500 t − Time − ns t − Time − ns Figure 28 Figure 29 DRIVER OUTPUT 20 V STEP RESPONSE 16 VCC = ±15 V Gain = 5 RL = 25 Ω RF = 2 kΩ tr/tf= 5 ns See Figure 3 12 VO − Output Voltage − V VO − Output Voltage − mV DRIVER OUTPUT 400 mV STEP RESPONSE 8 4 0 −4 −8 −12 −16 0 50 100 150 200 250 300 350 400 450 500 t − Time − ns Figure 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS RECEIVER RECEIVER PEAK-TO-PEAK OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE PEAK-TO-PEAK OUTPUT VOLTAGE vs LOAD RESISTANCE 15 VO(PP) − Peak-to-Peak Output Voltage − V VO(PP) − Peak-to-Peak Output Voltage Swing − V 15 10 5 0 −5 TA = 25°C RF = 1 kΩ RL = 150 Ω Gain = 1 −10 −15 5 6 7 8 9 10 11 12 13 14 10 TA = 25°C RF = 1 kΩ Gain = 1 VCC = ±15 V VCC = ±5 V 5 0 VCC = ±5 V −5 −10 VCC = ±15 V −15 10 15 100 Figure 31 Figure 32 RECEIVER RECEIVER INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE 0.5 5 G=1 RF = 1 kΩ 0 4 I IB − Input Bias Current − µ A VIO − Input Offset Voltage − mV G=1 RF = 1 kΩ VCC = ±5 V −0.5 −1 VCC = ±15 V −1.5 −2 −40 −20 0 20 40 60 80 100 VCC = ±15 V IIB+ 3 VCC = ±5 V IIB+ 2 1 0 −40 VCC = ±15 V IIB− VCC = ±5 V IIB− −20 TA − Free-Air Temperature − °C 0 20 Figure 34 POST OFFICE BOX 655303 40 60 TA − Free-Air Temperature − °C Figure 33 18 1000 RL − Load Resistance − Ω VCC − Supply Voltage − V • DALLAS, TEXAS 75265 80 100 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 RECEIVER RECEIVER COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE INPUT-TO-OUTPUT CROSSTALK vs FREQUENCY 85 0 −10 80 Input-to-Output Crosstalk − dB CMRR − Common-Mode Rejection Ratio − dB TYPICAL CHARACTERISTICS VCC = ±15 V 75 70 VCC = ±5 V 65 1 kΩ 1 kΩ − + VI 60 1 kΩ 55 −40 −20 VO 1 kΩ 0 −20 −30 VCC = ±15 V RF = 1 kΩ RL = 150 Ω Gain = 2 VI = 200 mV
   Receiver 1 = Output Receiver 2 = Input −40 −50 −60 −70 Receiver 1 = Input Receiver 2 = Output −80 20 40 60 80 −90 100k 100 1M TA − Free-Air Temperature − °C Figure 35 10M f − Frequency − Hz 100M 500M Figure 36 RECEIVER POWER SUPPLY REJECTION RATIO vs FREE-AIR TEMPERATURE RECEIVER-TO-DRIVER CROSSTALK vs FREQUENCY Receiver-to-Driver Crosstalk − dB −10 95 VCC = ±15 V RF = 1 kΩ Gain = 2 PSRR − Power Supply Rejection Ratio − dB 0 −20 −30 Receiver 2 = Input Driver 2 = Output −40 Receiver 1 = Input Driver 1 = Output −50 −60 Receiver 1 = Input Driver 2 = Output −70 −80 −90 100k Receiver 2 = Input Driver 1 = Output 1M 10M f − Frequency − Hz 100M 500M G=1 RF = 1 kΩ 90 85 VCC = 15 V 80 VCC = 5 V VCC = −15 V 75 VCC = −5 V 70 65 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C Figure 37 Figure 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS RECEIVER RECEIVER SUPPLY CURRENT vs FREE-AIR TEMPERATURE NORMALIZED OUTPUT RESPONSE vs FREQUENCY 7 3 Normalized Output Response − dB 6 I CC − Supply Current − mA VCC = ±15 V RL = 150 Ω Gain = 1 VI = 200 mV 2 VCC = ±15 V 5 4 VCC = ±5 V 3 2 1 1 RF = 360 Ω 0 −1 RF = 510 Ω −2 −3 RF = 750 Ω −4 RF = 1 kΩ −5 −6 0 −40 −20 0 20 40 60 80 −7 100k 100 1M TA − Free-Air Temperature − °C RECEIVER RECEIVER NORMALIZED OUTPUT RESPONSE vs FREQUENCY OUTPUT DISTORTION vs OUTPUT VOLTAGE 1 0 0 −10 −1 −20 −2 RF = 360 Ω −3 RF = 510 Ω −4 RF = 620 Ω −5 RF = 1 kΩ −6 −7 −8 VCC = ±15 V RL = 150 Ω Gain = 2 VI = 200 mV −9 100k 500M VCC = ±15 V RF = 510 Ω RL = 150 Ω f = 1 MHz Gain = 5 −30 −40 −50 −60 2nd Harmonic −70 −80 3rd Harmonic −90 −100 1M 10M f − Frequency − Hz 100M 500M 0 Figure 41 20 100M Figure 40 Output Distortion − dB Normalized Output Response − dB Figure 39 10M f − Frequency − Hz 5 10 15 VO(PP) − Output Voltage − V Figure 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 20 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS RECEIVER RECEIVER SMALL AND LARGE SIGNAL FREQUENCY RESPONSE SMALL AND LARGE SIGNAL FREQUENCY RESPONSE 3 −3 VI = 500 mV VI = 500 mV 0 −6 −3 Output Level − dBV VI = 250 mV −12 −15 VI = 125 mV −18 −21 VI = 250 mV −6 −9 VI = 125 mV −12 −15 VI = 62.5 mV −27 −18 VCC = ±15 V RF = 510 Ω RL = 150 Ω Gain = 1 −30 100k 1M −21 10M f − Frequency − Hz 100M VI = 62.5 mV VCC = ±15 V RF = 390 Ω RL = 150 Ω Gain = 2 −24 100k 500M 1M Figure 43 10M f − Frequency − Hz 100M 500M Figure 44 RECEIVER DIFFERENTIAL GAIN AND PHASE vs DC INPUT OFFSET VOLTAGE 0.10 0.20 VCC = ±15 V RL = 150 Ω RF = 1 kΩ f = 3.58 MHz Gain = 2 40 IRE Modulation 0.09 0.08 0.07 Gain 0.18 0.16 0.14 Phase 0.06 0.12 0.05 0.10 0.04 0.08 0.03 0.06 0.02 0.04 0.01 0.02 0 −0.7 −0.5 −0.3 −0.1 0.1 0.3 0.5 Differential Phase − ° −24 Differential Gain − % Output Level − dBV −9 0 0.7 DC Input Offset Voltage − V Figure 45 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS RECEIVER DIFFERENTIAL GAIN AND PHASE vs DC INPUT OFFSET VOLTAGE 0.10 0.20 VCC = ±5 V RL = 150 Ω RF = 1 kΩ f = 3.58 MHz Gain = 2 40 IRE Modulation Differential Gain − % 0.08 0.07 0.18 0.16 0.14 0.06 0.12 Gain 0.05 0.10 0.04 0.08 0.03 0.06 0.02 0.04 Differential Phase − ° 0.09 0.02 0.01 Phase 0 −0.7 −0.5 −0.3 −0.1 0.1 0.3 0.5 0 0.7 DC Input Offset Voltage − V Figure 46 RECEIVER DIFFERENTIAL GAIN AND PHASE vs NUMBER OF 150-Ω LOADS 0.40 0.35 Differential Gain − % 0.25 VCC = ±15 V RF = 1 kΩ Gain = 2 f = 3.58 MHz 40 IRE Modulation 100 IRE Ramp 0.30 0.20 0.15 Gain 0.25 Phase 0.20 0.10 0.15 0.10 0.05 0.05 0 0 1 2 3 4 5 6 7 Number of 150-Ω Loads Figure 47 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8 Differential Phase − ° 0.45 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS RECEIVER DIFFERENTIAL GAIN AND PHASE vs NUMBER OF 150-Ω LOADS 0.40 0.35 Differential Gain − % 0.25 VCC = ±5 V RF = 1 kΩ Gain = 2 f = 3.58 MHz 40 IRE Modulation 100 IRE Ramp 0.30 0.20 0.15 0.25 Phase 0.20 0.10 0.15 Differential Phase − ° 0.45 Gain 0.10 0.05 0.05 0 0 1 2 3 4 5 6 7 8 Number of 150-Ω Loads Figure 48 RECEIVER OUTPUT 10-V STEP RESPONSE 400 9 300 7 200 5 VO − Output Voltage − V VO − Output Voltage − mV RECEIVER OUTPUT 400-mV STEP RESPONSE 100 0 −100 Gain = +2 RL = 150 Ω RF = 1 kΩ tr/tf= 300 ps See Figure 4 −200 −300 3 1 −1 Gain = +2 RL = 150 Ω RF = 1 kΩ tr/tf= 5 ns See Figure 4 −3 −5 −7 −400 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 t − Time − ns t − Time − ns Figure 50 Figure 49 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 TYPICAL CHARACTERISTICS RECEIVER OUTPUT 20 V STEP RESPONSE 16 VCC = ±15 V Gain = 5 RL = 150 Ω RF = 2 kΩ tr/tf= 5 ns See Figure 4 VO − Output Voltage − V 12 8 4 0 −4 −8 −12 −16 0 50 100 150 200 250 300 350 400 450 500 t − Time − ns Figure 51 APPLICATION INFORMATION The THS6002 contains four independent operational amplifiers. Two are designated as drivers because of their high output current capability, and two are designated as receivers. The receiver amplifiers are current feedback topology amplifiers made for high-speed operation and are capable of driving output loads of at least 80 mA. The drivers are also current feedback topology amplifiers. However, the drivers have been specifically designed to deliver the full power requirements of ADSL and therefore can deliver output currents of at least 400 mA at full output voltage. The THS6002 is fabricated using Texas Instruments 30-V complementary bipolar process, HVBiCOM. This process provides excellent isolation and high slew rates that result in the device’s excellent crosstalk and extremely low distortion. independent power supplies Each amplifier of the THS6002 has its own power supply pins. This was specifically done to solve a problem that often occurs when multiple devices in the same package share common power pins. This problem is crosstalk between the individual devices caused by currents flowing in common connections. Whenever the current required by one device flows through a common connection shared with another device, this current, in conjunction with the impedance in the shared line, produces an unwanted voltage on the power supply. Proper power supply decoupling and good device power supply rejection helps to reduce this unwanted signal. What is left is crosstalk. However, with independent power supply pins for each device, the effects of crosstalk through common impedance in the power supplies is more easily managed. This is because it is much easier to achieve low common impedance on the PCB with copper etch than it is to achieve low impedance within the package with either bond wires or metal traces on silicon. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION power supply restrictions Although the THS6002 is specified for operation from power supplies of ± 5 V to ±15 V (or singled-ended power supply operation from 10 V to 30 V), and each amplifier has its own power supply pins, several precautions must be taken to assure proper operation. 1. The power supplies for each amplifier must be the same value. For example, if the drivers use ±15 volts, then the receivers must also use ±15 volts. Using ±15 volts for one amplifier and ±5 volts for another amplifier is not allowed. 2. To save power by powering down some of the amplifiers in the package, the following rules must be followed. • • • The amplifier designated Receiver 1 must always receive power whenever any other amplifier(s) within the package is used. This is because the internal startup circuitry uses the power from the Receiver 1 device. The −VCC pins from all four devices must always be at the same potential. Individual amplifiers are powered down by simply opening the +VCC connection. As an example, if only the two drivers within the THS6002 are used, then the package power is reduced by removing the +VCC connection to Receiver 2. This reduces the power consumption by an amount equal to the quiescent power of a single receiver amplifier. The +VCC connections to Receiver 1 and both drivers are required. Also, all four amplifiers must be connected to −VCC, including Receiver 2. The THS6002 incorporates a standard Class A-B output stage. This means that some of the quiescent current is directed to the load as the load current increases. So under heavy load conditions, accurate power dissipation calculations are best achieved through actual measurements. For small loads, however, internal power dissipation for each amplifier in the THS6002 can be approximated by the following formula: P D ǒ ≅ 2V CC I Ǔ ) ǒVCC _ VOǓ CC ǒ Ǔ V O R L Where: PD VCC ICC VO RL = power dissipation for one amplifier = split supply voltage = supply current for that particular amplifier = output voltage of amplifier = load resistance To find the total THS6002 power dissipation, we simply sum up all four amplifier power dissipation results. Generally, the worst case power dissipation occurs when the output voltage is one-half the VCC voltage. One last note, which is often overlooked: the feedback resistor (RF) is also a load to the output of the amplifier and should be taken into account for low value feedback resistors. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION device protection features The THS6002 has two built-in protection features that protect the device against improper operation. The first protection mechanism is output current limiting. Should the output become shorted to ground the output current is automatically limited to the value given in the data sheet. While this protects the output against excessive current, the device internal power dissipation increases due to the high current and large voltage drop across the output transistors. Continuous output shorts are not recommended and could damage the device. Additionally, connection of the amplifier output to one of the supply rails (±VCC) can cause failure of the device and is not recommended. The second built-in protection feature is thermal shutdown. Should the internal junction temperature rise above approximately 180_C, the device automatically shuts down. Such a condition could exist with improper heat sinking or if the output is shorted to ground. When the abnormal condition is fixed, the internal thermal shutdown circuit automatically turns the device back on. thermal information The THS6002 is packaged in a thermally-enhanced DWP package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 52(a) and Figure 52(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 52(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. This is discussed in more detail in the PCB design considerations section of this document. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 52. Views of Thermally Enhanced DWP Package 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION recommended feedback and gain resistor values As with all current feedback amplifiers, the bandwidth of the THS6002 is an inversely proportional function of the value of the feedback resistor. This can be seen from Figures 17 and 18. For the driver, the recommended resistors for the optimum frequency response for a 25-Ω load system are 680-Ω for a gain = 1 and 620-Ω for a gain = 2 or −1. For the receivers, the recommended resistors for the optimum frequency response are 560 Ω for a gain = 1 and 390 Ω for a gain = 2 or −1. These should be used as a starting point and once optimum values are found, 1% tolerance resistors should be used to maintain frequency response characteristics. Because there is a finite amount of output resistance of the operational amplifier, load resistance can play a major part in frequency response. This is especially true with the drivers, which tend to drive low-impedance loads. This can be seen in Figure 7, Figure 19, and Figure 20. As the load resistance increases, the output resistance of the amplifier becomes less dominant at high frequencies. To compensate for this, the feedback resistor should change. For 100-Ω loads, it is recommended that the feedback resistor be changed to 820 Ω for a gain of 1 and 560 Ω for a gain of 2 or −1. Although, for most applications, a feedback resistor value of 1 kΩ is recommended, which is a good compromise between bandwidth and phase margin that yields a very stable amplifier. Consistent with current feedback amplifiers, increasing the gain is best accomplished by changing the gain resistor, not the feedback resistor. This is because the bandwidth of the amplifier is dominated by the feedback resistor value and internal dominant-pole capacitor. The ability to control the amplifier gain independently of the bandwidth constitutes a major advantage of current feedback amplifiers over conventional voltage feedback amplifiers. Therefore, once a frequency response is found suitable to a particular application, adjust the value of the gain resistor to increase or decrease the overall amplifier gain. Finally, it is important to realize the effects of the feedback resistance on distortion. Increasing the resistance decreases the loop gain and increases the distortion. It is also important to know that decreasing load impedance increases total harmonic distortion (THD). Typically, the third order harmonic distortion increases more than the second order harmonic distortion. offset voltage The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF RG IIB− − RS IIB+ + + VOS − V VIO OS ǒ + "V IO "I IB) R Ǔ S ǒ 1) R R F G Ǔ "I IB* R F Figure 53. Output Offset Voltage Model POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION noise calculations and noise figure Noise can cause errors on very small signals. This is especially true for the receiver amplifiers which are generally used for amplifying small signals coming over a transmission line. The noise model for current feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only difference between the two is that the CFB amplifiers generally specify different current noise parameters for each input while VFB amplifiers usually only specify one noise current parameter. The noise model is shown in Figure 54. This model includes all of the noise sources as follows: • • • • en = amplifier internal voltage noise (nV/√Hz) IN+ = noninverting current noise (pA/√Hz) IN− = inverting current noise (pA/√Hz) eRx = thermal voltage noise associated with each resistor (eRx = 4 kTRx ) eRs RS en Noiseless + _ eni IN+ eno eRf RF eRg IN− RG Figure 54. Noise Model The total equivalent input noise density (eni) is calculated by using the following equation: e ni + Ǹǒ ǒ 2 e nǓ ) IN ) R Ǔ S 2 ǒ ) IN– ǒRF ø RGǓǓ 2 ǒ Ǔ ) 4 kTR s ) 4 kT R ø R F G Where: k = Boltzmann’s constant = 1.380658 × 10−23 T = temperature in degrees Kelvin (273 +°C) RF || RG = parallel resistance of RF and RG To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the overall amplifier gain (AV). e no + e 28 ǒ Ǔ R A + e ni 1 ) F (Noninverting Case) ni V RG POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION noise calculations and noise figure (continued) As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel resistance term. This leads to the general conclusion that the most dominant noise sources are the source resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and make noise calculations much easier to calculate. This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is typically 50 Ω in RF applications. ȱ ȧ Ȳ ȳ ȧ ȴ e 2 NF + 10log e ni Rs Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage, we can approximate noise figure as: NF + ȱ ȡǒ Ǔ2 ǒ ȧ en ) IN ) ȧ Ȣ ȧ 10logȧ1 ) 4 kTR ȧ S ȧ Ȳ ȣȳ Ǔ S ȧ 2 R Ȥȧ ȧ ȧ ȧ ȧ ȴ The Figure 55 shows the noise figure graph for the THS6002. NOISE FIGURE vs SOURCE RESISTANCE 20 18 TA = 25°C Noise Figure − dB 16 14 12 10 8 6 4 2 0 10 100 1k 10k Rs − Source Resistance − Ω Figure 55. Noise Figure vs. Source Resistance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION PCB design considerations Proper PCB design techniques in two areas are important to assure proper operation of the THS6002. These areas are high-speed layout techniques and thermal-management techniques. Because the THS6002 is a high-speed part, the following guidelines are recommended. D Ground plane − It is essential that a ground plane be used on the board to provide all components with a low inductive ground connection. Although a ground connection directly to a terminal of the THS6002 is not necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves two functions. It provides a low inductive ground to the device substrate to minimize internal crosstalk and it provides the path for heat removal. D Input stray capacitance − To minimize potential problems with amplifier oscillation, the capacitance at the inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input must be as short as possible, the ground plane must be removed under any etch runs connected to the inverting input, and external components should be placed as close as possible to the inverting input. This is especially true in the noninverting configuration. An example of this can be seen in Figure 56, which shows what happens when 1.8 pF is added to the inverting input terminal in the noninverting configuration. The bandwidth increases dramatically at the expense of peaking. This is because some of the error current is flowing through the stray capacitor instead of the inverting node of the amplifier. Although, in the inverting mode, stray capacitance at the inverting input has little effect. This is because the inverting node is at a virtual ground and the voltage does not fluctuate nearly as much as in the noninverting configuration. DRIVER NORMALIZED FREQUENCY RESPONSE vs FREQUENCY Normalized Frequency Response − dB 3 2 1 VCC = ±15 V VI = 200 mV RL = 25 Ω RF = 1 kΩ Gain = 1 0 CI = 0 pF (Stray C Only) −1 −2 CI = 1.8 pF 1 kΩ −3 −4 Cin Vin −5 −6 −7 100 Vout − + 50 Ω RL = 25 Ω 1M 10M 100M 500M f − Frequency − Hz Figure 56. Driver Normalized Frequency Response vs. Frequency 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
          SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION PCB design considerations (continued) D Proper power supply decoupling − Use a minimum of a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches (2,54 mm) between the device power terminal and the ceramic capacitors. Because of its power dissipation, proper thermal management of the THS6002 is required. Although there are many ways to properly heatsink this device, the following steps illustrate one recommended approach for a multilayer PCB with an internal ground plane. 1. Prepare the PCB with a top side etch pattern as shown in Figure 57. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. These holes should be 13 mils (0,33 mm) in diameter. They are kept small so that solder wicking through the holes is not a problem during reflow. 3. Place four more holes under the package, but outside the thermal pad area. These holes are 25 mils (0,635 mm) in diameter. They may be larger because they are not in the area to be soldered so that wicking is not a problem. 4. Connect all nine holes, the five within the thermal pad area and the four outside the pad area, to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS6002 package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated through hole. 6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area with its five holes. The four larger holes outside the thermal pad area, but still under the package, should be covered with solder mask. 7. Apply solder paste to the exposed thermal pad area and all of the operational amplifier terminals. 8. With these preparatory steps in place, the THS6002 is simply placed in position and run through the solder reflow operation as any standard surface mount component. This results in a part that is properly installed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION PCB design considerations (continued) Additional 4 vias outside of thermal pad area but under the package Via diameter = 25 mils (0,635 mm)) Thermal pad area (150 mils x 170 mils) (3,81 mm x 4,32 mm) with 5 vias Via diameter = 13 mils(0,33 mm) Figure 57. PowerPad PCB Etch and Via Pattern The actual thermal performance achieved with the THS6002 in its PowerPAD package depends on the application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3 inches (76,2 mm x 76,2 mm), then the expected thermal coefficient, θJA, is about 21.5_C/W. For a given θJA, the maximum power dissipation is shown in Figure 58 and is calculated by the following formula: P D + ǒ T Ǔ –T MAX A q JA Where: PD = Maximum power dissipation of THS6002 (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case (0.37°C/W) θCA = Thermal coefficient from case to ambient More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION PCB design considerations (continued) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 9 Tj = 150°C PCB Size = 3” x 3” (76,2 mm x 76,2 mm) No Air Flow Maximum Power Dissipation − W 8 7 θJA = 21.5°C/W 2 oz Trace and Copper Pad with Solder 6 5 4 3 2 θJA = 43.9°C/W 2 oz Trace and Copper Pad without Solder 1 0 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C Figure 58. Maximum Power Dissipation vs Free-Air Temperature POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION ADSL The THS6002 was primarily designed as a line driver and line receiver for ADSL (asymmetrical digital subscriber line). The driver output stage has been sized to provide full ADSL power levels of 20 dBm onto the telephone lines. Although actual driver output peak voltages and currents vary with each particular ADSL application, the THS6002 is specified for a minimum full output current of 400 mA at its full output voltage of approximately 12 V. This performance meets the demanding needs of ADSL at the central office end of the telephone line. A typical ADSL schematic is shown in Figure 59. 15 V THS6002 Driver 1 VI+ 0.1 µF + 6.8 µF 12.5 Ω + _ 1:2 1 kΩ 100 Ω To Telephone Line 1 kΩ 0.1 µF 6.8 µF + −15 V 1 kΩ 15 V THS6002 Driver 2 VI− 15 V 0.1 µF + 2 kΩ 6.8 µF 0.1 µF 12.5 Ω + _ 1 kΩ − + 1 kΩ THS6002 Receiver 1 VO+ −15 V 1 kΩ 0.1 µF 1 kΩ 6.8 µF + 15 V −15 V 2 kΩ 0.1 µF 1 kΩ − + VO− THS6002 Receiver 2 0.01 µF −15 V Figure 59. THS6002 ADSL Application 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION ADSL (continued) The ADSL transmit band consists of 255 separate carrier frequencies each with its own modulation and amplitude level. With such an implementation, it is imperative that signals put onto the telephone line have as low a distortion as possible. This is because any distortion either interferes directly with other ADSL carrier frequencies or it creates intermodulation products that interfere with ADSL carrier frequencies. The THS6002 has been specifically designed for ultra low distortion by careful circuit implementation and by taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended distortion measurements are shown in Figure 23. It is commonly known that in the differential driver configuration, the second order harmonics tend to cancel out. Thus, the dominant total harmonic distortion (THD) will be primarily due to the third order harmonics. For this test, the load was 25 Ω and the output signal produced a 20 VO(PP) signal. Thus, the test was run at full signal and full load conditions. Because the feedback resistor used for the test was 4 kΩ, the distortion numbers are actually in a worst-case scenario. Distortion should be reduced as the feedback resistance drops. This is because the bandwidth of the amplifier increases dramatically, which allows the amplifier to react faster to any nonlinearities in the closed-loop system. Another significant point is the fact that distortion decreases as the impedance load increases. This is because the output resistance of the amplifier becomes less significant as compared to the output load resistance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION HDSL Shown in Figure 60 is an example of the THS6002 being used for HDSL-2 applications. The receiver amplifiers within the THS6002 have been configured as predrivers for the driver amplifiers. This dual composite amplifier setup has the effect of raising the open loop gain for the combination of both amplifiers, thereby giving improved distortion performance. 7.5 kΩ 1 kΩ 11 kΩ 12 V 12 V 6 Receiver 1 − 7 + 9 THS6002 4 + 5 2 30 Ω − 1:1.5 Driver 1 Output 27.4 VO(PP) −12 V −12 V 135 Ω 1 kΩ 511 Ω Input 3 V(PP) 1 kΩ 1 kΩ 7.5 kΩ 12 V 2 U2 − 1 + 6 1 kΩ 11 kΩ THS4001 12 V 12 V 15 −12 V Receiver 2 − 14 + 12 17 + 16 19 30 Ω − Driver 2 −12 V −12 V 1 kΩ 511 Ω Figure 60. HDSL-2 Line Driver general configurations A common error for the first-time CFB user is to create a unity gain buffer amplifier by shorting the output directly to the inverting input. A CFB amplifier in this configuration is now commonly referred to as an oscillator. The THS6002, like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors directly from the output to the inverting input is not recommended. This is because, at high frequencies, a capacitor has a very low impedance. This results in an unstable amplifier and should not be considered when using a current-feedback amplifier. Because of this, integrators and simple low-pass filters, which are easily implemented on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply place an RC-filter at the noninverting terminal of the operational-amplifier (see Figure 61). 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION general configurations (continued) RG RF ǒ V O + V I 1) R R F G Ǔǒ Ǔ 1 1 ) sR1C1 − VO + VI R1 f –3dB + 1 2pR1C1 C1 Figure 61. Single-Pole Low-Pass Filter If a multiple pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is because the filtering elements are not in the negative feedback loop and stability is not compromised. Because of their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize distortion. An example is shown in Figure 62. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f C2 RG = RF RG –3dB + ( 1 2pRC RF 1 2− Q ) Figure 62. 2-Pole Low-Pass Sallen-Key Filter There are two simple ways to create an integrator with a CFB amplifier. The first one shown in Figure 63 adds a resistor in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant and the feedback impedance never drops below the resistor value. The second one shown in Figure 64 uses positive feedback to create the integration. Caution is advised because oscillations can occur because of the positive feedback. C1 RF RG VI − + VO THS6002 S) 1 ȣ ȡ R C1 F O + ǒ FǓ ȧ V R ȧ S I G Ȣ Ȥ V R Figure 63. Inverting CFB Integrator POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 
    
           SLOS202E− JANUARY 1998− REVISED MARCH 2007 APPLICATION INFORMATION general configurations (continued) RG RF For Stable Operation: R2 R1 || RA − THS6002 R1 + R2 VO VO ≅ VI VI RA ( ≥ RF RG RF RG sR1C1 1+ ) C1 Figure 64. Non-Inverting CFB Integrator Another good use for the THS6002 driver amplifiers are as very good video distribution amplifiers. One characteristic of distribution amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the number of lines increases and the closed-loop gain increases. Be sure to use termination resistors throughout the distribution system to minimize reflections and capacitive loading. 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) THS6002CDWP ACTIVE SO PowerPAD DWP 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 THS6002C Samples THS6002IDWP ACTIVE SO PowerPAD DWP 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS6002I Samples THS6002IDWPR ACTIVE SO PowerPAD DWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS6002I Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of