THS6032CVFPR

THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER Check for Samples: THS6032 FEATURES 1 • 23 • • • • • • • Low-Power ADSL Line Driver Ideal for Central Office – 1.35-W Total Power Dissipation for Full-Rate ADSL Into a 25-Ω Load Low-Impedance Shutdown Mode – Allows Reception of Incoming Signal During Standby Two Modes of Operation – Class-G Mode: 4 Power Supplies, 1.35 W Power Dissipation – Class-AB Mode: 2 Power Supplies, 2 W Power Dissipation Low Distortion – THD = –62 dBc at f = 1 MHz, VO(PP) = 20 V, 25-Ω Load – THD = –69 dBc at f = 1 MHz, VO(PP) = 2 V, 25-Ω Load 400-mA Minimum Output Current Into a 25-Ω Load High-Speed: – 65-MHz Bandwidth (–3dB) , 25-Ω Load – 100-MHz Bandwidth (–3dB) , 100-Ω Load – 1200-V/μs Slew Rate Thermal Shutdown and Short-Circuit Protection Evaluation Module Available THERMALLY-ENHANCED SOIC (DWP) PowerPADä PACKAGE (TOP VIEW) PAD† VCCH− 1OUT VCCL− 1IN− 1IN+ NC SHDN1 SHDN2 PAD† 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 PAD† VCCH+ 2OUT VCCL+ 2IN− 2IN+ NC NC DGND PAD† NC − Not Connected This terminal is internally connected to the thermal pad. † MicroStar Juniorä (GQE) PACKAGE (TOP VIEW) VFP PACKAGE (TOP VIEW) Power PAD? HIGH-SPEED xDSL LINE DRIVER/RECEIVER FAMILY DEVICE DRIVER RECEIVER THS6002 • • THS6012 • THS6022 THS6032 5V ±5 V ±15 V • • 500-mA differential line driver and receiver • • 500-mA differential line driver • • • 250-mA differential line driver • • • 500-mA low-power ADSL central-office line driver • DESCRIPTION THS6062 • • • Low-noise ADSL receiver THS6072 • • • Low-power ADSL receiver THS7002 • • • Low-noise programmable-gain ADSL receiver 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD, MicroStar Junior are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2009, Texas Instruments Incorporated THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION The THS6032 is a low-power line driver ideal for asymmetrical digital subscriber line (ADSL) applications. This device contains two high-current, high-speed current-feedback drivers, which can be configured differentially for driving ADSL signals at the central office. The THS6032 features a unique class-G architecture to lower power consumption to 1.35 W. The THS6032 can also be operated in a traditional class-AB mode to reduce the number of power supplies to two. The class-G architecture supplies current to the load from four supplies. For low output voltages (typically –2.5 < VO < +2.5), some of the output current is supplied from the +VCC(L) and –VCC(L) supplies (typically ±5 V). For large output voltages (typically VO < –2.5 and VO > +2.5), the output current is supplied from +VCC(H) and –VCC(H) (typically ±15 V). This current sharing between VCC(L) and VCC(H) minimizes power dissipation within the THS6032 output stages for high crest factor ADSL signals. The THS6032 features a low-impedance shutdown mode, which allows the central office to receive incoming calls even after the device has been shut down. The THS6032 is available packaged in the patented PowerPAD ™ package. This package provides outstanding thermal characteristics in a small-footprint surface-mount package, which is fully compatible with automated surface-mount assembly procedures. It is also available in the new MicroStar Junior ™ BGA package. This package is only 25 mm2 in area, allowing for high-density PCB designs. Shutdown (SHDN1 and SHDN2) allows for powering down the internal circuitry for power conservation or for multiplexing. Separate shutdown controls are available for each channel on the THS6032. The control levels are TTL compatible. When turned off, each driver output is placed in a low impedance state which is determined by the voltage at DGND. This virtual ground at the outputs allows proper termination of a transmission line. AVAILABLE OPTIONS (1) PACKAGED DEVICES TA PowerPAD PLASTIC SMALL OUTLINE (2) (DWP) PowerPAD PLASTIC MSOP (3) (GQE) PowerPAD TQFP (VFP) EVALUATION MODULES 0°C to +70°C THS6032CDWP THS6032CGQER THS6032CVFP THS6032 EVM (DWP package) THS6032GQE EVM (GQE package) –40°C to +85°C THS6032IDWP THS6032IGQER THS6032IVFP — (1) (2) (3) 2 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. The DWP packages are available taped and reeled. Add an R suffix to the device type (for example, THS6032CDWPR). The GQE packages are only available taped and reeled. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). VALUE UNIT 33 V VCC(L) and VCC(H) Supply voltage (2) VI Input voltage IO Output current (3) 800 mA VID Differential input voltage ±4 V ±VCCH Total power dissipation at (or below) 25°C free-air temperature TJ Operating free-air temperature Tstg Storage temperature (2) (3) See Dissipation Ratings Table Maximum junction temperature TA (1) (3) +150 °C 0 to +70 °C –40 to +85 °C –65 to +150 °C C-suffix I-suffix Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. VCC(L) must always be less than or equal to VCC(H). The THS6032 incorporates a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a thermally-dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See the Thermal Information section for more information about using the PowerPAD thermally-enhanced packages. DISSIPATION RATINGS (1) (1) PACKAGE θJA (°C/W) θJC (°C/W) TA = +25°C POWER RATING DWP 21.5 0.37 5.8 W GQE 37.8 4.56 3.3 W VFP 30 1.2 4.1 W This data was taken using 2 oz. trace and copper pad that is soldered directly to a JEDEC standard 4 layer 3 in × 3 in PCB. RECOMMENDED OPERATING CONDITIONS VCC(L) – Class G mode Supply voltage VCC(L) – Class AB mode VCC(H) TA Operating free-air temperature C-suffix I-suffix MIN NOM MAX ±3 ±5 ±VCCH 0 0 0 ±5 ±15 ±16 0 +70 –40 +85 Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 UNIT V °C 3 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS At VCC(L) = ±5 V, VCC(H) = ±15 V, RL = 25 Ω, and TA = +25°C (unless otherwise noted). THS6032 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE Gain = 1, RF = 1.3 kΩ RL = 25 Ω 65 RL = 100 Ω 100 Gain = 2, RF = 1.1 kΩ RL = 25 Ω 60 RL = 100 Ω 70 Small signal bandwidth (–3 dB) BW Bandwidth for 0.1-dB flatness SR ts Gain = 1 30 Gain = 2 25 Full-power bandwidth (1) VOPP = 20 V Slew rate (2) Gain = 5, VO(PP) = 20 V Settling time to 0.1% Gain = 1, RL = 25 Ω, 5-V Step MHz MHz MHz 19 MHz 1200 V/μs 120 ns NOISE/DISTORTION PERFORMANCE THD Vn Total harmonic distortion Input voltage noise In VO = 20 V(pp), Gain = 5, f = 1 MHz –62 VO = 2 V(pp), Gain = 2, f = 1 MHz –69 f = 10 kHz 2.4 dBc In+ 11 In– 15 Input current noise f = 10 kHz Differential gain error Gain = 2, NTSC RL = 150 Ω 0.016% RL = 25 Ω 0.020% Differential phase error Gain = 2, NTSC RL = 150 Ω 0.04° RL = 25 Ω 0.30° Crosstalk f = 1 MHz, Gain = 2, RF = 1.1 kΩ nV/√Hz nV/√Hz –62 dB DC PERFORMANCE Z(t) Open loop transimpedance VIO RL = 1 kΩ 2 TA = +25°C Input offset voltage 1.5 TA = full range MΩ 5 7 Offset voltage drift 10 TA = +25°C Differential offset voltage 0.5 TA = full range 6 TA = +25°C Negative input bias current 1.5 TA = full range IIB 1.5 TA = full range μV/°C mV 9 12 TA = +25°C Positive input bias current 3 mV 9 μA 12 INPUT CHARACTERISTICS VICR Input common-mode voltage CMRR Common-mode rejection ratio rI TA = full range Inverting terminal Input resistance Noninverting terminal Differential input capacitance (1) (2) 4 ±13.2 ±13.4 V 64 72 dB 15 Ω 400 kΩ 1.4 pF Full power bandwidth = slew rate/2π VPEAK. Slew rate is defined from the 25% to the 75% output levels. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 ELECTRICAL CHARACTERISTICS (continued) At VCC(L) = ±5 V, VCC(H) = ±15 V, RL = 25 Ω, and TA = +25°C (unless otherwise noted). THS6032 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT CHARACTERISTICS VO Output voltage IO Output current (3) ISC Short-circuit current Single-ended RL = 25 Ω ±10.5 ±11 Differential RL = 50 Ω ±21 ±22 RL = 25 Ω 400 440 mA 800 mA (3) V POWER SUPPLY VCC Supply voltage VCC(L) 0 ±5 ±VCCH VCC(H) ±5 ±15 ±16.5 4.3 5.8 TA = +25°C VCC(L) ICC Quiescent current (per amplifier) 6.2 TA = +25°C VCC(H) VCC(L) PSRR TA = full range Power-supply rejection ratio VCC(H) 4 TA = full range 90 TA = full range 80 TA = +25°C 69 TA = full range 66 mA 5 5.5 TA = +25°C V mA 100 dB 80 dB SHUTDOWN CHARACTERISTICS VIL Shutdown voltage for power up Relative to DGND terminal VIH Shutdown voltage for power down Relative to DGND terminal IIH Shutdown input current high V(SHDN) = 5 V IIL Shutdown input current low V(SHDN) = 0.5 V ZO Output impedance (while in shutdown state) V(SHDN) = 2.5 V, f = 1 MHz ICCL ICCH Supply current (per amplifier) (while in shutdown state) V(SHDN) = 2.5 V, VO = 0 V 0.8 V 200 300 μA 20 40 μA 2 V Ω 0.5 0.05 0.2 2.4 3 mA tdis Disable time (4) 1.1 μs ten Enable time (4) 1.5 μs (3) (4) A heat sink is required to keep junction temperature below absolute maximum when an output is heavily loaded or shorted. See Absolute Maximum Ratings table. Disable/enable time begins when the logic signal is applied to the shutdown terminal and ends when the supply current has reached half of its final value. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 5 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com TERMINAL FUNCTIONS TERMINAL NAME DWP PACKAGE TERMINAL NO. GQE PACKAGE TERMINAL NO. VFP PACKAGE TERMINAL NO. 1OUT 3 B1 1 1IN– 5 F1 5 1IN+ 6 H1 7 2OUT 18 B9 24 2IN– 16 G9 20 2IN+ 15 H9 18 VCCH– 2 A3 30 VCCH+ 19 A7 27 VCCL– 4 D1 3 VCCL+ 17 D9 22 SHDN1 8 J2 10 SHDN2 9 J4 11 DGND 12 J7 14 1, 10, 11, 20 N/A N/A 7, 13, 14 N/A N/A PAD NC PIN ASSIGNMENTS V CCH− VCCH+ MicroStar Junior? (GQE) PACKAGE (TOP VIEW) 1 1OUT VCCL− 2 4 5 6 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC F NC NC NC NC NC NC NC G NC NC NC NC NC NC NC NC H NC NC NC NC NC NC NC A NC NC B NC C NC NC D NC E NC 3 NC 7 8 9 NC NC 2OUT NC VCCL+ NC 2IN− 1IN− NC 2IN+ 1IN+ Note: 6 NC NC NC DGND NC SHDN2 NC SHDN1 J NC Shaded terminals are used for thermal connection to the ground plane. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 NC NC VCCH− NC NC VCCH+ NC NC VFP PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 1OUT NC VCCL− NC 1IN− NC 1IN+ NC 1 24 2 23 3 22 4 PowerPAD? 2OUT NC VCCL+ NC 2IN− NC 2IN+ NC 21 5 20 6 19 7 18 8 17 NC SHDN1 SHDN2 NC NC DGND NC NC 9 10 11 12 13 14 15 16 NC − No internal connection FUNCTIONAL BLOCK DIAGRAM (SOIC PACKAGE) 19 1OUT 3 18 17 1IN− 1IN+ VCCH− VCCL− SHDN1 SHDN2 A. 5 6 − − + + 16 15 VCCH+ 2OUT VCCL+ 2IN− 2IN+ 2 4 8 9 12 DGND Terminals 1, 10, 11, and 20 are internally connected to the thermal pad. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 7 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 0.4 RF = 1.3 kΩ RF = 1 kΩ 0.3 0 Output Amplitude − dB −1 RF = 1.5 kΩ −2 −3 −4 −5 −6 −7 100 k VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +1 RL = 25 Ω VO = 0.2 VRMS 1M 0.1 RF = 1 kΩ −0.0 −0.1 −0.2 −0.3 10 M 100 M −0.4 100 k 500 M RF = 1.3 kΩ 1M 10 M 100 M 1M 10 M 100 M OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 15 RF = 1.1 kΩ 5.8 RF = 1.3 kΩ 5.6 100 k VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RL = 25 Ω VO = 0.4 VRMS Figure 3. 6.0 5.7 1 Figure 2. RF = 820 Ω 5.9 2 Figure 1. Output Amplitude − dB 6.1 RF = 1.3 kΩ 3 −1 100 k 500 M 22 1M 100 M 11 10 9 7 100k 500 M 21 RF = 820 Ω 12 8 10 M RF = 330 Ω 14 13 RF = 1.5 kΩ VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RL= 25 Ω VO = 0.2 VRMS 1M RF = 510 Ω 20 19 RF = 1 kΩ 18 17 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +10 RL= 25 Ω VO = 0.2 VRMS 16 15 14 13 10M 100M 500M 100k 1M 10M 100M f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 4. Figure 5. Figure 6. CLASS-AB MODE OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY SMALL AND LARGE SIGNAL FREQUENCY RESPONSE 8 V O − Normalized Output Voltage − dBV 6 6 Gain = +2 RF =1.1 kΩ 4 VCC(H) = ± 15 V VCC(L) = GND 2 0 Gain = +1 RF =1.3 kΩ −2 RL = 25 Ω VI = 0.2 VRMS −4 −6 100 k 1M 10 M 4 2 Gain = +1, RF = 1.3 kΩ 0 −2 −4 −6 100 M 500 M f − Frequency − Hz Figure 7. −8 100 k 500M 18 Gain = +2, RF = 1.1 kΩ Output Amplitude − dB Class-AB Mode Output Amplitude − dB 8 500 M f − Frequency − Hz 16 6.2 4 f − Frequency − Hz VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RL = 25 Ω VO = 0.4 VRMS 6.3 5 0 RF = 1.5 kΩ RF = 1.1 kΩ RF = 820 Ω 6 f − Frequency − Hz 6.4 Output Amplitude − dB 0.2 7 Output Amplitude − dB Output Amplitude − dB 1 8 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +1 RL = 25 Ω VO = 0.2 VRMS Output Amplitude − dB 2 8 OUTPUT AMPLITUDE vs FREQUENCY VCC(H) = ± 15 V VCC(L) = ± 5 V RL = 100 Ω VI = 0.2 VRMS 1M 10 M 100 M 500 M 12 6 0 −6 −12 −18 100 k VCC(H) = ± 15 V VCC(L) = ± 5 V VO(PP) = 4 V VO(PP) = 2 V VO(PP) = 1 V VO(PP) = 0.5 V VO(PP) = 0.25 V Gain = +1 RL = 25 Ω RF = 1.3 k Ω 1M 10 M f − Frequency − Hz f − Frequency − Hz Figure 8. Figure 9. Submit Documentation Feedback 100 M 500 M Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 TYPICAL CHARACTERISTICS (continued) CLASS-G MODE DISTORTION vs FREQUENCY SMALL AND LARGE SIGNAL FREQUENCY RESPONSE 18 VCC(H) = ± 15 V VCC(L) = ± 5 V VO(PP) = 4 V 12 VO(PP) = 2 V 6 VO(PP) = 1 V 0 VO(PP) = 0.5 V −6 −12 100 k VCC(H) = ± 15 V VCC(L) = ± 5 V to ± 7.5 V Gain = +2 RF = 1.1 kΩ RL = 25 Ω VO(PP) = 2 V −30 −40 −50 −60 −70 −80 3rd Harmonic −90 Gain = +2 RL = 25 Ω 10 M 100 M −100 100 k 500 M f − Frequency − Hz −40 −50 THD −60 −70 3rd Harmonic −80 2nd Harmonic −90 1M −100 100 k 10 M 20 M 1M 10 M 20 M f − Frequency − Hz f − Frequency − Hz Figure 10. Figure 11. Figure 12. 2ND ORDER DISTORTION vs OUTPUT VOLTAGE 3RD ORDER DISTORTION vs OUTPUT VOLTAGE THD vs OUTPUT VOLTAGE −50 −50 −50 VCC(L) = ± 5 V −65 −55 3RD Order Distortion − dBc −60 −70 −75 VCC(L) = ± 7.5 V −80 −85 VCC(H) = ± 15 V Gain = +5 RF= 1.1 kΩ RL = 25 Ω f = 1 MHz VCC(L) = ± 6 V VCC(L) = GND −60 −65 −70 −75 −80 VCC(L) = ± 6 V −85 VCC(L) = ± 5 V −90 VCC(L) = ± 6 V −60 −65 −70 5 10 15 20 −85 −90 0 VO(PP) − Output Voltage − V 10 15 20 Figure 14. Figure 15. CROSSTALK vs FREQUENCY SLEW RATE vs OUTPUT VOLTAGE STEP VOLTAGE AND CURRENT NOISE vs FREQUENCY 1400 100 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RF = 1.1 kΩ RL = 25 Ω 1200 Input = Ch. 2 Output = Ch. 1 Input = Ch. 1 Output = Ch. 2 1000 −SR 800 600 400 200 −70 0 1M 10 M 100 M 500 M f − Frequency − Hz Figure 16. 0 5 VCC(H) = ± 15 V VCC(L) = ± 5 V TA = 25°C +SR 10 15 VO(pp) − Output Voltage Step − V Figure 17. 20 Hz VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RF = 1.1 kΩ RL = 25 Ω −60 −80 100 k 5 VO(PP) − Output Voltage − V I n − Current Noise − pA/ −50 0 20 Hz −40 15 V n − Voltage Noise − nV/ −30 10 Figure 13. SR − Slew Rate − V/ ms −20 5 VO(PP) − Output Voltage − V 0 −10 VCC(H) = ± 15 V Gain = +5 RF= 1.1 kΩ RL = 25 Ω f = 1 MHz −80 −90 0 VCC(L) = ± 7.5 V VCC(L) = ± 5 V −75 VCC(L) = ± 7.5 V VCC(L) = GND VCC(L) = GND −55 Total Harmonic Distortion − dBc VCC(H) = ± 15 V Gain = +5 RF= 1.1 kΩ RL = 25 Ω f = 1 MHz −55 2ND Order Distortion − dBc VCC(H) = ± 15 V VCC(L) = GND Gain = +2 RF = 1.1 kΩ RL = 25 Ω VO(PP) = 2 V −30 2nd Harmonic RF = 1.1 k Ω 1M THD Class-AB Mode Distortion − dBc VO(PP) = 8 V Class-G Mode Distortion − dBc V O − Normalized Output Voltage − dBV −20 −20 24 Crosstalk − dB CLASS-AB MODE DISTORTION vs FREQUENCY In− 10 In+ Vn 1 10 100 1k 10 k Figure 18. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 100 k f − Frequency − Hz 9 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) POWER SUPPLY REJECTION RATIO vs FREQUENCY VCC(H) = ± 15 V VCC(L) = ± 5 V RL= 1 kΩ 120 100 80 60 40 20 1k 10 k 100 k 1M 10 M 100 M 1G 120 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RF = 1.1 kΩ RL = 25 Ω 100 80 60 −VCC(L) +VCC(L) 40 20 ±VCC(H) 0 10 k 100 k 60 50 40 30 20 10 0 10 k 100 k 1M 10 M Figure 21. SUPPLY CURRENT vs FREE-AIR TEMPERATURE MAXIMUM OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE 2.0 5.0 4.5 ICC(L) 4.0 ICC(H) 3.5 3.0 2.5 2.0 −40 −20 0 20 40 60 80 VCC(H)= ± 15 V VCC(L)=± 5 V 11.8 11.6 +VOUT 11.4 11.2 11.0 −VOUT 10.8 10.6 −40 100 V IO − Input Offset Voltage − mV VOUT − Maximum Output Voltage − V 12.0 VCC(H) = ± 15 V VCC(L) = ± 5 V Per Amplifier TA − Free-Air Temperature − °C −20 0 20 40 60 80 VCC(H) = ± 15 VCC(L) = ± 5 V 1.8 1.6 1.4 1.2 1.0 −40 100 −20 0 20 40 60 Figure 22. Figure 23. Figure 24. INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE DIFFERENTIAL GAIN vs LOADING DIFFERENTIAL PHASE vs LOADING 0.05 0.04 Differential Gain − % 1.5 1.25 1 0.75 lib− 0.5 PAL 0.02 NTSC −20 0 20 40 60 80 TA − Free-Air Temperature − °C Figure 25. 100 0.3 PAL 0.2 NTSC 0.1 VCC(H) = ± 15 V VCC(L) = ± 5 V 0.25 Gain = 2 RF = 1.1 kΩ 40 IRE Modulation Worst Case ± 100 IRE Ramp 0.4 0.03 0.01 0 −40 100 0.5 Gain = 2 RF = 1.1 kΩ 40 IRE Modulation Worst Case ± 100 IRE Ramp 1.75 lib+ 80 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C 2 100 M f − Frequency − Hz Figure 20. 5.5 I CC − Supply Current − mA 100 M VCC(H) = ± 15 V VCC(L) = ± 5 V RF = 1 kΩ RL = 25 Ω 70 Figure 19. 6.0 I IB − Input Bias Current − m A 10 M 80 f − Frequency − Hz f − Frequency − Hz 10 1M Differential Phase − % Transimpedance − dBΩ PSRR − Power Supply Rejection Ratio − dB 140 COMMON-MODE REJECTION RATIO vs FREQUENCY CMRR − Common-Mode Rejection Ratio − dB TRANSIMPEDANCE vs FREQUENCY VCC(H) = ± 15 V VCC(L) = ± 5 V 0.0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 Number of 150 Ω Loads Number of 150 Ω Loads Figure 26. Figure 27. Submit Documentation Feedback 7 8 Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 TYPICAL CHARACTERISTICS (continued) STANDBY SUPPLY CURRENT vs FREE-AIR TEMPERATURE VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RF = 1 kΩ 100 10 I CC(H) − Stanby Supply Current − mA Zo − Closed Loop Output Impedance − Ω 56 3.00 1000 Shut-down Mode 1 Not Shut-down 0.1 2.75 1M 10 M 100 M f − Frequency − Hz 52 2.25 50 48 2.00 ICC(L) 46 1.75 500 M 44 −40 −20 0 SHUTDOWN ISOLATION vs FREQUENCY −60 Reverse Isolation −80 −30 −40 −50 Forward Isolation −60 Reverse Isolation −70 −80 −90 100 k 1M 10 M 100 M −90 100 k 500 M f − Frequency − Hz 1-V STEP RESPONSE 10 M 100 M 200 0 500 M −0.4 200 t − Time − ns Figure 33. 6 8 10 12 14 16 18 20 10-V PULSE RESPONSE 8 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RL = 25 Ω RF = 1.1 kΩ 1 6 0 −1 4 2 0 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RF = 1.1 kΩ RL = 25 Ω TR/TF = 6 ns −2 −4 −6 −3 150 4 Figure 32. −2 −0.6 2 t − Time − m s V O − Output Voltage − V V O − Output Voltage − V −0.2 100 400 0 2 −0.0 50 600 5-V STEP RESPONSE VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RL = 25 Ω RF = 1.1 kΩ 0 800 −200 1M 3 0.2 0 Figure 31. 0.6 0.4 100 Gain = +2 RF = 1.1 kΩ RL = 25 Ω 5 f − Frequency − Hz Figure 30. V O − Output Voltage − V VSD - Shutdown Voltage - V VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = −1 RL = 25 Ω RF = 1.1 kΩ VI = 0.2 VRMS −20 −50 −70 80 10 VO - Output Voltage - mV Forward Isolation Shutdown Isolation − dB Shutdown Isolation − dB −40 60 SHUTDOWN RESPONSE −10 −10 −30 40 Figure 29. SHUTDOWN ISOLATION vs FREQUENCY VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RL = 25 Ω RF = 1.1 kΩ VI = 0.2 VRMS 20 TA − Free-Air Temperature − °C Figure 28. −20 54 ICC(H) 2.50 1.50 0.01 100 k VCC(H) = ± 15 V VCC(L) = ± 5 V VSD = 2.5 V Per Amplifier I CC(L) − Stanby Supply Current − mA CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY −8 0 50 100 150 t − Time − ns Figure 34. 200 0 25 50 75 100 125 150 175 200 225 250 t − Time − ns Figure 35. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 11 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com APPLICATION INFORMATION ADSL The THS6032 was primarily designed as a low-power line driver for ADSL (asymmetrical digital subscriber line). The driver output stage has been sized to provide full ADSL power levels of 20 dBm onto the telephone lines. Although actual driver output peak voltages and currents vary with each particular ADSL application, the THS6032 is specified for a minimum full output current of 400 mA at its full output voltage of approximately 11 V. This performance meets the demanding needs of ADSL at the central office end of the telephone line. A typical ADSL schematic is shown in Figure 36. VCC(H)15 V 0.1 mF + THS6032 Driver 1 VI+ 0.1 mF 6.8 mF 12.5 Ω + _ 1:2 680 Ω Telephone Line 0.1 mF 6.8 mF + −VCC(H) −15 V 1 kΩ VCC(L) 6 V 200 Ω 15 V + 0.1 mF THS6032 Driver 2 VI− 100 Ω 0.1 mF 2 kΩ 6.8 mF 0.1 mF 12.5 Ω + _ 1 kΩ − + THS6072 VO+ 680 Ω 0.1 mF 6.8 mF + 1 kΩ −VCC(L) −6 V 2 kΩ Driver 1 kΩ − + VO− THS6072 0.1 mF −15 V Receiver Figure 36. THS6032 ADSL Application The ADSL transmit band consists of 255 separate carrier frequencies, each with its own modulation and amplitude level. With such an implementation, it is imperative that signals put onto the telephone line have as low a distortion as possible. This is because any distortion either interferes directly with other ADSL carrier frequencies or it creates intermodulation products that interfere with ADSL carrier frequencies. 12 Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 The THS6032 has been specifically designed for ultra low distortion by careful circuit implementation and by taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended distortion measurements are shown in Figure 11 through Figure 15. It is commonly known that in the differential driver configuration, the second order harmonics tend to cancel out. Thus, the dominant total harmonic distortion (THD) will be primarily due to the third order harmonics. Additionally, distortion should be reduced as the feedback resistance drops. This is because the bandwidth of the amplifier increases, which allows the amplifier to react faster to any nonlinearities in the closed-loop system. Another significant point is the fact that distortion decreases as the impedance load increases. This is because the output resistance of the amplifier becomes less significant as compared to the output load resistance. One problem that has been receiving a lot of attention in the ADSL area is power dissipation. One way to substantially reduce power dissipation is to lower the power supply voltages. This is because the RMS voltage of an ADSL central office signal is 1.65-V RMS at each driver's output with a 1:2 transformer. But, to meet ADSL requirements, the drivers must have a voltage peak-to-RMS crest factor of 5.6 in order to keep the bit-error probability rate below 10–7. Hence, the power supply voltages must be high enough to accomplish the driver's peak output voltage of 1.65 V × 5.6 = 9.25 V(PEAK). This high peak output voltage requirement, coupled with a low RMS voltage requirement, does not lend itself to conventional high efficiency designs. One way to save power is to decrease the bias currents internal to the amplifier. The drawback of doing this is an increase in distortion and a lower frequency response bandwidth. This is where the THS6032 class-G architecture is useful. The class-G output stage utilizes both a high supply voltage [VCC(H) typically ± 15 V] and a low supply voltage [(VCC(L) typically ± 6 V]. As long as the output voltage is less than [VCC(L) – 2.5 V], then part of the output current will be drawn from the VCC(L) supplies. If the output signal goes above this cutoff point [for example, VO > VCC(L) – 2.5 V], then all of the output current will be supplied by VCC(H). To ensure that the cutoff point does not introduce distortion into the system, the entire output stage is always biased on. This constant biasing scheme will cause a decrease in the efficiency over hard switching class-G circuits, but the very low distortion results tend to outweigh the efficiency loss. The biasing scheme used in the THS6032 can be shown by the currents being supplied by the VCC(L) power supplies in Figure 37. This graph shows there is no discrete current transfer point between the VCC(L) supplies and the VCC(H) supplies. This was done to ensure low distortion throughout the entire output range. By changing the VCC(L) supply voltage, the system efficiency can be tailored to suit almost any system with high crest factor requirements. OUTPUT CURRENT DISTRIBUTION vs OUTPUT VOLTAGE 100 Output Current Distribution − % VCC(H) = 15 V VI = 1 MHz RL = 25 Ω ICC(L) Current Draw 90 80 70 60 VCC(L) = ±5 V 50 40 VCC(L) = ±7.5 V 30 20 10 0 0 1 2 3 4 5 6 7 RMS − Output Voltage − V Figure 37. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 13 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com CLASS-AB MODE OPERATION The class-G architecture produces sizable power dissipation savings over traditional class-AB designs while maintaining low distortion requirements. The only drawback to the class-G design is the requirement of 4 power supply voltages, 2 more than a typical line driver requires. In certain instances, the addition of two separate power supplies may be cost prohibitive or PCB space prohibitive. In these cases there are two options, use a traditional amplifier, such as a THS6012, or use the THS6032 in class-AB mode. Using the THS6032 in class-AB mode will give several functional benefits over the THS6012. This includes shutdown capability, low-impedance output while in shutdown state, and a slight reduction in quiescent current. One important thing to remember is that the THS6032 running in class-AB mode, will be only about as efficient as the THS6012. This means that the power dissipation of the THS6032 will increase dramatically and must be accounted for. Failure to do so will result in a part which continuously overheats and may lead to failure. To use the THS6032 in class-AB mode, the user should always connect the VCC(L) power supply pins to GND. The internal VCC(L) paths were not designed for continuous full output current and could possibly fail. The VCC(H) paths were designed for the full output currents and thus, should be used for class-AB mode operation. The performance of the THS6032 while in class-AB mode is very similar to the class-G mode. Figure 7 and Figure 12 show THS6032 performance while in class-AB mode. DEVICE PROTECTION FEATURES The THS6032 has two built-in features that protect the device against improper operation. The first protection mechanism is output current limiting. Should the output become shorted to ground the output current is automatically limited to the value given in the data sheet. While this protects the output against excessive current, the device internal power dissipation increases due to the high current and large voltage drop across the output transistors. Continuous output shorts are not recommended and could damage the device. Additionally, connection of the amplifier output to one of the high supply rails [ ±VCC(H) ] can cause failure of the device and is not recommended. The second built-in protection feature is thermal shutdown. Should the internal junction temperature rise above approximately +180°C, the device automatically shuts down. Such a condition could exist with improper heat sinking or if the output is shorted to ground. When the junction temperature drops below +150°C, the internal thermal shutdown circuit automatically turns the device back on. THERMAL INFORMATION The THS6032 is available in a thermally-enhanced DWP package and a VFP package, which are members of the PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 38(a) and Figure 38(b) for the DWP views]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 38©)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. DIE Thermal Pad Side View (a) DIE End View (b) Bottom View (c) A. The thermal pad is electrically isolated from all terminals in the package. Figure 38. Views of Thermally-Enhanced DWP Package 14 Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 The THS6032 is also available in the MicroStar Junior GQE package. Just like the DWP and VFP packages, the GQE package utilizes the PowerPAD functionality to improve thermal performance. The GQE package is part of the new ball-grid array (BGA) family developed by Texas Instruments (TI). This package allows for even higher-density layouts with virtually no loss in thermal performance. Its construction is similar to the DWP and VFP construction [see Figure 39 (a) and (b)], but uses the terminal balls to transfer the heat away from the die. (TOP VIEW) (Side VIEW) Die (b) (a) NOTE: Shaded areas are part of the thermally-conductive path. Figure 39. Views of Thermally-Enhanced GQE Package The PowerPAD packages allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads or balls are being soldered), the thermal areas can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. This is discussed in more detail in the PCB design considerations section of this document. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heat sinking. Because of its power dissipation, proper thermal management of the THS6032 is required. There are several ways to properly heat sink all three PowerPAD packages. There are several TI application notes on how to best accomplish the thermal mounting scheme required for each package. For the DWP and VFP packages, refer to the Texas Instruments Technical Brief, PowerPAD Thermally-Enhanced Package (SLMA002). There is also a more compact technical paper entitled PowerPad Made Easy (SLMA004). For the GQE – MicroStar Junior package, refer to the MicroStar BGA Packaging Reference Guide (SSYZ015A) and the compact version entitled MicroStar Junior Made Easy (SSYA009). This literature is available on TI's web site at http://www.ti.com. The actual thermal performance achieved with the THS6032 in its PowerPAD package depends on the application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3 inches, then the expected thermal coefficient, θJA, is about 21.5°C/W for the DWP package, 37.8°C/W for the GQE package, and 30°C/W for the VFP package. Although the maximum recommended junction temperature (TJ) is listed as +150°C, performance at this elevated temperature will suffer. To ensure optimal performance, the junction temperature should be kept below +125°C. Above this temperature, distortion will tend to increase. Figure 40 shows the recommended power dissipation with a junction temperature of +125°C. Also shown is what happens if no solder is used to solder the PowerPAD to the PCB. The θJA increases dramatically with a vast reduction in power dissipation. For a given θJA and a maximum junction temperature, the power dissipation is calculated by the following formula: ǒ T P D + –T MAX A q JA Ǔ (1) Where: PD = Power dissipation of THS6032 (watts) TMAX = Maximum junction temperature allowed in the design (+125°C recommended) TA = Free-ambient air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case (DWP = 0.37°C/W, GQE = 4.56°C/W, VFP = 1.2°C/W) θCA = Thermal coefficient from case to ambient Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 15 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 9 TJ = 125°C Maximum Power Dissipation − W 8 DWP θJA = 21.5°C/W 7 VFP θJA = 30°C/W 6 5 GQE θJA = 37.8°C/W 4 3 2 1 0 −40 DWP θJA = 43.9°C/W No Solder Utilized −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C Figure 40. Maximum Power Dissipation vs Free-Air Temperature PCB DESIGN CONSIDERATIONS Proper PCB design techniques in two areas are important to assure proper operation of the THS6032. These areas are high-speed layout techniques and thermal-management techniques. Because the THS6032 is a high-speed part, the following guidelines are recommended. • Ground plane – It is essential that a ground plane be used on the board to provide all components with a low-inductance ground connection. Although a ground connection directly to a terminal of the THS6032 is not necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves two functions. It provides a low-inductance ground to the device substrate to minimize internal crosstalk, and it provides a path for heat removal. • Input stray capacitance – To minimize potential problems with amplifier oscillation, the capacitance at the inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input must be as short as possible, the ground plane must be removed under any etch runs connected to the inverting input, and external components should be placed as close as possible to the inverting input. This is especially true in the noninverting configuration. An example of this can be seen in Figure 41, which shows what happens when a 2.2 pF capacitor is added to the inverting input terminal in the noninverting configuration. The bandwidth increases dramatically at the expense of peaking. This is because some of the error current is flowing through the stray capacitor instead of the inverting node of the amplifier. While the device is in the inverting mode, stray capacitance at the inverting input has a minimal effect. This is because the inverting node is at a virtual ground and the voltage does not fluctuate nearly as much as in the noninverting configuration. This can be seen in Figure 42, where a 27-pF capacitor adds only 2.5 dB of peaking. In general, as the gain of the system increases, the output peaking due to this capacitor decreases. While this can initially appear to be a faster and better system, overshoot and ringing are more likely to occur under fast transient conditions. Therefore, proper analysis of adding a capacitor to the inverting input node should always be performed to ensure stable operation. 16 Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 4 2 1 4 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +1 RL = 25 Ω VO = 0.2 VRMS Ci = 2.2 pF 0 −1 −2 −3 Ci = 0 pF −4 Ci = 27 pF VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = −1 RL = 25 Ω VO = 0.2 VRMS 3 Output Amplitude − dB Output Amplitude − dB 3 2 1 0 −1 Ci = 0 pF −2 −3 −4 −5 100 k 1M 10 M 100 M 500 M −5 100 k f − Frequency − Hz Ci 1M 10 M 100 M 500 M f − Frequency − Hz 1.3 kΩ 1.1 kΩ 1.1 kΩ − + VI VI VO 50 Ω 25 Ω 50 Ω Ci Figure 41. • • − + VO RL = 25 Ω Figure 42. Proper power supply decoupling – Use a minimum of a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor on each supply terminal. It may be possible to share the tantalum capacitor among several amplifiers depending on the application, but a 0.1-μF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-μF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminal and the ceramic capacitors. Differential power supply decoupling – The THS6032 was designed to drive low-impedance differential signals. The 25-Ω load that each amplifier drives causes large amounts of current to flow from amplifier to amplifier. Power-supply decoupling for differential-currents must be provided to ensure low distortion in the THS6032. By simply connecting a 0.1-μF ceramic capacitor from the +VCC(H) pin to the –VCC(H) pin, along with another 0.1-μF ceramic capacitor from the +VCC(L) pin to the –VCC(L) pin, differential current loops will be minimized (see Figure 36). This will help keep the THS6032 operating at peak performance. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 17 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES As with all current feedback amplifiers, the bandwidth of the THS6032 is an inversely-proportional function of the value of the feedback resistor. This can be seen from Figure 1 to Figure 6. The recommended resistors for the optimum frequency response with a 25-Ω load system can be seen in Table 1. These should be used as a starting point. When optimum values are found, 1%- tolerance resistors should be used to maintain frequency response characteristics. For most applications, a feedback-resistor value of 1.3 kΩ is recommended; this value provides a good compromise between bandwidth and phase margin that yields a very stable amplifier. Consistent with current-feedback amplifiers, increasing the gain is best accomplished by changing the gain resistor, not the feedback resistor. This is because the bandwidth of the amplifier is dominated by the feedback resistor value and the internal dominant-pole capacitor. The ability to control the amplifier gain independently of the bandwidth constitutes a major advantage of current-feedback amplifiers over conventional voltage-feedback amplifiers. Therefore, once a frequency response is found suitable to a particular application, adjust the value of the gain resistor to increase or decrease the overall amplifier gain. Finally, it is important to realize the effects of the feedback resistance on distortion. Increasing the resistance decreases the loop gain and increases the distortion. It is also important to know that decreasing load impedance increases total harmonic distortion (THD). Typically, the third-order harmonic distortion increases more than the second-order harmonic distortion. Table 1. Recommended Feedback Resistor Values for 25-Ω Loads GAIN Rf 1 1.3 kΩ 2, –1 1.1 kΩ 5 820 kΩ 7.8 680 kΩ 10 510 kΩ SHUTDOWN CONTROL There are two shutdown pins that control the shutdown for each amplifier of the THS6032. When the shutdown pin signals are low, the THS6032 is active. But, when a shutdown pin is high (≥2 V), the corresponding amplifier is turned off. The shutdown logic is not latched, and should always have a signal applied to it. To help ensure a fixed logic state, an internal 50-kΩ resistor to DGND is utilized. An external resistor, such as a 3.3 kΩ, to DGND may be added to help improve noise immunity in harsh environments. If no external resistor is used and SHDNX pins are left unconnected, the THS6032 defaults to a power-on state. A simplified circuit is shown in Figure 43. +VCC(H) To Internal Bias Circuitry Control SHDNX 50 kΩ DGND −VCC(H) DGND Figure 43. Simplified THS6032 Shutdown Control Circuit 18 Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 SHUTDOWN FUNCTION The THS6032 incorporates a shutdown circuit to conserve power. Traditionally, when an amplifier is placed into shutdown mode, the input and output circuitry are turned off. This conserves a large amount of power, but the output impedance will be a very high, typically greater than several kΩ. This situation does not maintain proper line termination, resulting in a severe reduction of the receive signal coming through the transmission line (see Figure 36). The THS6032 eliminates this problem. When the SHDNX pin voltage is greater than 2 V, the THS6032 enters shutdown mode to conserve power. Unlike the traditional amplifier, the THS6032's output impedance is typically 0.5 Ω at 1 MHz (see Figure 28). The shutdown mode function results in the proper termination of the line with no degradation in performance of the receive signal coming through the transmission line. There are a few design considerations that must be observed in order to fully achieve this type of functionality. To better understand these design considerations, it is helpful to examine what is happening inside the THS6032. Figure 44 shows the simplified shutdown components. Notice that there are two similar input stages; the normal input stage consisting of transistors Q1 through Q4 and the shutdown input stage consisting of transistors QS1 through QS4. When in shutdown mode, the I(BIAS – 1) and I(BIAS – 2) current sources are turned off. This turns off the normal input stage of the amplifier. The I(BIAS – S1) and I(BIAS – S2) current sources are then turned on. The shutdown input stage signals are then fed through the same internal circuitry which the normal input stage drove. This allows for sinking and sourcing large amounts of current at the output of the THS6032 during shutdown operation. The QS1 through QS4 transistors are not designed for performance like the Q1 through Q4 transistors, because their only function is to amplify the DC ground reference, DGND. A 1-kΩ resistor connects internally to the output node of the amplifier, which provides a feedback loop in shutdown mode. This forces the output impedance to become very small, allowing proper transmission line termination. +VCC(H) IBIAS−S1 QS1 Active Load IBIAS−1 Q1 QS3 Q5 1 kΩ +IN Pin DGND Q3 −IN Pin Q6 QS2 QS4 To Internal Output Node IBIAS−S2 Q4 Q2 Active Load IBIAS−2 Shut−Down Circuitry To Output Drive Circuitry −V CC(H) Figure 44. Simplified THS6032 Input Stages Because the DGND-pin voltage is effectively a noninverting terminal, any signal or voltage fluctuation at this node is amplified by the THS6032. This could possibly cause a noisy output to appear during shutdown operation. Figure 45 shows the frequency response of the THS6032 due to an input signal at the DGND terminal. The maximum DGND voltage signal which the THS6032 will follow linearly during shutdown operation is less than ±4 V. With this dynamic range capability, it is recommended that the DGND pin be as noise-free as possible to ensure proper transmission line termination. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 19 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com DGND OUTPUT AMPLITUDE vs FREQUENCY 3 DGND Output Amplitude − dB 2 VO(PP) = 0.2 V 1 0 −1 VO(PP) = 2 V −2 −3 −4 −5 −6 100 k VCC(H) = ± 15 V VCC(L) = ± 5 V RL = 25 Ω VSD = +10 V VI = DGND Pin 1M 10 M 100 M f − Frequency − Hz Figure 45. The second design consideration is due to transistors Q5 and Q6. These transistors ensure that the +IN to –IN voltage separation is less than a VBE drop (about 0.7 V). This protects the other transistors, Q1 to Q4, from saturating during fast transients. Transistors Q5 and Q6 also enhance the slew rate capabilities of the THS6032. When a fast transient is applied to the input, these transistors quickly apply the currents to the active load stages. A design issue with this setup is that while in shutdown mode, a large enough signal being applied to the input pins may turn on these transistors. Once the input voltage differential between the +IN and –IN pins reaches ±0.7-V, transistors Q5 and Q6 turn on, applying the difference signal to the rest of the amplifier circuitry. Because these two transistors are designed for much higher performance levels than the shutdown circuitry transistors (QS3 and QS4), they will become dominant and the difference input signal will be utilized instead of the DGND signal. Because the external negative feedback resistor path is still connected around the amplifier, this difference input signal will be amplified just like a normal amplifier is designed to do (see Figure 46). As long as the +IN and –IN input signals are kept below ±0.7 V, the isolation from input-to-output is very high, as shown in the Shutdown Isolation vs Frequency graphs (see Figure 30 and Figure 31). To ensure proper shutdown functionality of the THS6032, it is important to keep the DGND voltage noise-free. Additionally, the +IN and –IN signals should be limited to less than ±0.7 V during shutdown mode. This will ensure proper line termination functionality while conserving power. SHUTDOWN FEEDTHROUGH 7 VOUT − Output Voltage − V 6 G=5 G=2 G = +1; 5 G = −1 4 3 2 VCC(H)= ± 15 V VCC(L)=± 5 V RL = 25 Ω VSD = 5 V 1 0 0 2 4 6 8 10 VIN − Input Voltage − V Figure 46. 20 Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 SLEW RATE The slew rate performance of a current-feedback amplifier like the THS6032 is affected by many different factors. Some of these factors are external to the device, such as amplifier configuration and PCB parasitics, and others are internal to the device, such as available currents and node capacitance. Understanding some of these factors should help the PCB designer arrive at a more optimum circuit with fewer problems. Whether the THS6032 is used in an inverting amplifier configuration or a noninverting configuration can impact the output slew rate. Slew rate performance in the inverting configuration is generally faster than the noninverting configuration. This is because in the inverting configuration the input terminals of the amplifier are at a virtual ground and do not significantly change voltage as the input changes. Consequently, the time to charge any capacitance on these input nodes is less than for the noninverting configuration, where the input nodes actually do change in voltage an amount equal to the size of the input step. In addition, any PCB parasitic capacitance on the input nodes further degrades the slew rate, simply because there is more capacitance to charge. If the main supply voltage VCC(H) to the amplifier is reduced, slew rate decreases because there is less current available within the amplifier to charge the capacitance on the input nodes as well as other internal nodes. Also, as the load resistance decreases, the slew rate typically decreases due to the increasing internal currents, which slow down the transitions. Internally, the THS6032 has other factors that impact the slew rate. The amplifier's behavior during the slew rate transition varies slightly depending upon the rise time of the input. This is because of the way the input stage handles faster and faster input edges. Slew rates (as measured at the amplifier output) of less than about 1200 V/μs are processed by the input stage in a very linear fashion. Consequently, the output waveform smoothly transitions between initial and final voltage levels. For slew rates greater than 1200 V/μs, additional slew-enhancing transistors present in the input stage (transistors Q5 and Q6 in Figure 44) begin to turn on to support these faster signals. The result is an amplifier with extremely fast slew rate capabilities. The additional aberrations present in the output waveform with these faster slewing input signals are due to the brief saturation of the internal current mirrors. This phenomenon, which typically lasts less than 20 ns, is considered normal operation and is not detrimental to the device in any way. If for any reason this type of response is not desired, then increasing the feedback resistor or slowing down the input signal slew rate reduces the effect. SLEWING 20-V PULSE 16 6 12 4 8 V O − Output Voltage − V V O − Output Voltage − V SLEWING 10-V PULSE 8 2 SR = 1400 V/ms VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RF = 1.1 kΩ RL = 25 Ω TR/TF = 1 ns 0 −2 −4 −6 4 SR = 4000 V/ms VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RF = 1.1 kΩ RL = 25 Ω TR/TF = 1 ns 0 −4 −8 −12 −8 −16 0 25 50 75 100 125 150 175 200 225 250 t − Time − ns 0 25 50 75 100 125 150 175 200 225 250 t − Time − ns Figure 47. Figure 48. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 21 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com NOISE CALCULATIONS AND NOISE FIGURE Noise can cause errors on very small signals. This is especially true for the amplifying small signals. The noise model for current feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only difference between the two is that the CFB amplifiers generally specify different current noise parameters for each input, while VFB amplifiers usually only specify one noise current parameter. The noise model is shown in Figure 49. This model includes all of the noise sources as follows: • en = Amplifier internal voltage noise (nV/√Hz) • IN+ = Noninverting current noise (pA/√Hz) • IN– = Inverting current noise (pA/√Hz) • eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx) eRs RS en Noiseless + _ eni IN+ eno eRf RF eRg IN− RG Figure 49. Noise Model The total equivalent input noise density (eni) is calculated by using the following equation: e ni + Ǹ ǒenǓ ) ǒIN ) 2 R Ǔ S 2 ǒ ) IN– ǒR F ø R G ǓǓ 2 ǒ ) 4 kTRs ) 4 kT R ø R F G Ǔ (2) Where: k = Boltzmann's constant = 1.380658 × 10-23 T = Temperature in degrees Kelvin (273 +°C) RF || RG = Parallel resistance of RF and RG To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the overall amplifier gain (AV). e no + e ni A V ǒ + e ni 1 ) Ǔ RF (Noninverting Case) RG (3) As the previous equations show, to keep noise at a minimum, small-value resistors should be used. As the closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel resistance term. This leads to the general conclusion that the most dominant noise sources are the source resistor (RS) and the internal-amplifier noise voltage (en). Because noise is summed in a root-mean-squares method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and make noise calculations much easier. For more information on noise analysis, refer to Noise Analysis in Operational Amplifier Circuits (SLVA043A). Another noise measurement usually preferred in RF applications is the noise figure (NF). Noise figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined, and is typically 50 Ω in RF applications. 22 Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 ȱ eni 2 ȳ ȧ 2ȧ ȲǒeRsǓ ȴ NF + 10log (4) Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage, we can approximate noise figure as: NF + ȱ ȡǒe Ǔ2 ) ǒIN ) n ȧ ȧ Ȣ 10logȧ1 ) 4 kTRS ȧ ȧ Ȳ R S ȳ Ǔ2ȣ ȧȧ Ȥȧ ȧ ȧ ȴ (5) Figure 50 shows the noise figure graph for the THS6032. 20 18 Noise Figure − dB 16 14 12 10 8 6 4 f = 10 kHz TA = 25°C 2 0 10 100 1000 10000 Source Resistance − RS (Ω ) Figure 50. Noise Figure vs Source Resistance OFFSET VOLTAGE The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input-bias currents (IIB) times the corresponding gains. Figure 51 can be used to calculate the output offset voltage. Figure 51. Output Offset Voltage Model Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 23 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com GENERAL CONFIGURATIONS A common error for the first-time CFB user is to create a unity-gain buffer amplifier by shorting the output directly to the inverting input. A CFB amplifier in this configuration oscillates, so this is not recommended. The THS6032, like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors directly from the output to the inverting input is not recommended. This is because, at high frequencies, a capacitor has a very low impedance. This results in an unstable amplifier, and should not be considered when using a current-feedback amplifier. Because of this, simple low-pass filters, which are easily implemented on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply place an RC-filter at the noninverting terminal of the operational-amplifier (see Figure 52). RG RF VO R 1 = (1 + F )[ ] VI RG (1 + sR1C1) − VO + VI R1 f-3dB = C1 1 2pR1C1 Figure 52. Single-Pole Low-Pass Filter If a multiple pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is because the filtering elements are not in the negative feedback loop and stability is not compromised. Because of their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize distortion. One implementation of the Sallen-Key filter is shown in Figure 53. For more information on Sallen-Key filters, refer to the Analysis of the Sallen-Key Architecture (SLOA024A). R1 = R1 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) C1 + _ VI R1 R2 f-3dB = C2 RG RF RG = 1 2pRC RF 1 (2 - ) Q Figure 53. 2-Pole Low-Pass Sallen-Key Filter Another good use for the THS6032 amplifier is as a video distribution amplifier. One characteristic of distribution amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the number of lines increases and the closed-loop gain increases. Be sure to use termination resistors throughout the distribution system to minimize reflections and capacitive loading. 24 Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 THS6032 www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009 1.1 kΩ 1.1 kΩ 1/2 THS6032 75 Ω Transmission Line 75 Ω − VO1 + VI 75 Ω 75 Ω N Lines 75 Ω VON 75 Ω Figure 54. Video Distribution Amplifier Application DRIVING A CAPACITIVE LOAD Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS6032 has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device's phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 55. A minimum value of 10 Ω should work well for most applications. For example, in ADSL systems, setting the series resistor value to 12.5 Ω both isolates any capacitance loading and provides the proper line-impedance matching at the source end. 1.1 kΩ 1.1 kΩ Input _ 10 Ω Output THS6032 + CLOAD Figure 55. Driving a Capacitive Load EVALUATION BOARD Evaluation boards are available for the THS6032. Each board has been configured for proper thermal management of the THS6032 depending on package selection. The circuitry has been designed for a typical ADSL application as shown previously in this document. To order the evaluation board, contact your local TI sales office or distributor. Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 25 THS6032 SLOS233F – APRIL 1999 – REVISED AUGUST 2009....................................................................................................................................................... www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (October, 2007) to Revision F .............................................................................................. Page • Removed Product Preview sidebar stamp; device and document are at production data status ........................................ 1 • Corrected typical value for Differential phase error (typo) .................................................................................................... 4 Changes from Revision D (May, 2001) to Revision E ..................................................................................................... Page • Updated document format to current standards ................................................................................................................... 1 • Changed Figure 51 to correct errors in circuit design ........................................................................................................ 23 26 Submit Documentation Feedback Copyright © 1999–2009, Texas Instruments Incorporated Product Folder Link(s): THS6032 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) THS6032CDWP ACTIVE SO PowerPAD DWP 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 THS6032C THS6032IDWP ACTIVE SO PowerPAD DWP 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS6032I THS6032IDWPR ACTIVE SO PowerPAD DWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS6032I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of