THS6182DWEVM
User’s Guide
August 2003
High Performance Linear Products
SLOU152A
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third−party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products & application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Secruity
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range described in the EVM User’s
Guide.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI field
representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification, please
contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware that
these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
-4
Information About Cautions and Warnings
Preface
About This Manual
How to Use This Manual
This document contains the following chapters:
- Chapter 1 − Introduction and Description
- Chapter 2 − Using the THS6182DWEVM
- Chapter 3 − THS6182DWEVM Applications
- Chapter 4 − EVM Hardware Description
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
iii
Trademarks
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Electrostatic Sensitive Components
This EVM contains components that can potentially be damaged by
electrostatic discharge. Always transport and store the EVM in its
supplied ESD bag when not in use. Handle using an antistatic
wristband. Operate on an antistatic work surface. For more
information on proper handling, refer to SSYA008.
Related Documentation From Texas Instruments
The URL’s below are correct as of the date of publication of this manual. Texas
Instruments applications apologizes if they change over time.
- THS6182 data sheet (SLLLS544)
- Application report (SLMA002), PowerPAD Thermally Enhanced Package,
http://www−s.ti.com/sc/psheets/slma004/slma002.pdf
- Application report (SLMA004), PowerPAD Made Easy,
http://www−s.ti.com/sc/psheets/slma004/slma004.pdf
- Application report (SSYA008), Electrostatic Discharge (ESD),
http://www−s.ti.com/sc/psheets/ssya008/ssya008.pdf
- Application report (SLOA100), Active Output Impedance for ADSL Line
Drivers, http://www−s.ti.com/sc/psheets/sloa100/sloa100.pdf
Trademarks
PowerPAD is a trademark of Texas Instruments.
iv
Contents
1
Introduction and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Evaluation Modue Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
THS6182DWEVM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
EVM Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
1-2
1-2
1-2
2
Using the THS6182DWEVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
3
THS6182DWEVM Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Standard Gain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Active Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Receive Path Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
Single-Ended Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
EVM Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
3-1
3-2
3-3
3-6
3-7
3-8
v
Contents
1−1
2−1
3−1
3−2
3−3
3−4
3−5
4−1
4−2
4−3
4−4
Full Schematic of the Populated Circuit on the THS6182DWEVM (Default Configuration)
Interconnection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Configuration Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Positive Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Implementation of the Receive Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADSL Spectrum and High-Pass Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Ended Amplifier Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Top Layer 1 (Signals for THS6182DWEVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Plane (Layer 2) (Ground 1 Plane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Plane (Layer 3) (Power Plane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bottom (Layer 4) (Ground and Signal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3
2-1
3-2
3-3
3-6
3-7
3-8
4-2
4-3
4-3
4-4
4−1
vi
THS6182DWEVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Chapter 1
The Texas Instruments THS6182DW evaluation module (EVM) helps
designers evaluate the performance of the THS6182 operational amplifier.
Also, this EVM is a good example of high-speed PCB design.
This document details the THS6182DWEVM. It includes a list of EVM features,
a brief description of the module illustrated with a series of schematic
diagrams, EVM specifications, details on connecting and using the EVM, and
a discussion of high-speed amplifier design considerations.
This EVM enables the user to implement various circuits to clarify the available
configurations presented by the schematic of the EVM. The user is not limited
to the circuit configurations presented. The EVM provides enough hardware
hooks that the only limitation should be the creativity of the user.
Topic
Page
1.1
Evaluation Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2
THS6182DWEVM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3
EVM Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Introduction and Description
1-1
Evaluation Modue Features
1.1 Evaluation Modue Features
The THS6182EVM provides a platform for developing high-speed operational
amplifier application circuits. It contains the THS6182 high-speed dual
operational amplifier, a number of passive components, and various features
and footprints that enable the user to experiment with, test, and verify various
operational amplifier circuit implementations. The PC board measures 4.0 by
2.8 inches. THS6182 high-speed operational amplifier EVM features include:
- Active termination capability (R3 and R12)
- Snubber circuit (R1 and C1), for use with active termination
- Hooks for a recieve path signal (TP1 through TP4)
- Noninverting gain configuration for DSL
- High-pass filter (HPF) function for ADSL (C2 and R23)
- Short-loop length for the power supply differential high-frequency path
(C9)
1.2 THS6182DWEVM Operating Conditions
Supply voltage range, ±VCC
±5 to ±15 Vdc (see the device data sheet)
Supply current, ICC
(see the device data sheet)
For complete THS6182 amplifier IC specifications, parameter measurement
information, and additional application information, see the THS6182 data
sheet (SLLS544).
1.3 EVM Default Configuration
As delivered, the EVM has a fully functional example circuit, requiring added
power supplies, a signal source, and monitoring instrument. See Figure 1−1
for the complete EVM schematic.
The default configuration has a differential gain of 2.22, as determined by R2,
R23, and R11 in combination with series matching resistors R6, R7, R15, and
R16, and a 50-Ω load on the outputs at J1 and J3.
Some components such as R20, R21, R24–R29, C3–C11, FB1, FB2, JP1,
JP2, J5–J7, and TP8–TP10, etc., are omitted on the application schematics
of Chapter 3 for clarity.
1-2
EVM Default Configuration
Figure 1−1. Full Schematic of the Populated Circuit on the THS6182DWEVM (Default
Configuration)
18
+V
Z1
J2
IN2
R9
0W
R8
8
0W
*
+
1
TP2
TP1
U1A
THS6182
J1
R6
2
−
12.4 W
49.9 W
3
R10
49.9 W
R5
R4
*
OUT1
R7
R2
1.5 kW
−V
*
R3
C2
*
R1
R23
750 W
Z3
*
*
C1
*
R26
R22
*
0.1 mF
C5
*
*
R12
*
R13
*
R14
*
Z2
J4
IN2
R18
0W
R17
13
TP3
−
19
+
U1B
THS6182
0W
R19
49.9 W
*
TP4
J3
R15
R16
12.4 W
49.9 W
J5
J6
GND
−VCC
JP2
R29
10 kW
FB2
R21
C4
0.1 mF
JP1
R24
10 kW
R28
10 kW
C3
R20
100 W
−V
+V
BIAS−2
22 mF
C9
1 mf, 50 V
C8
**
0.1 mF
4
5
6
7
14
15
0.1 mF
10
9
C7
TP8
BIAS−1
IADJ
12
R27
0W
GND
**
R25
10 kW
FB1
22 mF
C10
+V
TP9
100 W
0.1 mF
C6
OUT2
+V
TP10
J7
+VCC
TP5 TP6 TP7
20
R11
1.5 kW
Install near U1
17
Not installed
16
GND
*
**
U1C
THS6182
Introduction and Description
1-3
1-4
Chapter 2
!"#
This section describes how to connect the THS6182DWEVM to test
equipment. It is recommended that the user connect the EVM as described in
this section to avoid damage to the EVM or the THS6182 installed on the
board.
Figure 2−1. Interconnection Diagram
6182DW
Using the THS6182DWEVM
2-1
Figure 2−1 shows the connections to measure the output signal of output 1
while a single-ended signal is inserted into EVM channel 1’s noninverting
input. If the oscilloscope input is connected to J3 and the signal source is
connected to J2, EVM channel 2 is also configured for a noninverting signal
path. When the oscilloscope’s input impedance is 50 Ω, the voltage gain from
J2 to J3 is 1.33 V.
Once power is available at the power terminals of the EVM, removing either
JP1 and/or JP2 causes bias current to flow at the desired amount. With both
JP1 and JP2 installed, the circuit is disabled.
If a balanced (differential) signal is inserted into J2 and J4, a balanced signal
is present at J1 and J3.
2-2
Chapter 3
!"# $
Example applications are presented in this chapter. These applications
demonstrate the most popular circuits, but many other circuits can be
constructed. The user is encouraged to experiment with different circuits,
exploring new and creative design techniques.
Topic
Page
3.1
Standard Gain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Active Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3
Receive Path Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4
High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5
Single-Ended Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
THS6182DWEVM Applications
3-1
Standard Gain Configuration
3.1 Standard Gain Configuration
The THS6182DWEVM default configuration is a fully differential input, fully
differential output gain of about 2.2 (at the output connectors using an
instrument with 50-Ω load on each input). A simplified schematic is shown in
Figure 3−1. This gain is calculated according to an equation that is similar to
the one that describes an instrumentation amplifier:
V (diff)
+ 1 ) 2 R2
Differential gain + O
R23
V (diff)
I
(1)
where
R2 = R11
Series resistors R6, R7, R15 and R16 affect output voltage at J1 and J3. The
designer needs to take the voltage divider law into account for their load
impedance and R6, R7, R15 and R16. When a designer monitors the output
at TP1 and TP3 using a high-impedance differential probe, the default gain is
5 V.
Figure 3−1. Default Configuration Operation
+V
TP2
TP1
18
J2
IN2
Z1
0W
R9
0W
8
U1A
THS6182
+
2
1
−
R10
49.9W
3
R6
R7
12.4 W
49.9W
J1
OUT1
R2
1.5 k W
−V
C2
0.1 m F
R23
750 W
TP3
20
J4
IN2
Z2
R18
0W
0W
R19
49.9W
3-2
13
U1B
THS6182
−
+
19
R11
1.5 k W
TP4
J3
OUT2
R15
R16
12.4 W
49.9W
Active Termination
3.2 Active Termination
Although this application is specifically for use as an ADSL line driver, the
principals shown can be applied to other applications.
Active termination is a technique that allows the designer to use a small value
resistor for the series resistance (R6 and, or R15). The circuit then utilizes positive feedback to make the impedance of this resistor appear much larger,
when looking from the line-side. This accomplishes two things:
- A very small resistance exists between the amplifier and the transformer.
This lowers the output voltage swing range required from the driver stage.
- Proper matching impedance appears when looking from the line to the
amplifier.
Figure 3−2 shows the basic circuit for differential positive feedback.
Figure 3−2. Differential Positive Feedback
+V
J2
Vin1
U1A
THS6182
18
Z1
R9
0W
0W
8
1
TP1
Vo1
+
R6 = Rs
2
−
R10
49.9 W
12.4 W
3
R2 = RF
1.5 k W
−V
C2
0.1 mF
R3 = Rp
2kW
C1
20
0W
R18
0W
13
TP3
Vo2
−
Line =
100 W
TP4
Vout+
R12 = Rp
2kW
Z2
V Line
1:n
R1
R23 = 2 RG
750 W
J4
Vin2
TP2
Vout+
19
+
U1B
THS6182
R11 = RF
1.5 k W
R15 = Rs
12.4 W
R19
49.9 W
THS6182DWEVM Applications
3-3
Active Termination
Active feedback creates larger impedance (Z) than what is actually placed
there by series resistors RS:
Z(W) +
R
S
R
1– F
R
P
(2)
The important thing to consider is that regardless of the forward gain from Vin
to Vo, the active impedance (Z) value remains constant.
Solving equation 2 for Rp, the following equation is produced:
R +
P
R
F
R
(3)
1* S
P
Using Z = 50 Ω and values from Figure 3−2 in equation 3, yields 1995 Ω for
RP. The closest E96(1%) value to 1995 Ω is 2 kΩ, as shown in Figure 3−2.
Now that the return impedance is corrected, forward voltage gain from input
to output is calculated. Equation 3 shows the simplified forward gain from Vin
to Vo.
V "
+
A + O
V
V "
in
ǒ Ǔ
ǒ Ǔǒ Ǔ
R
1)
F
R || R
P
G
R
R
1*
R
F
P
L
R )R
L
S
if R
L
tt R
P
(4)
where
R
R + LINE
L
2 n2
(5)
With a transformer ratio( n ) of 1 and a RLINE of 100 Ω, RL is 50 Ω.
When the value RL and the values in Figure 3−2 are used in equation 4, the
resulting voltage gain is 14.5. Because RG does not affect the value of the
apparent output impedance of the circuit, voltage gain can be adjusted by
changing RG.
The reader is cautioned that active termination is a very complex topic, with
many considerations. Please carefully read the Texas Instruments Application
Report Active Output Impedance for ADSL Line Drivers, (SLOA100) to gain
a more complete understanding of the topic and all the subtle implications of
active termination.
R1 and C1 are located on the EVM so that a snubber circuit may be
implemented. Some transformers have a high resonant frequency (as low as
25 MHz but as high as 150 MHz). When using traditional termination (just R6,
and R15—no active termination), there is typically not a reason to use these
components. But, when active termination is used, the effective impedance of
these two resistor values drops substantially. Thus, there can be very small
3-4
Active Termination
resistor isolation between the amplifier and the transformer, causing a
resonance problem. Couple this with the feedback path of R3 and R12, and
this can cause the amplifier to oscillate. The snubber is utilized to eliminate this
oscillation. As a rule of thumb, to select the proper snubber values, select:
R19 + 2
R
LINE
n2
(6)
Then select C5:
C5 +
2
p
1
R19
F
(7)
C
where FC = at least 10X the highest operating frequency (1.104 MHz is the
highest ADSL operating frequency). 20X or even larger may be preferable.
THS6182DWEVM Applications
3-5
Receive Path Implementation
3.3 Receive Path Implementation
Test points TP1 through TP4 are located on the EVM to facilitate the addition
of the receive signal path to the signal chain as shown in Figure 3−3. When
implementing the receive path, a hybrid must be used as ADSL is full duplex.
The hybrid cancels out the TX signal and allows the RX signal from the line to
come through. The THS6182DWEVM does not have receive or hybrid circuitry
included. Texas Instruments assumes that the customer has a proprietary
hybrid design, and therefore they would prefer to implement it. The user should
know their nominal line impedance characteristics and thus should be able to
match them better. Texas Instruments does have an EVM that contains a
THS6062 ADSL receiver, and this EVM can be purchased separately to
facilitate construction of a complete ADSL transmit/receive interface.
Figure 3−3. Implementation of the Receive Signal Path
R
+V
U2A
THS6062
1
8
2R
+V
J2
Vin1
Z1
0W
R9
0W
1
−
RX Vout+
+
4
R6 = Rs
−
R10
49.9 W
3
TP1
Vo1
U1A
THS6182
+
2
18
8
2
12.4 W
−V
3
R2 = RF
1.5 k W
R
−V
R3 = Rp
2kW
C2
0.1 mF
TP2
Vout+
C1
V Line
1:n
Line =
100 W
R1
R23=2 RG
750 W
TP4
Vout−
R12 = Rp
2kW
Vo
R
R11 = RF
1.5 k W
J4
Vin2
20
Z2
R18
0W
0W
R19
49.9 W
3-6
13
−
19
R15 = Rs
+
U1B
THS6182
R
12.4 W
TP3
Vo2
2R
6
5
U2B
THS6062
−
7
+
RX Vout−
High-Pass Filter
3.4 High-Pass Filter
Because ADSL CPE is designed to transmit from 25.875 kHz to 138 kHz, C2
and R23 can be used to implement an HPF function. These are selected to be
20X lower than 25 kHz (1.25 kHz). Some designs use a capacitor—some do
not. This path allows for a common gain setting between the two channels.
This helps (but does not assure) the signals are truly differential.
Figure 3−4 compares the frequency spectrum of ADSL to a simulation of the
high-pass filter on the THS6182DWEVM.
Figure 3−4. ADSL Spectrum and High-Pass Filter Response
(Above not on a logarithmic scale)
Note that the high-pass filter function is not a true high-pass filter. C2 in series
with R23 creates a zero at about 10 Hz. As the frequency decreases from
about 3 kHz to 10 Hz, the circuit changes from a gain stage into two unity gain
buffers.
THS6182DWEVM Applications
3-7
Single-Ended Gain Stages
3.5 Single-Ended Gain Stages
Although ADSL is the obvious application for the THS6182DWEVM, it can also
be configured for other applications. If the common gain resistor R8 is
removed, there is an array of components that allow various dc and ac coupled
gain stages to be constructed.
Referring to Figure 3−5, for example, two dc coupled gain stages are formed
by removing R9 and adding R4 and R14. There are many other possibilities.
Figure 3−5. Single-Ended Amplifier Configuration
+V
TP1
J2
IN2
U1A
THS6182
+
2
TP2
18
Z1
0W
R9
8
0W
R10
49.9 W
1
−
3
R5
1.5 k W
R6
R7
12.4 W
49.9 W
J1
OUT1
R2
1.5 k W
−V
J4
IN2
R14
1.5 k W
20
Z2
0W
R18
0W
R19
49.9 W
3-8
TP3
13
−
+
19
U1B
THS6182
R11
1.5 k W
R15
12.4 W
TP4
R16
49.9 W
J3
OUT2
Chapter 4
!"# %
This chapter describes the EVM hardware. It includes the EVM parts list, and
printed circuit-board layout.
Table 4−1. THS6182DWEVM Bill of Materials
Description
SMD
Size
Reference
Designator
Manfacturer’s Part #
Distributor’s Part #
1
Bead, ferrite, 3A, 80 Ω
1206
FB1, FB2
2
(Steward)
HI1206N800R−00
(Digi−Key)
240−1010−1−ND
2
CAP, 22 µF, tantalum, 25 V, 10%
D
C6, C7
2
(AVX) TAJD226K025R
(Garrett)
TAJD226K025R
3
CAP, 0.1 µF, ceramic, X7R, 50 V
0805
C3, C4, C8,
C10
4
(AVX)
08055C104KAT2A
(Garrett)
08055C104KAT2A
4
Open
1206
C1
1
5
CAP, 0.1 µF, ceramic, X7R, 50 V
1206
C2
1
(AVX)
12065C104KAT2A
(Garrett)
12065C104KAT2A
6
CAP, 1.0 µF, ceramic, Y5V, 50 V
1206
C9
1
(AVX)
12065G105ZAT2A
(Garrett)
12065G105ZAT2A
7
Open
0805
R3, R4, R5,
R12, R13, R14
6
8
Resistor, 0 Ω, 1/8 W
0805
R9, R18, R27
3
(Phycomp)
9C08052A0R00JLHFT
(Garrett)
9C08052A0R00JLHFT
9
Resistor, 100 Ω, 1/8 W, 1%
0805
R20, R21
2
(Phycomp)
9C08052A1000FKHFT
(Garrett)
9C08052A1000FKHFT
10
Resistor, 750 Ω, 1/8 W, 1%
0805
R23
1
(Phycomp)
9C08052A7500FKHFT
(Garrett)
9C08052A7500FKHFT
11
Resistor, 1.5 kΩ, 1/8 W, 1%
0805
R2, R11
2
(Phycomp)
9C08052A1501FKHFT
(Garrett)
9C08052A1501FKHFT
12
Resistor, 10 kΩ, 1/8 W, 1%
0805
R24, R25,
R28, R29
4
(Phycomp)
9C08052A1002FKHFT
(Garrett)
9C08052A1002FKHFT
13
Open
1206
R1, R8, R17,
Z3
4
14
Resistor, 0 Ω, 1/4 W
1206
Z1, Z2,
2
(Phycomp)
9C12063A0R00JLHFT
(Garrett)
9C12063A0R00JLHFT
15
Resistor, 12.4 Ω, 1/4 W, 1%
1206
R6, R15
2
(Phycomp)
9C12063A12R4FKRFT
(Garrett)
9C12063A12R4FKRFT
16
Resistor, 49.9 Ω, 1/4 W, 1%
1206
R7, R10, R16,
R19
4
(Phycomp)
9C12063A49R9FKRFT
(Garrett)
9C12063A49R9FKRFT
Item
PCB
QTY
EVM Hardware Description
4-1
Table 4−1. THS6182DWEVM Bill of Material (Continued)
Item
Description
SMD
Size
Reference
Designator
PCB
QTY
Manfacturer’s Part #
Distributor’s Part #
17
Connector, BNC, vertical, PCB
J1, J2, J3, J4
4
(Amphenol) 31−5329
(Newark) 89F2885
18
Jack, banana, 0.25” diameter
hole
J5, J6, J7
3
(HH Smith) 101
(Newark) 35F865
19
Header, 0.1” centers, 0.025”
square pins
JP1, JP2
2
(Sullins) PZC36SAAN
(Digi−Key)
S1011−36−ND
20
Shunts
JP1, JP2
2
(Sullins) SSC02SYAN
(Digi−Key) S9002−ND
21
Test point, black
TP5, TP6, TP7
3
(Keystone) 5001
(Digi−Key) 5001K−ND
22
Test points, red
TP1, TP2, TP3,
TP4, TP8, TP9,
TP10
7
(Keystone) 5000
(Digi−Key) 5000K−ND
23
Standoff, 4−40 hex, 0.625” length
4
(Keystone) 1804
(Allied) 839−2089
24
Screw, Phillips, 4−40, .250”
4
SHR−0440−016−SN
25
IC, THS6182
1
(TI) THS6182DW
26
Printed-circuit board
1
(TI) EDGE #6442073
2
POS.
U1
Figure 4−1. Top Layer 1 (Signals for THS6182DWEVM)
4-2
Figure 4−2. Internal Plane (Layer 2) (Ground 1 Plane)
Figure 4−3. Internal Plane (Layer 3) (Power Plane)
EVM Hardware Description
4-3
Figure 4−4. Bottom (Layer 4) (Ground and Signal)
4-4
