THS6182
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SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
LOW-POWER DISSIPATION ADSL LINE DRIVER
FEATURES
•
•
•
•
•
•
•
•
•
Low-Power Dissipation Increases ADSL Line
Card Density
Low THD of -88 dBc (100 Ω, 1 MHz)
Low MTPR Driving +20 dBm on the Line
– -76 dBc With High Bias Setting
– -74 dBc With Low Bias Setting
Wide Output Swing of 44 VPP Differential Into
a 200-Ω Differential Load (VCC = ±12 V)
High Output Current of 600 mA (Typ)
Wide Supply Voltage Range of ±5 V to ±15 V
Pin Compatible with EL1503C and EL1508C
– Multiple Package Options
Multiple Power Control Modes
– 11 mA/ch Full Bias Mode
– 7.5 mA/ch Mid Bias Mode
– 4 mA/ch Low Bias Mode
– 0.25 mA/ch Shutdown Mode
– IADJ Pin for User Controlled Bias Current
– Stable Operation Down to 1.8 mA/ch
Low Noise for Increased Receiver Sensitivity
– 3.2 nV/√Hz Voltage Noise
– 1.5 pA/√Hz Noninverting Current Noise
– 10 pA/√Hz Inverting Current Noise
APPLICATIONS
•
Ideal for Full Rate ADSL Applications
DESCRIPTION
The THS6182 is a current feedback differential line
driver ideal for full rate ADSL systems. Its extremely
low-power dissipation is ideal for ADSL systems that
must achieve high densities in ADSL central office
rack applications. The unique architecture of the
THS6182 allows the quiescent current to be much
lower than existing line drivers while still achieving
high linearity without the need for excess open loop
gain. Fixed multiple bias settings of the amplifiers
allow for enhanced power savings for line lengths
where the full performance of the amplifier is not
required. To allow for even more flexibility and power
savings, an IADJ pin is available to further lower the
bias currents while maintaining stable operation with
as little as 1.8 mA per channel. The wide output
swing of 44 VPP differentially with ±12-V power
supplies allows for more dynamic headroom, keeping
distortion at a minimum. With a low 3.2 nV/√Hz
voltage noise coupled with a low 10 pA/√Hz inverting
current noise, the THS6182 increases the sensitivity
of the receive signals, allowing for better margins
and reach.
TYPICAL ADSL CO-LINE DRIVER CIRCUIT
USING ACTIVE IMPEDANCE
1 kΩ
+12 V
8.68 Ω
−
CODEC
VIN+
+
THS6182a
−12 V
1.33 kΩ
953 Ω
1:1.2
20-dBm
Line
Power
1.33 kΩ
100 Ω
1 kΩ
+12V
8.68 Ω
−
CODEC
VIN−
+
THS6182b
−12 V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2007, Texas Instruments Incorporated
THS6182
www.ti.com
SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PRODUCT
PACKAGE (1)
THS6182RHF
Leadless 24-pin
4, mm x 5, mm PowerPAD™
RHF-24
THS6182D
SOIC-16
D-16
THS6182
THS6182DW
SOIC-20
DW-20
THS6182
THS6182DWP
SOIC-20 PowerPAD
DWP-20
THS6182
(1)
PACKAGE CODE
SYMBOL
ORDER NUMBER
TRANSPORT MEDIA
THS6182RHFR
Tape and reel
(3000 devices)
THS6182RHFT
Tape and reel
(250 devices)
THS6182D
Tube (40 devices)
THS6832DR
Tape and reel
(2500 devices)
THS6182DW
Tube (25 devices)
THS6182DWR
Tape and reel
(2000 devices)
THS6182DWP
Tube (25 devices)
THS6182DWPR
Tape and reel
(2000 devices)
6182
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
PACKAGE DISSIPATION RATINGS (1)
(1)
(2)
(3)
PACKAGE
PowerPAD SOLDERED (2)
θJA
PowerPAD NOT SOLDERED (3)
θJC
RHF-24 (2)
32°C/W
74°C/W
1.7°C/W
D-16
--
62.9°C/W
25.7°C/W
DW-20
--
45.4°C/W
16.4°C/W
DWP-20 (2)
21.5°C/W
43.9°C/W
0.37°C/W
θJC
θJA values shown are typical for standard test PCBs only.
For high-power dissipation applications, use of the PowerPAD package with the PowerPad on the underside of the chip. This acts as a
heatsink and must be connected to a thermally dissipating plane for proper dissipation. Failure to do so may result in exceeding the
maximum junction temperature which could permanently damage and/or reduce the lifetime the device. See TI technical brief SLMA002
for more information about utilizing the PowerPAD thermally enhanced package.
Use of packages without the PowerPAD or not soldering the PowerPAD to the PCB, should be limited to low-power dissipation
applications.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VCC+to VCC-
2
Supply voltage
Dual supply
±5
±12
±15
Single supply
10
24
30
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SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
ELECTRICAL
THS6132
±16.5 V
VCC
Supply voltage
VI
Input voltage
IO
Output current
VIO
Differential input voltage
±VCC
1000 mA
±2 V
THERMAL
Maximum junction temperature, any condition
TJ
150°C
Maximum junction temperature, continuous operation, long term reliability
Tstg
(2)
125°C
Storage temperature
65°C to 150°C
ESD
ESD ratings
(1)
(2)
HBM
2000 V
CDM
1500 V
MM
200 V
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute-maximum-rated conditions for extended periods may degrade device reliability. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those ispecified is not implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, TA = 25°C, VCC = ±12 V, RF = 2 kΩ,
Gain = +5, IADJ = Bias1 = Bias2 = 0 V, RL = 50 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE/DISTORTION PERFORMANCE
MTPR
Multitone power ratio
Gain = +9.5, 163 kHz to 1.1 MHz DMT,
+20 dBm Line Power, See Figure 1 for circuit
-76
dBc
Receive band spill-over
Gain =+5, 25 kHz to 138 kHz with MTPR signal applied,
See Figure 1 for circuit
-95
dBc
2nd harmonic
HD
Harmonic distortion, VO(PP) = 2 V
f = 1 MHz
3rd harmonic
Vn
Input voltage noise
In
Input current noise
Crosstalk
Differential load = 200 Ω
-88
Differential load = 50 Ω
-70
Differential load = 200 Ω
-107
Differential load = 50 Ω
-84
VCC = ±5 V, ±12 V, ±15 V, f = 100 kHz
+Input
-Input
VCC = ±5 V, ±12 V, ±15 V, f = 100 kHz
f = 1 MHz, VO(PP) = 2 V,
VCC = ±5 V, ±12 V, ±15 V
3.2
1.5
10
dBc
dBc
nV/√Hz
pA/√Hz
RL = 100 Ω
-65
dBc
RL = 25 Ω
-60
dBc
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range, TA = 25°C, VCC = ±12 V, RF = 2 kΩ,
Gain = +5, IADJ = Bias1 = Bias2 = 0 V, RL = 50 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
RL = 100 Ω
±3.9
±4.1
RL = 25 Ω
±3.7
±3.9
RL = 100 Ω
±10.7
±11
±10
±10.6
RL = 100 Ω
±13.5
±13.9
RL = 25 Ω
±12.7
±13.4
VCC = ±5 V
±350
±400
VCC = ±12 V
±450
±600
VCC = ±15 V
±450
±600
MAX
UNIT
OUTPUT CHARACTERISTICS
VCC = ±5 V
VO
Single-ended output voltage swing
VCC = ±12 V
VCC = ±15 V
RL = 5 Ω
IO
Output current
I(SC)
(1)
RL = 10 Ω
RL = 25 Ω
VCC = ±12 V
V
V
V
mA
Short-circuit current (1)
RL = 1 Ω
Output resistance
Open-loop
Output resistance—terminate mode
f = 1 MHz,
Gain = +10
0.05
Ω
Output resistance—shutdown mode
f = 1 MHz,
Open-loop
8.5
kΩ
1000
mA
Ω
6
POWER SUPPLY
VCC
Dual supply
Operating range
Single supply
VCC = ± 5 V
Quiescent current (each driver) (2)
Full-bias mode (Bias-1 = 0,
Bias-2 = 0)
(Trimmed with VCC = ±12 V at 25°C)
ICC
VCC = ± 12 V
VCC = ±15 V
±4
±12
±16.5
8
24
33
9.7
10.7
TA = 25°C
TA = full range
11.7
TA = 25°C
11
TA = full range
TA = 25°C
11.5
TA = full range
7.5
Low; Bias-1 = 0, Bias-2 = 1
Shutdown; Bias-1 = 1, Bias-2 = 1
PSRR
Power supply rejection ratio
12.5
13
Mid; Bias-1 - 1, Bias-2 = 0
Quiescent current (each driver)
Variable bias modes, VCC = ±12 V
12
12.5
VCC = ±5 V,
∆VCC = ±0.5 V
TA = 25°C
-50
TA = full range
-47
VCC = ±12 V, ±15 V,
∆VCC = ±1 V
TA = 25°C
-56
TA = full range
-53
V
mA
mA
mA
8.5
4
5
0.25
0.9
mA
-56
-60
dB
DYNAMIC PERFORMANCE
Gain = +1, RF = 1.2 kΩ
RL = 100 Ω
BW
Single-ended small-signal bandwidth
(-3 dB), VO = 0.1 Vrms
RL = 25 Ω
80
Gain = +5, RF = 1 kΩ
35
Gain = +10, RF = 1 kΩ
20
Gain = +1, RF = 1.5 kΩ
65
Gain = +2, RF = 1 kΩ
60
Gain = +5, RF = 1 kΩ
40
Gain = +10, RF = 1 kΩ
SR
(1)
(2)
(3)
4
Single-ended slew rate
(3)
VO = 10 VPP,
100
Gain = +2, RF = 1 kΩ
Gain = +5
MHz
MHz
22
450
V/µs
A heatsink is required to keep the junction temperature below absolute maximum rating when an output is heavily loaded or shorted.
See Absolute Maximum Ratings section for more information.
Approximately 0.5 mA (total) flows from VCC+ to GND for internal logic control bias.
Slew rate is defined from the 25% to the 75% output levels.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range, TA = 25°C, VCC = ±12 V, RF = 2 kΩ,
Gain = +5, IADJ = Bias1 = Bias2 = 0 V, RL = 50 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
20
UNIT
DC PERFORMANCE
TA = 25°C
Input offset voltage
VOS
TA = full range
VCC = ±5 V, ±12 V, ±15 V
Differential offset voltage
0.5
10
TA = full range
Offset drift
VCC = ±5 V, ±12 V, ±15 V
+Input bias current
µV/°C
50
TA = 25°C
-Input bias current
8
15
TA = full range
20
TA = 25°C
8
15
TA = full range
Open loop transimpedance
mV
15
TA = full range
IIB
ZOL
25
TA = 25°C
µA
20
RL = 1 kΩ, VCC = ±12 V, ±15 V
900
kΩ
INPUT CHARACTERISTICS
VCC = ±5 V
VICR
Input common-mode voltage range
VCC = ±12 V
VCC = ±15 V
CMRR
Common-mode rejection ratio
RI
Input resistance
Ci
Input capacitance
VCC = ±5 V, ±12 V, ±15 V
TA = 25°C
±2.7
TA = full range
±2.6
TA = 25°C
±9.5
TA = full range
±±9.3
TA = 25°C
±12.4
TA = full range
±12.1
TA = 25°C
48
TA = full range
44
±3
V
±9.8
V
±12.7
V
54
dB
+Input
800
-Input
30
kΩ
Ω
1.7
pF
LOGIC CONTROL CHARACTERISTICS
VIH
Bias pin voltage for logic 1
VIL
Bias pin voltage for logic 0
IIH
Bias pin current for logic 1
VIH = 3.3 V, GND = 0 V
4
30
µA
IIL
Bias pin current for logic 0
VIL = 0.5 V, GND = 0 V
1
10
µA
(4)
2
Relative to GND pin voltage
0.8
V
Transition time, logic 0 to logic 1 (4)
1
µs
Transition time, logic 1 to logic 0 (4)
1
µs
Transition time is defined as the time from when the logic signal is applied to the time when the supply current has reached half its final
value.
LOGIC TABLE (1) (2)
(1)
(2)
BIAS-1
BIAS-2
0
0
Full bias mode
FUNCTION
Amplifiers ON with lowest distortion possible (default state)
DESCRIPTION
1
0
Mid bias mode
Amplifiers ON with power savings with a reduction in distortion performance
0
1
Low bias mode
Amplifiers ON with enhanced power savings and a reduction of distortion performance
1
1
Shutdown mode
Amplifiers OFF and output has high impedance
The default state for all logic pins is a logic zero (0).
The GND pin useable range is from VCC- to (VCC+ - 4 V).
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SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
RG 750 Ω
+18 V
4.87 Ω
−
CODEC
+
V IN+
THS6182a
1 kW
RG
1.33 kW
1:1.6
20-dBm
Line
Power
100 Ω
1 kW
RF 750 Ω
+18 V
4.87 Ω
−
CODEC
+
V IN−
THS6182b
Figure 1. Single-Supply ADSL CO Line Driver Circuit Utilizing Active Impedance (SF = 4)
PIN ASSIGNMENTS
19
D2 OUT
VCC − 3
18
VCC +
17
GND
GND
GND
A.
6
4
5
16
GND
16
D2 IN−
D1 OUT
D1 IN− 1
2
15
D2 OUT
V CC −
3
14
GND
4
13
VCC +
GND
GND
5
12
GND
GND
6
15
GND
D1 IN+
6
11
D2 IN+
GND
7
14
GND
BIAS−2
7
10
I ADJ
D1 IN+
8
13
D2 IN+
BIAS−1
8
9
BIAS−2
9
12
I ADJ
BIAS−1
10
11
N/C
N/C
N/C
1
24 23 22 21 20
19
N/C
VCC−
2
3
18
17
N/C
N/C
N/C
GND
4
5
Power
PAD TM
6
7
16
15
14
13
8
9 10 11 12
BIAS−2
2
N/C
N/C
VCC+
N/C
N/C
N/C
GND
BIAS−1
I
ADJ
D2IN+
D1 OUT
N/C
D2 IN−
D2 OUT
D2 IN−
20
D1 IN−
1
THS6182
Leadless 24−pin PowerPAD
4 mm X 5 mm (RHF) PACKAGE
(TOP VIEW)
D1 OUT
D1 IN−
THS6182
SOIC−16 (D) PACKAGE
(TOP VIEW)
D1IN+
THS6182
SOIC−20 (DW) AND
SOIC−20 PowerPAD (DWP) PACKAGES
(TOP VIEW)
The PowerPAD is electrically isolated from all active circuity and pins. Connection of the PowerPAD to the PCB
ground plane is highly recommended, although not required, as this plane is typically the largest copper plane on a
PCB. The thermal performance will be better with a large copper plane than a small one.
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Output voltage headroom
vs Output current
2
Common-mode rejection ratio
vs Frequency
3
Crosstalk
vs Frequency
4
Total quiescent current
5
Large signal output amplitude
vs Frequency
Voltage and current noise
vs Frequency
6-8
9
Overdrive recovery
10
Power supply rejection ratio
vs Frequency
11
Output amplitude
vs Frequency
12-37
Slew rate
vs Output voltage
38
Closed-loop output impedance
vs Frequency
39
vs Supply voltage
40
vs Temperature
41
Common-mode rejection ratio
vs Common-mode voltage
42
Input bias current
vs Temperature
43
Input offset voltage
vs Temperature
2nd Harmonic distribution
vs Frequency
45-52
3rd Harmonic distribution
vs Frequency
53-60
2nd Harmonic distribution
vs Output voltage
61-64
3rd Harmonic distribution
vs Output voltage
65-68
Quiescent current
COMMON-MODE REJECTION
RATIO
vs
FREQUENCY
OUTPUT VOLTAGE HEADROOM
vs
OUTPUT CURRENT
2.5
CROSSTALK
vs
FREQUENCY
0
80
VCC = ±12 V
Gain = 2
RL= 25 Ω
70
2
VCC = ±5 V
1
50
40
30
0
2 00
400
600
O ut p ut C ur r ent − mA
Figure 2.
800
−30
−40
Gain = +1
−60
−70
10
−80
0
10 k
Gain = +5
−50
20
0.5
0
VCC = ±12 V
RL= 100 Ω
−20
Crosstalk −dB
1.5
−10
60
VCC = ±12 V
CMRR −dB
Output Voltage Headroom −(VCC−Vout)
44
−90
100 k
1M
10 M
f − Frequency − Hz
Figure 3.
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100 k
1M
10 M
100 M
f − Frequency − Hz
Figure 4.
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LARGE SIGNAL OUTPUT
AMPLITUDE
vs
FREQUENCY
Large Signal Output Amplitude −dB(VPP )
15
M id Bias Mo de
10
Lo w Bias Mo de
0
10
0
VO = 0.5 VPP
−6
−12
VO = 0.25 VPP
−18
100 k
1M
10 M
100 M
f − Frequency − Hz
VO = 2 VPP
6
VO = 1 VPP
VO = 0.5 VPP
−6
In−
10 0
100
10
10
Vn
In+
1
10
1M
10 M
100 M
f f − Frequency − Hz
3
15
VCC= ±12 V
Gain = 5
RL= 100 Ω
10
1
5
0
0
Vin
−1
−5
−2
1
100 k
−10
Vo ut
−3
−15
0 .0
0 .5
1.0
Figure 8.
Figure 9.
Figure 10.
POWER SUPPLY REJECTION
RATIO
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
2
1
0
Output Amplitude −dB
Vcc+
50
Vcc−
30
20
VCC = ±12 V
Gain = 5
RF = 500 Ω
RL = 100 Ω
10k
Figure 11.
100M
1
RF = 2 k
−3
−4
RF = 1 k
0
−1
−6
10M
RF = 1.2 k
RF = 1 k
−2
−5
100k
1M
f −Freq uency −Hz
2
Output Amplitude −dB
70
40
1G
Time (µ S)
60
−10
1k
100
1k
10 k
f − Frequency − Hz
1G
80
0
VO = 0.25 VPP
−12
2
VO = 0.25 VPP
10
VO = 0.5 VPP
−6
OVERDRIVE RECOVERY
1000
−12
1M
10 M
100 M
f − Frequency − Hz
VO = 1 VPP
0
Figure 7.
10 0 0
0
VO = 2 VPP
6
100 k
Hz
12
VO = 4 VPP
12
−18
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
VCC = ± 5 V
Gain = 5
RF = 750 Ω
RL= 25 Ω
Full Bias
VO = 8 VPP
18
1G
LARGE SIGNAL OUTPUT
AMPLITUDE
vs
FREQUENCY
VO = 4 VPP
100 k
PSSR −Power Supply Rejection Ratio −dB
VO = 1 VPP
Figure 6.
−18
8
6
Figure 5.
18
Large Signal Output Amplitude −dB(VPP)
100
VO = 2 VPP
Input Voltage −V
0.1
1
R s et t o G N D − k Ω
Vn − Voltage Noise − nV/
0.01
VO = 4 VPP
12
VCC = ±12V
Gain = 10
RF = 500 Ω
RL= 100 Ω
Full Bias
VO = 16 VPP
24
Hz
5
18
I n − Current Noise − pA/
Total Quiescent Current (mA)
Full Bias M o d e
20
30
VCC= ±12 V
Gain = 5
RF = 500 Ω
RL= 100 Ω
Full Bias
VO = 8 VPP
Output Voltage −V
24
VCC= ±12 V
Large Signal Output Amplitude −dB(VPP)
TOTAL QUIESCENT CURRENT
25
LARGE SIGNAL OUTPUT
AMPLITUDE
vs
FREQUENCY
VCC = ±15 V
Gain = 1
RL = 25 Ω
VO = 0.1 Vrms
Full Bias
−7
100 k
RF = 1.2 k
−1
RF = 2 k
−2
−3
−4
−5
−6
VCC = ±15 V
Gain = 1
RL = 100 Ω
VO = 0.1 Vrms
Full Bias
−7
1M
10 M
100 M
f − Frequency − Hz
Figure 12.
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100 k
1M
10 M
100 M
f − Frequency − Hz
Figure 13.
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OUTPUT AMPLITUDE
vs
FRQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
16
16
15
15
RF = 750
RF = 500
21
RF = 750
RF = 500
RF = 1 k
12
11
RF = 2 k
10
VCC = ±15 V
Gain = 5
RL = 25 Ω
VO = 0.1 Vrms
Full Bias
9
8
7
100 k
13
12
11
10
9
8
1M
10 M
100 M
f − Frequency − Hz
VCC = ±15 V
Gain = 5
RL = 100 Ω
VO = 0.1 Vrms
Full Bias
7
100 k
1G
19
Output Amplitude −dB
13
RF = 500
20
14
Output Amplitude −dB
Output Amplitude −dB
14
OUTPUT AMPLITUDE
vs
FREQUENCY
RF = 1 k
RF = 2 k
18
17
RF = 1 k
16
15
14
13
VCC = ±15 V
Gain = 10
RL = 25 Ω
VO = 0.1 Vrms
Full Bias
12
100 k
1M
10 M
RF = 2 k
1M
100 M
10 M
f − Frequency − Hz
Figure 14.
Figure 15.
Figure 16.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
21
2
20
1
2
RF = 1.2 k
RF = 500
VCC = ±15 V
Gain = 10
RL = 100 Ω
VO = 0.1 Vrms
Full Bias
12
100 k
RF = 2 k
1M
−5
10 M
100 M
VCC = ±12 V
Gain = 1
RL = 100 Ω
VO= 0.1 Vrms
Full Bias
−7
100 k
1G
1M
10 M
100 M
f − Frequency − Hz
Figure 18.
Figure 19.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
RF = 750
RF = 500
RF = 1 k
7
6
RF = 2 k
VCC = ±12 V
Gain = 2
RL = 25 Ω
VO = 0.1 Vrms
Full Bias
3
1
1M
10 M
100 M
f − Frequency − Hz
1G
RF = 2 k
0
−3
VCC = ±12 V
Gain = 2
RL = 100 Ω
VO = 0.1 Vrms
Full Bias
−9
100 k
1M
13
f − Frequency − Hz
Figure 21.
Submit Documentation Feedback
1G
RF = 2 k
11
10
8
100 M
RF = 1 k
12
9
10 M
RF = 500
14
6
−6
Figure 20.
15
9
RF = 500
1G
16
RF = 825
100 k
−4
−6
12
5
RF = 2 k
−3
f − Frequency − Hz
Output Amplitude −dB
Output Amplitude −dB
VCC = ±12 V
Gain = 1
RL = 25 Ω
VlO = 0.1 Vrms
Full Bias
−1
−2
Figure 17.
8
2
−4
−7
100 k
100 M
9
3
−3
−6
1M
10 M
f − Frequency − Hz
RF = 2 k
−2
−5
10
4
−1
Output Amplitude −dB
13
RF = 1 k
0
Output Amplitude −dB
Output Amplitude −dB
Output Amplitude −dB
17
14
RF = 1 k
0
18
16
RF = 1.2 k
1
RF = 1 k
19
15
100 M
f − Frequency − Hz
7
100 k
VCC = ±12 V
Gain = 5
RL = 25 Ω
VO = 0.1 Vrms
Full Bias
1M
10 M
f − Frequency − Hz
100 M
Figure 22.
9
THS6182
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SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
16
RF = 500
RF = 2 k
11
VCC = ±12 V
Gain = 5
RL = 25 Ω
VO = 0.1 Vrms
Mid Bias
7
100 k
RF = 2 k
11
VCC = ±12 V
Gain = 5
RL = 25 Ω
VO = 0.1 Vrms
Low Bias
10
7
100 k
RF = 2 k
VCC = ±12 V
Gain = 5
RL = 100 Ω
VO = 0.1 Vrms
Mid Bias
15
20
14
19
13
RF = 500
11
9
8
1M
10 M
f − Frequency − Hz
RF = 1 k
12
10
RF = 2 k
VCC = ±12 V
Gain = 5
RL = 100 Ω
VO = 0.1 Vrms
Low Bias
7
100 k
100 M
RF = 500
18
RF = 1 k
17
RF = 2 k
16
VCC = ±12 V
Gain = 10
RL = 25 Ω
VO = 0.1 Vrms
Full Bias
15
14
13
1M
10 M
f − Frequency − Hz
12
100 k
100 M
1M
10 M
Figure 27.
Figure 28.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
16
16
15
15
RF = 500
19
RF = 1 k
16
RF = 2 k
VCC = ±12 V
Gain = 10
RL = 100 Ω
VO = 0.1 Vrms
Full Bias
1M
10 M
f − Frequency − Hz
Figure 29.
13
RF = 1 k
12
11
10
9
8
100 M
Output Amplitude −dB
Output Amplitude −dB
17
7
100 k
RF = 500
14
14
18
100 M
f − Frequency − Hz
Figure 26.
RF = 500
Output Amplitude −dB
Output Amplitude −dB
Output Amplitude −dB
RF = 1 k
20
10
100 M
21
RF = 750
RF = 500
12
100 k
10 M
OUTPUT AMPLITUDE
vs
FREQUENCY
21
13
1M
f − Frequency − Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
11
14
7
100 k
100 M
RF = 2 k
VCC = ±12 V
Gain = 5
RL = 100 Ω
VO = 0.1 Vrms
Full Bias
OUTPUT AMPLITUDE
vs
FREQUENCY
13
15
8
16
7
100 k
11
10
9
1M
10 M
f − Frequency − Hz
RF = 1 k
12
Figure 25.
RF = 750
12
13
Figure 24.
14
Output Amplitude −dB
12
100 M
RF = 500
Figure 23.
15
8
RF = 1 k
8
16
9
13
9
1M
10 M
f − Frequency − Hz
RF = 750
14
Output Amplitude −dB
Output Amplitude −dB
Output Amplitude −dB
RF = 1 k
12
10
15
14
13
8
RF = 750
RF = 500
15
14
9
16
16
RF = 750
15
10
OUTPUT AMPLITUDE
vs
FREQUENCY
VCC= ±12 V
Gain = −5
RL = 25 Ω
VO = 0.1 Vrms
Full Bias
13
RF = 1 k
12
11
10
9
8
1M
10 M
f − Frequency − Hz
Figure 30.
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100 M
VCC = ±12 V
Gain = −5
RL = 100 Ω
VO = 0.1 Vrms
Full Bias
7
100 k
1M
10 M
f − Frequency − Hz
Figure 31.
100 M
THS6182
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SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
OUTPUT AMPLITUDE
vs
FREQUENCY
3
RF = 1.2 k
2
RF = 1 k
0
−1
RF = 2 k
−2
VCC = ±5 V
Gain = 1
RL = 25 Ω
VO = 0.1 Vrms
Full Bias
−3
−4
−5
−6
100 k
1M
RF = 2 k
−2
−3
VCC = ±5 V
Gain = 1
RL = 100 Ω
VO = 0.1 Vrms
Full Bias
−5
−6
100 k
1G
RF = 750
14
0
−1
−4
10 M
100 M
f − Frequency − Hz
RF = 500
15
RF = 1.2 k
1
Output Amplitude −dB
Output Amplitude −dB
16
RF = 1 k
2
1
OUTPUT AMPLITUDE
vs
FREQUENCY
Output Amplitude −dB
3
OUTPUT AMPLITUDE
vs
FREQUENCY
13
RF = 2 k
12
11
10
VCC = ±5 V
Gain = 5
RL = 25 Ω
VO = 0.1 Vrms
Full Bias
9
8
1M
10 M
100 M
7
100 k
1G
1M
f − Frequency − Hz
10 M
100 M
f − Frequency − Hz
Figure 32.
Figure 33.
Figure 34.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
16
21
21
RF = 500
15
RF = 500
20
RF = 500
20
RF = 750
19
13
RF = 1 k
12
RF = 2 k
11
10
VCC = ±5 V
Gain = 5
RL = 100 Ω
VO = 0.1 Vrms
Full Bias
9
8
18
RF = 1 k
17
RF = 2 k
16
15
VCC = ±5 V
Gain = 10
RL = 25 Ω
VO = 0.1 Vrms
Full Bias
14
13
1M
10 M
100 M
100 k
f − Frequency − Hz
RF = 1 k
17
16
RF = 2 k
15
VCC = ±5 V
Gain = 10
RL = 25 Ω
VlO = 0.1 Vrms
Full Bias
13
1M
10 M
12
100 k
100 M
1M
10 M
Figure 35.
Figure 36.
Figure 37.
SLEW RATE
vs
OUTPUT VOLTAGE
CLOSED LOOP OUTPUT
IMPEDANCE
vs
FREQUENCY
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
25
400
SR−
300
200
100
0
5
10
15
Output Voltage − Vp−p
Figure 38.
20
Ta = 25 deg.C
Icc+ (Full)
Shutdown
100
Total Quiescent Current −mA
Zo −Closed Loop Output Impedance −Ohms
1000
SR+
100 M
f − Frequency − Hz
f − Frequency − Hz
500
0
18
14
12
7
100 k
Slew−Raie (V/us)
Output Amplitude −dB
19
Output Amplitude −dB
Output Amplitude −dB
14
Mid Bias
10
Low Bias
1
VCC = ± 12 V
Gain = 10
RL = 500 Ω
Full Bias
0.1
20
Icc− (Full)
Icc+ (Mid)
15
A
Icc− (Mid)
10
Icc+ (Low)
Icc− (Low)
5
Icc− (SD)
Icc+ (SD)
0.01
100 k
1M
10 M
f − Frequency − Hz
Figure 39.
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100 M
3
5
9
13
7
11
Supply Voltage − +/−Vcc
15
Figure 40.
11
THS6182
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SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
QUIESCENT CURRENT
vs
TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
COMMON-MODE VOLTAGE
25
13
90
Vcc = +/−15 V
Common−Mode Rejection Ratio −dB
Icc+ (Full)
Icc− (Full)
20
Icc+ (Mid)
15
Icc− (Mid)
10
Icc+ (Low)
Icc− (Low)
Icc− (SD)
5
Icc+ (SD)
−20
12
−40 Deg C
70
85 Deg C
60
25 Deg C
50
40
30
0
20
40
60
Temperature − Deg.C
80
−14
100
11
Iib−
10
9
8
−10
−6
−2
2
6
10
Common−Mode Voltage − V
6
−40
14
100
INPUT OFFSET VOLTAGE
vs
TEMPERATURE
2ND HARMONIC DISTORTION
vs
FREQUENCY
2ND HARMONIC DISTORTION
vs
FREQUENCY
−40
−40
−50
Vio − Channel A
Differential configuration
−50
Low Bias
Low Bias
4.5
4
Vio − Channel B
−20
0
20
40
60
Temperature − Deg C
80
Full Bias
−80
VCC = ±12 V
Gain = 10
RL = 200 Ω
RF = 1 kΩ
VO= 2 VPP
−100
100 k
100
1M
10 M
f − Frequency − Hz
−60
Full Bias
Mid Bias
−70
−80
VCC = ±5 V
Gain = 10
RL = 200 Ω
RF = 1 kΩ
VO = 2 VPP
−90
−100
100 k
100 M
1M
10 M
f − Frequency − Hz
100 M
Figure 44.
Figure 45.
Figure 46.
2ND HARMONIC DISTORTION
vs
FREQUENCY
2ND HARMONIC DISTORTION
vs
FREQUENCY
2ND HARMONIC DISTORTION
vs
FREQUENCY
−45
−45
Differential configuration
−55
−55
Mid Bias
Low Bias
−70
−75
−80
100 k
Full Bias
1M
Differential configuration
VCC = ±12 V
Gain = 10
RL = 50 Ω
RF = 1 kΩ
VO = 2 VPP
10 M
f − Frequency − Hz
Figure 47.
−50
−60
−65
Low Bias
−70
−75
100 M
−80
100 k
Low Bias
−60
Mid Bias
2nd HD −dBc
2nd HD −dBc
−50
−60
−40
Differential configuration
−50
−65
Mid Bias
−70
−90
3
−40
2nd HD −dBc
−60
2nd HD −dBc
Input Offset Voltage −mV
80
Figure 43.
3.5
2nd HD −dBc
0
20
40
60
Temperature − Deg C
Figure 42.
Differential configuration
12
−20
Figure 41.
5.5
5
Iib+
7
20
0
−40
80
Input Bias Current −uA
Vcc = +/−12 V
Total Quiescent Current −mA
INPUT BIAS CURRENT
vs
TEMPERATURE
Full Bias
VCC = ±5 V
Gain = 10
RL = 50 Ω
RF = 1 kΩ
VO = 2 VPP
1M
10 M
f − Frequency − Hz
Figure 48.
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−70
Mid Bias
Full Bias
−80
VCC = ±12 V
Gain = 5
RL = 200 Ω
RF = 1 kΩ
VO = 2 VPP
−90
100 M
−100
100 k
1M
10 M
f − Frequency − Hz
Figure 49.
100 M
THS6182
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SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
2ND HARMONIC DISTORTION
vs
FREQUENCY
2ND HARMONIC DISTORTION
vs
FREQUENCY
−45
−40
Differential configuration
−50
−50
−55
−55
Full Bias
VCC = ±5 V
Gain = 5
RL = 200 Ω
RF = 1 kΩ
VO = 2 VPP
−80
1M
10 M
f − Frequency − Hz
−60
Mid Bias
−65
−70
Low Bias
VCC = ±12 V
Gain = 5
RL = 50 Ω
RF = 1 kΩ
VO = 2 VPP
−75
Full Bias
−80
−85
100 k
100 M
2nd HD −dBc
Mid Bias
2nd HD −dBc
1M
10 M
−60
Mid Bias
−65
Low Bias
−70
VCC = ±5 V
Gain = 5
RL = 50 Ω
RF = 1 kΩ
VO = 2 VPP
−75
Full Bias
−80
−85
100 k
100 M
1M
10 M
f − Frequency − Hz
f − Frequency − Hz
100 M
Figure 50.
Figure 51.
Figure 52.
3RD HARMONIC DISTORTION
vs
FREQUENCY
3RD HARMONIC DISTORTION
vs
FREQUENCY
3RD HARMONIC DISTORTION
vs
FREQUENCY
−30
−30
VCC = ±12 V
Gain = 10
RL = 200 Ω
RF = 1 kΩ
VO = 2 VPP
Low Bias
−50
−60
Low Bias
−70
−50
−60
Full Bias
Mid Bias
−70
VCC = ±5 V
Gain = 10
RL = 200 Ω
RF = 1 kΩ
VO = 2 VPP
Full Bias
Mid Bias
−80
−90
−90
Differential configuration
−100
100 k
Differential configuration
−40
Low Bias
1M
10 M
f − Frequency − Hz
−100
100 k
100 M
3rd HD −dBc
−50
−40
3rd HD −dBc
−40
−30
Differential configuration
1M
10 M
f − Frequency − Hz
−60
Mid Bias
−70
Full Bias
VCC = ±5 V
Gain = 10
RL = 50 Ω
RF = 1 kΩ
VO = 2 VPP
−80
−90
−100
100 k
100 M
1M
10 M
f − Frequency − Hz
100 M
Figure 53.
Figure 54.
Figure 55.
3RD HARMONIC DISTORTION
vs
FREQUENCY
3RD HARMONIC DISTORTION
vs
FREQUENCY
3RD HARMONIC DISTORTION
vs
FREQUENCY
−30
−30
−30
Differential configuration
Differential configuration
−40
−40
Low Bias
−50
−70
−80
−90
−100
100 k
3rd HD −dBc
−50
−60
−40
Low Bias
Mid Bias
Full Bias
VCC = ±12 V
Gain = 10
RL = 50 Ω
RF = 1 kΩ
VO = 2 VPP
1M
10 M
f − Frequency − Hz
Figure 56.
−60
−70
−80
−90
100 M
−50
3rd HD −dBc
2nd HD −dBc
−70
−100
100 k
3rd HD −dBc
Differential configuration
−50
Low Bias
−90
3rd HD −dBc
−45
Differential configuration
−60
−80
2ND HARMONIC DISTORTION
vs
FREQUENCY
−100
100 k
Mid Bias
Full Bias
Figure 57.
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Low Bias
−60
−70
Mid Bias
VCC = ±12 V
Gain = 5
RL = 200 Ω
RF = 1 kΩ
VO = 2 VPP
1M
10 M
f − Frequency − Hz
VCC = ±5 V
Gain = 5
RL = 200 Ω
RF = 1 kΩ
VO = 2 VPP
−80
Full Bias
−90
Differential configuration
100 M
−100
100 k
1M
10 M
f − Frequency − Hz
100 M
Figure 58.
13
THS6182
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SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
3RD HARMONIC DISTORTION
vs
FREQUENCY
3RD HARMONIC DISTORTION
vs
FREQUENCY
−30
−30
−80
Low Bias
−50
Mid Bias
−70
Full Bias
−80
−60
−70
Full Bias
Mid Bias
VCC = ±5 V
Gain = 5
RL 50 Ω
RF = 1 kΩ
VO = 2 VPP
−80
−90
−90
Differential configuration
−100
100 k
Differential configuration
Low Bias
−40
1M
10 M
−100
100 k
100 M
2nd HD −dBc
−60
VCC = ±12 V
Gain = 5
RL = 50 Ω
RF = 1 kΩ
VO = 2 VPP
3rd HD −dBc
3rd HD −dBc
−50
−75
Differential configuration
Low Bias
−40
2ND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
Mid Bias
−90
Full Bias
VCC = ±12 V
Gain = 5
RL = 200 Ω
RF = 1 kΩ
f = 1 MHz
−95
−100
1M
10 M
f − Frequency − Hz
f − Frequency − Hz
−85
100 M
0
5
10 15 20
25 30
Output Voltage − Vpp
35
Figure 59.
Figure 60.
Figure 61.
2ND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
2ND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
2ND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−75
−65
40
−65
Low Bias
Low Bias
Differential configuration
Low Bias
−85
Mid Bias
−90
VCC = ±5 V
Gain = 5
RL = 200 Ω
RF = 1 kΩ
f = 1 MHz
Full Bias
−95
−70
−70
Mid Bias
Full Bias
VCC = ±12 V
Gain = 5
RL = 50 Ω
RF = 1 kΩ
f = 1 MHz
−75
−100
2nd HD −dBc
2nd HD −dBc
2nd HD −dBc
−80
−80
0
5
Output Voltage − Vpp
10
Mid Bias
Full Bias
−75
VCC = ±5 V
Gain = 5
RL = 50 Ω
RF = 1 kΩ
f = 1 MHz
−80
0
5
10
15
20
Output Voltage − Vpp
25
30
0
2
4
6
Figure 62.
Figure 63.
Figure 64.
3RD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
3RD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
3RD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
−70
−65
−70
−75
−75
Low Bias
Mid Bias
−90
Full Bias
−95
VCC = ±5 V
Gain = 5
RL = 200 Ω
RF = 1 kΩ
f = 1 MHz
Full Bias
−95
VCC = ±12 V
Gain = 5
RL = 200 Ω
RF = 1 kΩ
f = 1 MHz
2
4
6
8
10
−80
−85
Mid Bias
−90
Full Bias
−95
Differential configuration
−100
0
14
Mid Bias
−85
−90
−100
−75
Low Bias
−80
3rd HD −dBc
3rd HD −dBc
3rd HD −dBc
Low Bias
−80
10
VCC = ±12 V
Gain = 5
RL = 50 Ω
RF = 1 kΩ
f = 1 MHz
Differential configuration
Differential configuration
−85
8
Output Voltage − Vpp
−100
Output Voltage − Vpp
0
5
10
15 20 25 30
Output Voltage − Vpp
Figure 65.
Figure 66.
35
Submit Documentation Feedback
40
0
5
10
15
20
Output Voltage − Vpp
Figure 67.
25
30
THS6182
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SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
3RD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−65
Differential configuration
−70
Low Bias
Mid Bias
3rd HD −dBc
−75
−80
−85
−90
Full Bias
−95
VCC = ±5 V
Gain = 5
RL = 50 Ω
RF = 1 kΩ
f = 1 MHz
−100
0
2
4
6
Output Voltage − Vpp
8
10
Figure 68.
Submit Documentation Feedback
15
THS6182
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SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
APPLICATION INFORMATION
The THS6182 contains two independent operational amplifiers. These amplifiers are current feedback topology
amplifiers made for high-speed operation. They have been specifically designed to deliver the full power
requirements of ADSL and therefore can deliver output currents of at least 400 mA at full output voltage.
The THS6182 is fabricated using Texas Instruments 30-V complementary bipolar process, HVBiCOM. This
process provides excellent isolation and high slew rates that result in the device's excellent crosstalk and
extremely low distortion.
DEVICE PROTECTION FEATURE
The THS6182 has a built-in thermal protection feature. Should the internal junction temperature rise above
approximately 160°C, the device automatically shuts down. Such a condition could exist with improper heat
sinking or if the output is shorted to ground. When the abnormal condition is fixed, the internal thermal shutdown
circuit automatically turns the device back on. This occurs at approximately 145°C, junction temperature. Note
that the THS6182 does not have short-circuit protection and care should be taken to minimize the output current
below the absolute maximum ratings.
THERMAL INFORMATION
The THS6182 is available in a thermally-enhanced DWP and RHF package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 69(a) and Figure 69(b), for the DWP package example]. This arrangement results in the
lead frame being exposed as a thermal pad on the underside of the package [see Figure 69(c)]. Because this
thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing
a good thermal path away from the thermal pad. Note that the PowerPAD is electronically isolated from the
active circuitry and any pins. Thus, the PowerPAD can be connected to any potential voltage within the absolute
maximum voltage range. Ideally, connection of the PAD to the ground plane is preferred as the plane typically is
the largest copper plane on a PCB.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device. This
is discussed in more detail in the PCB design considerations section of this document.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
A.
The thermal pad is electrically isolated from all terminals in the package.
Figure 69. Views of Thermally Enhanced DWP Package
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APPLICATION INFORMATION (continued)
RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES
As with all current feedback amplifiers, the bandwidth of the THS6182 is an inversely proportional function of the
value of the feedback resistor. The recommended resistors with a ±12-V power supply for the optimum
frequency response with a 25-Ω load system is 1 kΩ for a gain of 5. These should be used as a starting point
and once optimum values are found, 1% tolerance resistors should be used to maintain frequency response
characteristics.
Consistent with current feedback amplifiers, increasing the gain is best accomplished by changing the gain
resistor, not the feedback resistor. This is because the bandwidth of the amplifier is dominated by the feedback
resistor value and internal dominant-pole capacitor. The ability to control the amplifier gain independently of the
bandwidth constitutes a major advantage of current feedback amplifiers over conventional voltage feedback
amplifiers.
It is important to realize the effects of the feedback resistance on distortion. Increasing the resistance decreases
the loop gain and increases the distortion. It is also important to know that decreasing load impedance increases
total harmonic distortion (THD). Typically, the third order harmonic distortion increases more than the second
order harmonic distortion.
Finally, in a differential configuration as shown in Figure 1, it is important to note that there is a differential gain
and a common-mode gain which are different from each other. Differentially, the gain is at 1 + RF/RG. While
common-mode gain = 1 due to RG being connected directly between each amplifier and not to ground. This can
lead to potential problems as the stability of the amplifier is determined by RF. Thus, RF must be large enough to
ensure the common-mode stability, even though a large differential gain may be required.
OFFSET VOLTAGE
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB)
times the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
Figure 70. Output Offset Voltage Model
NOISE CALCULATIONS
Noise can cause errors on very small signals. This is especially true for the amplifying small signals. The noise
model for current feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only
difference between the two is that the CFB amplifiers generally specify different current noise parameters for
each input while VFB amplifiers usually only specify one noise current parameter. The noise model is shown in
Figure 71. This model includes all of the noise sources as follows:
• en = Amplifier internal voltage noise (nV/√Hz)
• IN+ = Noninverting current noise (pA/√Hz)
• IN- = Inverting current noise (pA/√Hz)
• eRX = Thermal voltage noise associated with each resistor (eRX = 4 kTRx)
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APPLICATION INFORMATION (continued)
eRs
RS
en
Noiseless
+
_
eni
eno
IN+
IN−
eRf
RF
eRg
RG
Figure 71. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
e
Where:
ni
+
Ǹ
ǒenǓ ) ǒIN )
2
R
Ǔ
S
2
ǒ
) IN–
ǒR F ø R G ǓǓ
2
ǒ
) 4 kTRs ) 4 kT R ø R
F
G
Ǔ
k = Boltzmann’s constant = 1.380658 × 10−23
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and RG
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
R
e no + e A + e ni 1 ) F (Noninverting Case)
ni V
RG
ǒ
Ǔ
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term.
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS6182 has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device's phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 72. A minimum value of 2 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
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APPLICATION INFORMATION (continued)
1 kΩ
1 kΩ
Input
_
2Ω
Output
THS6182
+
CLOAD
Figure 72. Driving a Capacitive Load
PCB DESIGN CONSIDERATIONS
Proper PCB design techniques in two areas are important to assure proper operation of the THS6182. These
areas are high-speed layout techniques and thermal-management techniques. Because the THS6182 is a
high-speed part, the following guidelines are recommended.
• Ground plane - It is essential that a ground plane be used on the board to provide all components with a low
inductive ground connection. Although a ground connection directly to a terminal of the THS6012 is not
necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves
two functions. It provides a low inductive ground to the device substrate to minimize internal crosstalk and it
provides the path for heat removal. Note that the BiCom process is a SOI process and thus, the substrate is
isolated from the active circuitry.
• Input stray capacitance - To minimize potential problems with amplifier oscillation, the capacitance at the
inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane should be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This is
especially true in the noninverting configuration.
• Proper power supply decoupling - Use a minimum of a 6.8-µF tantalum capacitor in parallel with a 0.1-µF
ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several
amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply
terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the
supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power terminal
and the ceramic capacitors.
• For a differential configuration as shown in Figure 1, it is recommended that a 0.1-µF or 1-µF capacitor be
added across the power supplies (from VCC+ to VCC- ) as close as possible to the THS6182. This allows for
differential currents to flow properly, signficantly reducing even-order harmonic distortion. The 0.1-µF
capacitors to ground should also be used as previously stipulated.
Because of its power dissipation, proper thermal management of the THS6182 is required. Although there are
many ways to properly heatsink this device, the following steps illustrate one recommended approach for a
multilayer PCB with an internal ground plane utilizing the 20 pin DWP PowerPAD package.
1. Prepare the PCB with a top side etch pattern as shown in Figure 73. There should be etch for the leads
as well as etch for the thermal pad.
2. Place 18 holes in the area of the thermal pad. These holes should be 13 mils in diameter. They are kept
small so that solder wicking through the holes is not a problem during reflow.
3. It is recommended, but not required, to place six more holes under the package, but outside the thermal
pad area. These holes are 25 mils in diameter. They may be larger because they are not in the area to be
soldered so that wicking is not a problem.
4. Connect all 24 holes, the 18 within the thermal pad area and the 6 outside the pad area, to the internal
ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the
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APPLICATION INFORMATION (continued)
heat transfer during soldering operations. This makes the soldering of vias that have plane connections
easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer.
Therefore, the holes under the THS6182 package should make their connection to the internal ground
plane with a complete connection around the entire circumference of the plated through hole.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area
with its five holes. The four larger holes outside the thermal pad area, but still under the package, should
be covered with solder mask.
7. Apply solder paste to the exposed thermal pad area and all of the operational amplifier terminals.
8. With these preparatory steps in place, the THS6182 DWP is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
0.080
0.026
0.024
0.1025
0.476
0.120
0.085
0.178
0.450
0.0165
0.021
PowerPAD and via placement
pad area (0.085 x 0.120) with 15
vias (Via diameter = 0.013)
.039
0.026
Vias should go through the board connecting the top layer
PowerPad to any and all ground planes. (The larger the ground
plane, the larger the area to distribute the heat.) Solder resist should
be used on the bottom side ground plane in order to prevent wicking
of the solder through the vias during the reflow process.
All Units in Inches
Figure 73. 20-Pin DWP PowerPAD PCB Etch and Via Pattern
The RHF package is similar to the DWP package with respect to PCB mounting procedures. The recommended
PCB layout is as shown in Figure 74.
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APPLICATION INFORMATION (continued)
0.4953
0.1905
Pad size
24 x (0.3048 x 0.762) mm
0.3721
0.1905
0.4953
2.2987
0.3641
4.9022
3.302
5.9182
PowerPAD and Via layout
(Pad size 3.65 mm x 2.65 mm ,
9 Vias with diameter = 0.254 mm)
0.682
1.143
0.563
2.65
0.762
3.65
Vias should go through the board connecting the top layer PowerPAD to any and all
ground planes. The larger the ground plane, the more area to distribute the heat.
Solder resist should be used on the bottom side ground plane to prevent wicking of
the solder through the vias during the reflow process.
Figure 74. Suggested PCB Layout
The actual thermal performance achieved with the THS6182 in the 20-pin DWP PowerPAD package depends on
the application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3
inches, then the expected thermal coefficient, ΘJA, is about 21.5°C/W. (See the Package Dissipation Ratings
Table for all other package metrics.) For a given ΘJA, the maximum power dissipation is calculated by the
following formula:
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APPLICATION INFORMATION (continued)
ǒ
T
P
D
+
–T
MAX A
q
JA
Ǔ
Where:
PD
TMAX
TA
θJA
= Maximum power dissipation of THS6182 (watts)
= Absolute maximum operating junction temperature (125°C)
= Free-ambient air temperature (°C)
= θJC + θCA
θJC = Thermal coefficient from junction to case. See the Package Dissipation Ratings table.
θCA = Thermal coefficient from case to ambient determined by PCB layout and construction.
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
GENERAL CONFIGURATIONS
A common error for the first-time CFB user is to create a unity gain buffer amplifier by shorting the output directly
to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS6182,
like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors
directly from the output to the inverting input is not recommended. This is because, at high frequencies, a
capacitor has a very low impedance. This results in an unstable amplifier and should not be considered when
using a current-feedback amplifier. Because of this, integrators and simple low-pass filters, which are easily
implemented on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply place an
RC-filter at the noninverting terminal of the operational-amplifier (see Figure 75).
RG
RF
V
−
VI
+
R1
VO
O +
V
I
ǒ
R
1)
C1
f
–3dB
+
R
F
G
Ǔǒ
Ǔ
1
1 ) sR1C1
1
2pR1C1
Figure 75. Single-Pole Low-Pass Filter
If a multiple pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is
because the filtering elements are not in the negative feedback loop and stability is not compromised. Because
of their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize
distortion. An example is shown in Figure 76.
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APPLICATION INFORMATION (continued)
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB
RG =
+
(
1
2pRC
RF
1
2−
Q
)
Figure 76. 2-Pole Low-Pass Sallen-Key Filter
EVALUATION BOARD
An evaluation board is available for the THS6182. This board has been configured for proper thermal
management of the THS6182. The circuitry has been designed for a typical ADSL application as shown
previously in this document. For more detailed information, refer to the THS6182EVM User's Guide (literature
number SLOU152). To order the evaluation board contact your local TI sales office or distributor.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THS6182D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
THS6182
THS6182DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
THS6182
THS6182DWP
ACTIVE SO PowerPAD
DWP
20
25
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS6182
THS6182DWPR
ACTIVE SO PowerPAD
DWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS6182
THS6182RHFR
ACTIVE
VQFN
RHF
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
6182
THS6182RHFT
ACTIVE
VQFN
RHF
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
6182
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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