THS6222
SBOS974D – AUGUST 2019 – REVISED THS6222
APRIL 2021
SBOS974D – AUGUST 2019 – REVISED APRIL 2021
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THS6222 8 V to 32 V, Differential HPLC Line Driver with Common-Mode Buffer
1 Features
3 Description
•
•
•
•
•
The THS6222 is a differential line-driver amplifier
with a current-feedback architecture manufactured
using Texas Instruments' proprietary, high-speed,
silicon-germanium (SiGe) process. The device is
targeted for use in broadband, high-speed, power line
communications (HPLC) line driver applications that
require high linearity when driving heavy line loads.
•
•
•
•
•
Supply range (VS): 8 V to 32 V
Integrated midsupply common-mode buffer
Large-signal bandwidth: 195 MHz (VO = 16 VPP)
Slew rate (16 V step): 5500 V/µs
Low distortion (VS = 12 V, 50 Ω load):
– HD2: –80 dBc (1 MHz)
– HD3: –90 dBc (1 MHz)
Output current: 338 mA (VS = 12 V, 25 Ω load)
Wide output swing (VS = 12 V):
– 19.4 VPP (100 Ω load)
– 18.6 VPP (50 Ω load)
Adjustable power modes:
– Full-bias mode: 19.5 mA
– Mid-bias mode: 15 mA
– Low-bias mode: 10.4 mA
– Low-power shutdown mode
– IADJ pin for variable bias
Integrated overtemperature protection
Pin-compatible with the 24-pin THS6212 VQFN
The unique architecture of the THS6222 uses minimal
quiescent current while achieving very high linearity.
The amplifier has an adjustable current pin (IADJ)
that sets the nominal current consumption along with
the multiple bias modes that allow for enhanced
power savings where the full performance of the
amplifier is not required. Shutdown bias mode
provides further power savings during receive mode
in time division multiplexed (TDM) systems while
maintaining high output impedance. The integrated
midsupply common-mode buffer eliminates external
components, reducing system cost and board space.
2 Applications
•
•
•
•
•
•
The wide output swing of 57 VPP (100 Ω load) with
32-V power supplies, coupled with over 650 mA
current drive (25 Ω load), allows for wide dynamic
range that keeps distortion minimal.
SGCC HPLC line drivers
Smart meters
Data concentrators
Power line communications gateways
Home networking PLC
Differential DSL line drivers
The THS6222 is available in a 24-pin VQFN package
with exposed thermal pad and is specified for
operation from –40°C to +85°C ambient temperature.
Device Information
PACKAGE(1)
PART NUMBER
VQFN (24)
THS6222
(1)
1-bit power mode control
BODY SIZE (NOM)
5.00 mm × 4.00 mm
Wafer Sale (19)
1261.00 µm × 1641.00 µm
VQFN (16)
3.0 mm × 3.0 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
+12 V
Full-bias / shutdown
THS6222
IADJ
PLC ASIC
BIAS
2
BIAS
1
D1
IN+
5k
RT2
249
CM
Buffer
520
100 k
Optional
VCM
100 nF
D1
OUT
±
5k
VS±
D2
IN+
100 nF
1:1
D1
INt
RG
274
Thermal
Protection
RL
50
+12 V
D2
INt
50
Power Line
RF2
1.24 k
±
D2
OUT
+
D
GND
RS1
2.49
RF1
1.24 k
100 k
RT1
249
100 nF
+12 V
AV =
10 V/V
+
VS+
DAC f
VS+
Bias Current Control
100 nF
RS2
2.49
100 nF
VSt
GND
GND
Typical Line-Driver Circuit Using the THS6222
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SBOS974D – AUGUST 2019 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics: VS = 12 V .......................... 6
6.6 Electrical Characteristics: VS = 32 V .......................... 8
6.7 Timing Requirements ............................................... 10
6.8 Typical Characteristics: VS = 12 V............................ 10
6.9 Typical Characteristics: VS = 32 V............................ 17
7 Detailed Description......................................................20
7.1 Overview................................................................... 20
7.2 Functional Block Diagram......................................... 20
7.3 Feature Description...................................................21
7.4 Device Functional Modes..........................................25
8 Application and Implementation.................................. 26
8.1 Application Information............................................. 26
8.2 Typical Applications.................................................. 26
8.3 What to Do and What Not to Do............................... 28
9 Power Supply Recommendations................................28
10 Layout...........................................................................29
10.1 Layout Guidelines................................................... 29
10.2 Wafer and Die Information...................................... 30
10.3 Layout Examples.................................................... 32
11 Device and Documentation Support..........................33
11.1 Development Support............................................. 33
11.2 Documentation Support.......................................... 33
11.3 Receiving Notification of Documentation Updates.. 33
11.4 Support Resources................................................. 33
11.5 Trademarks............................................................. 33
11.6 Electrostatic Discharge Caution.............................. 33
11.7 Glossary.................................................................. 33
12 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2020) to Revision D (April 2021)
Page
• Corrected the wrong pin diagram image that was tagged incorrectly during system migration..........................3
Changes from Revision B (April 2020) to Revision C (November 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document .................1
• Added VQFN (16) Package to the Device Information table.............................................................................. 1
• Updated the RHF package in the Pin Configuration and Functions section.......................................................3
• Added the RGT package in the Pin Configuration and Functions section..........................................................3
Changes from Revision A (December 2019) to Revision B (April 2020)
Page
• Added Wafer Sale Package and Body Size (NOM) to the Device Information table ......................................... 1
• Added the YS Die bondpad and functions..........................................................................................................3
• Updated Table 1 BIAS-1 and BIAS-2 Logic Table.............................................................................................25
• Added Wafer and Die Information section........................................................................................................ 30
Changes from Revision * (August 2019) to Revision A (December 2019)
Page
• Changed device status from advance information to production data ...............................................................1
2
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3
17
D2_OUT
IADJ
4
16
NC
VCM
5
15
NC
NC
6
14
NC
NC
7
13
NC
Thermal
D2_IN+
2
DGND
IADJ
BIAS-1
VS–
VS+
15
14
13
12
D1_OUT
11
D1_IN–
3
10
D2_IN–
4
9
D2_OUT
Thermal Pad
12
NC
11
NC
10
NC
9
NC
NC
8
Pad
1
8
DGND
D1_IN+
VS+
D2_IN±
7
18
VS–
2
6
D2_IN+
NC
D1_OUT
20
D1_IN±
BIAS-2
VS+
21
19
16
VS±
22
1
5
BIAS-1
23
D1_IN+
VCM
BIAS-2
24
5 Pin Configuration and Functions
Not to scale
Figure 5-2. RGT Package
16-Pin VQFN With Exposed Thermal Pad
Top View
Not to scale
NC = no internal connection.
Figure 5-1. RHF Package
24-Pin VQFN With Exposed Thermal Pad
Top View
Table 5-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
RHF
RGT
BIAS-1(2)
23
15
I
Bias mode control, LSB
BIAS-2(2)
24
16
I
Bias mode control, MSB
D1_IN–
19
11
I
Amplifier D1 inverting input
D2_IN–
18
10
I
Amplifier D2 inverting input
D1_IN+
1
1
I
Amplifier D1 noninverting input
D2_IN+
2
2
I
Amplifier D2 noninverting input
D1_OUT
20
12
O
Amplifier D1 output
D2_OUT
17
9
O
Amplifier D2 output
DGND(3)
3
3
I
Ground reference for bias control pins
Bias current adjustment pin
IADJ
4
4
I
6-16
6
—
No internal connection
VCM
5
5
O
Common-mode buffer output
VS–
22
7, 14
P
Negative power-supply connection
VS+
21
8, 13
P
Positive power-supply connection
P
Electrically connected to die substrate and VS–. Connect to VS– on the printed
circuit board (PCB) for best performance.
NC
Thermal Pad
(1)
(2)
(3)
I = input, O = output, and P = power,
The THS6222 defaults to the shutdown (disable) state if a signal is not present on the bias pins.
The DGND pin ranges from VS– to (VS+ – 5 V).
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D1_IN+
1
D2_IN+
2
DGND
3
IADJ
4
VCM
5
BIAS-2
BIAS-1
VS±
VS±
VS+
VS+
SBOS974D – AUGUST 2019 – REVISED APRIL 2021
19
18
17
16
15
14
THS6222
13
D1_OUT
12
D1_OUT (OPT)
11
D1_IN±
10
D2_IN±
PAD #1
6
9
D2_OUT (OPT)
8
D2_OUT
7
VS+
VS±
Figure 5-3. YS Die
19-Pad Wafer Sale
Top View
Bond Pad Functions
PAD
NAME
Type(1)
DESCRIPTION
BIAS-1(2)
18
I
Bias mode parallel control, LSB
BIAS-2(2)
19
I
Bias mode parallel control, MSB
D1_IN–
11
I
Amplifier D1 inverting input
D2_IN–
10
I
Amplifier D2 inverting input
D1_IN+
1
I
Amplifier D1 noninverting input
D2_IN+
2
I
Amplifier D2 noninverting input
D1_OUT
13
O
Amplifier D1 output (must be used for D1 output)
D1_OUT (OPT)
12
O
Optional amplifier D1 output (pad can be left unconnected or connected to pad 13)
D2_OUT
8
O
Amplifier D2 output (must be used for D2 output)
D2_OUT (OPT)
9
O
Optional amplifier D2 output (can be left unconnected or connected to pad 8)
DGND(3)
3
I
Ground reference for bias control pins
IADJ
4
I
Bias current adjustment pin
VCM
5
O
Common-mode buffer output
VS–
6, 16, 17
P
Negative power-supply connection
VS+
7, 14, 15
P
Positive power-supply connection
—
—
Must be connected to the lowest voltage potential on the die (generally VS–)
Backside
(1)
(2)
(3)
4
NO.
I = input, O = output, and P = power.
The THS6222 defaults to the shutdown (disable) state if a signal is not present on the bias pins.
The DGND pin ranges from VS– to (VS+ – 5 V).
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Supply voltage, VS = (VS+) –
Voltage
Bias control pin voltage, referenced to DGND
Common-mode voltage, VCM
(2)
(3)
33
V
0
16.5
V
(VS–) – 0.5
(VS+) + 0.5
Maximum junction, TJ (under any condition)
150
Maximum junction, TJ (continuous operation, long-term reliability)(3)
125
Storage, Tstg
(1)
MAX
See Common-Mode Buffer
All pins except VS+, VS–, VCM, and BIAS control
Temperature
MIN
(VS–)(2)
–65
UNIT
V
V
°C
150
Stresses beyond those listed under Absolute Maximum Rating may cause permanent device damage. These are stress ratings only,
which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Refer to Breakdown Supply Voltage for breakdown test results.
The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature can result in reduced reliability or lifetime of the device. THS6222 has thermal protection that shuts down the device at
approximately 175°C junction temperature and recovery at approximately 145°C.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±3500
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VS
Supply voltage, VS = (VS+) – (VS–)
8
32
V
DGND
DGND pin voltage
VS–
VS+ – 5
V
TA
Ambient operating air temperature
–40
85
°C
25
6.4 Thermal Information
THS6222
THERMAL
METRIC(1)
RHF (VQFN)
RGT (VQFN)
24 PINS
16 PINS
UNIT
43.4
48.4
°C/W
35
55.1
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
21.3
22.6
°C/W
ΨJT
Junction-to-top characterization parameter
1.3
1.6
°C/W
YJB
Junction-to-board characterization parameter
21.2
22.6
°C/W
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THS6222
THERMAL METRIC(1)
RθJC(bot)
(1)
RHF (VQFN)
RGT (VQFN)
24 PINS
16 PINS
9.3
8.6
Junction-to-case (bottom) thermal resistance
UNIT
°C/W
For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Electrical Characteristics: VS = 12 V
at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 50 Ω, series isolation resistor (RS) = 2.5 Ω
each, RF = 1.24 kΩ, RADJ = 0 Ω, VCM = open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
Small-signal bandwidth
AV = 5 V/V, RF = 1.5 kΩ, VO = 2 VPP
250
AV = 10 V/V, RF = 1.24 kΩ, VO = 2 VPP
180
AV = 15 V/V, RF = 1 kΩ, VO = 2 VPP
165
0.1-dB bandwidth flatness
LSBW
Large-signal bandwidth
VO = 16 VPP
SR
Slew rate (20% to 80%)
VO = 16-V step
Rise and fall time (10% to 90%)
VO = 2 VPP
HD2
HD3
2nd-order harmonic distortion
3rd-order harmonic distortion
AV = 10 V/V,
VO = 2 VPP,
RL = 50 Ω
AV = 10 V/V,
VO = 2 VPP,
RL = 50 Ω
MHz
17
MHz
195
MHz
5500
V/µs
2.1
Full bias, f = 1 MHz
–80
Mid bias, f = 1 MHz
–78
Low bias, f = 1 MHz
–78
Full bias, f = 10 MHz
–61
Mid bias, f = 10 MHz
–61
Low bias, f = 10 MHz
–61
Full bias, f = 1 MHz
–90
Mid bias, f = 1 MHz
–86
Low bias, f = 1 MHz
–83
Full bias, f = 10 MHz
–69
Mid bias, f = 10 MHz
–65
Low bias, f = 10 MHz
–62
ns
dBc
dBc
en
Differential input voltage noise
f ≥ 1 MHz, input-referred, with
and without 100 nF noise-decoupling
capacitor on VCM pin
in+
Noninverting input current noise
f ≥ 1 MHz, each amplifier
1.4
pA/√Hz
in-
Inverting input current noise
f ≥ 1 MHz, each amplifier
18
pA/√Hz
2.5
nV/√Hz
DC PERFORMANCE
ZOL
Open-loop transimpedance gain
1300
kΩ
±12
Input offset voltage (each amplifier)
TA = –40°C
±16
TA = 85°C
±11
mV
±1
Noninverting input bias current
TA = –40°C
±1
TA = 85°C
±1
µA
±8
Inverting input bias current
6
TA = –40°C
±7
TA = 85°C
±4
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6.5 Electrical Characteristics: VS = 12 V (continued)
at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 50 Ω, series isolation resistor (RS) = 2.5 Ω
each, RF = 1.24 kΩ, RADJ = 0 Ω, VCM = open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
Common-mode input range
CMRR
Common-mode rejection ratio
Each input with respect to midsupply
±3.0
Each input
64
TA = –40°C
67
TA = 85°C
62
Noninverting differential input
resistance
V
dB
10 || 2
Inverting input resistance
kΩ || pF
43
Ω
COMMON-MODE BUFFER CHARACTERISTICS
Voltage at VCM with respect to
midsupply
VCM-OS
Common-mode offset voltage
±2.5
mV
TA = –40°C
±5
TA = 85°C
±1
Common-mode voltage noise
With and without 100-nF VCM noisedecoupling capacitor, f ≥ 50 kHz
20
nV/√Hz
Common-mode output resistance
f = DC
AC-coupled inputs
650
Ω
DC-coupled inputs
520
Ω
OUTPUT CHARACTERISTICS
VO
IO
Output voltage swing
Output current (sourcing and sinking)
RL = 100 Ω, RS = 0 Ω
±9.7
RL = 50 Ω, RS = 0 Ω
±9.3
RL = 25 Ω, RS = 0 Ω
±8.4
RL = 25 Ω, RS = 0 Ω, based on
VO specification
±338
Short-circuit output current
ZO
Closed-loop output impedance
f = 1 MHz, differential
V
mA
±0.81
A
0.03
Ω
POWER SUPPLY
VS
Operating voltage
DGND
DGND pin voltage
IS+
IS–
Quiescent current
Quiescent current
8
TA = –40°C to +85°C
12
8
VS–
32
32
0
Full bias (BIAS-1 = 0, BIAS-2 = 0)
19.5
Mid bias (BIAS-1 = 1, BIAS-2 = 0)
15
Low bias (BIAS-1 = 0, BIAS-2 = 1)
10.4
Bias off (BIAS-1 = 1, BIAS-2 = 1)
1.1
Full bias (BIAS-1 = 0, BIAS-2 = 0)
18.8
Mid bias (BIAS-1 = 1, BIAS-2 = 0)
14.4
Low bias (BIAS-1 = 0, BIAS-2 = 1)
9.8
Bias off (BIAS-1 = 1, BIAS-2 = 1)
0.4
VS+ – 5
V
V
mA
mA
Current through DGND pin
Full bias (BIAS-1 = 0, BIAS-2 = 0)
0.8
mA
+PSRR
Positive power-supply rejection ratio
Differential
83
dB
–PSRR
Negative power-supply rejection ratio
Differential
83
dB
BIAS CONTROL
Bias control pin voltage range
With respect to DGND,
TA = –40°C to +85°C
0
3.3
12
V
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6.5 Electrical Characteristics: VS = 12 V (continued)
at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 50 Ω, series isolation resistor (RS) = 2.5 Ω
each, RF = 1.24 kΩ, RADJ = 0 Ω, VCM = open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER
Bias control pin logic threshold
Bias control pin current(1)
Open-loop output impedance
(1)
TEST CONDITIONS
MIN
Logic 1, with respect to DGND,
TA = –40°C to +85°C
2.1
TYP
MAX
UNIT
V
Logic 0, with respect to DGND,
TA = –40°C to +85°C
0.8
BIAS-1, BIAS-2 = 0.5 V (logic 0)
–9.6
BIAS-1, BIAS-2 = 3.3 V (logic 1)
0.3
Off bias (BIAS-1 = 1, BIAS-2 = 1)
µA
1
70 || 5
MΩ || pF
Current is considered positive out of the pin.
6.6 Electrical Characteristics: VS = 32 V
at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 100 Ω, RF = 1.24 kΩ, RADJ = 0 Ω, VCM =
open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
Small-signal bandwidth, –3 dB
AV = 5 V/V, RF = 1.5 kΩ, VO = 2 VPP
285
AV = 10 V/V, RF = 1.24 kΩ, VO = 2 VPP
205
0.1-dB bandwidth flatness
LSBW
Large-signal bandwidth
VO = 40 VPP
SR
Slew rate (20% to 80% level)
VO = 40-V step
Rise and fall time
VO = 2 VPP
HD2
2nd-order harmonic distortion
AV = 10 V/V,
VO = 2 VPP,
RL = 100 Ω
13
MHz
170
MHz
11,000
V/µs
2
Full bias, f = 1 MHz
–86
Low bias, f = 1 MHz
–79
Full bias, f = 10 MHz
–71
Low bias, f = 10 MHz
–101
Low bias, f = 1 MHz
–88
Full bias, f = 10 MHz
–80
Low bias, f = 10 MHz
–65
3rd-order harmonic distortion
AV = 10 V/V,
VO = 2 VPP,
RL = 100 Ω
en
Differential input voltage noise
f ≥ 1 MHz, input-referred
in+
in-
ns
dBc
–63
Full bias, f = 1 MHz
HD3
MHz
dBc
2.5
nV/√Hz
Noninverting input current noise (each
f ≥ 1 MHz
amplifier)
1.7
pA/√Hz
Inverting input current noise (each
amplifier)
18
pA/√Hz
f ≥ 1 MHz
DC PERFORMANCE
ZOL
Open-loop transimpedance gain
Input offset voltage
8
1500
kΩ
±12
mV
Input offset voltage drift
TA = –40°C to +85°C
–40
µV/°C
Input offset voltage matching
Amplifier A to B
±0.5
mV
Noninverting input bias current
±1
µA
Inverting input bias current
±6
µA
Inverting input bias current matching
±8
µA
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6.6 Electrical Characteristics: VS = 32 V (continued)
at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 100 Ω, RF = 1.24 kΩ, RADJ = 0 Ω, VCM =
open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
CMRR
Common-mode input range
Each input
±11
±12
V
Common-mode rejection ratio
Each input
53
65
dB
Noninverting input resistance
10 || 2
Inverting input resistance
kΩ || pF
38
Ω
COMMON-MODE BUFFER CHARACTERISTICS
VCM-OS
Common-mode offset voltage
Voltage at VCM with respect to
midsupply
Common-mode voltage noise
With and without 100-nF VCM noisedecoupling capacitor, f ≥ 50 kHz
Common-mode output resistance
f = DC
±3.9
mV
21
nV/√Hz
520
Ω
OUTPUT CHARACTERISTICS
Output voltage swing(1)
VO
Output current (sourcing and sinking)
IO
(1)
RL = 100 Ω
±28.5
RL = 25 Ω
±16.3
RL = 25 Ω, based on VO specification
±580
±665
Short-circuit output current
ZO
Output impedance
V
f = 1 MHz, differential
mA
1
A
0.01
Ω
POWER SUPPLY
VS
Operating voltage
IS+
Quiescent current
8
TA = –40°C to +85°C
12
8
32
Full bias (BIAS-1 = 0, BIAS-2 = 0)
23
Mid bias (BIAS-1 = 1, BIAS-2 = 0)
17.7
Low bias (BIAS-1 = 0, BIAS-2 = 1)
12.2
Bias off (BIAS-1 = 1, BIAS-2 = 1)
IS–
Quiescent current
32
1.5
Full bias (BIAS-1 = 0, BIAS-2 = 0)
22
Mid bias (BIAS-1 = 1, BIAS-2 = 0)
16.7
Low bias (BIAS-1 = 0, BIAS-2 = 1)
11.2
Bias off (BIAS-1 = 1, BIAS-2 = 1)
0.5
V
mA
1.8
mA
0.8
Current through GND pin
Full bias (BIAS-1 = 0, BIAS-2 = 0)
1
mA
+PSRR
Positive power-supply rejection ratio
Differential
83
dB
–PSRR
Negative power-supply rejection ratio
Differential
77
dB
BIAS CONTROL
Bias control pin range
Bias control pin logic threshold
Bias control pin current(2)
(1)
(2)
With respect to DGND,
TA = –40°C to +85°C
Logic 1, with respect to DGND,
TA = –40°C to +85°C
0
3.3
V
1.9
V
Logic 0, with respect to DGND,
TA = –40°C to +85°C
BIAS-1, BIAS-2 = 0.5 V (logic 0)
16.5
0.8
–15
–10
BIAS-1, BIAS-2 = 3.3 V (logic 1)
0.1
1
µA
See Output Voltage and Current Drive and Figure 6-51 for output voltage vs output current characteristics.
Current is considered positive out of the pin.
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6.7 Timing Requirements
MIN
NOM
MAX
UNIT
tON
Turnon time delay: time for output to start tracking the input
25
ns
tOFF
Turnoff time delay: time for output to stop tracking the input
275
ns
6.8 Typical Characteristics: VS = 12 V
3
3
0
0
Normalized Gain (dB)
Normalized Gain (dB)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
-3
-6
-9
AV = 5 V/V, RF = 1.5 k:
AV = 10 V/V, RF = 1.24 k:
AV = 15 V/V, RF = 1 k:
AV = 20 V/V, RF = 850 :
-12
-15
10M
-3
-6
-9
-12
100M
Frequency (Hz)
-15
10M
1G
D001
VO = 2 VPP
D040
Figure 6-2. Large-Signal Frequency Response
27
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
Band0
Band1
Band2
Band3
TA = 40qC
TA = 25qC
TA = 85qC
24
Closed-Loop Gain (dB)
Transmit Power (dBm/Hz)
100M
Frequency (Hz)
VO = 16 VPP
Figure 6-1. Small-Signal Frequency Response
21
18
15
12
9
0
2.5
5
7.5
10 12.5 15 17.5
Frequency (MHz)
20
22.5
25
6
10M
D030
Figure 6-3. Out-of-Band Suppression
100M
Frequency (Hz)
1G
D005
AV = 15 V/V, VO = 2 VPP
SGCC HPLC profiles, crest factor = 5 V/V, see the Broadband
PLC Line Driving section for more details.
10
AV = 10 V/V, RF = 1.24 k:
AV = 15 V/V, RF = 1 k:
Figure 6-4. Small-Signal Frequency Response vs Temperature
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6.8 Typical Characteristics: VS = 12 V (continued)
26
27
23
24
Closed-loop Gain (dB)
Closed-loop Gain (dB)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
20
17
14
11
RF = 250 :
RF = 500 :
RF = 909 :
RF = 1240 :
8
5
10M
21
18
15
12
100M
Frequency (Hz)
9
10M
1G
D039
AV = 10 V/V, VO = 2 VPP
1G
D004
Figure 6-6. Small-Signal Frequency Response vs RF
20.5
24.1
20.4
24
20.3
23.9
Closed-loop Gain (dB)
Closed-loop Gain (dB)
100M
Frequency (Hz)
AV = 15 V/V, VO = 2 VPP
Figure 6-5. Small-Signal Frequency Response vs RF
20.2
20.1
20
19.9
19.8
RF = 250 :
RF = 500 :
RF = 909 :
RF = 1240 :
19.7
19.6
19.5
10M
23.8
23.7
23.6
23.5
23.4
RF = 100 :
RF = 250 :
RF = 500 :
RF = 700 :
RF = 1000 :
23.3
23.2
23.1
23
10M
100M
Frequency (Hz)
D041
AV = 10 V/V, VO = 2 VPP
100M
Frequency (Hz)
1G
D042
AV = 15 V/V, VO = 2 VPP
Figure 6-7. Small-Signal Gain Flatness vs RF
Figure 6-8. Small-Signal Gain Flatness vs RF
3
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
10M
AV = 10 V/V,
RF = 1.24 k:
AV = 15 V/V,
RF = 1 k:
0
Normalized Gain (dB)
Normalized Gain (dB)
RF = 100 :
RF = 250 :
RF = 500 :
RF = 700 :
RF = 1000 :
-3
-6
-9
-12
-15
10M
100M
Frequency (Hz)
D043
CL = 22 pF, RS = 0 :
CL = 33 pF, RS = 0 :
CL = 47 pF, RS = 2 :
CL = 100 pF, RS = 5 :
CL = 100 pF, RS = 5 :
100M
Frequency (Hz)
D006
VO = 100 mVPP
VO = 16 VPP
Figure 6-9. Large-Signal Gain Flatness
Frequency response is measured at the device output pin
before the isolation resistor.
Figure 6-10. Small-Signal Frequency Response vs CLOAD
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6.8 Typical Characteristics: VS = 12 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
25
23
22
Closed-loop Gain (dB)
17
14
11
8
5
10M
VO = 2 VPP
VO = 5 VPP
VO = 10 VPP
VO = 16 VPP
19
16
13
VO = 2 VPP
VO = 5 VPP
VO = 10 VPP
VO = 16 VPP
10
10M
100M
Frequency (Hz)
100M
Frequency (Hz)
D007
AV = 10 V/V
AV = 15 V/V
Figure 6-11. Large-Signal Frequency Response vs VO
Figure 6-12. Large-Signal Frequency Response vs VO
21
25
15
12
19
16
13
10
10M
100M
Frequency (Hz)
Closed-Loop Gain (dB)
Figure 6-14. Small-Signal Frequency Response vs Bias Modes
Input-Referred Voltage Noise, en (nV/—Hz
26
Full-bias
Mid-bias
Low-bias
20
17
14
11
8
100M
Frequency (Hz)
1G
100
100
en
in+
in
10
1
100
D047
AV = 15 V/V, VO = 16 VPP
10
1k
10k
100k
Frequency (Hz)
1M
1
10M
D018
.
Figure 6-15. Large-Signal Frequency Response vs Bias Modes
12
D003
AV = 15 V/V, VO = 2 VPP
Figure 6-13. Small-Signal Frequency Response vs Bias Modes
23
100M
Frequency (Hz)
D002
AV = 10 V/V, VO = 2 VPP
5
10M
Full-bias
Mid-bias
Low-bias
22
18
Closed-Loop Gain (dB)
Closed-Loop Gain (dB)
Full-bias
Mid-bias
Low-bias
9
10M
D008
Input-Referred Current Noise, in (pA/—Hz
Closed-loop Gain (dB)
20
Figure 6-16. Input Voltage and Current Noise Density vs
Frequency
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6.8 Typical Characteristics: VS = 12 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
-75
-45
HD2, RL = 50:
HD3, RL = 50:
HD2, RL = 100:
HD3, RL = 100:
Harmonic Distortion (dBc)
-55
-60
HD2
HD3
-77
Harmonic Distortion (dBc)
-50
-65
-70
-75
-80
-85
-90
-95
-79
-81
-83
-85
-87
-89
-91
-93
-100
-95
-105
1M
10M
Frequency (Hz)
5
100M
VO = 2 VPP
D014
Figure 6-18. Harmonic Distortion vs Gain
-30
-10
HD2
HD3
HD2
HD3
-20
Harmonic Distortion (dBc)
-40
Harmonic Distortion (dBc)
20
f = 1 MHz, VO = 2 VPP
Figure 6-17. Harmonic Distortion vs Frequency
-50
-60
-70
-80
-90
-30
-40
-50
-60
-70
-100
0.5
1
10
-80
0.5
20
Output Voltage (VPP)
1
10
Output Voltage (VPP)
D010
f = 1 MHz, AV = 10 V/V
20
D011
f = 10 MHz, AV = 10 V/V
Figure 6-19. Harmonic Distortion vs VO
Figure 6-20. Harmonic Distortion vs VO
-60
-45
HD2
HD3
-65
HD2
HD3
-50
-70
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
10
Gain (V/V)
D009
-75
-80
-85
-90
-95
-55
-60
-65
-70
-75
-80
-85
-90
-100
-95
-105
10
100
Load Resistance, RL (:)
300
-100
10
D012
100
Load Resistance, RL (:)
f = 1 MHz, VO = 2 VPP, AV = 10 V/V
f = 10 MHz, VO = 2 VPP, AV = 10 V/V
Figure 6-21. Harmonic Distortion vs RL
Figure 6-22. Harmonic Distortion vs RL
300
D013
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6.8 Typical Characteristics: VS = 12 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
15
-30
IMD2
IMD3
-40
VIN u 10 gain
VO (AV = 10)
12.5
10
-45
7.5
-50
5
Voltage (V)
-55
-60
-65
2.5
0
-2.5
-70
-5
-75
-7.5
-80
-10
-85
-12.5
-90
10k
-15
100k
1M
10M
Frequency (Hz)
100M
Time, 15 Ps per division
D015
D023
±12.2 kHz tone spacing, VO = 2 VPP per tone
VIN = 2.8-VPP triangular waveform
Figure 6-23. Intermodulation Distortion vs Frequency
Figure 6-24. Overdrive Recovery
1.25
D1OUT
D1OUT
D2OUT
1
D1OUT
D1OUT
D2OUT
7
Output Voltage (V)
Output Voltage (V)
0.75
9
D2OUT
0.5
0.25
0
-0.25
-0.5
D2OUT
5
3
1
-1
-3
-5
-0.75
-7
-1
-9
-1.25
Time, 25 ns per division
Time, 25 ns per division
D046
D019
VO step = 16 VPP
VO step = 2 VPP
Figure 6-26. Large-Signal Pulse Response
1k
10k
100k
1M
Frequency (Hz)
10M
15
ZOL
0
Phase
-15
-30
-45
-60
-75
-90
-105
-120
-135
-150
-165
-180
100M
1G
Open-Loop Transimpedance Gain, ZOL (dB:)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
100
Open-Loop Transimpedance Phase (q)
Open-Loop Transimpedance Gain, ZOL (dB:)
Figure 6-25. Small-Signal Pulse Response
130
120
110
100
90
80
70
60
50
40
30
20
10
0
100
D016
Full-bias simulation
10k
100k
1M
Frequency (Hz)
10M
D036
Mid-bias simulation
Figure 6-27. Open-Loop Transimpedance Gain and Phase vs
Frequency
14
1k
15
ZOL
0
Phase
-15
-30
-45
-60
-75
-90
-105
-120
-135
-150
-165
-180
100M
1G
Open-Loop Transimpedance Phase (q)
Intermodulation Distortion (dBc)
-35
Figure 6-28. Open-Loop Transimpedance Gain and Phase vs
Frequency
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6.8 Typical Characteristics: VS = 12 V (continued)
1k
10k
100k
1M
Frequency (Hz)
15
ZOL
0
Phase
-15
-30
-45
-60
-75
-90
-105
-120
-135
-150
-165
-180
100M
1G
10M
1M
Open-Loop Output Impedance (:)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
100
Open-Loop Transimpedance Phase (q)
Open-Loop Transimpedance Gain, ZOL (dB:)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
Full-bias
Mid-bias
Low-bias
Shutdown
100k
10k
1k
100
10
1
100k
1M
D037
Low-bias simulation
18
15
16
Quiescent Current (mA)
Quiescent Current (mA)
20
20
10
ICC, TA = 40qC
ICC, TA = 25qC
ICC, TA = 85qC
IEE, TA = 40qC
IEE, TA = 25qC
IEE, TA = 85qC
-5
-10
Full-bias
Mid-bias
Low-bias
Power-down
14
12
10
8
6
-15
4
-20
2
-25
0
4
8
12
16
20
24
Single-Supply Voltage, VS (V)
28
32
0
20
PSRR and CMRR (dB)
18
16
14
12
10
Full-bias
Mid-bias
Low-bias
Power-down
4
2
0
-40
-25
1.5
-10
5
20
35
50
Ambient Temperature, TA (qC)
2
2.5 3 3.5
RADJ (k:)
4
4.5
5
5.5
6
D020
Figure 6-32. Quiescent Current vs RADJ
22
6
1
Average of 30 devices
Figure 6-31. Quiescent Current vs Single-Supply Voltage
8
0.5
D021
RL = no load, average of 30 devices
Quiescent Current (mA)
D017
Figure 6-30. Open-Loop Output Impedance vs Frequency
25
0
100M
Simulation
Figure 6-29. Open-Loop Transimpedance Gain and Phase vs
Frequency
5
10M
Frequency (Hz)
65
80
160
150
140
130
120
110
100
90
80
70
60
50
40
30
1k
D044
RL = no load, average of 30 devices
PSRR+
PSRR
CMRR
10k
100k
1M
Frequency (Hz)
10M
100M
D026
TJ = 50°C, simulation
Figure 6-33. Quiescent Current vs Temperature
Figure 6-34. PSRR and CMRR vs Frequency
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6.8 Typical Characteristics: VS = 12 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
22
B1, TA = 40(qC)
B1, TA = 25(qC)
B1, TA = 85(qC)
18
Voltage (V)
Quiescent Current (mA)
20
B2, TA = 40(qC)
B2, TA = 25(qC)
B2, TA = 85(qC)
16
14
12
10
8
0
1
2
3
4
5
6
7
8
Bias Pin Voltage (V)
9
10
11
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
12
Time, 25 ns per division
D024
D025
B1 = full-bias to mid-bias transition with B2 = DGND, B2 =
full-bias to low-bias transition with B1 = DGND, DGND = VS–
Figure 6-35. Mode Transition Voltage Threshold
16
B1, B2
D1OUT D2OUT
D1OUT
D2OUT
.
Figure 6-36. Full-Bias and Shutdown Mode Transition Timing
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6.9 Typical Characteristics: VS = 32 V
3
23
0
20
Closed-loop Gain (dB)
Normalized Gain (dB)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 100 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
-3
-6
-9
-12
AV = 5 V/V, RF = 1.5 k:
AV = 10 V/V, RF = 1.24 k:
AV = 15 V/V, RF = 1 k:
AV = 20 V/V, RF = 850 :
-15
10M
100M
Frequency (Hz)
17
14
11
8
RF = 500 :
RF = 909 :
RF = 1240 :
5
10M
1G
100M
Frequency (Hz)
D100
VO = 2 VPP
26
20
23
Closed-loop Gain (dB)
Closed-loop Gain (dB)
Figure 6-38. Small-Signal Frequency Response vs RF
23
17
14
11
5
10M
VO = 2 VPP
VO = 10 VPP
VO = 20 VPP
VO = 40 VPP
20
17
14
11
100M
Frequency (Hz)
VO = 2 VPP
VO = 5 VPP
VO = 10 VPP
VO = 16 VPP
8
10M
1G
100M
Frequency (Hz)
D103
AV = 10 V/V
1G
D104
AV = 15 V/V
Figure 6-39. Large-Signal Frequency Response vs VO
Figure 6-40. Large-Signal Frequency Response vs VO
23
-30
Full-bias
Mid-bias
Low-bias
IMD2
IMD3
-35
Intermodulation Distortion (dBc)
20
Closed-Loop Gain (dB)
D101
VO = 2 VPP
Figure 6-37. Small-Signal Frequency Response
8
1G
17
14
11
8
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
5
10M
100M
Frequency (Hz)
1G
-90
10k
100k
D121
VO = 40 VPP
1M
10M
Frequency (Hz)
100M
D111
.
Figure 6-41. Large-Signal Frequency Response vs Bias Modes
Figure 6-42. Intermodulation Distortion vs Frequency
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6.9 Typical Characteristics: VS = 32 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 100 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
-75
-45
HD2, RL = 50:
HD3, RL = 50:
HD2, RL = 100:
HD3, RL = 100:
Harmonic Distortion (dBc)
-55
-60
HD2
HD3
-77
Harmonic Distortion (dBc)
-50
-65
-70
-75
-80
-85
-90
-95
-79
-81
-83
-85
-87
-89
-91
-93
-100
-95
-105
1M
10M
Frequency (Hz)
5
100M
VO = 2 VPP
-55
HD2
HD3
HD2
HD3
-60
-80
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
D110
Figure 6-44. Harmonic Distortion vs Gain
-75
-85
-90
-95
-65
-70
-75
-80
-100
0.5
1
10
-85
0.5
20
Output Voltage (VPP)
1
10
Output Voltage (VPP)
D106
f = 1 MHz, RL = 50 Ω
20
D107
f = 10 MHz, RL = 50 Ω
Figure 6-45. Harmonic Distortion vs VO
Figure 6-46. Harmonic Distortion vs VO
-60
-45
HD2
HD3
-65
HD2
HD3
-50
-70
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
20
f = 1 MHz, VO = 2 VPP RL = 50 Ω
Figure 6-43. Harmonic Distortion vs Frequency
-75
-80
-85
-90
-95
-55
-60
-65
-70
-75
-80
-85
-90
-100
-95
-105
10
100
Load Resistance, RL (:)
300
-100
10
D108
f = 1 MHz, VO = 2 VPP
100
Load Resistance, RL (:)
300
D109
f = 10 MHz, VO = 2 VPP
Figure 6-47. Harmonic Distortion vs RL
18
10
Gain (V/V)
D105
Figure 6-48. Harmonic Distortion vs RL
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6.9 Typical Characteristics: VS = 32 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 100 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
1.25
1
D2OUT
D1OUT
D1OUT
D2OUT
20
15
0.5
Output Voltage (V)
Output Voltage (V)
0.75
25
D1OUT
D1OUT
D2OUT
0.25
0
-0.25
-0.5
D2OUT
10
5
0
-5
-10
-0.75
-15
-1
-20
-25
-1.25
Time, 25 ns per division
Time, 25 ns per division
D122
D114
VO step = 40 VPP
VO step = 2 VPP
Figure 6-50. Large-Signal Pulse Response
24
16
14
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
Full-bias
Mid-bias
Low-bias
Power-down
22
20
Quiescent Current (mA)
Single-Ended Output Voltage (V)
Figure 6-49. Small-Signal Pulse Response
Sourcing, TA = 40qC
Sourcing, TA = 25qC
Sourcing, TA = 85qC
Sinking, TA = 40qC
Sinking, TA = 25qC
Sinking, TA = 85qC
18
16
14
12
10
8
6
4
2
0
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
D117
0
Average of 30 devices
0.5
1
1.5
2
2.5 3 3.5
RADJ (k:)
4
4.5
5
5.5
6
D115
Average of 30 devices
Output voltage is slammed and IO is pulsed to maintain TJ as
close to TA as possible.
Figure 6-52. Quiescent Current vs RADJ
Figure 6-51. Single-Ended Output Voltage vs IO and
Temperature
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7 Detailed Description
7.1 Overview
The THS6222 is a differential line-driver amplifier with a current-feedback architecture. The device is targeted for
use in line-driver applications such as narrow-band and broadband power-line communications (PLC) that are
often found in smart metering and home networking applications.
The THS6222 is designed as a single-port differential line driver solution that can be a drop-in replacement for
the THS6212. The integrated common-mode buffer featured in the THS6222 reduces the number of external
components required for level shifting the input common-mode voltage in PLC applications that are often ac
coupled, resulting in space savings on the circuit board and reducing the overall system cost. The THS6222
uses an architecture that does not allow using the two current-feedback amplifiers, D1 and D2, independently;
therefore, these amplifiers must always be driven differentially.
The architecture of the THS6222 is designed to provide maximum flexibility with adjustable power modes that
are selectable based on application performance requirements, and also provides an external current adjustment
pin (IADJ) to further optimize the quiescent power of the device. The wide output swing (18.6 VPP) into 50-Ω
differential loads with 12-V power supplies and high current drive of the THS6222 make the device ideally suited
for high-power, line-driving applications. By using 32-V power supplies and with good thermal design that keep
the device within the safe operating temperature, the THS6222 is capable of swinging 57 VPP into 100-Ω loads.
7.2 Functional Block Diagram
THS6222
IADJ
BIAS
2
BIAS
1
VS+
Bias Current Control
D1
IN+
+
VS+
100 k
5k
CM
Buffer
520
VCM
100 k
5k
VS±
D2
IN+
D1
OUT
D1
INt
Thermal
Protection
D2
INt
±
D2
+
D
GND
20
D1
±
D2
OUT
VSt
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7.3 Feature Description
7.3.1 Common-Mode Buffer
The THS6222 is a differential line driver that features an integrated common-mode buffer. Most common line
driving applications for the THS6222 are ac-coupled applications; see Figure 8-2. Therefore, the inputs must be
common-mode shifted to ensure the input signals are within the common-mode specifications of the device. To
maximize the dynamic range, the common-mode voltage is shifted to midsupply in most ac-coupled applications.
With the integrated common-mode buffer, no external components are required to shift the input common-mode
voltage. Often, engineers choose to connect a noise-decoupling capacitor to the VCM pin. However, as shown
in Figure 7-1, assuming the circuit is reasonably shielded from external noise sources, no difference in commonmode noise is observed with the 100 nF capacitor or without the capacitor.
Voltage Noise (nV/—Hz)
300
VS = 12 V, no VCM capacitor
VS = 12 V, 100-nF VCM capacitor
VS = 32 V, no VCM capacitor
VS = 32 V, 100-nF VCM capacitor
100
10
1k
10k
100k
Frequency (Hz)
1M
D052
Figure 7-1. Common-Mode Voltage Noise Density vs Frequency
There are ESD protection diodes in series directly at the output of the common-mode buffer between the internal
520 Ω resistor and the common-mode buffer output. These diodes are referenced to midsupply. Any voltage that
is 1.4 V above or below the midsupply applied to the VCM pin forward biases the protection diodes. This biasing
results in either current flowing into or out of the VCM pin. The current is limited by the 520 Ω resistor in series,
but to prevent permanent damage to the device, the current must be limited to the current specifications in the
Absolute Maximum Ratings table.
7.3.2 Thermal Protection and Package Power Dissipation
The THS6222 is designed with thermal protection that automatically puts the device in shutdown mode when
the junction temperature reaches approximately 175°C. In this mode, the device behavior is the same as if
the bias pins are used to power-down the device. The device resumes normal operation when the junction
temperature reaches approximately 145°C. In general, the thermal shutdown condition must be avoided. If and
when the thermal protection triggers, thermal cycling occurs where the device repeatedly goes in and out of
thermal shutdown until the junction temperature stabilizes to a value that prevents thermal shutdown.
A common technique to calculate the maximum power dissipation that a device can withstand is by using the
junction-to-ambient thermal resistance (RθJA), provided in the Thermal Information table. Using the equation
power dissipation = (junction temperature, TJ – ambient temperature, TA) / RθJA, the amount of power a package
can dissipate can be estimated. Figure 7-2 illustrates the package power dissipation based on this equation to
reach junction temperatures of 125°C and 150°C at various ambient temperatures. The RθJA value is determined
using industry standard JEDEC specifications and allows ease of comparing various packages. Power greater
than that in Figure 7-2 can be dissipated in a package by good printed circuit board (PCB) thermal design, using
heat sinks, and or active cooling techniques. See the Thermal Design By Insight, Not Hindsight application report
for an in-depth discussion on thermal design.
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Power Dissipation (W)
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4.5
4.25
4
3.75
3.5
3.25
3
2.75
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
-40 -30 -20 -10
TJ = 125qC
TJ = 150qC
0 10 20 30 40 50 60 70 80 90
Ambient Temperature (qC)
SBOS
Figure 7-2. Package Power Dissipation vs Ambient Temperature
7.3.3 Output Voltage and Current Drive
The THS6222 provides output voltage and current capabilities that are unsurpassed in a low-cost, monolithic op
amp. Under no load at room temperature, the output voltage typically swings closer than 1.1 V to either supply
rail and typically swings to within 1.1 V of either supply with a 100 Ω differential load. The THS6222 can deliver
over 350 mA of current with a 25 Ω load.
6
1
5
0.8
Single-Ended Output Voltage (V)
Single-Ended Output Voltage (V)
Good thermal design of the system is important, including use of heat sinks and active cooling methods, if
the THS6222 is pushed to the limits of its output drive capabilities. Figure 7-3 and Figure 7-4 show the output
drive of the THS6222 under two different sets of conditions where TA is approximately equal to TJ. In practical
applications, TJ is often much higher than TA and is highly dependent on the device configuration, signal
parameters, and PCB thermal design. In order to represent the full output drive capability of the THS6222 in
Figure 7-3 and Figure 7-4, TJ ≈ TA is achieved by pulsing or sweeping the output current for a duration of less
than 100 ms.
4
3
2
Sourcing, TA = 40qC
Sourcing, TA = 25qC
Sourcing, TA = 85qC
Sinking, TA = 40qC
Sinking, TA = 25qC
Sinking, TA = 85qC
1
0
-1
-2
-3
-4
Full-bias
Mid-bias
Low-bias
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-5
-6
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
D022
-1
-700
-500
-300
-100 100
300
500
Output Current (mA)
700
900
D045
VS = 12 V, TJ ≈ TA ≈ 25°C
VS = 12 V, TJ ≈ TA
Figure 7-3. Slammed Single-Ended Output Voltage
vs IO and Temperature
Figure 7-4. Linear Single-Ended Output Voltage vs
IO and Temperature
In Figure 7-3, the output voltages are differentially slammed to the rail and the output current is single-endedly
sourced or sunk using a source measure unit (SMU) for less than 100 ms. The single-ended output voltage of
each output is then measured prior to removing the load current. After removing the load current, the outputs are
brought back to mid-supply before repeating the measurement for different load currents. This entire process is
repeated for each ambient temperature. Under the slammed output voltage condition of Figure 7-3, the output
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transistors are in saturation and the transistors start going into linear operation as the output swing is backed off
for a given IO,
In Figure 7-4, the inputs are floated and the output voltages are allowed to settle to the mid-supply voltage.
The load current is then single-endedly swept for sourcing (greater than 0 mA) and sinking (less than 0 mA)
conditions and the single-ended output voltage is measured at each current-forcing condition. The current sweep
is completed in a few seconds (approximately 3 to 4 seconds) so as not to significantly raise the junction
temperature (TJ) of the device from the ambient temperature (TA). The output is not swinging and the output
transistors are in linear operation in Figure 7-4 until the current drawn exceeds the device capabilities, at which
point the output voltage starts to deviate quickly from the no load output voltage.
To maintain maximum output stage linearity, output short-circuit protection is not provided. This absence of
short-circuit protection is normally not a problem because most applications include a series-matching resistor
at the output that limits the internal power dissipation if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to the adjacent positive power-supply pin, in most cases, permanently
damages the amplifier.
7.3.4 Breakdown Supply Voltage
To estimate the margin beyond the maximum supply voltage specified in the Absolute Maximum Ratings table
and exercise the robustness of the device, several typical units were tested beyond the specifications in the
Absolute Maximum Ratings table. Figure 7-5 shows the configuration used for the test. The supply voltage,
VS, was swept manually and quiescent current was recorded at each 0.5-V supply voltage increment. Figure
7-6 shows the results of the single-supply voltage where the typical units started breaking. Under a similar
configuration as the one shown in Figure 7-5, a unit was subjected to VS = 42 V for 168 hours and tested
for quiescent current at the beginning and at the end of the test. There was no notable difference in the
quiescent current before and after the 168 hours of testing and the device did not show any signs of damage or
abnormality.
The primary objective of these tests was to estimate the margins of robustness for typical devices and
does not imply performance or maximum limits beyond those specified in the Abolute Maximum Ratings and
Recommended Operating Conditions tables.
VS
THS6222
IADJ
BIAS
2
BIAS
1
VS+
Bias Current Control
D1
IN+
+
VS+
RF1
1.25 k
100 k
5k
D1
OUT
±
CM
Buffer
520
Open VCM
100 k
5k
VS±
D2
IN+
D1
INt
Open
D2
INt
RF2
1.25 k
±
D2
OUT
+
D
GND
RG
274
Thermal
Protection
VSt
Figure 7-5. Breakdown Supply Voltage Test Configuration
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45
Unit 1
Unit 2
Unit 3
Quiescent Current (mA)
40
35
Unit 4
Unit 5
30
25
20
15
10
5
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
27.5
30.0
32.5
35.0
37.5
40.0
42.5
45.0
47.5
50.0
0
D038
Single-Supply Voltage (V)
Figure 7-6. Typical Device Breakdown Supply Voltage (TA = 27°C)
7.3.5 Surge Test Results
Line drivers such as the THS6222 often directly interface with power lines through a transformer and various
protection components in high-speed power line communications (HPLC) smart-meters and digital subscriber
line (DSL) applications. Surge testing is an important requirement for such applications. To validate the
performance and surge survivability of the THS6222, the THS6222 circuit configuration shown in Figure 7-7
was subjected to a ±4 kV common-mode surge and a ±2 kV differential-mode surge. The common-mode and
differential-mode surge voltages were applied at VCM and V DIFF, respectively, in Figure 7-7. The 1.2/50 µs surge
profile was used per the IEC 61000-4-5 test with REQ = 42 Ω as explained in the TI's IEC 61000-4-x Tests and
Procedures application report. Five devices were tested in full-bias and shutdown modes, and were subjected to
the surge five times for each polarity. No device showed any discernable change in quiescent current after being
subjected to the surge test, and the out-of-band suppression tests did not show any performance deterioration
either, as shown in Figure 7-8 through Figure 7-11 for the state grid corporation of China (SGCC) HPLC bands.
Full-bias /
Shutdown
+12 V
THS6222
IADJ
BIAS
2
BIAS
1
VS+
+12 V
AV =
10 V/V
Bias Current Control
100 nF
D1
IN+
+
VS+
5k
CM
Buffer
520
VCM
100 k
RT2
49.9
5k
VS±
D2
IN+
100 nF
±
100 nF
1:1
VCM
D1
INt
RG
274
Thermal
Protection
TVS
VCM
RF2
1.24 k
±
Varistor VDIFF
+12 V
D2
INt
D2
OUT
+
D
GND
RS1
2.49
RF1
1.24 k
100 k
RT1
49.9
D1
OUT
RS2
2.49
100 nF
VSt
Figure 7-7. Surge Test Configuration
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-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
Pre-surge
Post-surge
Transmit Power (dBm/Hz)
Transmit Power (dBm/Hz)
www.ti.com
0
2.5
5
7.5
10 12.5 15 17.5
Frequency (MHz)
20
22.5
25
0
Pre-surge
Post-surge
5
7.5
10 12.5 15 17.5
Frequency (MHz)
2.5
5
7.5
20
22.5
25
20
22.5
25
D049
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
Pre-surge
Post-surge
0
2.5
5
7.5
D050
Figure 7-10. China SGCC HPLC Band2 Pre-Surge
and Post-Surge
10 12.5 15 17.5
Frequency (MHz)
Figure 7-9. China SGCC HPLC Band1 Pre-Surge
and Post-Surge
Transmit Power (dBm/Hz)
Transmit Power (dBm/Hz)
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
2.5
Pre-surge
Post-surge
D048
Figure 7-8. China SGCC HPLC Band0 Pre-Surge
and Post-Surge
0
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
10 12.5 15 17.5
Frequency (MHz)
20
22.5
25
D051
Figure 7-11. China SGCC HPLC Band3 Pre-Surge
and Post-Surge
7.4 Device Functional Modes
The THS6222 has four different functional modes set by the BIAS-1 and BIAS-2 pins. Table 7-1 shows the truth
table for the device mode pin configuration and the associated description of each mode.
Table 7-1. BIAS-1 and BIAS-2 Logic Table
BIAS-1
BIAS-2
FUNCTION
DESCRIPTION
0
0
Full-bias mode (100%)
Amplifiers on with lowest distortion possible
1
0
Mid-bias mode (75%)
Amplifiers on with power savings and a reduction in distortion performance
0
1
Low-bias mode (50%)
Amplifiers on with enhanced power savings and a reduction of overall
performance
1
1
Shutdown mode
Amplifiers off and output is high impedance
If the PLC application requires switching the line driver between all four power modes and if the PLC applicationspecific integrated circuit (ASIC) has two control bits, then the two control bits can be connected to the bias pins
BIAS-1 and BIAS-2 for switching between any of the four power modes. However, most PLC applications only
require the line driver to switch between one of the three active power modes and the shutdown mode. This
type of 1-bit power mode control is illustrated in Figure 8-1, where the line driver can be switched between the
full-bias and shutdown modes using just one control bit from the PLC ASIC. If switching between the mid-bias or
low-bias modes and the shutdown mode is required for the application, then either the BIAS-1 or BIAS-2 pin can
be connected to ground and the control pin from the PLC ASIC can be connected to the non-grounded BIAS pin.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The THS6222 is typically used for high output power line-driving applications with various load conditions, as is
often the case in power line communications (PLC) applications. In the Typical Applications section, the amplifier
is presented in a typical, broadband, current-feedback configuration driving a 50 Ω line load. However, the
amplifier is also applicable for many different general-purpose and specific line-driving applications beyond what
is shown in the Typical Applications section.
8.2 Typical Applications
8.2.1 Broadband PLC Line Driving
The THS6222 provides the exceptional ac performance of a wideband current-feedback op amp with a highly
linear, high-power output stage. The low output headroom requirement and high output current drive capability
makes the THS6222 an excellent choice for 12 V PLC applications. The primary advantage of a currentfeedback op amp such as the THS6222 over a voltage-feedback op amp is that the ac performance (bandwidth
and distortion) is relatively independent of signal gain. Figure 8-1 shows a typical ac-coupled broadband
PLC application circuit where a current-output digital-to-analog converter (DAC) of the PLC application-specific
integrated circuit (ASIC) drives the inputs of the THS6222. Though Figure 8-1 shows the THS6222 interfacing
with a current-output DAC, the THS6222 can just as easily be interfaced with a voltage-output DAC by using
much larger terminating resistors, RT1 and RT2.
1-bit power mode control
Full-bias / shutdown
+12 V
THS6222
IADJ
BIAS
2
BIAS
1
VS+
+12 V
PLC ASIC
Bias Current Control
100 nF
D1
IN+
+
VS+
5k
RT2
249
CM
Buffer
520
100 k
Optional
VCM
100 nF
5k
VS±
D2
IN+
100 nF
D1
OUT
±
100 nF
1:1
D1
INt
RG
274
Thermal
Protection
RL
50
+12 V
D2
INt
50
Power Line
RF2
1.24 k
±
D2
OUT
+
D
GND
RS1
2.49
RF1
1.24 k
100 k
RT1
249
DAC f
AV =
10 V/V
RS2
2.49
100 nF
VSt
Figure 8-1. Typical Broadband PLC Configuration
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8.2.1.1 Design Requirements
The main design requirements for an ac-coupled wideband current-feedback operation are to choose power
supplies that satisfy the output voltage requirement, and also to use a feedback resistor value that allows for
the proper bandwidth while maintaining stability. Use the design requirements shown in Table 8-1 to design a
broadband PLC application circuit.
Table 8-1. Design Requirements
DESIGN PARAMETER
VALUE
Power supply
12 V, single-supply
Differential gain, AV
10 V/V
Spectrum profile
China SGCC HPLC band0, band1, band2, and band3
In-band power spectral density
–50 dBm/Hz
Minimum out-of-band suppression
35 dB
8.2.1.2 Detailed Design Procedure
The closed-loop gain equation for a differential line driver such as the THS6222 is given as AV = 1 + 2 ×
(RF / RG), where RF = RF1 = RF2. The THS6222 is a current-feedback amplifier and thus the bandwidth of
the closed-loop configuration is set by the value of the RF resistor. This advantage of the current-feedback
architecture allows for flexibility in setting the differential gain by choosing the value of the RG resistor without
reducing the bandwidth as is the case with voltage-feedback amplifiers. The THS6222 is designed to provide
optimal bandwidth performance with RF1 = RF2 = 1.24 kΩ. To configure the device in a gain of 10 V/V, the RG
resistor is chosen to be 274 Ω. See the TI Precision Labs for more details on how to choose the RF resistor to
optimize the performance of a current-feedback amplifier.
Often, a key requirement for PLC applications is the out-of-band suppression specifications. The in-band
frequencies carry the encoded data with a certain power level. The line driver must not generate any spurs
beyond a certain power level outside the in-band spectrum. In the design requirements of this application
example, the minimum out-of-band suppression specification of 35 dB means there must be no frequency spurs
in the out-of-band spectrum beyond the –80 dBm/Hz power spectral density, considering the in-band power
spectral density is –50 dBm/Hz.
The circuit shown in Figure 8-2 measures the out-of-band suppression specification. The minor difference in
components between the circuits of Figure 8-1 and Figure 8-2 does not have any significant impact on the
out-of-band suppression results.
+6 V
THS6222
IADJ
BIAS
2
BIAS
1
D1
IN+
+
VS+
CM
Buffer
±
Open VCM
100 k
5k
VS±
D2
IN+
RF1
1.24 k
1:1
D1
INt
Attenuation
RG
274
Thermal
Protection
D2
INt
Power
Spectrum
Analyzer
RF2
1.24 k
±
D2
OUT
+
D
GND
RS1
2.49
50
520
100 nF
D1
OUT
100 k
5k
100 nF
100 nF
AV =
10 V/V
Bias Current Control
100 nF
Arbitrary
Waveform
Generator
VS+
RS2
2.49
VSt
±6 V
Figure 8-2. Measurement Test Circuit for Out-of-Band Suppression
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8.2.1.3 Application Curve
Transmit Power (dBm/Hz)
Figure 8-3 shows the out-of-band suppression measurement results of the circuit. Out-of-band suppression
is a good indicator of the linearity performance of the device. The results in Figure 8-3 show over 40 dB of
out-of-band suppression, which is well beyond the 35 dB requirement and indicative of the excellent linearity
performance of the THS6222.
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
Band0
Band1
Band2
Band3
0
2.5
5
7.5
10 12.5 15 17.5
Frequency (MHz)
20
22.5
25
D030
Figure 8-3. Out-of-Band Suppression
8.3 What to Do and What Not to Do
8.3.1 Do
•
•
•
•
•
Include a thermal design at the beginning of the project.
Use well-terminated transmission lines for all signals.
Use solid metal layers for the power supplies.
Keep signal lines as straight as possible.
Keep the traces carrying differential signals of the same length.
8.3.2 Do Not
•
•
•
Do not use a lower supply voltage than necessary.
Do not use thin metal traces to supply power.
Do not treat the D1 and D2 amplifiers as independent single-ended amplifiers.
9 Power Supply Recommendations
The THS6222 supports single-supply and split-supply power supplies, and balanced and unbalanced bipolar
supplies. The device has a wide supply range of 8 V (–3 V to +5 V) to 32 V (±16 V). Choose power-supply
voltages that allow for adequate swing on both the inputs and outputs of the amplifier to prevent affecting
device performance. Operating from a single supply can have numerous advantages. With the negative supply
at ground, the errors resulting from the –PSRR term can be minimized. The DGND pin provides the ground
reference for the bias control pins. For applications that use split bipolar supplies, care must be taken to design
within the DGND voltage specifications and must be within VS– to (VS+ – 5 V); the DGND pin must be a
minimum bias of 5 V. Thus, the minimum positive supply that can be used in split-supply applications is VS+ =
5 V. The negative supply, VS–, can then be set to a voltage anywhere in between –3 V and –27 V, as per the
Recommended Operating Conditions specifications.
28
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10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the THS6222 requires careful attention
to board layout parasitic and external component types. The THS6222RHFEVM can be used as a reference
when designing the circuit board. Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Parasitic capacitance, particularly
on the output and inverting input pins, can cause instability; on the noninverting input, this capacitance can
react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance,
a window around the signal I/O pins must be opened in all ground and power planes around these pins.
Otherwise, ground and power planes must be unbroken elsewhere on the board.
2. Minimize the distance (less than 0.25 in, or 6.35 mm) from the power-supply pins to high-frequency 0.1 µF
decoupling capacitors. At the device pins, the ground and power plane layout must not be in close proximity
to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and
the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.
An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves
second-harmonic distortion performance. Larger (2.2 µF to 6.8 µF) decoupling capacitors, effective at lower
frequencies, must also be used on the main supply pins. These capacitors can be placed somewhat farther
from the device and can be shared among several devices in the same area of the PCB.
3. Careful selection and placement of external components preserves the high-frequency performance of the
THS6222. Resistors must be of a very low reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Metal film and carbon composition, axially-leaded resistors can also provide good
high-frequency performance.
Again, keep leads and PCB trace length as short as possible. Never use wire-wound type resistors in a
high-frequency application. Although the output pin and inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series output resistor, if any, as close as possible to the
output pin. Other network components, such as noninverting input termination resistors, must also be placed
close to the package. Where double-side component mounting is required, place the feedback resistor
directly under the package on the other side of the board between the output and inverting input pins. The
frequency response is primarily determined by the feedback resistor value, as described in the Boradband
PLC Line Driving section. Increasing the value reduces the bandwidth, whereas decreasing the value leads
to a more peaked frequency response. The 1.24 kΩ feedback resistor used in the Typical Characteristics: Vs
= 12 V is a good starting point for a gain of 10 V/V design.
4. Connections to other wideband devices on the board can be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as
a lumped capacitive load. Relatively wide traces (50-mils to 100-mils, 0.050-in to 0.100-In, or 1.27-mm to
2.54-mm) must be used, preferably with ground and power planes opened up around them.
5. Socketing a high-speed part such as the THS6222 is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, and
can make achieving a smooth, stable frequency response almost impossible. Best results are obtained by
soldering the THS6222 directly onto the board.
6. Use the VS– plane to conduct the heat out of the package. The package attaches the die directly to an
exposed thermal pad on the bottom, and must be soldered to the board. This pad must be connected
electrically to the same voltage plane as the most negative supply voltage (VS–) applied to the THS6222.
Place as many vias as possible on the thermal pad connection and connect the vias to a heat spreading
plane that is at the same potential as VS– on the bottom side of the PCB.
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10.2 Wafer and Die Information
Table 10-1 lists wafer and bond pad information for the YS package.
Table 10-1. Wafer and Bond Pad Information
WAFER BACKSIDE
FINISH
WAFER
THICKNESS
BACKSIDE POTENTIAL
BOND PAD
METALLIZATION
BOND PAD DIMENSIONS (X × Y)
Silicon without
backgrind
25 mils
Must be connected to the lowest voltage potential on
the die (generally VS–)
Al
76.0 µm × 76.0 µm
19
18
17
16
15
14
THS6222
13
12
11
PAD #1
1641.0
1
10
2
9
3
8
4
5
7
6
0
38
0
38
1261.0
All dimensions are in micrometers (µm).
Figure 10-1. Die Dimensions
30
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Table 10-2 lists the bond pad locations for the YS package. All dimensions are in micrometers (µm).
Table 10-2. Bond Pad Locations
PAD
NUMBER
PAD NAME
X MIN
Y MIN
X MAX
Y MAX
1
D1_IN+
71.050
878.875
147.050
954.875
Amplifier D1 noninverting input
2
D2_IN+
71.050
525.125
147.050
601.125
Amplifier D2 noninverting input
3
DGND
71.050
384.025
147.050
460.025
Ground reference for bias control pins
4
IADJ
71.050
267.025
147.050
343.025
Bias current adjustment pin
5
VCM
71.050
150.025
147.050
226.025
Common-mode buffer output
DESCRIPTION
6
VS–
209.175
85.925
285.175
161.925
Negative power-supply connection
7
VS+
1007.475
95.500
1083.475
171.500
Positive power-supply connection
8
D2_OUT
1007.475
222.500
1083.475
298.500
Amplifier D2 output (must be used for D2
output)
9
D2_OUT (OPT)
1007.475
369.900
1083.475
445.900
Optional amplifier D2 output (can be left
unconnected or connected to pad 8)
10
D2_IN–
1007.475
487.375
1083.475
563.375
Amplifier D2 inverting input
11
D1_IN–
1007.450
919.375
1083.450
995.375
Amplifier D1 inverting input
12
D1_OUT (OPT)
1007.475
1034.100
1083.475
1110.100
Optional amplifier D1 output (pad can be
left unconnected or connected to pad 13)
13
D1_OUT
1007.475
1181.500
1083.475
1257.500
Amplifier D1 output (must be used for D1
output)
14
VS+
851.675
1417.950
927.675
1493.950
Positive power-supply connection
15
VS+
718.900
1417.950
794.900
1493.950
Positive power-supply connection
16
VS–
557.375
1417.950
633.375
1493.950
Negative power-supply connection
17
VS–
424.600
1417.950
500.600
1493.950
Negative power-supply connection
18
BIAS-1
293.075
1417.750
369.075
1493.750
Bias mode parallel control, LSB
19
BIAS-2
159.250
1417.750
235.250
1493.750
Bias mode parallel control, MSB
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10.3 Layout Examples
VS+
Bias Control
THS6222
BIAS
2
IADJ
D1IN+
CBYP
BIAS
1
VS+
D1
IN+
+
VS+
±
CM
Buffer
D1
INt
520
Thermal
Protection
Open VCM
100 k
5k
RG
D2
INt
RF2
±
VS±
D2IN+
D1OUT
RF1
100 k
5k
RS1
D1
OUT
D2
IN+
D2
OUT
+
D
GND
D2OUT
RS2
VSt
CBYP
Figure 10-2. Representative Schematic for the Layout in Figure 10-3
Place bypass capacitor
close to power pins
Place the feedback resistors, RF1
and RF2, and the isolation resistors,
RS1 and RS2, as close to the device
pins as possible to minimize parasitics
RS1
D1OUT
Bias
Control
Considering high power capabilities,
use wide supply traces to the bypass
capacitors to minimize inductance
CBYP
CBYP
RG
20
21
22
23
24
RF1
D1IN+
1
D2IN+
2
18
3
17
4
16
5
15
6
14
7
13
19
Thermal Pad
Ground and power plane exist on
inner layers.
D2OUT
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed.
12
11
Connect the thermal pad to a heat
spreading plane; the plane must be at
the same potential as VS±
10
Place as many vias as possible under
the thermal pad and connect them to a
heat spreading plane that is at the
same potential as VS±
8
Open VCM
9
RF2 RS2
Figure 10-3. Layout Recommendations
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11 Device and Documentation Support
11.1 Development Support
TI Precision Labs
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
Texas Instruments, THS6212 Differential Broadband PLC Line Driver Amplifier data sheet
Texas Instruments, THS6214 Dual-Port, Differential, VDSL2 Line Driver Amplifiers data sheet
Texas Instruments, Thermal Design By Insight, Not Hindsight application report
Texas Instruments, TI's IEC 61000-4-x Tests and Procedures application report
Texas Instruments, THS6222 Evaluation Module user guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THS6222IRGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
THS6222IRHFR
ACTIVE
VQFN
RHF
24
3000
THS6222IRHFT
ACTIVE
VQFN
RHF
24
THS6222YS
ACTIVE
WAFERSALE
YS
0
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TH6222
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
(THS, THS6222)
6222
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
(THS, THS6222)
6222
1
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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